A wireless transmission processing system and method

Abstract

The application discloses a wireless transmission processing system and method, relates to the technical field of wireless transmission, and ensures that the time difference of each data from the mii interface of a sending end to the mii interface of a receiving end is a fixed time difference through full-duplex communication, so as to ensure the real-time performance and stability of the system, and the fixed time difference is greater than the maximum value of the time from the rising edge of the valid signal of the received data of the mii interface of the sending end to the rising edge of the transmission enable signal of the gmii interface of the sending end, so that the time synchronization requirement of EtherCAT is met. Moreover, the ST60 wireless chip is arranged in the first wireless module and the second wireless module, the ST60 wireless chip has the low-delay characteristic of nanosecond level, the distributed clock synchronization jitter of EtherCAT is less than or equal to 1us, that is, the nanosecond-level synchronization requirement of EtherCAT is met, so that the communication synchronization efficiency is improved.

Description

Technical Field

[0001] This application relates to the field of wireless transmission technology, and more specifically, to a wireless transmission processing system and method. Background Technology

[0002] EtherCAT (EtherControl Automation) is a high-performance, real-time industrial Ethernet bus protocol designed specifically for industrial automation. It features low latency, high synchronization, and flexible topology. Its core objective is to meet the stringent requirements of scenarios such as motion control and robot collaboration.

[0003] EtherCAT primarily relies on standard wired media for communication. However, commonly used wireless transmission media, such as Wi-Fi, Bluetooth, and LoRa, all suffer from variable transmission delays, making them unsuitable for EtherCAT's time synchronization requirements.

[0004] Therefore, how to improve communication synchronization efficiency by meeting the time synchronization requirements of EtherCAT under the premise of communication through wireless transmission medium is an urgent problem to be solved in this application. Summary of the Invention

[0005] In view of this, this application discloses a wireless transmission processing system and method, which aims to meet the time synchronization requirements of EtherCAT, namely the nanosecond-level synchronization requirements, so as to improve communication synchronization efficiency.

[0006] To achieve the above objectives, the disclosed technical solution is as follows:

[0007] This application discloses a wireless transmission processing system in a first aspect. The system includes a transmitter and a receiver. The transmitter includes at least a first wireless module equipped with a first ST60 chip. The receiver includes at least a second slave controller and a second wireless module equipped with a second ST60 chip. The system includes:

[0008] The second wireless module is used to convert the encoded EtherCAT frame sent by the first wireless module into an EtherCAT frame in SGMII differential transmission mode.

[0009] The second slave controller is used to parse the miidata bus data obtained from the EtherCAT frame based on the differential transmission mode of SGMII to update the EtherCAT frame; and to send the updated EtherCAT frame in the form of mii data bus within a fixed time difference.

[0010] Wherein, the fixed time difference is greater than the maximum value of the time from the rising edge of the valid data reception signal of the MII interface of the transmitting end to the rising edge of the transmit enable signal of the GMII interface of the transmitting end; the maximum value is determined by the number of bytes transmitted by the GMII interface of the transmitting end within a preset transmission period.

[0011] A second aspect of this application discloses a wireless transmission processing method, which is applied to the wireless transmission processing system described in any one of the first aspects above. The system includes a transmitting end and a receiving end; the transmitting end includes at least a first wireless module equipped with a first ST60 chip; the receiving end includes at least a second slave controller and a second wireless module equipped with a second ST60 chip. The method includes:

[0012] The second wireless module converts the encoded EtherCAT frame sent by the first wireless module into an EtherCAT frame using the differential transmission mode of SGMII.

[0013] The second slave controller parses the MII data bus data obtained from the EtherCAT frame based on differential transmission mode, obtains address information and operation commands, and executes them to update the EtherCAT frame.

[0014] Within a fixed time difference, the updated EtherCAT frame is transmitted via the second slave controller in the form of MII data on a bus; wherein, the fixed time difference is greater than the maximum value of the time from the rising edge of the valid data reception signal of the MII interface of the transmitting end to the rising edge of the transmit enable signal of the GMII interface of the transmitting end; the maximum value is determined by the number of bytes transmitted by the GMII interface of the transmitting end within a preset transmission period.

[0015] The above scheme achieves data transmission between two EtherCAT slave stations via wireless transmission. During wireless data transmission, updated EtherCAT frames are sent via the MII data bus within a fixed time difference. The minimum fixed time difference is the maximum time between the rising edge of the valid data reception signal on the sending end's MII interface and the rising edge of the transmit enable signal on the sending end's GMII interface. This scheme uses full-duplex communication to ensure that the time difference between each data transmission from the sending end's MII interface to the receiving end's MII interface is a fixed time difference, thus ensuring the system's real-time performance and stability. Furthermore, the fixed time difference is greater than the maximum time between the rising edge of the valid data reception signal on the sending end's MII interface and the rising edge of the transmit enable signal on the sending end's GMII interface, thereby meeting the EtherCAT time synchronization requirements. Additionally, since both the first and second wireless modules incorporate ST60 wireless chips, which have nanosecond-level low latency characteristics, and ensure that the EtherCAT distributed clock (DC) synchronization jitter is ≤1µs, the nanosecond-level synchronization requirements of EtherCAT are met, thereby improving communication synchronization efficiency. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of the structure of a wireless transmission processing system disclosed in an embodiment of this application;

[0018] Figure 2 This is a schematic diagram of the hardware interface framework of EtherCAT disclosed in the embodiments of this application;

[0019] Figure 3 This is a block diagram of a device connection between a transmitter and a receiver connected via a wireless transmission medium, as disclosed in an embodiment of this application.

[0020] Figure 4 This is an example diagram of a fixed time difference disclosed in an embodiment of this application;

[0021] Figure 5 This is a diagram showing the TX / RX mode switching cycle of the wireless chip disclosed in an embodiment of this application;

[0022] Figure 6 This is a schematic diagram of the structure of the mii2gmii module disclosed in the embodiments of this application;

[0023] Figure 7 A flowchart illustrating the functional design of the mii2gmii module disclosed in the embodiments of this application;

[0024] Figure 8 This is a schematic diagram of the structure of the gmii2mii module disclosed in the embodiments of this application;

[0025] Figure 9 A flowchart illustrating the functional design of the gmii2mii module disclosed in the embodiments of this application;

[0026] Figure 10 This is a schematic diagram of a wireless transmission processing procedure disclosed in an embodiment of this application. Detailed Implementation

[0027] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0028] In this application, the terms "comprising," "including," or any other variations thereof are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0029] As the background technology shows, EtherCAT primarily relies on standard wired media for communication. However, currently common wireless transmission media, such as Wi-Fi, Bluetooth, and LoRa, all suffer from variable transmission delays, failing to meet EtherCAT's time synchronization requirements. Therefore, how to improve communication synchronization efficiency by satisfying EtherCAT's time synchronization requirements while using wireless transmission media is a problem that this application urgently needs to solve.

[0030] To address the aforementioned issues, this application discloses a wireless transmission processing system and method. This system enables data transmission between two EtherCAT slave stations via wireless transmission. During wireless data transmission, updated EtherCAT frames are sent via a MII data bus within a fixed time difference. The minimum fixed time difference is the maximum time between the rising edge of the valid data reception signal on the sending end's MII interface and the rising edge of the transmit enable signal on the sending end's GMII interface. This scheme ensures a fixed time difference for each data transmission from the sending end's MII interface to the receiving end's MII interface through full-duplex communication, thereby ensuring the system's real-time performance and stability. Furthermore, the fixed time difference is greater than the maximum time between the rising edge of the valid data reception signal on the sending end's MII interface and the rising edge of the transmit enable signal on the sending end's GMII interface, thus meeting the EtherCAT time synchronization requirements. Additionally, since both the first and second wireless modules incorporate ST60 wireless chips, which feature nanosecond-level low latency, and guarantee EtherCAT distributed clock synchronization jitter ≤1µs, the nanosecond-level synchronization requirements of EtherCAT are met, thereby improving communication synchronization efficiency. The specific implementation method is explained in detail through the following examples.

[0031] refer to Figure 1 The diagram illustrates a wireless transmission processing system disclosed in this application. The system includes a sender and a receiver (rcv), connected via a wireless transmission medium. The sender includes at least a first slave controller (i.e., a first EtherCAT IP), a mii2gmii module, a first gmii2sgmii IP module, and a first wireless module equipped with a first ST60 chip. The receiver includes at least a second slave controller (i.e., a second EtherCAT IP), a second wireless module equipped with a second ST60 chip, a second gmii2sgmii IP module, and a gmii2mii module.

[0032] The data interaction between the sending and receiving ends is as follows:

[0033] The first slave controller is used to parse the received Media Independent Interface Bus (MIIData) data according to a preset protocol, obtain address information and operation commands, execute them, and obtain an updated EtherCAT frame.

[0034] The preset protocols include, but are not limited to, the Ethernet Control Automation Technology (EtherCAT) protocol. The EtherCAT protocol is preferred in this application. EtherCAT is a high-performance real-time industrial Ethernet bus protocol designed specifically for industrial automation, featuring low latency, high synchronization, and flexible topology. Its core objective is to meet the stringent requirements of scenarios such as motion control and robot collaboration. EtherCAT data transmission includes both preferred transmission media and wireless transmission media scenarios.

[0035] Wired transmission medium information:

[0036] EtherCAT primarily relies on standard wired media for communication:

[0037] Core type: Uses 100Base-TX standard Ethernet twisted pair cable, compatible with commercial Ethernet hardware (such as RJ-45 interface), achieving microsecond-level synchronization accuracy and bandwidth utilization of up to 100Mbps.

[0038] Wireless transmission medium information:

[0039] EtherCAT does not support wireless transmission media (such as microwave or infrared) because its design focuses on high real-time performance in wired environments. Currently common wireless media, such as Wi-Fi, Bluetooth, and LoRa, all have variable transmission delays and cannot meet EtherCAT's nanosecond-level synchronization requirements. EtherCAT requires a fixed transmission delay for the physical transmission process.

[0040] The transmission delay between EtherCAT slaves needs to be fixed to ensure that the calculation principle of EtherCAT Distributed Clock (DC) achieves nanosecond-level synchronization through a multi-stage compensation mechanism. EtherCAT wired transmission usually uses 100Base-TX standard Ethernet twisted-pair cable, and its transmission delay is fixed. This solution achieves a fixed value for wireless transmission delay through hardware and software methods.

[0041] EtherCAT's hardware interface framework, such as Figure 2 As shown.

[0042] Figure 2 The rtx_sw signal indicates that the ST60 wireless chip only supports half-duplex communication and requires the rtx_sw signal to switch between TX and RX modes.

[0043] The MII interface signals are described below:

[0044] TX_ER (Transmit Error): This signal indicates a data transmission error. It is synchronized with TX_CLK, active high, and indicates that data transmitted within the validity period of TX_ER is invalid. TX_ER has no effect at speeds of 10Mbps.

[0045] TX_EN (Transmit Enable): Sends an enable signal; only data transmitted within the validity period of TX_EN is valid.

[0046] TX_CLK: Transmit reference clock. At a rate of 100Mbps, the clock frequency is 25MHz; at a rate of 10Mbps, the clock frequency is 2.5MHz. Note that the direction of the TX_CLK clock is from the PHY side to the MAC side, and this clock is provided by the PHY chip.

[0047] TXD (Transmit Data) [3:0]: Data transmission signal, with a total of 4 signal lines.

[0048] RX_ER (Receive Error): This signal indicates a received data error. It is synchronized with RX_CLK and is active high. It indicates that data transmitted within the validity period of RX_ER is invalid. RX_ER has no effect at 10Mbps speeds.

[0049] RX_DV (Reveive Data Valid): Signal that the received data is valid. Its function is similar to TX_EN of the transmit channel.

[0050] RXD (Receive Data) [3:0]: Data receiving signal, a total of 4 signal lines.

[0051] RX_CLK: Receive data reference clock. At a rate of 100Mbps, the clock frequency is 25MHz; at a rate of 10Mbps, the clock frequency is 2.5MHz. RX_CLK is also provided by the PHY chip.

[0052] The GMII interface is described in Table 1.

[0053] The GMII interface includes the following key signals (taking the transmit and receive directions as examples):

[0054] Table 1

[0055]

[0056] The first wireless module sends the encoded EtherCAT frame obtained based on the updated EtherCAT frame to the second wireless module. This process specifically involves the data processing of the mii2gmii module and the first gmii2sgmii IP module, as follows:

[0057] The MII data is acquired via the MII data bus. This MII data is then connected to the first EtherCAT IP at the transmitting end. The first EtherCAT IP parses the MII data according to the EtherCAT protocol, obtains the address information and operation commands, executes them, and generates an updated EtherCAT frame. The first EtherCAT IP then connects the updated EtherCAT frame to the mii2gmii module via the MII data bus.

[0058] The mii2gmii module is used to convert updated EtherCAT frames into a gmii bus format and connect them to the first gmii2sgmii IP module.

[0059] The first gmii2sgmii IP module is used to convert the bus-format EtherCAT frames of gmii into the differential transmission format of sgmii and send the differential transmission EtherCAT frames to the first wireless module.

[0060] The first wireless module is used to parse and encode the differential transmission EtherCAT frame into a wireless transmission mode, obtain the encoded EtherCAT frame, and send the encoded EtherCAT frame to the second wireless module.

[0061] The second wireless module is used to convert the encoded EtherCAT frames sent by the first wireless module into EtherCAT frames using the differential transmission mode of SGMII.

[0062] The second EtherCAT IP is used to parse the MII data bus data obtained from the differential transmission EtherCAT frame, obtain address information and operation commands, and execute them to update the EtherCAT frame. Specifically, the process of obtaining the MII data bus data from the differential transmission EtherCAT frame involves the data processing procedures of the second gmii2sgmii IP module and the gmii2mii module, as follows:

[0063] The second wireless module is used to send EtherCAT frames converted to SGMII differential transmission mode to the second gmii2sgmii IP module.

[0064] The second gmii2sgmii IP module is used to parse the EtherCAT frames of the differential transmission mode of sgmii, obtain data in the form of gmii data bus, and send the data in the form of gmii data bus to the gmii2mii module.

[0065] The gmii2mii module is used to convert data in gmii data bus format into mii data bus data and send the mii data bus data to the second EtherCAT IP.

[0066] The second EtherCAT IP is used to parse the MII data bus data, obtain address information and operation commands, and execute them to update the EtherCAT frame. Within a fixed time difference (Δt), the updated EtherCAT frame is transmitted via the MII data bus. This fixed time difference is greater than the maximum value of the time from the rising edge of the receiving data valid signal (send_mii_rx_dv) of the transmitting end's MII interface to the rising edge of the transmit enable signal (send_gmii_tx_en) of the transmitting end's GMII interface (tsend_mii->gmii). This maximum value is determined by the number of bytes transmitted by the transmitting end's GMII interface within a preset transmission period. The second EtherCAT IP transmits the EtherCAT frame via the MII data bus within the fixed time difference, achieving wireless transmission between two EtherCAT slave stations, such as those operating at 100M Mbps.

[0067] A connection diagram of the devices connecting the transmitter and receiver via a wireless transmission medium is shown below. Figure 3 As shown.

[0068] Figure 3 The transmitting end also includes a first physical layer chip (i.e., a first PHY chip), a first FPGA chip (EtherCAT slave logic), a first conversion chip (i.e., a first GMII to SGMII chip), and a first RJ45 interface. The first FPGA chip is connected to both the first PHY chip and the first GMII to SGMII chip. The first RJ45 interface is connected to the first PHY chip.

[0069] The first PHY chip is a converter between digital signals and physical medium transmission signals; the first FPGA chip has the first slave controller IP logic programmed into it for data processing by the first slave controller; the first GMII to SGMII chip is a chip that converts GMII interface format data to SGMII interface format data.

[0070] The first wireless module is equipped with a first ST60 wireless chip; the first ST60 wireless chip is connected to the first conversion chip; the first ST60 wireless chip is a radio frequency transceiver for a preset frequency band of non-contact point-to-point communication.

[0071] Figure 3 The receiving end also includes a second physical layer chip (i.e., a second PHY chip), a second FPGA chip (EtherCAT slave n+1 logic), a second conversion chip (i.e., a second MGII to SGMII chip) and a second RJ45 interface.

[0072] The second FPGA chip is connected to both the second PHY chip and the second MGII to SGMII converter chip. The second RJ45 interface is connected to the second PHY chip.

[0073] The second physical layer chip is used for the conversion between digital signals and physical medium transmission signals; the second FPGA chip is programmed with the IP logic of the second slave controller for data processing by the controller; the second conversion chip is used to convert SGMII interface format data to GMII interface format data.

[0074] The second wireless module is equipped with a second ST60 wireless chip; the second ST60 wireless chip is connected to the second conversion chip; the second ST60 wireless chip is a radio frequency transceiver for a preset frequency band of non-contact point-to-point communication.

[0075] It should be noted that both the first and second ST60 chips are 60GHz band RF transceivers enabling short-range (e.g., as low as a few centimeters, or even lower) contactless point-to-point communication. The 60GHz RF millimeter-wave unlicensed V-band opens up new opportunities for contactless connectivity. By achieving unprecedented multi-gigabit data transmission rates, the application of this RF technology in embedded devices can eliminate the need for physical cables, rotary joints, and connectors.

[0076] The first and second ST60 chips have the following advanced features: high data transfer rate (up to 6.25Gbps) for fast data transfer; low latency (nanosecond level) to ensure real-time performance; excellent energy efficiency with power consumption as low as 100mW; compact form factor for easy PCB integration; and seamless connection without pairing.

[0077] The ST60 transceivers of both the first and second ST60 chips require no specific software drivers, thus helping developers optimize the bill of materials and simplify the software design process. Furthermore, developers can choose from a variety of external antennas to meet the needs of diverse applications.

[0078] The first ST60 chip uses a half-duplex transmission mode, meaning that only one of the transmit and receive modes can exist at any given time. The switching time between transmit and receive is 1600ns, and the transmit and receive modes are switched by the high and low levels of the chip's pins.

[0079] The second ST60 chip uses a half-duplex transmission mode, meaning that only one of the transmit and receive modes can exist at any given time. The switching time between transmit and receive is 1600ns, and the transmit and receive modes are switched by the high and low levels of the chip's pins.

[0080] The first and second physical chips are core components in computer networks and communication equipment responsible for physical layer signal processing. They act as converters between digital signals and signals transmitted through the physical medium, directly determining whether the device can achieve stable, high-speed data transmission over a specific physical medium (such as network cables or optical fibers). Their core functions revolve around "signal encoding / decoding, transmission / reception, and adaptation to the physical medium." In this solution, they primarily participate in wired transmission.

[0081] The first and second physical layer chips contain the EtherCAT slave controller IP logic, which is equivalent to an EtherCAT slave control chip. Its main functions include data processing and transmission, data storage and management, interface adaptation and configuration, clock synchronization and system coordination.

[0082] Since the first ST60 wireless chip and the second ST60 wireless chip only support the SGMII interface, the first conversion chip and the second conversion chip convert the GMII interface to the SGMII interface.

[0083] The first and second ST60 wireless chips are 60GHz band radio frequency transceivers that enable short-range (as low as a few centimeters) contactless point-to-point communication. They form the physical layer for wireless transmission.

[0084] Figure 3 The data interaction process between the sending and receiving ends is as follows:

[0085] 1. The transmitting end receives data at the first PHY chip.

[0086] 2. The data is processed by the first FPGA chip (EtherCAT slave logic) at the transmitting end;

[0087] 3. The first GMII to SGMII chip converts the processed data from the GMII interface to the SGMII interface and transmits the converted data to the first ST60 wireless chip at the transmitting end.

[0088] 4. The first ST60 wireless chip at the transmitting end transmits the converted data to the second ST60 wireless chip at the receiving end via the 60GHz frequency band.

[0089] 5. The second ST60 wireless chip at the receiving end transmits the received data through the first GMII to SGMII chip at the receiving end, and then into the second FPGA chip (EtherCAT slave n+1 logic) for data processing.

[0090] 6. The data processed by the second FPGA chip is transmitted to the next wired EtherCAT slave station through the second PHY chip.

[0091] The data exchange process from the receiving end to the sending end is as follows:

[0092] 1. The receiving end receives data at the second PHY chip;

[0093] 2. Data is transmitted transparently to the second FPGA chip (EtherCAT slave logic) at the receiving end;

[0094] 3. The second GMII to SGMII chip converts the transparently transmitted data from the GMII interface to the SGMII interface, and transmits the converted data to the second ST60 wireless chip at the receiving end.

[0095] 4. The second ST60 wireless chip at the receiving end transmits the converted data to the first ST60 wireless chip at the transmitting end via the 60GHz frequency band.

[0096] 5. The data received by the first ST60 wireless chip at the transmitting end is transmitted through the first GMII to SGMII chip at the transmitting end to the second FPGA chip (EtherCAT slave n+1 logic) for data pass-through.

[0097] 6. After data pass-through, the data is transmitted to the previous wired EtherCAT slave station via the second PHY chip.

[0098] It should be noted that both the first and second ST60 wireless chips only support half-duplex communication, requiring the rtx_sw signal to switch between TX and RX modes. To ensure full-duplex communication between the two chips within a periodic time T, the communication must maintain a fixed time difference between each data transmission from the sending end's 100Mbps MII interface (send_mii_rx_dv high) and the receiving end's 100Mbps MII interface (rcv_mii_tx_en high). This ensures the system's real-time performance and stability. The specific fixed time difference is as follows: Figure 4 As shown.

[0099] Figure 4 In this process, because `send_gmii_tx_en` is transmitted intermittently by pulling it high, `rcv_gmii_x_dv` is received intermittently. After the sending end raises `send_mii_rx_dv`, it waits for a period of time before raising `send_gmii_tx_en`, and then sends it to the receiving end through the first ST60 wireless chip. After receiving it, the receiving end raises `rcv_gmii_rx_dv`, and then raises `rcv_mii_tx_en` to send it. The fixed time difference must be a fixed value to ensure a fixed transmission delay, thereby improving the distributed DC synchronization performance. To achieve this, the first and second ST60 wireless chips in this solution need to meet the following two prerequisites:

[0100] Prerequisite 1: The TX / RX mode switching of the first or second ST60 wireless chip is controlled by the level of an external io signal (i.e., rtx_sw).

[0101] Prerequisite 2: After the TX / RX mode of the first or second ST60 wireless chip is switched, i.e. after the IO signal level changes, a mode conversion time (e.g., 1600ns) must be waited before data TX / RX can begin.

[0102] TX mode is the process of a device sending data, while RX mode is the process of a device receiving data. In Bluetooth communication, these two modes alternate to achieve bidirectional data transmission. This flexible mode switching allows Bluetooth devices to exchange data efficiently.

[0103] The following problems can be solved by adjusting the above-mentioned prerequisites:

[0104] Problem 1: Simultaneous Two-Way Mode

[0105] Based on the characteristics of the ST60 wireless chip, namely the two prerequisites mentioned above, for two-way communication to be achieved, one party must be in transmitting mode while the other party is in receiving mode. Specifically, as follows: Figure 5 As shown, Figure 5 This represents a timing diagram for the sender and receiver rtx_sw.

[0106] Figure 5 In the default configuration, after power-on, both the transmitting and receiving ends are in receive mode (high level for transmitting mode, low level for receiving mode), and both sides use a period T. The transmitting end toggles according to the periodic T, while the receiving end counts for one TT after receiving data. txThe time interval is raised to synchronize with the transmitting end, and the receiving end then flips periodically according to T. This ensures that when one party is in transmitting mode, the other is in receiving mode.

[0107] Problem 2: Fixed time difference Δt:

[0108] The time difference (i.e., the fixed time difference Δt) between the rising edge of send_mii_rx_dv and the rising edge of rcv_mii_tx_en is decomposed into the time between the rising edge of send_mii_rx_dv and the rising edge of send_gmii_tx_en (i.e., t). send_mii->gmii The time from the rising edge of rcv_gmii_rx_dv to the rising edge of rcv_mii_tx_en (i.e., t) gmii->rcv_mii In this context, the rising edges of send_gmii_tx_en and rcv_gmii_rx_dv occur simultaneously.

[0109] Figure 5 In this context, the time segment within the period will be divided into three parts. The first part is the period from the start of the period to T. 切换 Part 2 is T 切换 ->T tx Part 3 is T tx Towards the end of the cycle.

[0110] Because it's uncertain which segment of T the rising edge of send_mii_rx_dv falls into, and to obtain a fixed Δt, Δt > t is required. send_mii->gmii The maximum value is then obtained by the receiver, which in turn receives t. send_mii->gmii The value of t can control t gmii->rcv_mii The value of . That is, Δt = t send_mii->gmii +t gmii->rcv_mii ; as long as t send_mii->gmii The value is given to the receiving end, and then t is subtracted from the set Δt. send_mii->gmii The value of `rcv_mii_tx_en` can control when the receiving end sets `rcv_mii_rx_dv`. Therefore, counting can start when `send_mii_rx_dv` is set and stop when `send_gmii_tx_en` is sent, sending the count value `delay_cnt` as GMII data to the receiving end. After receiving the count value `delay_cnt`, the receiving end can calculate the expected count value for setting `rcv_mii_tx_en`: `exc_wt_cnt = Δt - delay_cnt`. The receiving end starts counting `wt_cnt` after `rcv_gmii_rx_dv` is set, and when `wt_cnt` equals `exp_wt_cnt`, `rcv_mii_tx_en` is set and data is sent, thus fixing `Δt`.

[0111] Problem 3: Determine the value of the fixed time difference:

[0112] Note 1: When sending data with GMII within a single cycle T, it cannot be interrupted. This is because the incoming data from MII is sent at 80ns per byte, while the outgoing data from GMII is sent at 8ns per byte. There cannot be a situation where GMII sends a few bytes, then there is no data in the FIFO, causing GMII_rx_dv to go low, and then the data re-sends after a full MII cycle.

[0113] Point 2: When the receiving end reads data from the MII, it cannot read intermittently. As long as `rcv_mii_tx_en` is enabled, the entire content of the EtherCAT frame must be read, not read in segments. This is because the sender transmits an EtherCAT frame in multiple T-cycles, and the data transmitted by `gmii` in one T-cycle is limited. The receiving end cannot be allowed to receive only a portion of a frame's data before the FIFO runs out of data, resulting in the need to wait for the next T-cycle of data to arrive before reading the data intermittently.

[0114] In solving problem two, when determining the requirement of a fixed Δt, Δt > t. send_mii->gmii The maximum value of t, and t send_mii->gmii The maximum value is related to the number of bytes sent by gmii within one T-cycle.

[0115] Based on points 1 and 2, let the number of bytes sent be x, and determine the conversion time of the wireless chip to be 1680ns (with an 80ns margin for mode conversion).

[0116] Based on point 2, it is necessary to ensure that the number of bytes read by the receiver within one period T is less than or equal to the number of bytes sent by gmii, thus deriving formula (1):

[0117] (2*1680+16x) / 80 <x(1);

[0118] That is: x > 52.5;

[0119] Based on point 1, it must be ensured that send_mii_rx_data has received at least x bytes before sending, such as... Figure 5 Because the position of the rising edge of send_mii_rx_dv within T1 is uncertain, and Δt needs to satisfy Δt>t send_mii->gmii If the maximum value of t is found, then t send_mii->gmii The maximum value is the rising edge of send_mii_rx_dv at T1. tx If the position is such that send_gmii_tx_en is in cycle T3, then send_gmii_tx_en must be in cycle T3. tx The matter was dealt with. Therefore, t send_mii->gmiiThe maximum value is 2T, that is:

[0120] Δt=2*(2*1680+16x)=6720+32x(2);

[0121] Since x is a positive integer and x > 52.5, Δt is at its minimum when x = 53. Therefore, Δt min = 8416 ns.

[0122] Because the clock period of GMII is 8ns, the following... Figure 9 The fixed count value corresponding to Δt min set in the middle is 8416 / 8=1052; the time of period T is T=2*1680+16*53=4208ns.

[0123] The structure of the mii2gmii module is as follows: Figure 6 As shown, the functional design flow of the mii2gmii module is as follows: Figure 7 As shown.

[0124] Figure 7 The process involves determining the rising edge of the frame data valid signal mii_rx_dx, whether the FIFO has stored 53 bytes, whether the number of bytes stored in the FIFO is greater than 53, and whether the FIFO is empty.

[0125] The structure of the gmii2mii module is as follows: Figure 8 As shown, the functional design flow of the gmii2mii module is as follows: Figure 9 As shown.

[0126] Figure 9 The process involves determining the rising edge of the valid data signal gmii_rx_dv, checking if fifo is empty, setting wt_cnt=exp_wt_cnt, and checking if fifo is empty.

[0127] In this embodiment, data transmission between two EtherCAT slave stations is achieved wirelessly. During wireless data transmission, updated EtherCAT frames are sent via the MII data bus within a fixed time difference. The minimum fixed time difference is the maximum time between the rising edge of the valid data reception signal of the MII interface at the transmitting end and the rising edge of the transmit enable signal of the GMII interface at the transmitting end. This scheme ensures that the time difference between each data transmission from the MII interface at the transmitting end to the MII interface at the receiving end is a fixed time difference through full-duplex communication, thereby ensuring the real-time performance and stability of the system. Furthermore, the fixed time difference is greater than the maximum time between the rising edge of the valid data reception signal of the MII interface at the transmitting end and the rising edge of the transmit enable signal of the GMII interface at the transmitting end, thus meeting the EtherCAT time synchronization requirements. Additionally, since both the first and second wireless modules are equipped with ST60 wireless chips, which have nanosecond-level low latency characteristics, and simultaneously ensure that the EtherCAT distributed clock synchronization jitter is ≤1µs, the nanosecond-level synchronization requirements of EtherCAT are met, thereby improving communication synchronization efficiency.

[0128] Based on the above embodiments Figure 1 The disclosed wireless transmission processing system, and the corresponding embodiments of this application also disclose a wireless transmission processing method, such as... Figure 10 As shown, this wireless transmission processing method is applied to the above embodiments. Figure 1 The wireless transmission processing system includes a transmitter and a receiver connected via a wireless transmission medium. The transmitter includes at least a first wireless module equipped with a first ST60 chip, and the receiver includes at least a second slave controller and a second wireless module equipped with a second ST60 chip. The wireless transmission processing method mainly includes the following steps:

[0129] S1001: The second wireless module converts the encoded EtherCAT frame sent by the first wireless module into an EtherCAT frame using the differential transmission mode of SGMII.

[0130] S1002: The EtherCAT frame is updated by parsing the MII data bus data obtained from the EtherCAT frame based on the differential transmission mode of SGMII through the second slave controller.

[0131] S1003: Within a fixed time difference, the updated EtherCAT frame is transmitted via the second slave controller in the form of MII data bus; wherein, the fixed time difference is greater than the maximum value of the time from the rising edge of the receive data valid signal of the MII interface of the transmitting end to the rising edge of the transmit enable signal of the GMII interface of the transmitting end; the maximum value is determined by the number of bytes transmitted by the GMII interface of the transmitting end within a preset transmission period.

[0132] The fixed time difference is obtained by a preset determination method under preset fixed conditions. See A1-A3 for details.

[0133] A1: The start time is when the receive data valid signal of the MII interface of the transmitting end is set, and the stop time is when the transmit enable signal of the MII interface of the receiving end is set.

[0134] A2: Calculate the first count value of the expected transmit enable signal of the MII interface of the receiving end during the start time to stop time.

[0135] The first count value is the expected count value exc_wt_cnt set by rcv_mii_tx_en.

[0136] A3: When the first count value equals the second count value, the process of determining the preset fixed conditions is completed; the second count value is the count value when the valid signal for receiving data is activated at the receiving end's GMII interface.

[0137] The count value when the valid signal for received data is activated on the GMII interface of the receiving end is Δt–delay_cnt.

[0138] exc_wt_cnt=Δt–delay_cnt, which is the process of determining the preset fixed conditions.

[0139] The process of obtaining a fixed time difference is shown in B1-B3.

[0140] B1: Under preset fixed conditions, set the number of bytes to be sent by the transmitting end and determine the wireless chip switching time.

[0141] B2: Determine the maximum value of the time from the rising edge of the valid data reception signal of the MII interface of the transmitting end to the rising edge of the transmit enable signal of the GMII interface of the transmitting end through the first preset calculation formula, the number of bytes sent, and the wireless chip conversion time.

[0142] Among them, the first pre-designed calculation formula is the time of periodic inversion of transceiver. The minimum number of bytes is deduced according to the formula (2*1680 + 16x) / 80 < x, and based on the minimum number of bytes, the minimum fixed time Δt = 2*(2*1680 + 16x) = 6720 + 32x is deduced.

[0143] B3: Determine the fixed time difference through the second pre-designed calculation formula, the number of transmitted bytes, the wireless chip conversion time and the maximum value.

[0144] Among them, the second pre-designed calculation formula is the above formula (2).

[0145] The minimum value of the fixed time difference is the maximum value of the time from the rising edge of the received data valid signal of the mii interface at the sending end to the rising edge of the transmit enable signal of the gmii interface at the sending end.

[0146] The execution process and principle of S1001 - S1003 are the same as those of the above embodiments Figure 1 and Figure 3 and the execution process and principle are consistent, which can be referred to and will not be elaborated here.

[0147] In the embodiment of the present application, data transmission between two EtherCAT slave stations is achieved through wireless transmission. During the wireless data transmission process, the updated EtherCAT frame is sent in the form of the mii data bus within the fixed time difference. The minimum value of the fixed time difference is the maximum value of the time from the rising edge of the received data valid signal of the mii interface at the sending end to the rising edge of the transmit enable signal of the gmii interface at the sending end. This solution ensures that the time difference from when the data enters the mii interface at the sending end to when it exits the mii interface at the receiving end is a fixed time difference through full-duplex communication, so as to ensure the real-time performance and stability of the system. And the fixed time difference is greater than the maximum value of the time from the rising edge of the received data valid signal of the mii interface at the sending end to the rising edge of the transmit enable signal of the gmii interface at the sending end, thereby meeting the time synchronization requirements of EtherCAT. And since the ST60 wireless chips are both set in the first wireless module and the second wireless module, the ST60 wireless chip has the low-latency characteristic at the nanosecond level, and at the same time ensures that the distribution clock synchronization jitter of EtherCAT ≤ 1us, that is, it meets the nanosecond-level synchronization requirements of EtherCAT, so as to improve the communication synchronization efficiency.

[0148] For the foregoing method embodiments, in order to simplify the description, they are all described as a series of actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, because according to this application, some steps can be performed in other orders or simultaneously. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily essential to this application.

[0149] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For apparatus embodiments, since they are basically similar to method embodiments, the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments.

[0150] The steps in the methods of the various embodiments of this application can be adjusted, combined, or deleted according to actual needs.

[0151] Finally, it should be noted that in this paper, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0152] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0153] The above description is only a preferred embodiment of this application. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of this application, and these improvements and modifications should also be considered within the scope of protection of this application.

Claims

1. A wireless transmission processing system, characterized in that, The system includes a transmitter and a receiver; the transmitter includes at least a first wireless module equipped with a first ST60 chip; the receiver includes at least a second slave controller and a second wireless module equipped with a second ST60 chip, and the system includes: The second wireless module is used to convert the encoded EtherCAT frame sent by the first wireless module into an EtherCAT frame in SGMII differential transmission mode. The second slave controller is used to parse the MII data bus data obtained from the EtherCAT frame based on the differential transmission mode of SGMII to update the EtherCAT frame; and to send the updated EtherCAT frame in the form of MII data bus within a fixed time difference. Wherein, the fixed time difference is greater than the maximum value of the time from the rising edge of the valid data reception signal of the MII interface of the transmitting end to the rising edge of the transmit enable signal of the GMII interface of the transmitting end; the maximum value is determined by the number of bytes transmitted by the GMII interface of the transmitting end within a preset transmission period.

2. The system according to claim 1, characterized in that, The transmitting end also includes a mii2gmii module; The mii2gmii module is used to convert the updated EtherCAT frame into a gmii bus format.

3. The system according to claim 2, characterized in that, The transmitting end also includes a first gmii2sgmii IP module; The first gmii2sgmii IP module is used to convert the GMII bus-type EtherCAT frame into the sgmii differential transmission form, and send the differential transmission EtherCAT frame to the first wireless module, so that the first wireless module can parse the differential transmission EtherCAT frame and encode it into a wireless transmission mode to obtain the encoded EtherCAT frame.

4. The system according to claim 1, characterized in that, The transmitting end also includes a first physical layer chip, a first FPGA chip, a first slave controller, and a first conversion chip; The first FPGA chip is connected to the first physical layer chip and the first conversion chip respectively; in ； The first physical layer chip is a converter between digital signals and signals transmitted through the physical medium; The first slave controller IP logic is programmed into the first FPGA chip for data processing by the first slave controller; The first conversion chip is a chip that converts GMII interface format data to SGMII interface format data.

5. The system according to claim 4, characterized in that, The first ST60 wireless chip is connected to the first conversion chip; the first ST60 wireless chip is a radio frequency transceiver for a preset frequency band of contactless point-to-point communication.

6. The system according to claim 1, characterized in that, The receiving end also includes a second gmii2sgmii IP module; The second gmii2sgmii IP module is used to parse the EtherCAT frames of the differential transmission mode of sgmii to obtain data in the form of gmii data bus.

7. The system according to claim 6, characterized in that, The receiving end also includes a gmii2mii module; The gmii2mii module is used to convert the data in the gmii data bus format into mii data bus data.

8. The system according to claim 1, characterized in that, The receiving end also includes a second physical layer chip, a second FPGA chip, and a second conversion chip; The second FPGA chip is connected to the second physical layer chip and the second conversion chip, respectively; The second physical layer chip is used for the conversion between digital signals and signals transmitted through the physical medium. The second slave controller IP logic is programmed into the second FPGA chip for use in controller data processing; The second conversion chip is used to convert SGMII interface format data to GMII interface format data.

9. The system according to claim 8, characterized in that, The second ST60 wireless chip is connected to the second conversion chip; the second ST60 wireless chip is a radio frequency transceiver for a preset frequency band of contactless point-to-point communication.

10. A wireless transmission processing method, characterized in that, The method is applied to the wireless transmission processing system according to any one of claims 1 to 9, the system comprising a transmitter and a receiver; the transmitter at least includes a first wireless module equipped with a first ST60 chip; The receiving end includes at least a second slave controller and a second wireless module equipped with a second ST60 chip, and the method includes: The second wireless module converts the encoded EtherCAT frame sent by the first wireless module into an EtherCAT frame using the differential transmission mode of SGMII. The second slave controller parses the MII data bus data obtained from the EtherCAT frame based on the differential transmission mode of SGMII to update the EtherCAT frame. Within a fixed time difference, the updated EtherCAT frame is sent via the second slave controller in the form of MII data bus; Wherein, the fixed time difference is greater than the maximum value of the time from the rising edge of the valid data reception signal of the MII interface of the transmitting end to the rising edge of the transmit enable signal of the GMII interface of the transmitting end; the maximum value is determined by the number of bytes transmitted by the GMII interface of the transmitting end within a preset transmission period.

Images