A phase change memory

Abstract

The application discloses a kind of phase change memories, belongs to phase change memory technical field.The phase change memory includes: first conductive layer, storage unit and second conductive layer are stacked along the first direction;Storage unit is coupled between first conductive layer and second conductive layer;Storage unit includes: phase change storage layer, gating layer and buffer layer are stacked along the first direction;Buffer layer is between phase change storage layer and gating layer, the relative dielectric constant of the material of buffer layer is greater than or equal to 2.0, and the conductivity of buffer layer is greater than and less than.The above technical solution, set up a buffer layer with relatively large dielectric constant between phase change storage layer and gating layer, buffer layer as a carrier potential barrier / valve, can alleviate the impact of OTS opening momentary surge current in gating layer on phase change storage layer, improve the durability and read interference resistance of phase change memory.

Description

Technical Field

[0001] This application relates to the field of phase-change memory technology, and more particularly to a phase-change memory. Background Technology

[0002] Phase-change memory (PCM) comprises word lines, bit lines, and memory cells coupled between the word lines and bit lines. Memory cells utilize the resistance changes of the phase-change material between different phases to store data. Applying a medium-width, low-amplitude current pulse to a memory cell switches it from a RESET state (amorphous, high-resistance state) to a SET state (crystalline, low-resistance state). Applying a short, strong current pulse switches it from a SET state to a RESET state. SET and RESET states store different data. Each memory cell includes a coupled phase-change storage layer and a gating layer. The phase-change storage layer, made of phase-change material, is used to store data. The gating layer includes an ovonic threshold switch (OTS). An OTS is a bidirectional nonlinear switching device that selects the memory cell. It conducts at high voltage, allowing current to flow through the selected memory cell; it cuts off at low voltage, preventing current from flowing through unselected cells, thus preventing crosstalk and write errors.

[0003] In related technologies, once the OTS is turned on, a relatively large surge current will be generated, which will impact the phase change memory layer and affect the working stability of the phase change memory. Summary of the Invention

[0004] This application provides a phase-change memory to at least partially solve the above-mentioned technical problems.

[0005] To achieve the above objectives, a phase-change memory is provided, comprising: A first conductive layer, a memory cell, and a second conductive layer are stacked along a first direction; the memory cell is coupled between the first conductive layer and the second conductive layer. The storage unit includes: a phase change storage layer, a gate layer, and a buffer layer stacked along the first direction; the buffer layer is located between the phase change storage layer and the gate layer, the relative permittivity of the buffer layer material is greater than or equal to 2.0, and the conductivity of the buffer layer is greater than... and less than .

[0006] In some embodiments, the storage cell further includes: a first electrode layer; the first electrode layer is located between the phase change storage layer and the gate layer; the first electrode layer includes a first layer and a second layer stacked along the first direction; and the buffer layer is located between the first layer and the second layer.

[0007] In some embodiments, the storage cell further includes: a first adhesive layer, a second adhesive layer, and a first electrode layer; the first adhesive layer is coupled to the phase change storage layer, the phase change storage layer is coupled to the buffer layer, the buffer layer is coupled to the second adhesive layer, the second adhesive layer is coupled to the first electrode layer, and the first electrode layer is coupled to the gate layer.

[0008] In some embodiments, the storage cell further includes: a first adhesive layer, a second adhesive layer, and a first electrode layer; the first adhesive layer is coupled to the phase change storage layer, the phase change storage layer is coupled to the second adhesive layer, the second adhesive layer is coupled to the buffer layer, the buffer layer is coupled to the first electrode layer, and the first electrode layer is coupled to the gate layer.

[0009] In some embodiments, the storage cell further includes: a first adhesive layer, a second adhesive layer, and a first electrode layer; the first adhesive layer is coupled to the phase change storage layer, the phase change storage layer is coupled to the second adhesive layer, the second adhesive layer is coupled to the first electrode layer, the first electrode layer is coupled to the buffer layer, and the buffer layer is coupled to the gate layer.

[0010] In some embodiments, the dimension of the buffer layer along the first direction is smaller than the thickness of the first electrode layer.

[0011] In some embodiments, the size of the buffer layer along the first direction is less than or equal to 3 nm.

[0012] In some embodiments, the bandgap of the material of the buffer layer is greater than or equal to 0.5 eV.

[0013] In some embodiments, the material of the buffer layer includes at least one of the following: AlN, TiN, TaN, AlON, , Nitrogen-doped aC, oxygen-doped aC, and silicon-doped aC.

[0014] In some embodiments, the phase change memory further includes a first electrode layer located between the phase change memory layer and the gating layer, wherein the material of the first electrode layer is aC.

[0015] The present application has the following beneficial effects: The phase change memory provided by the embodiments of the present application provides a buffer layer with a relatively large permittivity between the phase change memory layer and the gate layer. The buffer layer acts as a carrier barrier / valve, which can mitigate the impact of the surge current at the moment of OTS opening in the gate layer on the phase change memory layer, thereby improving the durability and read interference resistance of the phase change memory.

[0016] Other features and advantages of this application will be described in detail in the following detailed description section. Attached Figure Description To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0018] Figure 1 This is a schematic diagram of the structure of the phase-change memory provided in an exemplary embodiment of this disclosure; Figure 2 This is a schematic diagram of the structure of the phase-change memory provided in an exemplary embodiment of this disclosure; Figure 3 This is a schematic diagram of the structure of the phase-change memory provided in an exemplary embodiment of this disclosure; Figure 4 This is a schematic diagram of the structure of the phase-change memory provided in an exemplary embodiment of this disclosure; Figure 5 This is a schematic diagram of the structure of the phase-change memory provided in an exemplary embodiment of this disclosure; Figure 6 This is a schematic flowchart of a method for forming a phase-change memory provided in an exemplary embodiment of this disclosure.

[0019] Explanation of reference numerals in the attached figures: 1-First conductive layer; 2-Storage cell; 21-Phase change storage layer; 22-Gating layer; 23-Buffer layer; 24-First electrode layer; 241-First layer; 242-Second layer; 25-First adhesive layer; 26-Second adhesive layer; 27-Second electrode layer; 28-Third electrode layer; 3-Second conductive layer; Z-First direction. Detailed Implementation

[0020] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0021] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0022] In related technologies, the phase-change memory layer and the gate layer (including the OTS) are coupled. The inventors discovered that, from the perspective of band structure, the point of maximum bandgap in this structure is between the phase-change memory layer and the OTS (off state). Before the OTS in the gate layer is turned on, some charge carriers accumulate on both sides of the OTS due to the high potential barrier. At the instant the OTS is turned on, the potential barrier decreases, and the charge carriers surge through the OTS, forming an inrush current. This inrush current impacts the phase-change memory layer, affecting the operational stability of the phase-change memory.

[0023] The inventors discovered that the concept of a carrier buffer layer was validated in durability improvement experiments in FeFETs (ferroelectric field-effect transistors). FeFETs consist of a ferroelectric layer and a semiconductor channel. Through bandgap engineering, a buffer layer with strong charge storage capacity is inserted between the ferroelectric layer and the semiconductor channel to buffer the impact of additional charges on unselected cells. Introducing a buffer layer with a high dielectric constant into FeFETs effectively alleviates the accumulation of additional charges, improves the device's crosstalk immunity, and thus enhances the device's durability and consistency. Since ferroelectric memory devices are typically based on low-leakage capacitor structures, the buffer layer is usually in direct contact with the ferroelectric layer to improve its effectiveness. Furthermore, the inventors found that in phase-change memories (OTS), a strong inrush current is generated at the moment of OTS activation. For memory cells with low total resistance, they are prone to burnout during activation. Through bandgap structure analysis, the memory cell is in a high-resistivity state before OTS activation, similar to a capacitor, which generates a strong inrush current at the moment of activation. Electrodes with tungsten (W) are protected during the etching process, thus maintaining a narrow bandgap band structure, which leads to runaway surge current.

[0024] To address the technical problem that phase-change memory layers are easily impacted by surge currents, this application proposes a phase-change memory to overcome the aforementioned problem.

[0025] This application provides a phase-change memory, see the following embodiment. Figure 1 As shown, the phase-change memory includes: A first conductive layer 1, a storage cell 2, and a second conductive layer 3 are stacked along the first direction Z; the storage cell 2 is coupled between the first conductive layer 1 and the second conductive layer 3. Storage cell 2 includes: a phase change storage layer 21, a gate layer 22, and a buffer layer 23 stacked along a first direction Z; the buffer layer 23 is located between the phase change storage layer 21 and the gate layer 22, and the relative permittivity of the material of the buffer layer 23 is greater than or equal to 2.0, and the conductivity of the buffer layer 23 is greater than... and less than .

[0026] Through the above embodiments, a buffer layer 23 with a relatively high permittivity is provided between the phase change memory layer 21 and the gate layer 22. The buffer layer 23 acts as a carrier barrier / valve, mitigating the impact of the surge current during the OTS activation in the gate layer 22 on the phase change memory layer 21, thus improving the durability and read interference immunity of the phase change memory. Furthermore, the addition of the buffer layer 23 and the limitation of its conductivity range within a certain range... to This increases the overall resistance of memory cell 2, thus reducing the leakage current of memory cell 2. The addition of buffer layer 23 does not require additional architectural design, making it more flexible and applicable to a wider range of situations.

[0027] In some embodiments, the first conductive layer 1 includes word lines, and the second conductive layer 3 includes bit lines. Alternatively, the first conductive layer 1 includes bit lines, and the second conductive layer 3 includes word lines.

[0028] In some embodiments, the first conductive layer 1, the second conductive layer 3, and the peripheral control circuit are coupled together. The peripheral control circuit is used to apply voltage or current signals to the storage cell 2 through the first conductive layer 1 and the second conductive layer 3 to realize the switching of the storage cell 2 between the SET state and the RESET state.

[0029] In some embodiments, the material of the buffer layer 23 includes a first type of material. This first type of material has a relatively high permittivity and high conductivity, which can reduce the impact of adding the buffer layer 23 on the electrical characteristics of the storage cell 2, such as the voltage threshold Vt. The first type of material may include the materials shown in Table 1. The first type of material may include one material from Table 1 or a composite material formed from multiple materials from Table 1. Preferably, the first type of material includes at least one of the following: AlN (aluminum nitride), TiN (titanium nitride), TaN (tantalum nitride), AlON (aluminum oxynitride, aluminum oxynitride). (Tantalum pentoxide) (Titanium dioxide).

[0030] Table 1

[0031] In some embodiments, the relative permittivity and conductivity of the buffer layer 23 material are adapted to the memory cell array parameters through optimization of thickness and growth process (e.g., non-stoichiometry).

[0032] In some embodiments, see Figure 2 As shown, when the material of the buffer layer 23 includes the first type of material, the storage unit 2 further includes: a first electrode layer 24; the first electrode layer 24 is located between the phase change storage layer 21 and the gate layer 22; the first electrode layer 24 includes a first layer 241 and a second layer 242 stacked along the first direction Z; the buffer layer 23 is located between the first layer 241 and the second layer 242.

[0033] In some embodiments, the material of the first electrode layer 24 is aC (amorphous carbon).

[0034] In some embodiments, see Figure 2 As shown, when the material of the buffer layer 23 includes the first type of material, the storage unit 2 further includes: a second electrode layer 27 and a third electrode layer 28; the second electrode layer 27 is coupled to the first adhesive layer 25, and the third electrode layer 28 is coupled to the gate layer 22.

[0035] In some embodiments, see Figure 3 As shown, when the material of the buffer layer 23 includes the first type of material, the storage unit 2 further includes: a first adhesive layer 25, a second adhesive layer 26 and a first electrode layer 24; the first adhesive layer 25 is coupled to the phase change storage layer 21, the phase change storage layer 21 is coupled to the buffer layer 23, the buffer layer 23 is coupled to the second adhesive layer 26, the second adhesive layer 26 is coupled to the first electrode layer 24, and the first electrode layer 24 is coupled to the gate layer 22.

[0036] In some embodiments, see Figure 3 As shown, when the material of the buffer layer 23 includes the first type of material, the storage unit 2 further includes: a second electrode layer 27 and a third electrode layer 28; the second electrode layer 27 is coupled to the first adhesive layer 25, and the third electrode layer 28 is coupled to the gate layer 22.

[0037] In some embodiments, see Figure 4 As shown, when the material of the buffer layer 23 includes the first type of material, the storage unit 2 further includes: a first adhesive layer 25, a second adhesive layer 26 and a first electrode layer 24; the first adhesive layer 25 is coupled to the phase change storage layer 21, the phase change storage layer 21 is coupled to the second adhesive layer 26, the second adhesive layer 26 is coupled to the buffer layer 23, the buffer layer 23 is coupled to the first electrode layer 24, and the first electrode layer 24 is coupled to the gate layer 22.

[0038] In some embodiments, see Figure 4As shown, when the material of the buffer layer 23 includes the first type of material, the storage unit 2 further includes: a second electrode layer 27 and a third electrode layer 28; the second electrode layer 27 is coupled to the first adhesive layer 25, and the third electrode layer 28 is coupled to the gate layer 22.

[0039] In some embodiments, see Figure 5 As shown, when the material of the buffer layer 23 includes the first type of material, the storage unit 2 further includes: a first adhesive layer 25, a second adhesive layer 26 and a first electrode layer 24; the first adhesive layer 25 is coupled to the phase change storage layer 21, the phase change storage layer 21 is coupled to the second adhesive layer 26, the second adhesive layer 26 is coupled to the first electrode layer 24, the first electrode layer 24 is coupled to the buffer layer 23, and the buffer layer 23 is coupled to the gate layer 22.

[0040] In some embodiments, see Figure 5 As shown, when the material of the buffer layer 23 includes the first type of material, the storage unit 2 further includes: a second electrode layer 27 and a third electrode layer 28; the second electrode layer 27 is coupled to the first adhesive layer 25, and the third electrode layer 28 is coupled to the gate layer 22.

[0041] In some embodiments, the material of the buffer layer 23 includes a second type of material, which has a relatively high permittivity and high conductivity. The second type of material includes at least one of the following: nitrogen (N)-doped aC, oxygen (O)-doped aC, and silicon (Si)-doped aC. It should be noted that aC in this embodiment can also be replaced with other electrode materials further doped with at least one of oxygen (O), nitrogen (N), and silicon (Si) to form the second type of material. In some embodiments, see [reference needed]. Figure 2 As shown, when the material of the buffer layer 23 includes the second type of material, the storage unit 2 further includes: a first electrode layer 24; the first electrode layer 24 is located between the phase change storage layer 21 and the gate layer 22; the first electrode layer 24 includes a first layer 241 and a second layer 242 stacked along the first direction Z; the buffer layer 23 is located between the first layer 241 and the second layer 242.

[0042] In some embodiments, see Figure 2 As shown, when the material of the buffer layer 23 includes the second type of material, the storage unit 2 further includes: a second electrode layer 27 and a third electrode layer 28; the second electrode layer 27 is coupled to the first adhesive layer 25, and the third electrode layer 28 is coupled to the gate layer 22.

[0043] In some embodiments, see Figure 3As shown, when the material of the buffer layer 23 includes the second type of material, the storage unit 2 further includes: a first adhesive layer 25, a second adhesive layer 26 and a first electrode layer 24; the first adhesive layer 25 is coupled to the phase change storage layer 21, the phase change storage layer 21 is coupled to the buffer layer 23, the buffer layer 23 is coupled to the second adhesive layer 26, the second adhesive layer 26 is coupled to the first electrode layer 24, and the first electrode layer 24 is coupled to the gate layer 22.

[0044] In some embodiments, see Figure 3 As shown, when the material of the buffer layer 23 includes the second type of material, the storage unit 2 further includes: a second electrode layer 27 and a third electrode layer 28; the second electrode layer 27 is coupled to the first adhesive layer 25, and the third electrode layer 28 is coupled to the gate layer 22.

[0045] In some embodiments, see Figure 4 As shown, when the material of the buffer layer 23 includes the second type of material, the storage unit 2 further includes: a first adhesive layer 25, a second adhesive layer 26 and a first electrode layer 24; the first adhesive layer 25 is coupled to the phase change storage layer 21, the phase change storage layer 21 is coupled to the second adhesive layer 26, the second adhesive layer 26 is coupled to the buffer layer 23, the buffer layer 23 is coupled to the first electrode layer 24, and the first electrode layer 24 is coupled to the gate layer 22.

[0046] In some embodiments, see Figure 4 As shown, when the material of the buffer layer 23 includes the second type of material, the storage unit 2 further includes: a second electrode layer 27 and a third electrode layer 28; the second electrode layer 27 is coupled to the first adhesive layer 25, and the third electrode layer 28 is coupled to the gate layer 22.

[0047] In some embodiments, when the material of the buffer layer 23 includes a second type of material and the buffer layer 23 is located between the first layer 241 and the second layer 242, the material of the buffer layer 23 specifically includes at least one of nitrogen-doped aC, oxygen-doped aC, and silicon-doped aC.

[0048] In some embodiments, when the material of the buffer layer 23 includes a second type of material and the buffer layer 23 is located between the first electrode layer 24 and the second adhesive layer 26, the material of the buffer layer 23 specifically includes at least one of nitrogen-doped aC, oxygen-doped aC, and silicon-doped aC.

[0049] In some embodiments, where the material of the buffer layer 23 includes a second type of material and the buffer layer 23 is located between the phase change storage layer 21 and the second adhesion layer 26, the material of the buffer layer 23 specifically includes at least one of nitrogen-doped aC and silicon-doped aC.

[0050] Through the above embodiments, placing the buffer layer 23 between the phase-change storage layer 21 and the gate layer 22 can effectively form a carrier barrier inside the storage cell 2. This arrangement can directly buffer the influx of carriers at the moment the OTS is turned on, reducing inrush current and thus reducing the impact on the phase-change storage layer 21. At the same time, since the buffer layer 23 is located in the middle of the storage cell 2, its impact on the electrical characteristics of the entire storage cell 2 (such as the threshold voltage Vt) is small, and it can better maintain the original performance of the storage cell 2.

[0051] In some embodiments, the formation processes of the buffer layer 23 containing the first type of material and the buffer layer 23 containing the second type of material are different.

[0052] The formation process of the buffer layer 23 containing the first type of material includes thin film deposition processes, specifically including: chemical vapor deposition (CVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), molecular beam epitaxy (MBE), electron beam evaporation (EBE), and magnetron sputtering.

[0053] The process for forming the buffer layer 23 containing the second type of material includes a surface treatment process. The surface treatment process involves changing the outermost few atomic layers of the material itself (the existing substrate layer) into another phase or another composition through means such as ion / plasma bombardment, thereby changing the physical parameters of its surface, such as the relative permittivity, band gap, and conductivity, so as to transform its surface into the buffer layer 23.

[0054] In some embodiments, the dimension of the buffer layer 23 along the first direction Z is smaller than the thickness of the first electrode layer 24 (the dimension of the first electrode layer 24 along the first direction Z).

[0055] In some embodiments, the dimension of the buffer layer 23 along the first direction Z is less than or equal to 3 nm. If the dimension of the buffer layer 23 along the first direction Z is too large, the resistance of the buffer layer 23 will be too high, and the conductivity will be affected. When the buffer layer 23 contains a first type of material, the dimension of the buffer layer 23 along the first direction Z is preferably 1 nm. When the buffer layer 23 contains a second type of material, the dimension of the buffer layer 23 along the first direction Z is preferably 0.5 nm to 1 nm.

[0056] In some embodiments, the bandgap of the buffer layer 23 is greater than or equal to 0.5 eV. The bandgap refers to the energy difference between the top of the valence band and the bottom of the conduction band in a material. A buffer layer 23 with a large bandgap is less likely to excite electrons to transition from the valence band to the conduction band at room temperature, resulting in a lower free carrier concentration. Due to the low carrier concentration, the buffer layer 23 has lower conductivity and higher resistivity. By setting a larger bandgap in the buffer layer 23, an energy barrier is formed, hindering the free transport of carriers and slowing down the influx of carriers, thus reducing the surge current. Specifically, when the OTS is turned on, carriers need to overcome the barrier of the buffer layer 23 to enter the phase change storage layer 21, which slows down the influx of carriers and thus reduces the surge current.

[0057] In some embodiments, the storage cell 2 has a capacitor structure. By adjusting the parameters of the buffer layer 23, the capacitance of the storage cell 2 can be adjusted, thereby improving the RC delay of the storage cell 2. The time constant (τ) of the storage cell 2 is calculated using the following formula: τ = R × C, where R is the resistance value and C is the equivalent total capacitance value. It is generally considered that the charging power supply can be reached after 3τ to 5τ. Adding the buffer layer 23 to the storage cell 2 can be regarded as adding a new capacitor in series, reducing the equivalent total capacitance value of the storage cell 2, thereby reducing the time constant and improving the RC delay.

[0058] In some embodiments, the materials of the first conductive layer 1, the first adhesive layer 25, the second adhesive layer 26, and the second conductive layer 3 include tungsten (W).

[0059] In some embodiments, see Figure 6 As shown, this application proposes a method for forming a phase-change memory, comprising: S101: Form the first conductive layer 1; S102: Forming a memory cell 2 stacked with the first conductive layer 1 along the first direction Z. The memory cell 2 includes a phase change memory layer 21, a selection layer 22, and a buffer layer 23 stacked along the first direction Z. The buffer layer 23 is located between the phase change memory layer 21 and the selection layer 22. The relative permittivity of the material of the buffer layer 23 is greater than or equal to 2.0, and the conductivity of the buffer layer is greater than... and less than ; S103: A second conductive layer 3 is formed and stacked with the storage cell 2 along the first direction Z, and the storage cell 2 is coupled between the first conductive layer 1 and the second conductive layer 3.

[0060] In some embodiments, the material of the buffer layer 23 includes a first type of material, which includes at least one of the following: AlN, TiN, TaN, AlON, , The formation process of the buffer layer 23 obtained from the first type of material includes: chemical vapor deposition, atomic layer deposition, magnetron sputtering, pulsed laser deposition, molecular beam epitaxy, and electron beam evaporation.

[0061] In some embodiments, taking a 1 nm thick TiN buffer layer 23 as an example, the method for forming a phase change memory is specifically described as follows: A first conductive layer 1 is deposited, and a third electrode layer 28, a gate layer 22, and a first electrode layer 24 are sequentially deposited on the first conductive layer 1. After the first electrode layer 24 is deposited, the wafer is transferred to the atomic layer deposition equipment chamber, pre-vacuumed and temperature stabilized, and Ti and N chemical precursors are introduced using a carrier gas at 300°C for alternating deposition to grow a 1 nm thick TiN film as the buffer layer 23. Here, the carrier gas for each precursor enters the chamber in an independent pulse form. By controlling the flow rate and pulse frequency of the carrier gas carrying the two precursors respectively, the stoichiometry and growth rate of the film growth are adjusted. Then, the wafer is removed from the atomic layer deposition chamber and transferred to a second adhesion layer 26 deposition equipment under a nitrogen atmosphere for the deposition of the second adhesion layer 26. Then, the first adhesion layer 25, the second electrode layer 27, and the second conductive layer 3 of the phase change memory layer 21 are sequentially deposited.

[0062] In some embodiments, the material of the buffer layer 23 is a second type of material, which includes at least one of the following: nitrogen-doped aC, oxygen-doped aC, and silicon-doped aC; the process of forming the buffer layer 23 includes: bombarding the substrate layer with ions or plasma to form the buffer layer 23 on the surface of the substrate layer.

[0063] In some embodiments, where the buffer layer 23 comprises a second type of material, the second layer 242 can be used as a substrate layer. First, a first conductive layer 1 is formed, and a third electrode layer 28, a gate layer 22, and a second layer 242 are sequentially formed on the first conductive layer 1. The second layer 242 is bombarded with ions or plasma to transform the surface of the second layer 242 into a buffer layer 23. Then, a first layer 241, a second adhesive layer 26, a phase change storage layer 21, a first adhesive layer 25, and a second electrode layer 27 are sequentially formed on the buffer layer 23 to form a storage cell 2. A second conductive layer 3 is formed on the second electrode layer 27, and the storage cell 2 is coupled between the first conductive layer 1 and the second conductive layer 3.

[0064] In some embodiments, where the buffer layer 23 comprises a second type of material, the first electrode layer 24 can be used as a substrate layer. First, a first conductive layer 1 is formed, and a third electrode layer 28, a gate layer 22, and a first electrode layer 24 are sequentially formed on the first conductive layer 1. The first electrode layer 24 is bombarded with ions or plasma to transform the surface of the first electrode layer 24 into a buffer layer 23. Then, a second adhesion layer 26, a phase change storage layer 21, a first adhesion layer 25, and a second electrode layer 27 are sequentially formed on the buffer layer 23 to form a storage cell 2. A second conductive layer 3 is deposited on the second electrode layer 27, and the storage cell 2 is coupled between the first conductive layer 1 and the second conductive layer 3.

[0065] In some embodiments, where the buffer layer 23 comprises a second type of material, the second adhesive layer 26 can be used as a substrate layer. First, a first conductive layer 1 is formed, and a third electrode layer 28, a gate layer 22, a first electrode layer 24, and a second adhesive layer 26 are sequentially formed on the first conductive layer 1. The second adhesive layer 26 is bombarded with ions or plasma to transform the surface of the second adhesive layer 26 into the buffer layer 23. Then, a phase change storage layer 21, a first adhesive layer 25, and a second electrode layer 27 are sequentially formed on the buffer layer 23 to form a storage cell 2. A second conductive layer 3 is deposited on the second electrode layer 27, and the storage cell 2 is coupled between the first conductive layer 1 and the second conductive layer 3.

[0066] In some embodiments, taking nitrogen-doped aC as an example, the method for forming a phase change memory is specifically described as follows: A first conductive layer 1 is deposited, and a third electrode layer 28, a gate layer 22, and a first electrode layer 24 are sequentially deposited on the first conductive layer 1. After the first electrode layer 24 is deposited, the wafer is transferred to the nitrogen atmosphere treatment chamber of a magnetron sputtering apparatus. The 1 to 2 nm of aC oxidized on the surface is removed by ICP (inductively coupled plasma) backsputtering, and then backsputtering is stopped. The chamber is kept at an ambient temperature of 150°C, and a carrier gas containing 10% to 30% nitrogen is introduced to perform surface nitriding treatment for about 10 to 15 minutes. The wafer is then removed from the magnetron sputtering chamber and transferred to a second adhesion layer 26 deposition apparatus under a nitrogen atmosphere for the deposition of the second adhesion layer 26. Then, the first adhesion layer 25, the second electrode layer 27, and the second conductive layer 3 of the phase change memory layer 21 are sequentially deposited.

[0067] When the material of the buffer layer 23 includes the first type of material, the buffer layer 23 is formed using a thin film deposition process, which is suitable for scenarios requiring precise control of the dimensions and material properties of the buffer layer 23 along the first direction Z. When the material of the buffer layer 23 includes the second type of material, the buffer layer 23 is formed using a surface treatment process. This allows for rapid optimization of existing processes without changing the existing materials and structure, and rapid formation of the buffer layer 23, which is suitable for scenarios requiring minimal modification to the existing device structure.

[0068] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0069] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0070] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A phase-change memory, characterized in that, include: A first conductive layer (1), a memory cell (2), and a second conductive layer (3) are stacked along a first direction (Z); The storage unit (2) is coupled between the first conductive layer (1) and the second conductive layer (3); The storage unit (2) includes: a phase change storage layer (21), a gate layer (22), and a buffer layer (23) stacked along the first direction (Z); the buffer layer (23) is located between the phase change storage layer (21) and the gate layer (22), the material of the buffer layer (23) has a relative permittivity greater than or equal to 2.0, and the conductivity of the buffer layer is greater than... and less than .

2. The phase-change memory according to claim 1, characterized in that, The storage unit (2) further includes: a first electrode layer (24); the first electrode layer (24) is located between the phase change storage layer (21) and the gate layer (22); The first electrode layer (24) includes a first layer (241) and a second layer (242) stacked along the first direction (Z); The buffer layer (23) is located between the first layer (241) and the second layer (242).

3. The phase-change memory according to claim 1, characterized in that, The storage unit (2) further includes: a first adhesive layer (25), a second adhesive layer (26), and a first electrode layer (24); The first adhesive layer (25) is coupled to the phase change storage layer (21), the phase change storage layer (21) is coupled to the buffer layer (23), the buffer layer (23) is coupled to the second adhesive layer (26), the second adhesive layer (26) is coupled to the first electrode layer (24), and the first electrode layer (24) is coupled to the gate layer (22).

4. The phase-change memory according to claim 1, characterized in that, The storage unit (2) further includes: a first adhesive layer (25), a second adhesive layer (26), and a first electrode layer (24); The first adhesive layer (25) is coupled to the phase change storage layer (21), the phase change storage layer (21) is coupled to the second adhesive layer (26), the second adhesive layer (26) is coupled to the buffer layer (23), the buffer layer (23) is coupled to the first electrode layer (24), and the first electrode layer (24) is coupled to the gate layer (22).

5. The phase-change memory according to claim 1, characterized in that, The storage unit (2) further includes: a first adhesive layer (25), a second adhesive layer (26), and a first electrode layer (24); The first adhesive layer (25) is coupled to the phase change storage layer (21), the phase change storage layer (21) is coupled to the second adhesive layer (26), the second adhesive layer (26) is coupled to the first electrode layer (24), the first electrode layer (24) is coupled to the buffer layer (23), and the buffer layer (23) is coupled to the gate layer (22).

6. The phase-change memory according to any one of claims 2-5, characterized in that, The size of the buffer layer (23) along the first direction (Z) is smaller than the thickness of the first electrode layer (24).

7. The phase-change memory according to claim 6, characterized in that, The size of the buffer layer (23) along the first direction (Z) is less than or equal to 3 nm.

8. The phase-change memory according to any one of claims 2-5, characterized in that, The material of the buffer layer (23) has a band gap greater than or equal to 0.5 eV.

9. The phase-change memory according to claim 1, characterized in that, The material of the buffer layer (23) includes at least one of the following: AlN, TiN, TaN, AlON, , Nitrogen-doped aC, oxygen-doped aC, and silicon-doped aC.

10. The phase-change memory according to claim 9, characterized in that, The phase change memory further includes a first electrode layer (24) located between the phase change storage layer (21) and the gate layer (22), the material of the first electrode layer (24) being aC.

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