A method for manufacturing a deep trench capacitor structure

Abstract

The application discloses a preparation method of a deep trench capacitor structure, a deep trench capacitor and a semiconductor device. The method comprises the following steps: providing a semiconductor substrate formed with an N-type buried layer; performing ion implantation on the substrate to form a first doped region connected with the N-type buried layer; forming a first trench in the substrate, the first trench penetrating through the first doped region and the bottom of the first trench being located in the N-type buried layer; forming a first dielectric layer on the sidewall of the first trench; forming a first conductive layer on the first dielectric layer; forming at least one group of combined layers comprising a second dielectric layer and a second conductive layer on the second dielectric layer on the first conductive layer, and forming a capacitor structure in the first trench; the first doped region outside the sidewall of the first trench is connected with the first conductive layer at the bottom of the first trench through the N-type buried layer, and a lower plate via for connecting the first conductive layer and a metal layer is formed. The scheme provided by the application can form a lower plate via outside the sidewall of the first trench, and the process complexity is reduced.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing, specifically to a method for fabricating a deep trench capacitor structure, a deep trench capacitor, and a semiconductor device. Background Technology

[0002] DTC technology integrates large-capacity capacitors within a limited chip area by constructing capacitor structures within deep trenches, effectively supporting transient current response under high-frequency switching and improving power integrity. Currently, the formation of a DTC structure typically requires grinding a polysilicon layer, and during the grinding process, reserves must be made of polysilicon to form the upper and lower electrodes, increasing the complexity of the process. Summary of the Invention

[0003] This application provides a method for fabricating a deep trench capacitor structure, a deep trench capacitor, and a semiconductor device. It enables the formation of a lower electrode path connecting the first conductive layer and the metal layer on both sides of the first trench. This eliminates the need to reserve a conductive layer for the lower electrode when removing the conductive layer from the substrate surface, reducing process complexity. The specific solution is as follows: In a first aspect, embodiments of this application provide a method for fabricating a deep trench capacitor structure. The method includes: providing a semiconductor substrate in which an N-type buried layer is formed; performing ion implantation on the substrate to form a first doped region on the substrate, the first doped region being connected to the N-type buried layer; forming a first trench in the substrate, the first trench penetrating the first doped region and having its bottom located within the N-type buried layer; forming a first dielectric layer on the sidewall of the first trench; forming a first conductive layer on the first dielectric layer; forming at least one set of combined layers on the first conductive layer to form a capacitor structure located in the first trench, the combined layers including a second dielectric layer and a second conductive layer on the second dielectric layer; the first doped region on the outer sidewall of the first trench being connected to the first conductive layer at the bottom of the first trench through the N-type buried layer to form a lower electrode path for connecting the first conductive layer and a metal layer.

[0004] Optionally, forming a first dielectric layer on the sidewall of the first trench includes: forming a first dielectric layer on the sidewall of the first trench and at the bottom of the first trench; performing an etching step to remove the first dielectric layer at the bottom of the first trench until the N-type buried layer is exposed in the first trench.

[0005] Optionally, forming the first trench in the semiconductor substrate includes: forming a first oxide layer and a hard mask layer on the surface of the substrate; forming a first trench pattern on the hard mask layer by photolithography; and performing an etching step to form the first trench corresponding to the first trench pattern on the hard mask layer.

[0006] Optionally, forming the first conductive layer on the first dielectric layer includes: performing a furnace tube process to deposit the first conductive layer on the first dielectric layer in the first trench and on the surface of the hard mask layer on the substrate surface.

[0007] Optionally, forming at least one set of combined layers on the first conductive layer includes: performing an atomic layer deposition step to form a second dielectric layer on the first conductive layer; and performing a furnace tube process to deposit a second conductive layer on the second dielectric layer.

[0008] Optionally, after depositing the second conductive layer on the dielectric layer, the method further includes: removing the second conductive layer, the second dielectric layer, and the first conductive layer from the surface of the substrate until the substrate is exposed.

[0009] Optionally, after removing the second conductive layer, the second dielectric layer, and the first conductive layer from the substrate surface, the method further includes: forming an interlayer dielectric layer on the substrate surface; performing an etching step to form an upper electrode via for connecting the second conductive layer to a metal layer on the interlayer dielectric layer, and a lower electrode via for connecting the first conductive layer to a metal layer through the lower electrode via on the interlayer dielectric layer.

[0010] Optionally, the method further includes: forming a second trench for a deep trench isolation structure in the substrate while forming the first trench on the substrate; the depth of the first trench and the depth of the second trench are different.

[0011] Optionally, the method further includes: forming a first dielectric layer on the sidewall of the first trench while simultaneously forming a first dielectric layer on the sidewall of the second trench; and performing ion implantation on the substrate to form a second doped region at the bottom of the second trench.

[0012] Optionally, the method further includes: forming a first device and a second device in the two side regions of the second trench, wherein the first device and the second device are respectively a bipolar device, a CMOS device, and a DMOS device.

[0013] Optionally, forming a first dielectric layer on the sidewall of the first trench includes: performing a high-temperature thermal oxidation process or chemical vapor deposition to form a second oxide layer on the sidewall of the first trench, wherein the second oxide layer is the first dielectric layer.

[0014] Optionally, the step of performing a high-temperature thermal oxidation process to form a second oxide layer on the sidewall of the first trench includes: performing a high-temperature thermal oxidation process to form a third oxide layer on the wall of the first trench; removing the third oxide layer; and performing a high-temperature thermal oxidation process to form a second oxide layer on the sidewall of the first trench where the third oxide layer has been removed.

[0015] Secondly, embodiments of this application provide a deep trench capacitor structure, the deep trench capacitor structure comprising: a semiconductor substrate, wherein an N-type buried layer and a first doped region are formed in the substrate, the first doped region being connected to the N-type buried layer; a first trench is formed in the semiconductor substrate, penetrating the first doped region and having its bottom located in the N-type buried layer; a first dielectric layer is formed on the wall of the first trench; a deep trench capacitor structure is formed in the first trench, the deep trench capacitor structure comprising a first conductive layer formed on the first dielectric layer and connected to the N-type buried layer and at least one set of combined layers formed on the first conductive layer, the combined layers comprising a second dielectric layer and a second conductive layer on the second dielectric layer; the first doped region on the outer sidewall of the first trench is connected to the first conductive layer at the bottom of the first trench through the N-type buried layer, forming a lower electrode path for connecting the first conductive layer and a metal layer.

[0016] Thirdly, this application also provides a semiconductor device prepared by the method described in the first aspect of this application.

[0017] Compared with the prior art, this application has the following advantages: The method for fabricating a deep trench capacitor structure provided in this application includes the following steps: providing a semiconductor substrate in which an N-type buried layer is formed; performing ion implantation on the substrate to form a first doped region on the substrate, the first doped region being connected to the N-type buried layer; forming a first trench in the substrate, the first trench penetrating the first doped region and having its bottom located within the N-type buried layer; forming a first dielectric layer on the sidewall of the first trench; forming a first conductive layer on the first dielectric layer; forming at least one set of combined layers on the first conductive layer to form a capacitor structure located in the first trench, the combined layers including a second dielectric layer and a second conductive layer on the second dielectric layer; the first doped region on the outer sidewall of the first trench being connected to the first conductive layer at the bottom of the first trench through the N-type buried layer to form a lower electrode path for connecting the first conductive layer and a metal layer.

[0018] As can be seen, in the method provided in this application embodiment, since the first doped region is connected to the N-type buried layer and the bottom of the first trench is located in the N-type buried layer, after the first conductive layer is formed in the first trench, a lower electrode path located on the outer sidewall of the first trench can be formed, connecting the first conductive layer from the bottom of the first trench to the substrate surface. Thus, after the subsequent formation of the metal layer, the first conductive layer can be connected to the metal layer through the formed lower electrode path. Because the first conductive layer can be connected to the metal layer through the formed lower electrode path in this application embodiment, it is not necessary to predefine the area to be formed for the lower electrode and reserve a conductive layer for the lower electrode when subsequently removing the second conductive layer, the second dielectric layer, and the first conductive layer from the substrate surface. Therefore, the method for fabricating a deep trench capacitor structure provided in this application embodiment can form a lower electrode path connecting the first conductive layer and the metal layer on the outer sidewall of the first trench. Thus, when removing the conductive layer from the substrate surface, it is not necessary to reserve a conductive layer for the lower electrode, reducing process complexity. Attached Figure Description

[0019] Figure 1 This is a flowchart of the method for preparing the deep trench capacitor structure provided in the embodiments of this application.

[0020] Figure 2 This is a schematic diagram of the semiconductor substrate provided in the method for fabricating the deep trench capacitor structure provided in the embodiments of this application.

[0021] Figure 3 A schematic diagram of ion implantation of the substrate in the method for fabricating the deep trench capacitor structure provided in this application embodiment.

[0022] Figure 4 This is a schematic diagram of forming a trench structure on a substrate in the method for fabricating a deep trench capacitor structure provided in this application embodiment.

[0023] Figure 5 This is a schematic diagram of the formation of a third oxide layer on the inner wall of the first trench and the inner wall of the second trench in the method for preparing the deep trench capacitor structure provided in this application embodiment.

[0024] Figure 6 This is a schematic diagram of removing the third oxide layer from the inner wall of the first trench and the inner wall of the second trench in the method for preparing the deep trench capacitor structure provided in this application embodiment.

[0025] Figure 7 This is a schematic diagram of the formation of a second oxide layer on the inner wall of the first trench and the inner wall of the second trench in the method for preparing the deep trench capacitor structure provided in the embodiments of this application.

[0026] Figure 8This is a schematic diagram of removing the first dielectric layer at the bottom of the trench in the method for preparing the deep trench capacitor structure provided in this application embodiment.

[0027] Figure 9 This is a schematic diagram of ion implantation at the bottom of the trench in the deep trench capacitor structure provided in the embodiments of this application.

[0028] Figure 10 This is a schematic diagram of the formation of a first conductive layer on a first oxide layer in the method for preparing a deep trench capacitor structure provided in this application embodiment.

[0029] Figure 11 This is a schematic diagram of the formation of a second dielectric layer on the first conductive layer in the method for preparing a deep trench capacitor structure provided in this application embodiment.

[0030] Figure 12 This is a schematic diagram of the formation of a second conductive layer on the second dielectric layer in the method for preparing a deep trench capacitor structure provided in this application embodiment.

[0031] Figure 13 This is a schematic diagram of the removal of the second conductive layer, the first dielectric layer, and the first conductive layer in the preparation method of the deep trench capacitor structure provided in this application embodiment.

[0032] Figure 14 This is a schematic diagram of the interlayer dielectric layer formed on the substrate surface in the deep trench capacitor structure provided in the embodiments of this application.

[0033] Figure 15 This is a schematic diagram of the interlayer dielectric layer formed on the substrate surface in the deep trench capacitor structure provided in the embodiments of this application.

[0034] Figure 16 This is a schematic diagram of filling through holes in the method for preparing a deep trench capacitor structure provided in this application embodiment. Detailed Implementation

[0035] Many specific details are set forth in the following description to provide a full understanding of this application. However, this application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of this application; therefore, this application is not limited to the specific embodiments disclosed below.

[0036] It should be noted that the terms "first," "second," "third," etc., in the claims, specification, and drawings of this application are used to distinguish similar objects and are not used to describe a specific order or sequence. Such data are interchangeable where appropriate so that the embodiments of this application described herein can be implemented in a sequence other than that shown or described herein. Furthermore, the terms "comprising," "having," and their variations are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to these processes, methods, products, or apparatuses.

[0037] It should be understood that in the embodiments of this application, "at least one" means one or more, and "more than one" means two or more. "And / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. The character " / " generally indicates that the related objects before and after it are in an "or" relationship. "Contains A, B and / or C" means containing any one, two, or three of A, B, and C.

[0038] It should be understood that in the embodiments of this application, "B corresponding to A", "B corresponding to A", "A corresponds to B" or "B corresponds to A" means that B is associated with A, and B can be determined based on A. Determining B based on A does not mean that B is determined solely based on A; B can also be determined based on A and / or other information.

[0039] Based on the reasons mentioned in the background art, the first embodiment of this application provides a method for fabricating a deep trench capacitor structure, which can form a lower electrode path on both sides of the first trench. In this way, when removing the conductive layer on the substrate surface, there is no need to reserve a conductive layer for the lower electrode, thus reducing the complexity of the process.

[0040] The technical solution of this application will be described in detail below through specific embodiments. It should be noted that the following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.

[0041] The following, combined with Figures 1-16 This application describes a method for fabricating a deep trench capacitor structure according to embodiments of the present application.

[0042] like Figure 1 As shown, the method for fabricating the deep trench capacitor structure provided in this application includes the following steps S101 to S106.

[0043] Step S101: Provide a semiconductor substrate in which an N-type buried layer is formed.

[0044] In semiconductor manufacturing processes, a semiconductor substrate refers to the basic material used to fabricate semiconductor devices. Semiconductor substrates can include, but are not limited to, pure single-crystal silicon (Si), gallium arsenide (GaAs), gallium nitride (GaN), and silicon carbide (SiC). The material of the semiconductor substrate can be selected according to actual needs during the fabrication process. The substrate can be a P-type substrate, which refers to a semiconductor wafer material formed by doping single-crystal silicon with acceptor impurities (such as boron, gallium, etc.). Its majority carriers are holes, thus enabling the material to exhibit P-type conductivity (hole concentration > electron concentration). As the physical support and electrical foundation of the entire chip, the P-type substrate not only determines the doping polarity of subsequent epitaxial layers and well regions but also directly affects the isolation characteristics and breakdown voltage performance of the device.

[0045] The semiconductor substrate may include at least one N-type buried layer (NBL). The N-type buried layer is a high-concentration N-type doped region pre-formed on the surface of a P-type substrate. Specifically, the NBL region can be defined on the surface of the P-type substrate by photolithography, and formed by high-dose ion implantation of N-type impurities (such as arsenic (As) or antimony (Sb)) and high-temperature annealing. High-temperature annealing refers to the diffusion of implanted ions at a temperature of 1000–1200°C to form a deep junction (1–5 μm deep) and activate the impurities. In bipolar junction transistors (BJTs) or power MOSFETs, N-type buried layers, as low-resistance pathways with high concentrations of N-type doping, can effectively reduce the series resistance of the collector or drain, significantly improving current transfer efficiency and device performance. In CMOS processes, N-type buried layers can block the conduction path of parasitic PNP or NPN transistors composed of P-type substrates, N-wells, and P-wells, thereby suppressing latch-up and enhancing circuit reliability. In addition, N-type buried layers can also act as shielding, reducing substrate noise coupling and leakage current interference, and improving the stability and signal-to-noise ratio of analog or mixed-signal circuits.

[0046] In this embodiment, the N-type buried layer is used to connect with the first conductive layer in the first trench to be formed, thereby providing a basis for forming a lower electrode path from both sides of the first trench.

[0047] like Figure 2 The diagram shown is a schematic of the semiconductor substrate provided in the method for fabricating a deep trench capacitor structure according to an embodiment of this application. The semiconductor substrate may include a substrate layer 01 and an epitaxial layer 02. The substrate layer 01 includes at least one N-type buried layer 05. Figure 2(Example: A substrate comprising two N-type buried layers). The epitaxial layer 02 is located above the substrate layer 01, and the N-type buried layer 05 is located on the surface of the substrate layer 01 and is covered by the epitaxial layer 02.

[0048] An epitaxial layer is a new material layer with a specific doping concentration and crystal structure grown on a raw semiconductor substrate using epitaxy (Epi) technology. This process allows control over the composition, thickness, and doping type and concentration of the new layer, thereby achieving specific electrical properties. The epitaxial layer can be atomically matched to the substrate, forming a continuous crystal structure. The epitaxial layer can be the same material as the substrate (homogeneous epitaxy) or a different material (heterogeneous epitaxy). Specifically, the epitaxial layer can be silicon-based or silicon carbide-based.

[0049] After the epitaxial layer 02 is formed, a first oxide layer and a hard mask layer can be formed sequentially on the surface of the epitaxial layer 02 (i.e., on the surface of the substrate).

[0050] In practice, the first oxide layer 03 can be formed by performing a chemical vapor deposition (CVD) step and / or a thermal oxidation step. The thickness of the first oxide layer 03 can be between 50 Å and 150 Å, for example, the thickness of the first oxide layer 03 can be any one of 50 Å, 60 Å, 70 Å, 80 Å, 90 Å, 100 Å, 110 Å, 120 Å, 130 Å, 140 Å, 150 Å, etc. Thermal oxidation is a process of growing silicon dioxide by exposing the substrate to oxygen or water vapor in a high-temperature environment. Thermal oxidation includes dry oxidation and wet oxidation. Dry oxidation refers to using pure oxygen as an oxidant to generate a high-quality, dense oxide layer, while wet oxidation refers to using water vapor to react with silicon to generate an oxide layer. The growth rate of wet oxidation is faster than that of dry oxidation, but the oxide layer density is lower than that of dry oxidation. Chemical vapor deposition is a semiconductor manufacturing process in which a gaseous precursor undergoes a chemical reaction on a heated solid surface to generate a solid thin film, which is then deposited on a substrate.

[0051] After forming the first oxide layer 03, a hard mask layer 04 can be formed on the first oxide layer 03. In some examples, the thickness of the hard mask layer 04 can be between 100 Å and 800 Å. For example, the hard mask layer 04 can be any one of 100 Å, 150 Å, 200 Å, 250 Å, 300 Å, 350 Å, 400 Å, 450 Å, 500 Å, 550 Å, 600 Å, 750 Å, and 800 Å. The material of the hard mask layer 04 includes, but is not limited to, at least one of silicon nitride (Si3N4) hard mask layer, silicon dioxide (SiO2) hard mask layer, metal hard mask layer, and amorphous carbon hard mask layer. In this embodiment, silicon nitride is used as an example for the hard mask layer 04.

[0052] After forming the hard mask layer 04, its surface can be planarized. Specifically, an asher (lasma asher) can be used to lightly clean or activate the surface of the hard mask layer 04, or the surface can be ground to remove organic contaminants, improve photoresist adhesion, and provide a high-temperature resistant and etching-resistant hard mask layer 04 for subsequent deep trench lithography and etching.

[0053] Step S102: Ion implantation is performed on the substrate to form a first doped region on the substrate, and the first doped region is connected to the N-type buried layer.

[0054] This step is used to form a first doped region on the substrate that is connected to the N-type buried layer. This provides a basis for the subsequent formation of a lower electrode path on the outer side of the first trench sidewall.

[0055] like Figure 3 The diagram illustrates the ion implantation of a substrate in the fabrication method of the deep trench capacitor structure provided in this application embodiment. A layer of photoresist can be spin-coated onto the substrate surface, and the photoresist outside the first doped region to be formed can be removed to create an ion implantation window. Then, an N-type impurity (such as arsenic as) with a set dosage and energy is implanted. + Or antimony Sb + Ion implantation is performed on the substrate to allow the implanted ions to penetrate the epitaxial layer and reach the depth of the N-type buried layer 05, thus obtaining the first doped region 12. Afterwards, a high-temperature annealing process can be performed to activate the implanted impurities, causing the implanted first doped region 12 and the N-type buried layer to fuse into a continuous n-type buried layer under thermal diffusion. + Conductive pillar.

[0056] Step S103: A first trench is formed in the substrate, the first trench penetrating the first doped region and the bottom of the trench being located in the N-type buried layer.

[0057] This step is used to form deep trenches on the substrate for use as deep trench capacitor structures.

[0058] In a specific implementation, after forming the first oxide layer and the hard mask layer on the surface of the semiconductor substrate, a first trench pattern can be formed on the hard mask layer by photolithography; and an etching step can be performed to form the first trench corresponding to the first trench pattern on the hard mask layer.

[0059] In one alternative embodiment, while forming the first trench on the substrate, a second trench for a deep trench isolation structure is formed in the substrate; the depths of the first trench and the second trench are different.

[0060] The depths of the first trench and the second trench are different. For example, when the first trench is used to form a deep trench capacitor structure (DTC) and the second trench is used to form a deep trench isolation structure (DTI), the depth of the first trench is greater than the depth of the second trench.

[0061] In a specific implementation, the substrate may include at least one first region and at least one second region. The first region is for forming a first trench, and the second region is for forming a second trench. The first trench may be a trench for forming a deep trench capacitor (DTC), and the second trench may be a trench for forming a deep trench isolation (DTI). Devices may be pre-formed on the substrate before forming trenches in the first and second regions, or no devices may be formed on the substrate before forming trenches in the first and second regions.

[0062] In this embodiment, a photolithography process can be performed to form a first trench pattern and a second trench pattern in the first region and the second region, respectively. After forming a first oxide layer and a hard mask layer on the surface of the semiconductor substrate, a photolithography process is first performed to form the first trench pattern in the first region on the hard mask layer and the second trench pattern in the second region on the hard mask layer. First, a layer of photoresist with a thickness of approximately 3.6 μm is spin-coated onto the surface of the hard mask layer 04. Then, an exposure and development step is performed to define the first trench pattern of the first trench to be formed in the first region on the hard mask layer 04, and the second trench pattern of the second trench to be formed in the second region on the hard mask layer 04.

[0063] When the depth of the first trench to be formed is greater than the depth of the second trench to be formed, the width of the first trench pattern is greater than the width of the second trench pattern; when the depth of the first trench to be formed is less than the depth of the second trench to be formed, the width of the first trench pattern is greater than the width of the second trench pattern. In this embodiment, when forming the first trench pattern and the second trench pattern, a first etching rate for the first trench and a second etching rate for the second trench can be determined based on the depths of the first trench to be formed and the second trench to be formed, wherein the ratio of the first etching rate to the depth of the first trench is the same as the ratio of the second etching rate to the depth of the second trench. Thus, under the same etching environment and etching time, the time spent etching the first trench at the first etching rate and the time spent etching the second trench at the second etching rate are the same. Furthermore, the width of the first trench pattern and the width of the second trench pattern can be determined based on the first etching rate and the second etching rate. This allows for control of the first etching rate of the first trench and the second etching rate of the second trench by adjusting their widths. Specifically, the width of the trench pattern is proportional to the depth of the trench to be formed. If the depth of the first trench to be formed is greater than the depth of the second trench to be formed, then the width of the first trench pattern is greater than the width of the second trench pattern; conversely, if the depth of the first trench to be formed is less than the depth of the second trench to be formed, then the width of the first trench pattern is less than the width of the second trench pattern. For example, when the first trench is used to form a deep trench capacitor structure (DTC), the width of the corresponding first trench pattern can be approximately 1.5 μm; when the second trench is used to form a deep trench isolation structure (DTI), the width of the corresponding second trench pattern can be approximately 2.7 μm.

[0064] After forming a first trench pattern and a second trench pattern in the first region and the second region respectively, an etching process can be performed to simultaneously form a first trench corresponding to the first trench pattern and a second trench corresponding to the second trench pattern in the first region and the second region.

[0065] like Figure 4The diagram illustrates the formation of a trench structure on a substrate in the fabrication method of a deep trench capacitor structure provided in this application embodiment. Specifically, firstly, a layer of photoresist is spin-coated onto the surface of a hard mask layer 04. Then, an exposure and development step is performed, defining a first trench pattern for forming a first trench 06 in a first region on the hard mask layer 04 and a second trench pattern for forming a second trench 07 in a second region on the hard mask layer 04. Next, the hard mask layer 04 and the first oxide layer 03 are etched, forming etching windows in the first and second regions respectively. Using the remaining hard mask layer 04 as a barrier layer, the etching process continues through the etching windows onto the substrate, forming the first trench 06 and the second trench 07 on the substrate. In a specific implementation, a mixed gas of C4F8 (octafluorocyclobutane) and O2 (oxygen) can be used to perform reactive ion etching on the hard mask layer 04 and the first oxide layer 03, forming etching windows in the first region and the second region respectively; and a mixed gas of SF6 (sulfur hexafluoride) and O2 (oxygen) can be used to etch the substrate, simultaneously forming the first trench 06 and the second trench 07 on the substrate.

[0066] It should be noted that, in this application, the widths of the first and second trench patterns are determined based on the depths of the first and second trenches to be formed, and the width of the trench pattern is proportional to the trench depth. Therefore, when the depth of the first trench is less than the depth of the second trench, the width of the first trench pattern is also less than the width of the second trench pattern. Consequently, when an etching step is performed on the semiconductor substrate using the first and second trench patterns as etching windows, because the width of the first trench pattern is less than the width of the second trench pattern, the etching rate of the first trench is less than the etching rate of the second trench. Thus, within the same etching time, the depth of the first trench formed will be less than the depth of the second trench. This allows for the simultaneous formation of first and second trenches of different depths in the first and second regions of the substrate through a single etching process.

[0067] Step S103: Form a first dielectric layer on the sidewall of the first trench.

[0068] This step is used to form an isolation layer on the sidewall of the first trench, which is the first dielectric layer. The first dielectric layer may be an oxide layer.

[0069] Specifically, a high-temperature thermal oxidation process or chemical vapor deposition can be performed to form a second oxide layer on the sidewall of the first trench, and the second oxide layer serves as the first dielectric layer. The thickness of the second oxide layer is between 2000 Å and 6000 Å, for example, the thickness of the second oxide layer can be any one of 2000 Å, 2500 Å, 3000 Å, 3500 Å, 4000 Å, 4500 Å, 5000 Å, 5500 Å, 6000 Å, etc.

[0070] In one alternative embodiment, no device is formed on the substrate before the first oxide layer is formed on the first trench wall and the second trench wall, respectively. In this case, a high-temperature thermal oxidation process can be performed to form a second oxide layer on the first trench wall and the second trench wall, or a chemical vapor deposition process (such as high-density plasma-assisted chemical vapor deposition (HARP)) can be performed to form a second oxide layer on the first trench wall and the second trench wall; and the second oxide layer is used as the first dielectric layer.

[0071] Specifically, the formation of a second oxide layer on the first trench wall and the second trench wall by performing a high-temperature thermal oxidation process can be achieved through the following steps: first, perform a high-temperature thermal oxidation step to form a third oxide layer on the first deep trench wall and the second trench wall; then remove the third oxide layer; then perform a high-temperature thermal oxidation step again to form a second oxide layer on the first trench wall and the second trench wall where the third oxide layer has been removed.

[0072] This embodiment involves forming a thin third oxide layer on the inner walls of the first and second trenches before forming the second oxide layer. This third oxide layer is a temporary sacrificial oxide layer. The third oxide layer is then removed to repair etching damage to the first and second trench walls. The thickness of the third oxide layer is between 400 Å and 600 Å. For example, the thickness of the third oxide layer can be any one of 400 Å, 420 Å, 440 Å, 460 Å, 480 Å, 500 Å, 520 Å, 540 Å, 560 Å, 580 Å, or 600 Å.

[0073] The following combination Figures 5-7 The formation of the second oxide layer on the inner walls of the first and second trenches is described in detail. Figure 5 This is a schematic diagram illustrating the formation of a third oxide layer on the inner walls of the first and second trenches in the fabrication method of the deep trench capacitor structure provided in this application embodiment. Figure 6This is a schematic diagram illustrating the removal of the third oxide layer from the inner walls of the first and second trenches in the fabrication method of the deep trench capacitor structure provided in this application embodiment. Figure 7 This is a schematic diagram of the formation of a second oxide layer on the inner wall of the first trench and the inner wall of the second trench in the method for preparing the deep trench capacitor structure provided in the embodiments of this application.

[0074] like Figure 5 As shown, after simultaneously forming the first trench 06 and the second trench 07 on the substrate, a furnace tube process can be performed to grow a third oxide layer 08 on the sidewalls and bottom of the first trench 06 and the second trench 07 simultaneously through high-temperature thermal oxidation. Then, as... Figure 6 As shown, the third oxide layer 08 on the sidewalls and bottom of the first trench 06 and the second trench 07 can be removed using either dry etching or wet etching. When removing the third oxide layer 08 using wet etching, a solution such as HF (hydrofluoric acid) or DHF (diluted hydrofluoric acid) can be used. This repairs etching damage to the inner walls of the first trench 06 and the second trench 07, making the inner walls of the first trench 06 and the second trench 07 cleaner and smoother, providing a foundation for forming a high-quality second oxide layer on the inner walls of the first trench 06 and the second trench 07. Then, as... Figure 7 As shown, a furnace tube process can be performed to grow a second oxide layer 09 on the sidewall and bottom of the first trench 06 by high-temperature thermal oxidation, and simultaneously grow a second oxide layer 09 on the sidewall and bottom of the second trench 07.

[0075] In another alternative embodiment, a device is pre-formed on the substrate before the first oxide layer is formed on the first trench wall and the second trench wall, respectively. For example, a first device and a second device have already been formed on the substrate, and the second trench is located between the first device and the second device. In this case, a chemical vapor deposition process (such as high-density plasma-assisted chemical vapor deposition (HARP)) can be performed to form a second oxide layer on the first trench wall and the second trench wall.

[0076] It should be noted that the bottom of the first trench in this step will not include the first dielectric layer, so that the first conductive layer formed subsequently can form an electrical connection with the N-type buried layer.

[0077] In one specific implementation, a first dielectric layer can be formed on the sidewalls and bottom of the first trench; an etching step is then performed to remove the first dielectric layer at the bottom of the first trench until the N-type buried layer is exposed in the first trench. In another specific implementation, the first dielectric layer can be formed only on the sidewalls of the first trench, without forming a first dielectric layer at the bottom of the first trench, so that the N-type buried layer at the bottom of the first trench will not be covered by the first dielectric layer.

[0078] When the second trench is formed simultaneously with the first trench, a first dielectric layer can be formed simultaneously on the sidewalls and bottom of the first trench, and on the sidewalls and bottom of the second trench. Then, an etching step is performed to remove the first dielectric layer at the bottom of the first trench and the bottom of the second trench, exposing the N-type buried layer in the first trench. Alternatively, the first dielectric layer can be formed only on the sidewalls of the first trench and the second trench, without forming a first dielectric layer at the bottom of the first trench and the bottom of the second trench. In this case, the N-type buried layer at the bottom of the first trench will not be covered by the first dielectric layer.

[0079] like Figure 8 The diagram shown illustrates the removal of the first dielectric layer at the bottom of the trench in the fabrication method of the deep trench capacitor structure provided in this application embodiment. Taking silicon dioxide as the second oxide layer as an example, after forming the second oxide layer 09 (i.e., the first dielectric layer) in the first trench 06 and the second trench 07, a dry anisotropic etching process can be performed. An etching gas with a high selectivity for silicon dioxide (such as carbon tetrafluoride CF4 or octafluorocyclobutane C4F8) is used to remove the second oxide layer 09 formed at the bottom 10 of the first trench 06 and the second oxide layer 09 formed at the bottom 11 of the second trench 07. Anisotropy is a technique that primarily etches along the vertical direction. This allows for the removal of the second oxide layer 09 at the bottom of the first trench 06 and the second oxide layer 09 at the bottom of the second trench 07 while maintaining the second oxide layer 09 formed on the sidewalls of the first trench 06 and the second trench 07. In this case, when the second oxide layer 09 at the bottom of the first trench 06 is removed, the N-type buried layer 05 at the bottom of the first trench 06 will not be covered by the second oxide layer 09 (i.e., the first dielectric layer).

[0080] In an optional embodiment, when a first dielectric layer is formed on the sidewall of the first trench and a first dielectric layer is formed on the sidewall of the second trench simultaneously, ion implantation can also be performed on the substrate to form a second doped region at the bottom of the second trench. For example... Figure 9The diagram shows an ion implantation process at the bottom of the trench in a deep trench capacitor structure provided in this application embodiment. Ion implantation of the substrate forms a second doped region 21 at the bottom of the second trench 07. By forming the second doped region at the bottom of the second trench used to form the deep trench isolation structure, an N-type second doped region is formed at the bottom of the second trench, forming a PN junction with the P-type substrate. When a high voltage is applied to adjacent devices, this PN junction is typically in a reverse bias state, thereby regulating the electric field. Furthermore, the formed PN junction can prevent charge carriers from crossing the bottom of the trench, resulting in better isolation performance. Additionally, while performing ion implantation at the bottom of the second trench 07, ion implantation can also be performed simultaneously at the bottom of the first trench 06. This allows the formation of a high-concentration doped region at the bottom of the first trench 06. Subsequently, when forming the first conductive layer in the first trench, the first conductive layer connects to the high-concentration doped region, forming an N-type doped region. + –n + The homojunction improves the resistance at the contact point between the bottom first conductive layer and the highly doped region of the first trench 06, thereby optimizing the electrical performance.

[0081] Step S105: Form a first conductive layer on the first dielectric layer.

[0082] Step S106: Form at least one set of combined layers on the first conductive layer to form a capacitor structure located in the first trench, wherein the combined layer includes a second dielectric layer and a second conductive layer on the second dielectric layer.

[0083] Steps S105 and S106 are used to form a deep trench capacitor structure (DTC) in the first trench. The first trench, the first dielectric layer in the first trench, the first conductive layer on the first dielectric layer in the first trench, and the combined layer on the first conductive layer in the first trench together constitute the deep trench capacitor structure. It should be noted that when a second trench is also included on the substrate, steps S105 and S106 can also form a deep trench isolation structure (DTI) for deep trench isolation in the second trench. The second trench, the first dielectric layer in the second trench, the first conductive layer on the first dielectric layer in the second trench, and the combined layer on the first conductive layer in the second trench together constitute the deep trench isolation structure.

[0084] The number of combined layers in the deep trench capacitor structure (DTC) can be one, two, three, etc. For example, the deep trench capacitor structure (DTC) can be composed of a first trench, a first dielectric layer in the first trench, a first conductive layer on the first dielectric layer in the first trench, a second dielectric layer on the first conductive layer on the first dielectric layer in the first trench, and a second conductive layer on the second dielectric layer on the first conductive layer in the first trench; or, for example, the deep trench capacitor structure (DTC) can be composed of a first trench, a first dielectric layer in the first trench, a first conductive layer on the first dielectric layer in the first trench, a first second dielectric layer on the first conductive layer on the first dielectric layer in the first trench, a first second conductive layer on the first second dielectric layer, and a first second conductive layer on the first second dielectric layer. For example, the deep trench isolation structure may consist of a first trench, a first dielectric layer in the first trench, a first conductive layer on the first dielectric layer in the first trench, a first second dielectric layer on the first conductive layer on the first dielectric layer in the first trench, a first second dielectric layer on the first conductive layer on the first dielectric layer in the first trench, a first second conductive layer on the first conductive layer on the first dielectric layer in the first trench, a first second conductive layer on the first second dielectric layer, a second second dielectric layer on the first second conductive layer, a second second conductive layer on the second second dielectric layer, a third second dielectric layer on the second second conductive layer, and a third second conductive layer on the third second dielectric layer; and so on. For ease of explanation, this application embodiment uses a deep trench isolation structure consisting of a first trench, a first dielectric layer in the first trench, a first conductive layer on the first dielectric layer in the first trench, a second dielectric layer on the first conductive layer on the first dielectric layer in the first trench, and a second conductive layer on the second dielectric layer on the first conductive layer in the first trench as an example for detailed description.

[0085] Accordingly, the number of combined layers in the deep trench isolation structure can be one, two, three, etc. For example, the deep trench isolation structure is a structure composed of a second trench, a first dielectric layer in the second trench, a first conductive layer on the first dielectric layer in the second trench, a second dielectric layer on the first conductive layer on the first dielectric layer in the second trench, and a second conductive layer on the second dielectric layer on the first conductive layer in the second trench; or, for example, the deep trench isolation structure is a second trench, a first dielectric layer in the second trench, a first conductive layer on the first dielectric layer in the second trench, a first second dielectric layer on the first conductive layer on the first dielectric layer in the second trench, a first second conductive layer on the first second dielectric layer, and a first second conductive layer on the first second dielectric layer. The structure can be a second dielectric layer on an electrical layer and a second conductive layer on the second dielectric layer; for example, the deep trench isolation structure can be a second trench, a first dielectric layer in the second trench, a first conductive layer on the first dielectric layer in the second trench, a first second dielectric layer on the first conductive layer on the first dielectric layer in the second trench, a first second conductive layer on the first dielectric layer in the second trench, a first second conductive layer on the first dielectric layer, a second second dielectric layer on the first conductive layer, a second second conductive layer on the second dielectric layer, a third second dielectric layer on the second conductive layer, and a third second conductive layer on the third dielectric layer; etc. For ease of explanation, this application embodiment uses a deep trench isolation structure consisting of a second trench, a first dielectric layer in the second trench, a first conductive layer on the first dielectric layer in the second trench, a second dielectric layer on the first conductive layer on the first dielectric layer in the second trench, and a second conductive layer on the second dielectric layer on the first conductive layer in the second trench as an example for detailed description.

[0086] The following combination Figures 10-12 The formation of the deep trench capacitor structure and the deep trench isolation structure in the substrate is described in detail. Figure 10 This is a schematic diagram of the formation of a first conductive layer on the first oxide layer in the method for fabricating the deep trench capacitor structure provided in this application embodiment. Figure 11 This is a schematic diagram of the formation of a second dielectric layer on the first conductive layer in the method for fabricating a deep trench capacitor structure provided in this application embodiment. Figure 12 This is a schematic diagram of the formation of a second conductive layer on the second dielectric layer in the method for preparing a deep trench capacitor structure provided in this application embodiment.

[0087] like Figure 10As shown, after forming a second oxide layer 09 on the inner walls of the first trench 06 and the second trench 07, a furnace tube process can be performed on the semiconductor substrate to deposit a first conductive layer 15 on the second oxide layer 09 and on the surface of the hard mask layer 04 on the substrate surface. The material of the first conductive layer 15 can be polycrystalline silicon or a metal (such as titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), copper (Cu)). The thickness of the first conductive layer 15 is between 1500 Å and 2500 Å. For example, the thickness of the first conductive layer 15 can be any one of 1500 Å, 1600 Å, 1700 Å, 1800 Å, 1900 Å, 2000 Å, 2100 Å, 2200 Å, 2300 Å, 2400 Å, 2500 Å, etc. It should be noted that the thickness of the second oxide layer 09 between the first doped region 12 and the first conductive layer 15 is between 2000 Å and 6000 Å. Since the capacitance is inversely proportional to the thickness of the dielectric layer, when the thickness of the second oxide layer 09 (i.e., the dielectric layer) is large, the capacitance of the structure formed by the first doped region 12, the second oxide layer 09 and the first conductive layer 15 is very small and can be ignored. That is, the structure formed by the first doped region 12, the second oxide layer 09 and the first conductive layer 15 is not considered as a capacitor structure.

[0088] like Figure 11 As shown, after forming a first conductive layer 15 on the second oxide layer 09 and the surface of the hard mask layer 04 on the substrate surface, an atomic layer deposition step can be performed to form a second dielectric layer 16 on the first conductive layer 15. The second dielectric layer 16 can be a single-layer film (such as an oxide layer) or a composite film composed of an oxide layer and a high-dielectric-constant layer (high-k dielectric). The oxide layer can be silicon dioxide, and the high-dielectric-constant layer can be, but is not limited to, at least one of hafnium dioxide (HfO2), hafnium silicate (HfSiO4), zirconium oxide (ZrO2), and lanthanum oxide (La2O3). It should be noted that when the second dielectric layer 16 is a composite film layer, on the one hand, it can solve the quantum tunneling effect caused by the thinness of a single film layer (such as an oxide layer) being too small (such as less than 2nm), thus avoiding a sharp increase in gate leakage current; on the other hand, the oxide layer in the composite film layer is adjacent to the first conductive layer 15, which can prevent the interface roughness caused by the high dielectric constant layer directly contacting the first conductive layer 15 (such as polysilicon or metal).

[0089] like Figure 12As shown, after forming the second dielectric layer 16 on the first conductive layer 15, a furnace tube process can be performed to deposit a second conductive layer 17 on the second dielectric layer 16. That is, the second conductive layer 17 is filled on the second dielectric layer 16 in the first trench 06 and the second trench 07, and the second conductive layer 17 is formed on the second dielectric layer 16 on the surface of the substrate. Similar to the first conductive layer 15, the material of the second conductive layer 17 can be polycrystalline silicon or a metal (such as titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), copper (Cu)).

[0090] The first conductive layer 15 in the first trench 06 is the lower electrode of the deep trench capacitor structure (DTC) to be formed, and the second conductive layer 17 in the first trench 06 is the upper electrode of the deep trench capacitor structure (DTC) to be formed. Furthermore, the first conductive layer 15 in the first trench 06 is connected to the N-type buried layer 05, forming a lower electrode path located on both sides of the first trench 06, connecting the first conductive layer 15 to the surface of the epitaxial layer from the bottom of the first trench 06.

[0091] Furthermore, the deep trench capacitor structure fabrication method provided in this application simultaneously forms a deep trench isolation structure and a deep trench capacitor structure. Both the formed deep trench isolation structure and the deep trench capacitor structure include a first dielectric layer, a first conductive layer, a second dielectric layer, and a second conductive layer. The formed deep trench isolation structure can achieve electrical isolation between devices, and the formed deep trench capacitor structure can be used to construct high-density, high-performance on-chip capacitors. Therefore, the deep trench capacitor structure fabrication method provided in this application can simultaneously form a deep trench isolation structure and a deep trench capacitor structure on a substrate in a single process, effectively reducing the number of photolithography steps, lowering manufacturing costs and cycle time, simplifying process steps, and reducing process complexity. In addition, the collaborative design of the deep trench isolation structure and the deep trench capacitor structure in the fabrication method provided in this application can effectively utilize the vertical space of the chip, avoiding waste in planar layout (such as the combination of capacitors and isolation structures in DRAM), increasing chip density, and improving overall collaborative optimization.

[0092] Furthermore, the first doped region on the outer sidewall of the first trench is connected to the first conductive layer at the bottom of the first trench through the N-type buried layer, forming a lower electrode path for connecting the first conductive layer and the metal layer.

[0093] Since a lower electrode plate path is formed in the first trench in this embodiment, connecting the first conductive layer to the surface of the epitaxial layer from the bottom of the first trench, located on both sides of the first trench, the position above the lower electrode plate path can be used as the position of the lower electrode plate through hole for connecting the first conductive layer to the metal layer. In this way, when a lower electrode plate through hole connecting the lower electrode plate path and the metal layer is subsequently formed at the lower electrode plate through hole position, the first conductive layer can be connected to the metal layer through the lower electrode plate path and the lower electrode plate through hole position formed subsequently. Furthermore, the position above the second conductive layer can be used as the position of the upper electrode plate through hole for connecting the second conductive layer to the metal layer. Subsequently, an upper electrode plate through hole connecting the second conductive layer and the metal layer can be formed at the upper electrode plate through hole position, thereby providing a low-resistance and reliable external electrical connection path for the formed deep trench capacitor structure, enabling the deep trench capacitor structure to be integrated into the circuit and operate normally.

[0094] Furthermore, after depositing the second conductive layer on the second dielectric layer, the method for fabricating the deep trench capacitor structure provided in this application embodiment may further include the following steps: removing the second conductive layer, the second dielectric layer, and the first conductive layer from the substrate surface until the substrate is exposed. When a hard mask layer and a first oxide layer are formed on the substrate surface, the previously formed hard mask layer and the first oxide layer may also be removed simultaneously when removing the second conductive layer, the second dielectric layer, and the first conductive layer from the substrate surface, so that the lower electrode pathways on both sides of the first trench are exposed to the substrate surface.

[0095] like Figure 13 The diagram shown is a schematic of the removal of the second conductive layer, the first dielectric layer, and the first conductive layer in the fabrication method of the deep trench capacitor structure provided in this application embodiment. After filling the second conductive layer 17 on the second dielectric layer 16 in the first trench 06 and the second trench 07, and forming the second conductive layer 17 on the second dielectric layer 16 on the substrate surface, the second conductive layer 17, the second dielectric layer 16, the first conductive layer 15, the hard mask layer 04, and the first oxide layer 03 on the substrate surface can be removed by mechanical grinding or etching until the substrate is exposed (that is, the epitaxial layer 02 is exposed). In this way, the lower electrode passage on the outer sidewall of the first trench 06 is exposed to the substrate surface, providing a basis for the connection of the lower electrode.

[0096] Since a lower electrode plate passage is formed in the outer region of the sidewall of the first trench in this embodiment, when removing the second conductive layer, the second dielectric layer and the first conductive layer, it is not necessary to predefine the area to be formed of the lower electrode plate and reserve a conductive layer for the lower electrode plate, thus reducing the complexity of the process.

[0097] Furthermore, after removing the second conductive layer, the second dielectric layer, and the first conductive layer from the substrate surface, the method for fabricating the deep trench capacitor structure provided in this application embodiment may further include the following steps: forming an interlayer dielectric layer on the substrate surface; performing an etching step to form an upper electrode via for connecting the second conductive layer to a metal layer on the interlayer dielectric layer, and forming a lower electrode via for connecting the first conductive layer to a metal layer through the lower electrode via on the interlayer dielectric layer.

[0098] This step is used to form an interlayer dielectric layer, an upper electrode via, and a lower electrode via on the substrate surface. The formed interlayer dielectric layer can provide electrical isolation between multilayer metal interconnects, realize via connection, and reduce parasitic capacitance. The formed upper electrode via can connect the second conductive layer in the first trench to the metal layer subsequently formed on the surface of the interlayer dielectric layer. The formed lower electrode via can connect the first conductive layer in the first trench to the metal layer subsequently formed on the surface of the interlayer dielectric layer through the lower electrode via located on the outer sidewall of the first trench.

[0099] like Figure 14 The diagram shown is a schematic of the formation of an interlayer dielectric layer on the substrate surface in the deep trench capacitor structure provided in this application embodiment. After removing the second conductive layer 17, the second dielectric layer 16, the first conductive layer 15, the hard mask layer 04, and the first oxide layer 03 on the substrate surface, chemical vapor deposition or plasma-enhanced tetraethyl orthosilicate CVD (PECVD TEOS) can be performed to form an interlayer dielectric layer 18 (ILD (Interlayer Dielectric)). The interlayer dielectric layer refers to an insulating material (such as silicon dioxide, silicon nitride, or a low dielectric constant material) deposited between metal interconnect layers or between a metal and a device after the front-end process of the semiconductor device is completed. It is used to achieve electrical isolation between different conductive layers and prevent short circuits and crosstalk.

[0100] It should be noted that the substrate surface may not be smooth before the interlayer dielectric layer is deposited. In order to fully cover the uneven structure of the substrate surface, a relatively thick initial interlayer dielectric layer is usually deposited (e.g., the thickness of the initial interlayer dielectric layer is between 8000 Å and 15000 Å, for example, the thickness of the initial interlayer dielectric layer can be any one of 8000 Å, 8500 Å, 9000 Å, 9500 Å, 10000 Å, 10500 Å, 11000 Å, 11500 Å, 12000 Å, 12500 Å, 13000 Å, 14500 Å, 15000 Å, etc.). If the deposited interlayer dielectric layer is larger than a preset thickness (e.g., the preset thickness is between 4000 Å and 6000 Å, such as any one of 4000 Å, 4200 Å, 4400 Å, 4600 Å, 4800 Å, 5000 Å, 5200 Å, 5400 Å, 5600 Å, 5800 Å, 6000 Å, etc.), then the interlayer dielectric layer can be planarized (e.g., mechanically polished) until its thickness reaches the preset thickness. On one hand, planarizing the interlayer dielectric layer ensures a smooth surface, providing a flat substrate for the next photolithography step; on the other hand, maintaining the interlayer dielectric layer at the preset thickness avoids excessive stacking and difficulties in subsequent via etching.

[0101] like Figure 15 The diagram shows a schematic of an interlayer dielectric layer formed on the substrate surface in a deep trench capacitor structure provided in this application embodiment. After forming the interlayer dielectric layer 18 on the substrate surface, an upper electrode via 19 for connecting the second conductive layer 17 in the first trench 06 to the surface of the interlayer dielectric layer 18, and a lower electrode via 20 for connecting the first conductive layer 15 to the surface of the interlayer dielectric layer 18 through a lower electrode passage located outside the sidewall of the first trench, are formed in the interlayer dielectric layer 18. Thus, after a metal layer is subsequently formed on the surface of the interlayer dielectric layer 18, the connection between the second conductive layer 17 and the metal layer can be achieved through the upper electrode via 19, and the connection between the first conductive layer 15 and the metal layer can be achieved through the lower electrode via 20.

[0102] Subsequently, the through holes in the upper and lower electrode plates can be filled to form conductive channels. For example... Figure 16 The diagram shown illustrates the filling of through-holes in the fabrication method of the deep trench capacitor structure provided in this application embodiment. Conductive materials can be filled into the through-holes 19 of the upper electrode plate and 20 of the lower electrode plate to form conductive channels. The conductive materials may include, but are not limited to, tungsten (W), copper (Cu), etc.

[0103] It should be noted that, in this embodiment of the application, before devices are formed on both sides of the second trench, a first device and a second device can be formed respectively on both sides of the second trench. The first device and the second device can be devices among BCD devices. For example, the first device is one of Bipolar Transistor, CMOS, and DMOS among BCD devices, and the second device is one of other devices among Bipolar Transistor, CMOS, and DMOS among BCD devices besides the first device. In this way, the first device and the second device can be isolated by the deep trench isolation structure formed by the second trench.

[0104] The method for fabricating a deep trench capacitor structure provided in this application includes the following steps: providing a semiconductor substrate in which an N-type buried layer is formed; performing ion implantation on the substrate to form a first doped region on the substrate, the first doped region being connected to the N-type buried layer; forming a first trench in the substrate, the first trench penetrating the first doped region and having its bottom located within the N-type buried layer; forming a first dielectric layer on the sidewall of the first trench; forming a first conductive layer on the first dielectric layer; forming at least one set of combined layers on the first conductive layer to form a capacitor structure located in the first trench, the combined layers including a second dielectric layer and a second conductive layer on the second dielectric layer; the first doped region on the outer sidewall of the first trench being connected to the first conductive layer at the bottom of the first trench through the N-type buried layer to form a lower electrode path for connecting the first conductive layer and a metal layer.

[0105] As can be seen, in the method provided in this application embodiment, since the first doped region is connected to the N-type buried layer and the bottom of the first trench is located in the N-type buried layer, after the first conductive layer is formed in the first trench, a lower electrode path located on the outer sidewall of the first trench can be formed, connecting the first conductive layer from the bottom of the first trench to the substrate surface. Thus, after the subsequent formation of the metal layer, the first conductive layer can be connected to the metal layer through the formed lower electrode path. Because the first conductive layer can be connected to the metal layer through the formed lower electrode path in this application embodiment, it is not necessary to predefine the area to be formed for the lower electrode and reserve a conductive layer for the lower electrode when subsequently removing the second conductive layer, the second dielectric layer, and the first conductive layer from the substrate surface. Therefore, the method for fabricating a deep trench capacitor structure provided in this application embodiment can form a lower electrode path connecting the first conductive layer and the metal layer on the outer sidewall of the first trench. Thus, when removing the conductive layer from the substrate surface, it is not necessary to reserve a conductive layer for the lower electrode, reducing process complexity.

[0106] A second embodiment of this application provides a deep trench capacitor structure, comprising: a semiconductor substrate, wherein an N-type buried layer and a first doped region are formed in the substrate, the first doped region being connected to the N-type buried layer; a first trench is formed in the semiconductor substrate, penetrating the first doped region and with its bottom located in the N-type buried layer; a first dielectric layer is formed on the wall of the first trench; a deep trench capacitor structure is formed in the first trench, the deep trench capacitor structure including a first conductive layer formed on the first dielectric layer and connected to the N-type buried layer, and at least one set of combined layers formed on the first conductive layer, the combined layers including a second dielectric layer and a second conductive layer on the second dielectric layer; the first doped region on the outer sidewall of the first trench is connected to the first conductive layer at the bottom of the first trench through the N-type buried layer, forming a lower electrode path for connecting the first conductive layer and a metal layer. For details regarding the deep trench capacitor structure provided in the second embodiment of this application, please refer to the detailed description of the fabrication method of the deep trench capacitor structure provided in the first embodiment of this application, which will not be repeated here.

[0107] The third embodiment of this application provides a semiconductor device, which can be prepared by the method for preparing a deep trench capacitor structure provided in the first embodiment of this application. For details, please refer to the detailed description of the method for preparing a deep trench capacitor structure provided in the first embodiment of this application, which will not be repeated here.

[0108] Although this application discloses preferred embodiments as described above, it is not intended to limit this application. Any person skilled in the art can make possible changes and modifications without departing from the spirit and scope of this application. Therefore, the scope of protection of this application should be determined by the scope defined in the claims of this application.

Claims

1. A method for fabricating a deep trench capacitor structure, characterized in that, The method includes: A semiconductor substrate is provided, wherein an N-type buried layer is formed therein; Ion implantation is performed on the substrate to form a first doped region on the substrate, and the first doped region is connected to the N-type buried layer; A first trench is formed in the substrate, the first trench penetrating the first doped region and having its bottom located in the N-type buried layer; A first dielectric layer is formed on the sidewall of the first trench; A first conductive layer is formed on the first dielectric layer; At least one set of combined layers is formed on the first conductive layer to form a capacitor structure located in the first trench, wherein the combined layer includes a second dielectric layer and a second conductive layer on the second dielectric layer; The first doped region on the outer sidewall of the first trench is connected to the first conductive layer at the bottom of the first trench through the N-type buried layer, forming a lower electrode path for connecting the first conductive layer and the metal layer.

2. The method according to claim 1, characterized in that, The formation of a first dielectric layer on the sidewall of the first trench includes: A first dielectric layer is formed on the sidewall of the first trench and at the bottom of the first trench; An etching step is performed to remove the first dielectric layer at the bottom of the first trench until the N-type buried layer is exposed in the first trench.

3. The method according to claim 1, characterized in that, The formation of the first trench in the semiconductor substrate includes: A first oxide layer and a hard mask layer are formed on the surface of the substrate; The first trench pattern is formed on the hard mask layer by photolithography. An etching step is performed to form the first trench corresponding to the first trench pattern on the hard mask layer.

4. The method according to claim 3, characterized in that, The step of forming a first conductive layer on the first dielectric layer includes: Perform a furnace tube process to deposit a first conductive layer on the first dielectric layer in the first trench and on the surface of the hard mask layer on the substrate surface.

5. The method according to claim 4, characterized in that, The formation of at least one set of combined layers on the first conductive layer includes: An atomic layer deposition step is performed to form a second dielectric layer on the first conductive layer; Perform furnace tube process to deposit a second conductive layer on the second dielectric layer.

6. The method according to claim 1, characterized in that, After depositing a second conductive layer on the dielectric layer, the method further includes: Remove the second conductive layer, the second dielectric layer, and the first conductive layer from the surface of the substrate until the substrate is exposed.

7. The method according to claim 6, characterized in that, After removing the second conductive layer, the second dielectric layer, and the first conductive layer from the surface of the substrate, the method further includes: An interlayer dielectric layer is formed on the surface of the substrate; An etching step is performed to form an upper electrode via on the interlayer dielectric layer for connecting the second conductive layer to the metal layer, and a lower electrode via on the interlayer dielectric layer for connecting the first conductive layer to the metal layer through the lower electrode via.

8. The method according to claim 1, characterized in that, The method further includes: While the first trench is formed on the substrate, a second trench for a deep trench isolation structure is formed in the substrate; the depth of the first trench and the depth of the second trench are different.

9. The method according to claim 8, characterized in that, The method further includes: While forming a first dielectric layer on the sidewall of the first trench, a first dielectric layer is also formed on the sidewall of the second trench; Ion implantation is performed on the substrate to form a second doped region at the bottom of the second trench.

10. The method according to claim 8, characterized in that, The method further includes: A first device and a second device are formed on both sides of the second trench, respectively. The first device and the second device are one of bipolar devices, CMOS devices, and DMOS devices.

11. The method according to claim 1, characterized in that, A first dielectric layer is formed on the sidewall of the first trench, comprising: A high-temperature thermal oxidation process or chemical vapor deposition is performed to form a second oxide layer on the sidewall of the first trench, wherein the second oxide layer is the first dielectric layer.

12. The method according to claim 11, characterized in that, The step of performing a high-temperature thermal oxidation process to form a second oxide layer on the sidewall of the first trench includes: A high-temperature thermal oxidation process is performed to form a third oxide layer on the wall of the first trench; Remove the third oxide layer; A high-temperature thermal oxidation process is performed to form a second oxide layer on the sidewall of the first trench where the third oxide layer has been removed.

13. A deep trench capacitor structure, characterized in that, The deep trench capacitor structure includes: A semiconductor substrate having an N-type buried layer and a first doped region formed therein, the first doped region being connected to the N-type buried layer; A first trench is formed in the semiconductor substrate, penetrating the first doped region and with its bottom located in the N-type buried layer; A first dielectric layer is formed on the wall of the first trench; A deep trench capacitor structure is formed in the first trench. The deep trench capacitor structure includes a first conductive layer formed on the first dielectric layer and connected to the N-type buried layer, and at least one set of combined layers formed on the first conductive layer. The combined layer includes a second dielectric layer and a second conductive layer on the second dielectric layer. The first doped region on the outer sidewall of the first trench is connected to the first conductive layer at the bottom of the first trench through the N-type buried layer, forming a lower electrode path for connecting the first conductive layer and the metal layer.

14. A semiconductor device, characterized in that, It is prepared by the method described in any one of claims 1 to 12.

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