A short-circuit controllable semiconductor device structure and manufacturing process

Abstract

The application provides a short-circuit controllable semiconductor device structure and manufacturing process, relates to the fields of semiconductor device manufacturing and power electronics, and comprises a silicon substrate which is an N-type silicon material and is used for carrying a device structure to form a carrier transport channel, a carrier storage layer which is used for adjusting a carrier transport path and limiting a short-circuit current peak value, a trench gate structure which comprises a trench, a gate oxide layer and a polysilicon gate electrode, a P-well region which is used for forming a channel control region on both sides of the trench gate structure, and an N-well region which is used for adjusting minority carrier injection and forms a symmetrical matching relationship with the P-well region. The short-circuit controllable semiconductor device structure and manufacturing process realize longitudinal concentration control of the carrier storage layer by adopting a multiple ion implantation method and accurately controlling implantation energy and dopant dosage, adjust the carrier transport path, limit the short-circuit current peak value, and improve the performance of the semiconductor device.

Description

Technical Field

[0001] This invention relates to the fields of semiconductor device manufacturing and power electronics technology, specifically to a short-circuit controllable semiconductor device structure and manufacturing process. Background Technology

[0002] Insulated Gate Bipolar Transistor It is one of the core components of modern power electronic systems, possessing both high input impedance and low conduction loss characteristics, and is widely used in motor drives, energy conversion, and high-frequency switching. With the continuous increase in application power levels, short-circuit withstand capability has become a crucial metric for performance evaluation. Key indicators of safety and reliability. In the event of a short-circuit fault, the device must withstand current surges several times its rated value within microseconds and safely shut off to prevent thermal runaway or burnout. Existing designs generally improve short-circuit performance by optimizing trench structures, adjusting carrier concentration distribution, or employing external drive circuits. This design utilizes a multi-layer injection structure to form a carrier storage layer, achieving transient protection by limiting peak current. A two-stage drive strategy is employed to control the gate voltage, achieving limited short-circuit delay turn-off.

[0003] However, existing technologies still have significant shortcomings: short-circuit performance control methods rely on fixed structural parameters and external driving logic, making it impossible to achieve dynamic matching under different application scenarios. When the system operates in a high-voltage converter or low-voltage frequency converter environment, the optimal requirements for device short-circuit capability differ significantly. Traditional designs use a uniform threshold voltage and a fixed carrier injection concentration, resulting in an unavoidable trade-off between on-state voltage drop, switching speed, and short-circuit withstand capability. Excessively increasing short-circuit capability leads to increased conduction losses and response delay, while reducing short-circuit capability causes the device to lose its safety margin under fault conditions. This fixed design makes it difficult to balance high efficiency and high reliability, resulting in low performance utilization of power devices under various operating conditions, thus restricting the overall safety and energy efficiency improvement of the system. Summary of the Invention

[0004] To address the shortcomings of existing technologies, this invention provides a short-circuit controllable semiconductor device structure and manufacturing process. The technical problem this invention aims to solve is how to address the issues of excessive short-circuit current peak and inflexible carrier transport path adjustment in semiconductor devices through multiple ion implantation and segmented P-trap ion implantation techniques.

[0005] To achieve the above objectives, the present invention provides the following technical solution: a short-circuit controllable semiconductor device structure, comprising:

[0006] A silicon substrate, wherein the silicon substrate is an N-type silicon material, is used to support the device structure and form a carrier transport channel;

[0007] The carrier storage layer is used to regulate carrier transport paths and limit short-circuit current peaks.

[0008] A trench gate structure, wherein the trench gate structure includes trenches, a gate oxide layer, and a polysilicon gate electrode;

[0009] The P-well region is used to form a channel control region on both sides of the trench gate structure;

[0010] The N-well region is used to regulate minority carrier injection, and the N-well region forms a symmetrical matching relationship with the P-well region.

[0011] Preferably, the carrier storage layer has a doping concentration decreasing in the depth direction, and the P-well region adopts a segmented ion implantation structure.

[0012] A short-circuit controllable semiconductor device manufacturing process, comprising:

[0013] S1. Provide an N-type silicon substrate, and perform multiple ion implantations on the N-type silicon substrate to form a carrier storage layer, wherein the multiple ion implantations are performed using a multi-energy ion implantation method.

[0014] S2. Trench gate structure is formed by etching trenches on the surface of the N-type silicon substrate. The trench gate structure includes trenches, gate oxide layer and polysilicon gate electrode.

[0015] S3. P-type doped regions are formed by implantation definition on both sides of the trench gate structure. The P-type doped regions are then segmented by P-well ion implantation to form a multi-segment threshold voltage distribution. The segmented P-well ion implantation adopts a layout partitioning design.

[0016] S4. N-well ion implantation is performed above the P-well region to form an emission region;

[0017] S5. The surface of the N-type silicon substrate is divided into multiple cell layouts and metallized to form a multiple cell structure array. Based on the multiple cell structure array, photolithography is performed to form cell regions. The cell regions are then subjected to terminal metal interconnect processing to form a semiconductor device structure. The terminal metal interconnect processing includes interlayer dielectric deposition, contact hole etching, and metal electrode deposition.

[0018] Preferably, the multi-energy ion implantation method achieves depth concentration control by controlling the implantation energy and dopant dosage, wherein the implantation energy ranges from [specific range to be filled in]. The concentration range of the doping dose is: .

[0019] Preferably, the trench depth of the trench grid structure is The groove spacing of the grooved grid structure is The thickness range of the gate oxide layer is The thickness of the polycrystalline silicon gate electrode is Resistivity The polycrystalline silicon gate electrode is made of phosphorus-doped polycrystalline silicon material.

[0020] Preferably, the implantation definition process employs photolithographic mask ion implantation, and the activation temperature of the implantation definition process is [temperature value missing]. The depth of the P-well doped region is The threshold voltage difference range of the segmented P-trap ion implantation is [range missing]. The layout partitioning design is based on the trench gate structure to partition the area, and the photolithography mask layer is divided based on the partitioning to form the multi-segment threshold voltage distribution.

[0021] Preferably, the N-well ion implantation employs a multi-level implantation method, which includes two-stage energy implantation and three-stage energy implantation. The range of the two-stage energy implantation is... The third-level energy injection is based on the two-level energy injection, with the addition of an intermediate energy injection, the range of which is... The dose range of the N-trap ion implantation is .

[0022] Preferably, the multi-cell layout is divided using insulating isolation strips, and the width of the insulating isolation strips is [missing information]. The metallization process includes depositing a first metal layer and a second metal layer. The first metal layer is a titanium and titanium-nitrogen alloy layer, and the second metal layer is an aluminum and copper layer. The cell size of the multi-cell structure array is... The photolithography division adopts a double-layer mask alignment method, the interlayer dielectric deposition adopts plasma-enhanced chemical vapor deposition, the contact hole etching adopts reactive ion etching, and the metal electrode deposition adopts sputtering deposition.

[0023] This invention provides a short-circuit controllable semiconductor device structure and manufacturing process. It offers the following advantages:

[0024] This short-circuit controllable semiconductor device structure and manufacturing process, by employing multiple ion implantation methods and precisely controlling the implantation energy and doping dosage, achieves depth concentration control of the carrier storage layer, adjusts the carrier transport path, limits the peak short-circuit current, and improves the performance of the semiconductor device.

[0025] By employing segmented P-well ion implantation and multi-level N-well ion implantation techniques, a multi-segment threshold voltage distribution was formed, which modulated minority carrier implantation and optimized the emission region performance. Precisely designed trench gate structures and multi-cell arrays enhanced the device's controllability and stability. Attached Figure Description

[0026] Figure 1 This is a schematic diagram of the semiconductor device structure of the present invention;

[0027] Figure 2 This is a flowchart of the manufacturing process of the present invention;

[0028] Figure 3 This is a schematic diagram of the trench grid structure and well layout of the present invention;

[0029] Figure 4 A schematic diagram of the stripe interlacing distribution in a multi-threshold voltage region;

[0030] Figure 5 A schematic diagram of the longitudinal stripe distribution in the multi-threshold voltage region;

[0031] Figure 6 A schematic diagram of the staggered distribution of diagonal stripes in a multi-threshold voltage region;

[0032] Figure 7 A schematic diagram of the checkerboard-like distribution of multiple threshold voltage regions;

[0033] Figure 8 This is a schematic diagram of the periodic alternating distribution of multiple threshold voltage regions. Detailed Implementation

[0034] The technical solutions in the embodiments of the present invention have been clearly and completely described. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0035] Example 1

[0036] like Figure 1-8 As shown, an embodiment of the present invention provides a short-circuit controllable semiconductor device structure, including a silicon substrate, wherein the silicon substrate is an N-type silicon material, used to support the device structure to form a carrier transport channel.

[0037] The carrier storage layer is used to regulate carrier transport paths and limit short-circuit current peaks. The carrier storage layer has a depth-decreasing doping concentration structure, and the P-well region employs a segmented ion implantation structure.

[0038] The trench gate structure includes trenches, a gate oxide layer, and a polysilicon gate electrode.

[0039] The P-well region is used to form a channel control region on both sides of the trench gate structure.

[0040] The N-well region is used to regulate minority carrier injection, and the N-well region forms a symmetrical matching relationship with the P-well region.

[0041] A short-circuit controllable semiconductor device manufacturing process, comprising:

[0042] S1. Provide an N-type silicon substrate, and perform multiple ion implantations on the N-type silicon substrate to form a carrier storage layer. The multiple ion implantations employ a multi-energy ion implantation method. The multi-energy ion implantation method controls the depth concentration by controlling the implantation energy and dopant dosage. The implantation energy is... The concentration range of the doping dose is .

[0043] S2. Trench gate structures are formed by etching trenches on the surface of an N-type silicon substrate. The trench gate structure includes trenches, a gate oxide layer, and polysilicon gate electrodes. The trench depth of the trench gate structure is 1 μm, and the trench spacing is [missing information]. The thickness range of the gate oxide layer is The thickness of the polysilicon gate electrode is Resistivity The polycrystalline silicon gate electrode is made of phosphorus-doped polycrystalline silicon material.

[0044] S3. P-type doped regions are formed by implantation definition processing on both sides of the trench gate structure. These P-type doped regions are then subjected to segmented P-well ion implantation to create multi-segment threshold voltage distributions. The segmented P-well ion implantation employs a layout partitioning design. The implantation definition processing utilizes photolithography mask ion implantation, and the activation temperature for this process is [temperature missing]. The depth of the P-well doped region is The threshold voltage difference for segmented P-trap ion implantation is The layout partitioning design is based on a trench gate structure, which is used to partition the substrate. Based on these partitions, a photolithographic mask layer is created, forming multiple threshold voltage distributions. Photolithographic mask ion implantation is a process that combines photolithography and ion implantation. The process includes photolithography and ion implantation. The photolithography mask uses photolithography to form a mask pattern on the surface of a silicon substrate, defining the ion implantation area and shape. By performing ion implantation under the mask, specific dopants are introduced into specific areas of the substrate, changing the conductivity of the area to form P-type or N-type doped regions.

[0045] In this embodiment, segmented P-well ion implantation forms multiple regions with different threshold voltages through a layout partitioning method. Specifically, based on the periodic arrangement of the trench gate structure, the active region of the device is divided into region 1, region 2, region 3, and region 4, with each region distributed alternately, uniformly, and symmetrically in the layout.

[0046] For example, in a preferred embodiment, the threshold voltage of regions 1-4, The injected dose and the carrier storage layer injected dose can satisfy a corresponding relationship that increases with increasing threshold voltage, as shown in the table below:

[0047] Table 1: Different threshold voltage regions Example table of the relationship between injection and carrier storage layer injection.

[0048]

[0049] Different regions adopt different Injected doses to create different threshold voltage distributions, where region 1... The lowest injected dose corresponds to the lowest threshold voltage, in region 4. The highest injected dose corresponds to the highest threshold voltage. The threshold voltages of regions 2 and 3 fall between these two, with the overall threshold voltage difference being within a certain range. Within the range.

[0050] Because the threshold voltages differ in each region, the conduction states of different regions vary under the same gate drive signal. When the gate drive voltage is low, only the region with the lower threshold voltage forms a conduction channel first, while the region with the higher threshold voltage remains off. As the gate drive voltage increases further, the regions with higher threshold voltages are turned on sequentially, eventually achieving conduction in all regions.

[0051] By using the above method, under short-circuit or abnormal operating conditions, the effective conduction area can be effectively reduced under lower drive voltage conditions, thereby reducing the peak short-circuit current of the device.

[0052] The carrier storage layer is also designed using a layout partitioning method corresponding to the P-well region.

[0053] The injection dose of the carrier storage layer is set differently for different threshold voltage regions. The region with higher threshold voltage corresponds to a higher injection dose of the carrier storage layer to enhance its conductivity modulation capability, while the region with lower threshold voltage corresponds to a lower injection dose of the carrier storage layer.

[0054] Through the above-mentioned differentiated design, under the same gate drive voltage, the conduction current of each turned-on region tends to be consistent or close, avoiding the problem of unbalanced current between regions caused by the difference in threshold voltage.

[0055] S4. N-well ion implantation is performed above the P-well region to form the emission region. N-well ion implantation employs a multi-level implantation method, including two-stage and three-stage energy implantation. Two-stage energy implantation is... The three-stage energy injection is based on the two-stage energy injection plus an intermediate energy injection, where the intermediate energy injection is... The dose of N-trap ion implantation is .

[0056] S5. A multi-cell layout is performed on the surface of the N-type silicon substrate to form a multi-cell structure array. Based on the multi-cell structure array, photolithography is used to divide the substrate into cell regions. Termination metal interconnects are then performed on these cell regions to form a semiconductor device structure. The termination metal interconnects include interlayer dielectric deposition, contact hole etching, and metal electrode deposition. The multi-cell layout is separated by insulating isolation strips, the width of which is... The metallization process includes depositing a first metal layer and a second metal layer. The first metal layer is a titanium and titanium-nitrogen alloy layer, and the second metal layer is an aluminum and copper layer. The cell size of the multi-cell structure array is... The photolithography process employs a double-mask alignment method, and the interlayer dielectric deposition uses plasma-enhanced chemical vapor deposition, contact hole etching, reactive ion etching, and metal electrode deposition via sputtering.

[0057] Double-mask alignment refers to the precise alignment of two mask layers during photolithography. It is used for forming multi-layer structures or complex patterns to ensure accurate alignment between multiple mask layers.

[0058] Plasma-enhanced chemical vapor deposition (PECVD) utilizes plasma to excite chemical reactions, transforming a gaseous source into a solid material deposited on a substrate. It is widely used for thin film deposition, particularly in semiconductor manufacturing for depositing dielectric layers such as silicon oxide or silicon nitride.

[0059] Reactive ion etching is a dry etching technique that uses reactive ions to react with and remove the area to be etched by introducing a specific gas into the etching chamber and exciting plasma.

[0060] Sputter deposition is a method that uses high-energy particles to bombard a target, sputtering the target's atoms or molecules and depositing them onto a substrate. It is used to deposit metal electrode layers in semiconductor devices, providing uniform and high-quality metal layers, and is widely used in interconnect layer deposition for integrated circuits.

[0061] The above embodiments are designed with a focus on low power consumption and small size semiconductor devices, employing lower injection energy and doping concentration, making them suitable for the needs of low-power devices. By controlling the doping concentration of the carrier storage layer and the trench gate structure, the peak short-circuit current is limited, thereby controlling power consumption and peak current. This approach is applicable to low-power electronic products with stringent power management requirements, such as sensors and low-power integrated circuits.

[0062] Example 2

[0063] This embodiment provides a short-circuit controllable semiconductor device structure, including a silicon substrate, wherein the silicon substrate is an N-type silicon material, used to support the device structure and form a carrier transport channel.

[0064] The carrier storage layer is used to regulate carrier transport paths and limit short-circuit current peaks. The carrier storage layer has a depth-decreasing doping concentration structure, and the P-well region employs a segmented ion implantation structure.

[0065] The trench gate structure includes trenches, a gate oxide layer, and a polysilicon gate electrode.

[0066] The P-well region is used to form a channel control region on both sides of the trench gate structure.

[0067] The N-well region is used to regulate minority carrier injection, and the N-well region forms a symmetrical matching relationship with the P-well region.

[0068] A short-circuit controllable semiconductor device manufacturing process, comprising:

[0069] S1. Provide an N-type silicon substrate, and perform multiple ion implantations on the N-type silicon substrate to form a carrier storage layer. The multiple ion implantations employ a multi-energy ion implantation method. The multi-energy ion implantation method controls the depth concentration by controlling the implantation energy and dopant dosage. The implantation energy range is... The concentration range of the doping dose is .

[0070] S2. Trench gate structures are formed by etching trenches on the surface of an N-type silicon substrate. The trench gate structure includes trenches, a gate oxide layer, and a polysilicon gate electrode. The trench depth of the trench gate structure is... The groove spacing of the grooved grid structure is The thickness range of the gate oxide layer is The thickness of the polysilicon gate electrode is Resistivity The polycrystalline silicon gate electrode is made of phosphorus-doped polycrystalline silicon material.

[0071] S3. P-type doped regions are formed by implantation definition processing on both sides of the trench gate structure. These P-type doped regions are then subjected to segmented P-well ion implantation to create multi-segment threshold voltage distributions. The segmented P-well ion implantation employs a layout partitioning design. The implantation definition processing utilizes photolithography mask ion implantation, and the activation temperature for this process is [temperature missing]. The depth of the P-well doped region is The threshold voltage difference range for segmented P-trap ion implantation is: The layout partitioning design is based on the trench gate structure for partitioning, and the photolithography mask layer is divided based on the partitioning to form a multi-segment threshold voltage distribution.

[0072] In this embodiment, segmented P-well ion implantation also forms multiple regions with different threshold voltages through a layout partitioning method. Each region is periodically, symmetrically, and uniformly distributed within the device plane. The trench gate structure and contact structure are arranged in repeating units in the vertical direction, ensuring that regions with different threshold voltages are uniformly distributed throughout the entire device.

[0073] Therefore, under different gate drive voltage conditions, even if only a portion of the region is turned on, the effective conduction path of the device still maintains spatial uniformity and symmetry, which is beneficial for suppressing local current concentration and thermal unevenness. Simultaneously, the injection dose of the carrier storage layer is gradient-set according to the threshold voltage of each region to compensate for the differences in conduction capability between regions with different threshold voltages.

[0074] S4. N-well ion implantation is performed above the P-well region to form the emission region. N-well ion implantation employs a multi-level implantation method, including two-level and three-level energy implantation. The range of two-level energy implantation is... The three-stage energy injection is based on the two-stage energy injection, with the addition of an intermediate energy injection. The range of the intermediate energy injection is... The dose range for N-trap ion implantation is .

[0075] S5. A multi-cell layout is performed on the surface of the N-type silicon substrate to form a multi-cell structure array. Based on the multi-cell structure array, photolithography is used to divide the substrate into cell regions. Termination metal interconnects are then performed on these cell regions to form a semiconductor device structure. The termination metal interconnects include interlayer dielectric deposition, contact hole etching, and metal electrode deposition. The multi-cell layout is separated by insulating isolation strips, the width of which is... The metallization process includes depositing a first metal layer and a second metal layer. The first metal layer is a titanium and titanium-nitrogen alloy layer, and the second metal layer is an aluminum and copper layer. The cell size of the multi-cell structure array is... The photolithography process employs a double-mask alignment method, and the interlayer dielectric deposition uses plasma-enhanced chemical vapor deposition, contact hole etching, reactive ion etching, and metal electrode deposition via sputtering.

[0076] This embodiment is suitable for semiconductor devices with medium power requirements. Through a rationally designed ion implantation process and doping concentration, it provides a relatively balanced current control and power handling capability. Structurally, the use of deeper trenches and a thicker gate oxide layer enhances the device's voltage withstand capability and stability. It is suitable for electronic products with medium power requirements, such as consumer electronics, communication equipment, and industrial control systems.

[0077] Example 3

[0078] This embodiment provides a short-circuit controllable semiconductor device structure, including a silicon substrate, wherein the silicon substrate is an N-type silicon material, used to support the device structure and form a carrier transport channel.

[0079] The carrier storage layer is used to regulate carrier transport paths and limit short-circuit current peaks. The carrier storage layer has a depth-decreasing doping concentration structure, and the P-well region employs a segmented ion implantation structure.

[0080] The trench gate structure includes trenches, a gate oxide layer, and a polysilicon gate electrode.

[0081] The P-well region is used to form a channel control region on both sides of the trench gate structure.

[0082] The N-well region is used to regulate minority carrier injection, and the N-well region forms a symmetrical matching relationship with the P-well region.

[0083] A short-circuit controllable semiconductor device manufacturing process, comprising:

[0084] S1. Provide an N-type silicon substrate, and perform multiple ion implantations on the N-type silicon substrate to form a carrier storage layer. The multiple ion implantations employ a multi-energy ion implantation method. The multi-energy ion implantation method controls the depth concentration by controlling the implantation energy and dopant dosage. The implantation energy range is... The concentration range of the doping dose is .

[0085] S2. Trench gate structures are formed by etching trenches on the surface of an N-type silicon substrate. The trench gate structure includes trenches, a gate oxide layer, and a polysilicon gate electrode. The trench depth of the trench gate structure is... The groove spacing of the grooved grid structure is The thickness range of the gate oxide layer is The thickness of the polysilicon gate electrode is Resistivity The polycrystalline silicon gate electrode is made of phosphorus-doped polycrystalline silicon material.

[0086] S3. P-type doped regions are formed by implantation definition processing on both sides of the trench gate structure. These P-type doped regions are then subjected to segmented P-well ion implantation to create multi-segment threshold voltage distributions. The segmented P-well ion implantation employs a layout partitioning design. The implantation definition processing utilizes photolithography mask ion implantation, and the activation temperature for this process is [temperature missing]. The depth of the P-well doped region is The threshold voltage difference range for segmented P-trap ion implantation is: The layout partitioning design is based on the trench gate structure for partitioning, and the photolithography mask layer is divided based on the partitioning to form a multi-segment threshold voltage distribution.

[0087] S4. N-well ion implantation is performed above the P-well region to form the emission region. N-well ion implantation employs a multi-level implantation method, including two-level and three-level energy implantation. The range of two-level energy implantation is... The three-stage energy injection is based on the two-stage energy injection, with the addition of an intermediate energy injection. The range of the intermediate energy injection is... The dose range for N-trap ion implantation is .

[0088] S5. A multi-cell layout is performed on the surface of the N-type silicon substrate to form a multi-cell structure array. Based on the multi-cell structure array, photolithography is used to divide the substrate into cell regions. Termination metal interconnects are then performed on these cell regions to form a semiconductor device structure. The termination metal interconnects include interlayer dielectric deposition, contact hole etching, and metal electrode deposition. The multi-cell layout is separated by insulating isolation strips, the width of which is... The metallization process includes depositing a first metal layer and a second metal layer. The first metal layer is a titanium and titanium-nitrogen alloy layer, and the second metal layer is an aluminum and copper layer. The cell size of the multi-cell structure array is... The photolithography process employs a double-mask alignment method, and the interlayer dielectric deposition uses plasma-enhanced chemical vapor deposition, contact hole etching, reactive ion etching, and metal electrode deposition via sputtering.

[0089] Under high-power operating conditions, through the segmented design of the aforementioned multi-threshold voltage regions, only a portion of the low-threshold voltage regions participate in conduction under lower gate drive voltage conditions, thereby reducing the transient current peak and short-circuit energy under short-circuit conditions. Compared to a structure where all regions are simultaneously conducting, this embodiment improves the device's safety margin under short-circuit conditions while maintaining normal conduction capability.

[0090] Furthermore, by increasing the injection dose of the carrier storage layer in the high threshold voltage region, the conduction current distribution in each turned-on region is more balanced under the same gate drive conditions, reducing the current deviation between regions and improving the electrothermal stability of the device.

[0091] The aforementioned semiconductor devices, focused on high power and high current carrying capacity, employ higher injection energy and doping concentration to meet the demands of high-power applications. Deeper trench structures and thicker gate oxide layers ensure that the semiconductor devices can withstand high current and high power operating conditions, exhibiting high thermal stability and voltage resistance. They are suitable for high-end computers, large communication base stations, data centers, and other equipment requiring high power processing capabilities.

[0092] Example 4

[0093] This embodiment is based on a short-circuit controllable semiconductor device structure and manufacturing process. By comparing three different manufacturing process conditions, it analyzes the differences in electrical performance and structural quality of the semiconductor device. The specific implementation method is as follows:

[0094] 1. Experimental Materials and Equipment

[0095] The material has a diameter The N-type silicon substrate is phosphorus-doped, and the dopants used for multi-energy ion implantation are titanium, titanium-nitrogen alloy, aluminum, and copper.

[0096] The equipment includes ion implanters, lithography machines, etching machines, scanning electron microscopes, and electrical performance testing instruments.

[0097] 2. Experimental group setup

[0098] The experiment was divided into three groups, each using three different process conditions:

[0099] Group 1:

[0100] Ion implantation: Implantation energy is Doping dose is .

[0101] Trench grid structure:

[0102] trench depth is The trench spacing is The gate oxide layer thickness is The thickness of the polysilicon gate electrode is The resistivity is .

[0103] P-type doped region: implantation depth is Activation temperature is .

[0104] N-trap ion implantation: implantation dose is .

[0105] Group 2:

[0106] Ion implantation: Implantation energy is Doping dose is .

[0107] Trench grid structure:

[0108] trench depth is The trench spacing is The gate oxide layer thickness is The thickness of the polysilicon gate electrode is The resistivity is .

[0109] P-type doped region: implantation depth is Activation temperature is .

[0110] N-trap ion implantation: implantation dose is .

[0111] Group 3:

[0112] Ion implantation: Implantation energy is Doping dose is .

[0113] Trench grid structure:

[0114] trench depth is The trench spacing is The gate oxide layer thickness is The thickness of the polysilicon gate electrode is The resistivity is .

[0115] P-type doped region: implantation depth is Activation temperature is .

[0116] N-trap ion implantation: implantation dose is .

[0117] 3. Implementation Steps

[0118] Silicon substrate preparation:

[0119] A suitable N-type silicon substrate was selected, cleaned, and prepared for subsequent processing. Based on the different ion implantation process conditions for each group, multiple ion implantations were performed using multi-energy ion implantation to form a carrier storage layer. The implantation energy and doping dose were adjusted according to the group settings to achieve depth concentration control.

[0120] Etching of the trench gate structure:

[0121] Trenches are etched on the surface of a silicon substrate to form a trench gate structure. The depth, spacing, and gate oxide thickness of the trenches are adjusted according to the requirements of different groups.

[0122] Formation of P-type doped regions: P-type doped regions are defined on both sides of the trench gate structure, and segmented P-well ion implantation is formed using photolithography mask ion implantation. The activation temperature and doping depth are adjusted according to the requirements of different groups to obtain different threshold voltages.

[0123] N-well ion implantation: N-well ion implantation is performed above the P-well region, and the emitter region is formed by multi-energy implantation.

[0124] The implantation energy and dosage are adjusted according to the ion implantation process settings for each group.

[0125] Photolithography and metallization:

[0126] Photolithography is used to divide the multi-cell layout, and metallization is then performed on this basis. This includes process steps such as interlayer dielectric deposition, contact hole etching, and metal electrode deposition.

[0127] Electrical performance testing and structural characterization:

[0128] The trench gate structure and the morphology of the P and N wells were observed using a scanning electron microscope. Electrical performance testing instruments were used. Characteristic testing involves measuring the current-voltage characteristics of each sample group to evaluate performance such as threshold voltage, short-circuit current, and conduction current.

[0129] 4. Experimental Results and Comparative Analysis

[0130] Table 2: Electrical Performance Comparison Table.

[0131]

[0132] Threshold voltage: Group 1 has the lowest threshold voltage, indicating that under low-energy ion implantation conditions, the doping concentration of the P-type doped region is low, resulting in a low threshold voltage. Group 3 has the highest threshold voltage, indicating that higher ion implantation energy and a deeper doped layer result in a higher threshold voltage.

[0133] Short-circuit current peak value: Group 1 has the highest short-circuit current peak value, indicating that the device has a large current leakage. Group 3 has the lowest short-circuit current peak value, indicating that high-energy ion implantation and deep doping layer effectively limit the short-circuit current.

[0134] On-current: Group 3 has a slightly higher on-current due to the deeper doping layer and greater trench depth, which results in a slight improvement in the device's conduction performance.

[0135] Structural analysis:

[0136] Trench grid structure:

[0137] Group 1: Shallower trenches The gate oxide layer is relatively thin. This results in relatively weak control over the gate electrode, affecting the switching speed of the device.

[0138] Group 2: Deeper trenches The gate oxide layer thickness is The improved gate electrode control capability of the device has increased the complexity of manufacturing.

[0139] Group 3: Deeper trenches The thickest gate oxide layer The gate electrode has the strongest control capability, which can control the channel current, but it introduces greater manufacturing costs.

[0140] Experiments show that Group 1 is suitable for applications requiring higher current, but has a higher short-circuit current, necessitating optimized control of the carrier storage layer. Group 2 offers more balanced performance, suitable for devices with medium power requirements, a moderate threshold voltage, and relatively low short-circuit current. Group 3 is suitable for high-performance devices with high power and low short-circuit current requirements, but has a higher manufacturing cost.

[0141] To further verify the technical effectiveness of the multi-threshold voltage partitioning design and differentiated carrier storage layer injection in this invention, the following comparative analysis is conducted:

[0142] Comparative Example A: Using a uniform The injected dose forms a single threshold voltage distribution, and the remaining process conditions are the same as those in the embodiments of the present invention.

[0143] Comparative Example B: A segmented P-well injection method is used to form a multi-threshold voltage region, but the carrier storage layer uses a uniform injection dose and no differentiated design is performed.

[0144] Under the same short-circuit test conditions, different levels of gate drive voltage were applied to each sample, and their peak short-circuit current and on-current characteristics were tested respectively. The test included at least the peak short-circuit current, short-circuit energy, and on-current uniformity in each region.

[0145] Test results show that the embodiments of the present invention can effectively reduce the number of conducting regions and reduce the peak short-circuit current under low driving voltage conditions. At the same time, through the differentiated carrier storage layer injection design, the conducting current of each open region tends to be consistent, which is significantly better than the comparative example B structure.

[0146] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A short-circuit controllable semiconductor device structure, characterized in that, include: A silicon substrate, wherein the silicon substrate is an N-type silicon material, is used to support the device structure and form a carrier transport channel; The carrier storage layer is used to regulate carrier transport paths and limit short-circuit current peaks. A trench gate structure, wherein the trench gate structure includes trenches, a gate oxide layer, and a polysilicon gate electrode; The P-well region is used to form a channel control region on both sides of the trench gate structure; The N-well region is used to regulate minority carrier injection, and the N-well region forms a symmetrical matching relationship with the P-well region.

2. The short-circuit controllable semiconductor device structure according to claim 1, characterized in that: The carrier storage layer has a doping concentration decreasing in the depth direction, and the P-well region adopts a segmented ion implantation structure.

3. A short-circuit controllable semiconductor device manufacturing process, characterized in that, include: S1. Provide an N-type silicon substrate, and perform multiple ion implantations on the N-type silicon substrate to form a carrier storage layer, wherein the multiple ion implantations are performed using a multi-energy ion implantation method. S2. Trench gate structure is formed by etching trenches on the surface of the N-type silicon substrate. The trench gate structure includes trenches, gate oxide layer and polysilicon gate electrode. S3. P-type doped regions are formed by implantation definition on both sides of the trench gate structure. The P-type doped regions are then segmented by P-well ion implantation to form a multi-segment threshold voltage distribution. The segmented P-well ion implantation adopts a layout partitioning design. S4. N-well ion implantation is performed above the P-well region to form an emission region; S5. The surface of the N-type silicon substrate is divided into multiple cell layouts and metallized to form a multiple cell structure array. Based on the multiple cell structure array, photolithography is performed to form cell regions. The cell regions are then subjected to terminal metal interconnect processing to form a semiconductor device structure. The terminal metal interconnect processing includes interlayer dielectric deposition, contact hole etching, and metal electrode deposition.

4. The short-circuit controllable semiconductor device manufacturing process according to claim 3, characterized in that: The multi-energy ion implantation method achieves depth concentration control by controlling the implantation energy and dopant dosage, wherein the implantation energy range is... The concentration range of the doping dose is: .

5. The short-circuit controllable semiconductor device manufacturing process according to claim 3, characterized in that: The trench depth of the trench grid structure is The groove spacing of the grooved grid structure is The thickness range of the gate oxide layer is The thickness of the polycrystalline silicon gate electrode is Resistivity The polycrystalline silicon gate electrode is made of phosphorus-doped polycrystalline silicon material.

6. The short-circuit controllable semiconductor device manufacturing process according to claim 3, characterized in that: The implantation definition process employs photolithographic mask ion implantation, and the activation temperature of the implantation definition process is [temperature value missing]. The depth of the P-well doped region is The threshold voltage difference range of the segmented P-trap ion implantation is [range missing]. The layout partitioning design is based on the trench gate structure to partition the area, and the photolithography mask layer is divided based on the partitioning to form the multi-segment threshold voltage distribution.

7. The short-circuit controllable semiconductor device manufacturing process according to claim 3, characterized in that: The N-well ion implantation employs a multi-level implantation method, which includes two-level energy implantation and three-level energy implantation. The range of the two-level energy implantation is... The third-level energy injection is based on the two-level energy injection plus an intermediate energy injection, the range of which is... The dose range of the N-trap ion implantation is: .

8. The short-circuit controllable semiconductor device manufacturing process according to claim 3, characterized in that: The multi-cell layout is divided using insulating isolation strips, and the width of the insulating isolation strips is... The metallization process includes depositing a first metal layer and a second metal layer. The first metal layer is a titanium and titanium-nitrogen alloy layer, and the second metal layer is an aluminum and copper layer. The cell size of the multi-cell structure array is... The photolithography division adopts a double-layer mask alignment method, the interlayer dielectric deposition adopts plasma-enhanced chemical vapor deposition, the contact hole etching adopts reactive ion etching, and the metal electrode deposition adopts sputtering deposition.

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