A method for producing a semiconductor structure
By rounding the apex of the semiconductor fins of the FinFET, combined with wet oxidation and etching techniques, the problem of easy breakdown of gate oxides in high-voltage applications is solved, enabling high-quality and low-cost FinFET manufacturing suitable for 3D-NAND memory systems.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- INTERUNIVERSITAIR MICRO ELECTRONICS CENT (IMEC VZW)
- Filing Date
- 2025-11-26
- Publication Date
- 2026-05-29
AI Technical Summary
Existing technologies struggle to effectively optimize FinFET design for high-voltage applications, leading to gate oxides being susceptible to electric field accumulation, increasing the risk of breakdown, and resulting in complex and costly manufacturing processes.
By rounding the apex of the semiconductor fins of the FinFET, covering the top surface with a mask and partially removing the mask, combined with wet oxidation and etching techniques, the curvature radius of the apex is controlled, the accumulation of electric field intensity is reduced, and an appropriate gate oxide layer is used to reduce electrical stress.
This enables the reduction of electrical stress on the gate oxide in high-voltage applications, reduces the risk of breakdown, simplifies the manufacturing process and reduces costs, and is suitable for high-quality FinFET manufacturing of 3D-NAND memory systems.
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Figure CN122121194A_ABST
Abstract
Description
Technical Field
[0001] The present invention generally relates to a method for producing semiconductor structures. Background Technology
[0002] Modern semiconductor integrated circuit technology includes various types of field-effect transistors (FETs). FETs typically include at least one channel extending horizontally between a source and a drain, and this at least one channel comprises semiconductor material. Furthermore, FETs typically include a gate for controlling the current flowing through said at least one channel.
[0003] A prominent example of a FET is the FinFET. In a FinFET, semiconductor fins form the channel of the transistor, and the gate typically spans across the fins. Summary of the Invention
[0004] The objective of this invention is to realize a FinFET suitable for high-voltage applications, which may be referred to as a high-voltage FinFET (HV FinFET). High-voltage applications can be, for example, applications where the FinFET needs to withstand voltages to the gate and source-drain terminals that are higher (e.g., much higher) than those of the core logic FET. Examples of high-voltage applications are FinFETs for 3D-NAND memory systems, such as FinFETs for cell programming and / or cell erasure in 3D-NAND memory systems, or word-line FinFETs for cell programming and / or cell erasure in 3D-NAND memory systems. Therefore, the objective is to realize a 3D-NAND memory system.
[0005] It is recognized that high-voltage FET designs require careful optimization to facilitate the transition from planar FETs to FinFETs. Typically, the semiconductor fins of a high-voltage FinFET will support a thick gate oxide layer to withstand the strong electric field generated by the high voltages from the gate and source-drain terminals.
[0006] Another objective of this invention is to achieve high-quality HV FinFET. Another objective is to achieve high-quality 3D-NAND memory systems.
[0007] Another objective of this invention is to facilitate the simple and / or low-cost manufacturing of HV FinFETs. Another objective is to facilitate the simple and / or low-cost manufacturing of 3D-NAND memory systems.
[0008] These and other objectives of the present invention are at least partially satisfied by the invention as defined in the independent claims. Preferred embodiments are set forth in the dependent claims.
[0009] In the following text, relative spatial terms such as “top,” “bottom,” “lower,” and “vertical” should be understood as indicating the position or orientation within a reference frame of the semiconductor structure. In particular, these terms can be understood relative to the normal direction of the substrate on which the semiconductor structure is formed. Accordingly, terms such as “lateral” and “horizontal” should be understood as a position or orientation parallel to the substrate.
[0010] The first direction can be understood as the direction in which current flows within the finished transistor. The second direction can be understood as the direction transverse to the first direction. The third direction can be understood as the direction perpendicular to or from bottom to top. The first and second directions can be parallel to the substrate. The third direction can be perpendicular to the substrate.
[0011] According to a first aspect, a method for producing a semiconductor structure is provided, the method comprising: providing a semiconductor fin on a substrate, the semiconductor fin including a first side surface, a second side surface opposite to the first side surface, and a top surface, wherein a mask covers the top surface of the semiconductor fin; exposing a portion of the top surface of the semiconductor fin by removing a portion of the mask, the exposed portion of the top surface and the first side surface forming an exposed apex angle of the semiconductor fin by oxidizing the exposed portion of the top surface and the first side surface to round off the exposed apex angle of the semiconductor fin.
[0012] The semiconductor fins can be formed by etching semiconductor fins from a substrate or from a layer deposited on a substrate (e.g., etching semiconductor fins from a layer epitaxially grown on a substrate). The semiconductor fins may include, for example, silicon, germanium, or silicon-germanium, but are not limited thereto, and may include any semiconductor material. The substrate may include, for example, silicon, germanium, or silicon-germanium, but is not limited thereto, and may include any semiconductor material.
[0013] The semiconductor fin can extend in a first direction. The side surface can be perpendicular to a second direction. The semiconductor fin can include two opposing end faces. The end faces can be perpendicular to the first direction.
[0014] A mask covering the top surface of a semiconductor fin means that the mask extends over the entire area of the top surface. The mask covering the top surface of the fin may have been deposited on the substrate before the semiconductor fin is etched away, and may have already been used as an etching mask for etching away the semiconductor fin. Alternatively, a mask may be provided on the top surface of the semiconductor fin after it has been etched away. This mask may be a hard mask. The mask may include, but is not limited to, silicon nitride, silicon carbide, or any silicon carbide composite material, and may include any semiconductor material.
[0015] When a portion of the top surface of a semiconductor fin is exposed by removing a portion of a mask, that portion of the mask can be removed by etching, as will be discussed below. The exposed apex angle of the semiconductor fin can be the angle at the intersection between the first side surface and the top surface, which can be referred to as the left apex angle. The exposed apex angle of the semiconductor fin can also be the angle at the intersection between the second side surface and the top surface, which can be referred to as the upper right angle. Advantageously, both the upper left and upper right angles can be exposed and then rounded.
[0016] Semiconductor fins with rounded apex corners according to this method can be used to produce FinFETs, such as HV FinFETs. FinFETs can be produced by forming a gate across the semiconductor fin and forming source / drain (S / D) regions on opposite end faces of the semiconductor fin.
[0017] This FinFET can be used, for example, to produce the 3D-NAND memory system by integrating the FinFET as a word line transistor into the 3D-NAND memory system.
[0018] It is recognized that rounded corners can reduce the accumulation of electric field strength near the corners in finished FinFETs compared to less rounded corners. When voltage is applied to a semiconductor fin, sharp corners can locally amplify the electric field strength. Therefore, by rounding the corners, the electric field strength near the corners can be reduced.
[0019] The reduced electric field strength at the rounded apex means that the electrical stress applied to the gate oxide, which at least partially covers the semiconductor fin, can be reduced. In other words, given a voltage applied to the semiconductor fin, the chance of gate oxide breakdown can be reduced according to this method.
[0020] Due to the rounded apex, the stress applied to the gate oxide is reduced, which means, for example, that higher voltages can be applied to the semiconductor fins and / or a thinner gate oxide can be used without causing gate oxide breakdown.
[0021] Recognizing that covering the top surface with a mask and removing a portion of the mask to create an exposed apex allows for high control over the rounding of the angle. The amount of rounding can be controlled by removing smaller or larger portions of the mask, thus making the exposed portion of the top surface smaller or larger accordingly.
[0022] The semiconductor fin can have a width of at least 6 nm. For example, the semiconductor fin can have a width in the range of 6-100 nm. The semiconductor fin can have a length of at least 20 nm, preferably at least 100 nm, and more preferably at least 500 nm. These lengths are suitable for high-voltage applications.
[0023] The height of the semiconductor fin can be defined as the shortest distance from the substrate to the top surface of the semiconductor fin in a third-order direction. The semiconductor fin can have a height of at least 10 nm. For example, the semiconductor fin can have a height in the range of 10-120 nm. More preferably, the semiconductor fin can have a height of at least 40 nm, for example, in the range of 40-120 nm.
[0024] The S / D region can be formed during the fabrication of a FinFET. For example, the end face of the fin can be exposed through source / drain recesses. The S / D region can then be formed on the exposed end face. The S / D region can also be formed through epitaxial growth.
[0025] The exposed portion of the top surface may include a left-side exposed portion of the top surface. The left-side exposed portion of the top surface and the first side surface may form the exposed apex angle of the semiconductor fin, which may be referred to as the exposed left apex angle. Therefore, the exposed left-side exposed portion of the top surface may be a portion of the top surface extending from the intersection between the first side surface of the fin and the top surface toward the central axis of the top surface. Alternatively or additionally, the exposed portion of the top surface may include a right-side exposed portion of the top surface. The exposed right-side exposed portion of the top surface and the second side surface may form the exposed apex angle of the semiconductor fin, which may be referred to as the exposed upper right corner. Therefore, the exposed right-side exposed portion of the top surface may be a portion of the top surface extending from the intersection between the second side surface and the top surface of the fin toward the central axis of the top surface.
[0026] It should be understood that any processing described herein in relation to exposed apex corners may, by analogy, refer to an exposed upper-left corner, an exposed upper-right corner, or both. A semiconductor fin may include either an exposed upper-left corner or an exposed upper-right corner, or both. Furthermore, a semiconductor fin may include any number of additional exposed apex corners, which may be referred to as exposed apex corners.
[0027] Rounding the exposed apex of the semiconductor fin means increasing the effective radius of curvature of the apex.
[0028] For example, rounding can mean a radius of curvature in the range of 1 to 40 nm, preferably in the range of 1 to 20 nm, and more preferably in the range of 1 to 10 nm.
[0029] The rounding effect of oxidation means that the exposed portion of the top surface and the first side surface undergo oxidation. The masked portion of the top surface is shielded from oxidation, resulting in it being less oxidized than the exposed portion of the top surface and the first side surface. Therefore, the material of the semiconductor fin is oxidized near the exposed apex, causing the exposed apex to round off. The height of the semiconductor fin remains unchanged by rounding off the apex.
[0030] The width of the exposed portion of the top surface of the semiconductor fin can be at least 5% of the fin width. Alternatively, the width of the exposed portion of the top surface of the semiconductor fin can be at least 10% of the fin width. A larger exposed portion of the top surface of the semiconductor fin can result in a more rounded apex, i.e., a larger effective radius of curvature of the exposed apex.
[0031] The step of removing this portion of the mask may include lateral etching of at least a portion of the mask. Lateral etching means etching the mask material from the side toward the central axis of the mask, resulting in a reduction in the mask width. The mask may be etched in a second direction, i.e., parallel to the substrate and perpendicular to the first direction of fin extension. Lateral etching of the mask allows for highly controlled width of the exposed portion of the top surface, and thus highly controlled size and shape of the exposed apex corners and the rounding of the exposed apex corners.
[0032] Optionally, the step of removing this portion of the mask may include photolithography in combination with etching, using a photomask with or without a photolithographic mask. If photolithography is used, etching may be performed laterally or from top to bottom (vertically).
[0033] The process of lateral etching a mask can include wet etching. For example, the process of lateral etching a mask can include wet etching with a mixture of hydrofluoric acid (HF) and phosphoric acid (H3PO4). As an alternative example, the process of lateral etching a mask can include wet etching with a sulfur peroxide mixture (SPM). The sulfur peroxide mixture can be a mixture of sulfuric acid (H2SO4) and hydrogen peroxide (H2O2). Wet etching is advantageous for lateral etching because it performs isotropic etching and reduces damage to the structure compared to, for example, dry etching.
[0034] In some embodiments, the mask may include a first layer and a second layer, the first layer being disposed between the top surface of the semiconductor fin and the second layer, wherein removing the portion of the mask may include: removing a first portion of the first layer of the mask; and removing a first portion of the second layer of the mask; wherein the first portion of the second layer of the mask is the portion above the first portion of the first layer of the mask.
[0035] In other words, similar to the previous description, the first portion and the first side surface of the first layer that have been removed can form an exposed apex corner, which can be referred to as the exposed left apex corner. Additionally or alternatively, the second portion and the second side surface of the first layer that have been removed can form an exposed apex corner, which can be referred to as the exposed upper right corner.
[0036] The first and second layers of the mask may include different material compositions. The first and second layers may have different thicknesses. The first layer may include, for example, silicon oxide. The second layer may include, for example, silicon nitride, silicon carbonitride, or titanium nitride. The materials of the first and second layers can be selectively etched relative to each other, allowing one to be etched without the other. Using silicon oxide for the second layer is advantageous because silicon oxide is durable under physical stress. The width of the first portion removed from the first layer may differ from the width of the first portion removed from the second layer.
[0037] By using a mask with two layers, control over the steps of removing a portion of the mask and rounding the exposed apex corners can be further improved. For example, control can be improved by controlling the width of the first portion removed from the first layer in comparison with the width of the first portion removed from the second layer. Furthermore, for example, the material of the first layer can be selected to reduce strain induced on the fin.
[0038] The width of the first portion removed from the second layer of the mask can be greater than the width of the first portion removed from the first layer of the mask. Alternatively, the width of the first portion removed from the second layer of the mask can be less than the width of the first portion removed from the first layer of the mask.
[0039] By controlling the width of the first portion removed from the second layer and the width of the first portion removed from the first layer, as well as the relationship between the widths, control over the steps of removing a portion of the mask and rounding the exposed apex corners can be further improved.
[0040] The step of removing a first portion of the first layer of the mask can be performed in the first etching process; and the step of removing a first portion of the second layer of the mask can be performed in the second etching process, which can be performed after the first etching process.
[0041] Therefore, different etchants and different etching processes can be used for the first and second layers of the mask, allowing the etching of each layer to be controlled independently.
[0042] The steps of oxidizing the exposed portion of the top surface and the first side surface can be performed by wet oxidation. Wet oxidation can promote the formation of oxides with improved quality and improved oxidation integrity. Alternative oxidation methods include, for example, oxidation in humid air with chlorine (Cl) or dry oxidation. Note that any form of oxidation treatment is expected to provide benefits associated with the step of rounding the exposed apex by oxidizing it.
[0043] Wet oxidation can include the in-situ steam generation (ISSG) process.
[0044] It is recognized that the ISSG process effectively rounds the exposed apex corners. It is recognized that the ISSG process creates a suitable curvature for the rounded apex corners.
[0045] The ISSG process is a wet oxidation process. The ISSG process may include the formation of vapor within the processing chamber. Specifically, the ISSG process may include the formation of vapor very close to the substrate surface (and therefore very close to the semiconductor fins). It can be seen that the ISSG process differs from conventional in-furnace wet oxidation. In conventional in-furnace wet oxidation, vapor is generated outside the processing chamber.
[0046] The ISSG process can be carried out in a rapid heat treatment chamber.
[0047] The method may also include conformally coating the semiconductor fins with a gate oxide layer. The gate oxide layer can electrically insulate the semiconductor fins from, for example, a gate that can be formed to span the semiconductor fins. The gate oxide may include, for example, silicon dioxide, silicon oxynitride, hafnium dioxide, or zirconium hafnium dioxide, but is not limited thereto. Conformal coating may include, for example, oxide growth and / or atomic layer deposition (ALD).
[0048] The method may further include removing oxides formed during the steps of the exposed portion of the oxide top surface and the first side surface, wherein the removal of the oxides is performed prior to the step of conformally coating the semiconductor fins with a gate oxide layer.
[0049] Alternatively, the mask may be removed before the step of conformally coating the semiconductor fins with the gate oxide layer.
[0050] By removing the oxide formed during the steps of removing the exposed portion on the oxide top surface and the first side surface and / or the mask, it can be ensured that the oxide and / or mask do not form portions of the gate oxide of the finished transistor. Therefore, the oxide and / or mask can be replaced by another gate oxide with better electrical properties.
[0051] The gate oxide layer may have a thickness of at least 10 nm, preferably at least 20 nm, and more preferably at least 40 nm. These thicknesses may be more suitable for high-voltage applications.
[0052] The method may further include: forming a 3D-NAND memory system on a substrate; and forming word line transistors on the substrate, wherein the channel region of the word line transistors includes semiconductor fins.
[0053] A 3D-NAND memory system includes multiple memory cells arranged in a 3D matrix. Each memory cell may include a control gate for reading and / or writing and / or erasing data from the memory cell.
[0054] A word line can extend along a row of memory cells in a 3D-NAND memory system. This word line can be electrically connected to the control gate of that row of memory cells. Therefore, the voltage on the word line can control that row of memory cells. A word line transistor can be connected to the word line. The word line transistor can be configured to apply a voltage to the word line. In other words, the word line transistor can select which row of memory cells to access during operation of the 3D-NAND memory system.
[0055] 3D-NAND systems and corresponding word line transistors can have the same or similar advantages as those described in conjunction with the method. Attached Figure Description
[0056] The above and other objects, features, and advantages of the invention will be better understood from the following illustrative and non-limiting detailed description with reference to the accompanying drawings. Unless otherwise stated, the same reference numerals will be used for the same elements in the drawings.
[0057] Figure 1 A flowchart of a method for producing semiconductor structures is shown.
[0058] Figure 2 shows a cross-sectional view of the semiconductor structure according to an embodiment.
[0059] Figure 3 shows a cross-sectional view of a semiconductor structure according to various embodiments.
[0060] Figure 4 A cross-sectional view of a semiconductor structure according to an embodiment is shown. Detailed Implementation
[0061] The technical content and detailed description of the present invention are described below with reference to the accompanying drawings and preferred embodiments, but are not intended to limit the scope of the claims. However, the present invention can be implemented in many different forms and should not be construed as being limited to the embodiments set forth herein; rather, these embodiments are provided for thoroughness and completeness and to fully convey the scope of the invention to those skilled in the art.
[0062] Combination Figures 2a-2d refer to Figure 1 This document will describe a method 10 for producing a semiconductor structure 100. Method 10 will be described as comprising multiple steps. However, it should be recognized that some of these steps are optional and may not be performed or may be performed in various different ways. Therefore, the detailed description of the method provided herein should not be construed as limiting the scope of the description.
[0063] Method 10 includes providing 12 semiconductor fins 110 on substrate 102. Providing the semiconductor fins 110 101 may refer to obtaining the semiconductor fins 110, or it may refer to performing any number of processing steps required to produce the semiconductor fins 110. For example, the semiconductor fins 110 may be formed by etching them from substrate 102 or by etching them from a layer deposited on substrate 102 (e.g., etching them from a layer epitaxially grown on substrate 102).
[0064] Figure 2a A semiconductor fin 110 with a mask 120 covering the top surface 113 is shown. Figures 2a-2d All have the same orientation. The portion of mask 124 that will be removed later is marked in the figure (see below). Semiconductor fin 110 includes a first side surface 111, a second side surface 112 opposite to the first side surface 111, and a top surface 113. The semiconductor fin may extend in a first direction (x). The side surfaces may be perpendicular to the second direction (y). Semiconductor fin 110 may include two opposing end faces. The end faces may be perpendicular to the first direction (x).
[0065] Semiconductor fin 110 may include, for example, silicon, germanium, or silicon-germanium. Substrate 102 may include, for example, silicon, germanium, or silicon-germanium.
[0066] The semiconductor fin 110 may have a length of at least 20 nm extending in a first direction (x), preferably at least 100 nm, more preferably at least 500 nm. The semiconductor fin 110 may have a width 116 extending in a second direction (y) of at least 6 nm. For example, the semiconductor fin may have a width in the range of 6-100 nm. The height 117 of the semiconductor fin 110 may be defined as the shortest distance in a third direction (z) from the substrate 102 to the top surface 113 of the semiconductor fin 110. The semiconductor fin may have a height 117 of at least 10 nm. For example, the semiconductor fin may have a height in the range of 10-120 nm. More preferably, the semiconductor fin may have a height of at least 40 nm, for example in the range of 40-120 nm.
[0067] Mask 120 covers the top surface 113 of semiconductor fin 110. In other words, semiconductor fin 110 is disposed between substrate 102 and mask 120. The mask covering the top surface of the fin can be deposited on the substrate before etching the semiconductor fin and can be used as an etching mask for etching the semiconductor fin. Alternatively, a mask can be provided on the top surface of the semiconductor fin after etching.
[0068] As described above, method 10 includes exposing a portion 114 of the top surface 113 of semiconductor fin 110 by removing a portion 124 of mask 120. The exposed portion 114 of the top surface 113 and the first side surface 111 form an exposed apex 130 of semiconductor fin 110. Alternatively, the exposed apex 130 of semiconductor fin may be formed by the exposed portion 114 of the top surface 113 and the second side surface 112.
[0069] Figure 2b The semiconductor fin 110 is shown after portion 124 of mask 120 has been removed. In this figure, both portions 124 of mask 120 have been removed, exposing the upper left and upper right corners.
[0070] According to this method, one or more portions 124 of the mask can be removed.
[0071] In this figure, an exposed apex angle 130 of the semiconductor fin 110 is the angle at the intersection between the first side surface 111 and the top surface 113, and this exposed apex angle 130 can be referred to as the left apex angle. In this case, the exposed portion 114 of the top surface 113 is the portion of the top surface 113 extending from the intersection between the first side surface 111 and the top surface 113 of the semiconductor fin 110 toward the central axis of the top surface 113.
[0072] In this figure, another exposed apex angle 130 of the semiconductor fin 110 is the angle at the intersection between the second side surface 112 and the top surface 113, which can be referred to as the upper right corner. In this case, the exposed portion 114 of the top surface 113 is the portion of the top surface 113 extending from the intersection between the second side surface 112 and the top surface 113 of the semiconductor fin 110 toward the central axis of the top surface 113.
[0073] Based on the above, the exposed apex angle 130 can refer to either or both of the top left and top right corners.
[0074] The width 115 of the exposed top 114 extending along the first direction (x) may be at least 5% of the width 116 of the semiconductor fin 110, preferably at least 10% of the width 116 of the semiconductor fin 110.
[0075] Exposing a portion 114 of the top surface 113 of the 14 semiconductor fins 110 by removing a portion 124 of the 15 mask 120 may include laterally etching at least a portion of the mask 120. Lateral etching means etching the material of the mask 120 from the first side 111 and / or the second side 112 toward the central axis of the mask 120, resulting in a reduction in the width of the mask 120. In other words, the etching is performed in a first direction (x) parallel to the substrate.
[0076] The step of lateral etching mask 120 may include wet etching. Wet etching may include, for example, a combination of hydrofluoric acid (HF) and phosphoric acid (H3PO4).
[0077] As described above, method 10 includes rounding the exposed apex 130 of semiconductor fin 16 by oxidizing the exposed portion 114 of top surface 113 and the first side surface 111. Rounding the exposed apex 130 of semiconductor fin 110 means increasing the effective radius of curvature of the exposed apex 130.
[0078] Figure 2c The semiconductor fin 110 is shown after the rounded exposed corner.
[0079] Rounding by oxidation 17 means that the exposed portion 114 of the top surface 113 and the first side surface 111 are subjected to oxidation treatment. Alternatively, the exposed portion 114 of the top surface 113 and the second side surface 112 are subjected to oxidation treatment. The oxidation 17 step results in the formation of an oxide portion 150, which includes an oxide material that was the material of the semiconductor fin 110 prior to the oxidation 17 step.
[0080] The covered portion 118 of the top surface 113 covered by the mask 120 is shielded from oxidation treatment, such that it is at least less oxidized than the exposed portion 114 of the top surface and the first side surface 111 and / or the second side surface 112.
[0081] The steps of oxidizing the exposed portion 114 of the top surface 113 and the first side surface 111 can be performed by wet oxidation. Wet oxidation may include an in-situ vapor generation (ISSG) process.
[0082] Subsequently, the oxide formed during the step of oxidizing the exposed apex can be removed. For example, it may be advantageous to remove the oxide before depositing the gate oxide. Thus, the step of oxidizing the exposed apex can be optimized for rounding, and the deposition of the gate oxide can be optimized to give the gate oxide good electrical properties.
[0083] Alternatively, the oxide formed during the step of exposing the apex with oxide can be retained. The oxide formed during the step of exposing the apex with oxide can, for example, be integrated into the gate oxide.
[0084] Figure 2d A semiconductor fin 110 with rounded apex corners is shown after removing the oxide formed during the step of oxidizing the exposed apex corners. The semiconductor fin 110 with rounded apex corners according to this method can be used to produce FinFETs, such as HV FinFETs. FinFETs can be produced by forming a gate across the semiconductor fin 110 and forming source / drain (S / D) regions on the end face of the semiconductor fin 110.
[0085] refer to Figures 3a-3c In some embodiments, the mask 120 may include a first layer 120a and a second layer 120b, with the first layer 120a disposed between the top surface 113 of the semiconductor fin 110 and the second layer 120b. Figures 3a-3c They all have the same direction.
[0086] The step of removing portion 124 of mask 15 may optionally include removing the first portion 124a of the first layer 120a of mask 15a.
[0087] The step of removing portion 124 of mask 15b may optionally include removing the first portion 124b of the second layer 120b of mask 15b.
[0088] The first part 124b of the second layer 120b of mask 120 is the part above the first part 124a of the first layer 120a of mask 120.
[0089] The steps of removing the first portion 124a of the first layer 120a of the 15a mask 120 and removing the first portion 124b of the second layer 120b of the 15b mask 120 can be performed in any order relative to each other.
[0090] The width 115a of the first portion 124a removed from the first layer 120a may be different from the width 115b of the first portion 124b removed from the second layer 120b.
[0091] In some embodiments, such as Figure 3c As shown, the width 115b of the removed first portion 124b of the second layer 120b of the mask 120 can be greater than the width 115a of the removed first portion 124a of the first layer 120a of the mask 120.
[0092] In some embodiments, the step of removing the first portion 124a of the first layer 120a of the 15a mask 120 may be performed in the first etching process, while the step of removing the first portion 124b of the second layer 120b of the 15b mask 120 may be performed in the second etching process. The second etching process may be performed after the first etching process.
[0093] refer to Figure 4Method 10 may optionally include conformally coating the semiconductor fin 110 with a gate oxide layer 160. When the gate is formed across the semiconductor fin 110, the gate oxide 160 is disposed between the semiconductor fin 110 and the gate, thus electrically insulating the semiconductor fin 110 from the gate. The gate oxide layer 160 may have a thickness of at least 10 nm, preferably at least 20 nm, and more preferably at least 40 nm.
[0094] Method 10 may include, as an additional optional step, the removal of oxides formed during the step of removing oxides 18 from the exposed portion 114 of the oxide top surface 113 and the first side surface 111 and / or the second side surface 112. The step of removing the oxides 18 is performed prior to the step of conformally coating the semiconductor fin 110 20 with the gate oxide layer 160.
[0095] Method 10 may include, as an optional step, forming a 22 3D-NAND memory system on substrate 102.
[0096] Method 10 may include, as an additional optional step, forming a 24-word-line transistor on a substrate 102, wherein the channel region of the word-line transistor includes a semiconductor fin 110.
[0097] In some embodiments, method 10 includes:
[0098] A first layer 120a containing SiO and a second layer 120b containing SiN of a mask 120 are deposited on top of a substrate 102, wherein the substrate 102 contains Si.
[0099] Semiconductor fins 110 are etched from substrate 102 using mask 120 as an etching mask, such that mask 120 remains covering the top surface 113 of semiconductor fins 110.
[0100] By using an etch lateral etch mask 120 including HF and H3PO4, a portion 114 of the top surface 113 of the semiconductor fin 14 is exposed, forming the exposed apex 130 of the semiconductor fin 110, with a portion of the mask 130 remaining on the top surface 113 of the semiconductor fin 110.
[0101] The Si of the semiconductor fin 17 is oxidized by wet oxidation to form SiO, causing the exposed apex 130 to be rounded 16. The height 117 of the semiconductor fin 110 may not be changed by the rounding 16 of the exposed apex 130.
[0102] A SiO layer, known as STI oxide, is deposited by flowable chemical vapor deposition (FCVD), which covers at least a portion of the semiconductor fin 110, mask 120, and semiconductor structure 100. The semiconductor structure 110 is planarized by chemical mechanical polishing (CMP) until the top surface of the second layer 120b of mask 120 is exposed.
[0103] The STI oxide is recessed by HF etching, thereby exposing the second layer 120b of the mask 120, and the second layer 120b of the mask 120 is completely removed.
[0104] The STI oxide is further recessed, including the SiO formed during wet oxidation and the first layer 120a of the mask 120, in order to expose the desired height of the semiconductor fin 110.
[0105] The embodiments outlined above should not be construed as limiting the scope of the invention, but are merely examples of how the method can be performed.
[0106] In the foregoing, the inventive concept has been described primarily with reference to a limited number of examples. However, as will be readily understood by those skilled in the art, other examples besides those disclosed above are equally possible within the scope of the inventive concept as defined by the appended claims.
Claims
1. A method for producing a semiconductor structure (100), the method comprising: A semiconductor fin (110) is provided on a substrate (102), the semiconductor fin (110) including a first side surface (111), a second side surface (112) opposite to the first side surface (111) and a top surface (113), wherein a mask (120) covers the top surface (113) of the semiconductor fin (110); a portion (114) of the top surface (113) of the semiconductor fin (110) is exposed by removing a portion (124) of the mask (120), the exposed portion (114) of the top surface (113) and the first side surface (111) form an exposed apex (130) of the semiconductor fin (110); the exposed apex (16) of the semiconductor fin (110) is rounded by oxidizing the exposed portion (114) of the top surface (113) and the first side surface (111).
2. The method according to claim 1, characterized in that, The width (115) of the exposed portion (114) of the top surface (113) of the semiconductor (110) fin is at least 5% of the width (116) of the fin.
3. The method according to any one of the preceding claims, characterized in that, The removal of the portion (124) of the mask (120) includes lateral etching of at least a portion of the mask (120).
4. The method according to claim 3, characterized in that, The transverse etching mask (120) includes wet etching.
5. The method according to any one of the preceding claims, characterized in that, The mask (120) includes a first layer (120a) and a second layer (120b), the first layer (120a) being disposed between the top surface (113) of the semiconductor fin (110) and the second layer (120b), wherein removing (15) the portion (124) of the mask (120) includes: removing (15a) a first portion (124a) of the first layer (120a) of the mask (120); and removing (15b) a first portion (124b) of the second layer (120b) of the mask (120); wherein the first portion (124b) of the second layer (120b) of the mask (120) is the portion above the first portion (124a) of the first layer (120a) of the mask (120).
6. The method according to claim 5, characterized in that, The width (115b) of the removed first portion (124b) of the second layer (120b) of the mask (120) is greater than the width (115a) of the removed first portion (124a) of the first layer (120a) of the mask (120).
7. The method according to claim 5 or 6, characterized in that, The removal of the first portion (124a) of the first layer (120a) of the mask (120) (15a) is performed in a first etching process; and the removal of the first portion (124b) of the second layer (120b) of the mask (120) (15b) is performed in a second etching process, which follows the first etching process.
8. The method according to any one of the preceding claims, characterized in that, The oxidation (17) of the exposed portion (114) of the top surface (113) and the first side surface (111) is performed by wet oxidation.
9. The method according to claim 8, characterized in that, The wet oxidation process includes the in-situ steam generation (ISSG) process.
10. The method according to any one of the preceding claims, characterized in that, It also includes conformally coating (20) semiconductor fins (110) with a gate oxide layer (160).
11. The method according to claim 10, characterized in that, The method further includes removing (18) oxides formed during the step of oxidizing the exposed portion (114) of the top surface (113) and the first side surface (111), wherein the removal (18) of the oxides is performed prior to the step of conformally coating (20) the semiconductor fin (110) with the gate oxide layer (160).
12. The method according to claim 10 or 11, characterized in that, The gate oxide layer (160) has a thickness of at least 10 nm.
13. The method according to any one of the preceding claims, characterized in that, in, The length of the fin is at least 100 nm.
14. The method according to any one of the preceding claims, characterized in that, in, The semiconductor fin (110) comprises silicon.
15. The method according to any one of the preceding claims, characterized in that, Also includes: A 3D-NAND memory system (22) is formed on the substrate (102); A word line transistor (24) is formed on the substrate (102), wherein the channel region of the word line transistor includes the semiconductor fin (110).