Iii-n device with parasitic current suppression

Abstract

III-Nitride semiconductor devices including parasitic current suppression are described. In one example, a semiconductor device (200) includes a semiconductor substrate (299) including an active region (204) and an isolation region (203) surrounding the active region (204). The active region (204) includes a source region (215A), a gate region (215B), and a drain region (215D), where the source region (215A), the gate region (215B), and the drain region (215D) extend parallel to each other. A III-N heterojunction structure (297) is disposed on the semiconductor substrate (299), the III-N heterojunction structure (297) including a buffer layer (295) on the semiconductor substrate (299) and a barrier layer (293) on the buffer layer (295). A III-N gate layer (205) is disposed on the barrier layer (293), the III-N gate layer (205) including a gate portion (205A) disposed in the gate region (215B) and a gate extension (207A) extending from the gate portion (205A) to the isolation region (203).

Description

Technical Field

[0001] The disclosed implementation schemes generally relate to the field of III-N group semiconductor devices and their manufacture. Background Technology

[0002] Group III nitride materials (also known as III-N materials) possess a unique combination of physical and electrical properties that have been found to be beneficial to modern microelectronics and optoelectronics. These properties include wide bandgap, high saturation drift velocity and breakdown voltage, high thermal conductivity, and strong chemical and thermal stability. Due to these characteristics, III-N materials are considered promising for fabricating high-power, high-frequency transistors capable of operating at high temperatures and in harsh environments. Despite the rapid progress in III-N devices and their fabrication, several shortcomings remain, necessitating further innovations as described below. Summary of the Invention

[0003] The following is a simplified overview to provide a basic understanding of some examples of this disclosure. This summary is not a broad overview of the examples and is neither intended to identify key or essential elements of the examples nor to depict their scope. In fact, the main purpose of the summary is to present some concepts of this disclosure in a simplified form as a prelude to the more detailed description presented in subsequent sections.

[0004] In one example, a semiconductor device includes a semiconductor substrate comprising an active region and an isolation region surrounding the active region. The active region includes a source region, a gate region, and a drain region, wherein the source region, the gate region, and the drain region extend parallel to each other. A III-N heterojunction structure is disposed on the semiconductor substrate, the III-N heterojunction structure including a buffer layer on the semiconductor substrate and a barrier layer on the buffer layer. A III-N gate layer is disposed on the barrier layer, the III-N gate layer including a gate portion disposed in the gate region and a gate extension extending from the gate portion to the isolation region.

[0005] In one example, a method for manufacturing a III-N semiconductor device is disclosed. The method includes: forming a III-N heterojunction structure on a semiconductor substrate, the semiconductor substrate including an active region and an isolation region surrounding the active region, wherein the active region includes a source region, a gate region, and a drain region, and the source, gate, and drain regions extend parallel to each other; and the III-N heterojunction structure includes a buffer layer on the semiconductor substrate and a barrier layer on the buffer layer; and forming a III-N gate layer on the barrier layer, the III-N gate layer including a gate portion disposed in the gate region and a gate extension extending from the gate portion to the isolation region.

[0006] In one example, a semiconductor device includes a semiconductor substrate comprising an active region and an isolation region surrounding the active region. A III-N heterojunction structure is disposed on the semiconductor substrate, the III-N heterojunction structure including a buffer layer on the semiconductor substrate and a barrier layer on the buffer layer. The semiconductor device includes a first III-N transistor formed in a first portion of the active region, the first III-N transistor including a first source region, a first drain region, and a first gate region, wherein the first source region, the first drain region, and the first gate region extend parallel to each other. The semiconductor device includes a second III-N transistor formed in a second portion of the active region, the second III-N transistor including a second source region, a second drain region, and a second gate region, wherein the second source region, the second drain region, and the second gate region extend parallel to each other. A III-N gate layer is disposed on the barrier layer, wherein the III-N gate layer comprises: a first gate portion disposed in the first gate region; a first gate extension extending from the first gate portion to the isolation region, the first gate extension being close to a terminal portion of the first source region; a second gate portion disposed in the second gate region; and a second gate extension extending from the second gate portion to the isolation region, the second gate extension being close to a terminal portion of the second source region. Attached Figure Description

[0007] In the accompanying figures, embodiments of the present disclosure are shown by way of example and not limitation. Different references to “an” or “one” embodiments in this disclosure do not necessarily refer to the same embodiment, and such references may mean at least one. Furthermore, when a particular feature, structure, or characteristic is described in connection with an embodiment, whether or not it is explicitly described, that feature, structure, or characteristic may be combined with other embodiments.

[0008] To illustrate one or more exemplary embodiments of this disclosure, accompanying drawings are incorporated in and form a part of the specification. Various advantages and features of this disclosure are described in the following detailed description, taking into account the appended claims and the accompanying drawings, in which:

[0009] Figure 1A-1F The layout of a representative GaN device according to some examples of the present disclosure is depicted, wherein one or more gate layer extensions Ⅲ-N are provided to suppress parasitic current paths;

[0010] Figure 2A A partial layout of a GaN device, including one or more III-N gate layer extensions to mitigate current accumulation, is depicted according to an example.

[0011] Figure 2B Depicting Figure 2A The diagram shows a cross-sectional view of the GaN device along a cross-sectional plane passing through the III-N gate layer;

[0012] Figure 2C Depicting Figure 2A The diagram shows a cross-sectional view of the GaN device along a cross-sectional plane passing through the III-N gate layer extension extending into the isolation region; and

[0013] Figure 3 This is a flowchart of a method for manufacturing a semiconductor device comprising one or more GaN devices according to some examples of this disclosure. Detailed Implementation

[0014] Examples of this disclosure are described with reference to the accompanying drawings, in which similar reference numerals are generally used to refer to similar elements. The drawings are not drawn to scale and are provided only to illustrate examples. Numerous specific details, relationships, and methods are set forth below to provide an understanding of one or more examples. However, some examples may be practiced without such specific details. In other instances, well-known subsystems, components, structures, and techniques have not been shown in detail so as not to obscure the understanding of the examples. Therefore, examples of this disclosure may be practiced without such specific components.

[0015] Additionally, terms such as “coupled” and “connected”, and their derivatives, may be used in the following detailed description, claims, or both. These terms are not necessarily intended to be synonyms with each other. “Coupled” can be used to indicate that two or more elements (which may or may not be in direct physical or electrical contact with each other) cooperate or interact with each other. “Connected” can be used to indicate the establishment of communication (i.e., a communication relationship) between two or more elements coupled to each other. Furthermore, in one or more examples set forth herein, generally, if an element can be programmed to perform or otherwise structurally arranged to perform a certain function, then the element, component, or module can be configured to perform said function.

[0016] Without limitation, examples of this disclosure will be set forth below in the context of improving the performance characteristics of semiconductor devices based on group III nitride materials (also known as III-N materials), such as gallium nitride (GaN) devices.

[0017] GaN devices (e.g., GaN transistors) offer certain performance advantages over silicon, including lower on-state resistance (e.g., drain-source resistance or R0). DSONGaN transistors offer advantages such as lower switching losses and improved breakdown voltage. They comprise a heteroepitaxial structure (e.g., a heterojunction structure) with a junction between materials with different bandgap (e.g., aluminum gallium nitride (AlGaN) and gallium nitride) to provide a 2D electron gas (2DEG) formed within the AlGaN / GaN heteroepitaxial structure for device operation (e.g., forming a channel for a GaN device). The 2D electron gas (2DEG) may be referred to as a 2DEG channel. Depletion-mode (DMODE) GaN transistors are typically turned on, while enhancement-mode (EMODE) GaN transistors are typically turned off. In some examples, EMODE GaN transistors comprise a gate stack with a gallium nitride (p-GaN) layer containing a p-type dopant, such as magnesium (Mg) or other suitable p-type dopant. When the p-type dopant is activated, the p-GaN layer may deplete the 2DEG beneath the gate stack under zero or negative gate bias. Applying a positive gate voltage enhances the 2DEG below the gate and turns on the EMODE GaN device to allow current to flow between the source and drain.

[0018] In some examples, GaN devices may have one or more GaN layers formed on a suitable semiconductor substrate, such as a silicon substrate. The one or more GaN layers may form a heterojunction structure on the semiconductor substrate, wherein the p-GaN layer overlays the heterojunction structure to achieve EMODE device functionality. The p-GaN layer may contain an appropriate level of p-type dopant to control the threshold voltage (V) of the GaN device. T or V TH Generally, this is done to reduce the possibility of accidentally turning on the EMODE device, increase operability margins, and reduce leakage current (e.g., in the off state I). DS (e.g., those requiring higher threshold voltages)

[0019] In some examples, the GaN process flow may include an implantation stage for achieving device isolation, where suitable implantation species can be implanted into a defined region of the substrate. The implanted species can impair the crystallinity of the heterojunction structure in the defined region, thereby disrupting or preventing the formation of 2DEG channels in the defined region. Furthermore, the isolation implantation process may impair a portion of the p-GaN layer (e.g., any part of the p-GaN layer undergoing the isolation implantation process), causing said portion of the p-GaN layer to become weakly activated or deactivated. Therefore, the defined region is no longer used to form a GaN device, thus forming an isolation region for isolating the region where a GaN device can be formed (which may be referred to as the active region, active area, device region, or device area). Because the active region is not implanted with isolation implantation species, the crystallinity of the heterojunction structure in the active region is preserved.

[0020] In some arrangements, an isolation region may surround the active region where a GaN device is formed, such as an EMODE transistor containing a p-GaN layer as part of its gate stack. The p-GaN layer may surround the drain region of the EMODE transistor to separate the drain region from the source region. Furthermore, the entire p-GaN layer may be contained within the active region, thereby forming an additional channel region near the terminal portion of the drain region (e.g., in addition to the intended channel region located exactly midway between the source and drain regions that extend parallel to each other). In such arrangements, undesirable current paths (e.g., parasitic current paths) may be created between the terminal portions of the source and drain regions of the device, which can cause current accumulation at the drain region when the device is turned on. Under certain operating conditions, current accumulation can adversely affect device performance, for example, reducing the device's safe operating area (SOA). In some applications, such as power GaN applications, the problem of reduced SOA can be particularly detrimental.

[0021] To overcome current build-up and related performance issues, some arrangements may include isolation regions placed near the source and drain regions to deactivate (e.g., "cut off") any unwanted channel regions outside the source / drain regions (e.g., outside the intended channel region). Therefore, portions of the p-GaN layer may extend beyond the active region and may be subject to isolation implantation processes. Consequently, exposed portions of the p-GaN layer may be damaged (e.g., deactivated) and may lose their ability to block current conduction beneath the p-GaN layer. Therefore, although the risk of current build-up may be reduced in such arrangements due to the absence of an active region outside the intended channel region, in some examples, the deactivated p-GaN portion extending beyond the active region may create parasitic leakage paths between the source and drain regions. Furthermore, these parasitic leakage paths may also affect the VV of the GaN device. T Characterization, and thus affects its quality and reliability assessment.

[0022] The examples of this disclosure recognize the aforementioned challenges and provide solutions to mitigate current accumulation and leakage current problems (collectively referred to as parasitic current problems) in various GaN device configurations using customizable p-GaN layer extensions relative to the active region of the device. For the purposes of this disclosure, the p-GaN layer may be referred to as a III-N gate layer or simply as a gate layer, as illustrated herein with reference to the examples. According to some example arrangements, the III-N gate layer includes a gallium nitride layer containing p-type dopants that can be activated, partially activated (or deactivated), or deactivated. For example, the III-N gate layer may include a first portion having activated p-type dopants (e.g., a portion protected or masked from isolation implantation) and a second portion having deactivated (or partially activated) p-type dopants (e.g., a portion subjected to isolation implantation).

[0023] In some arrangements, one or more gate extensions extending from a portion of the III-N gate layer may be positioned close to a terminal portion of the device source region formed in the active region. In some arrangements, the gate extensions may extend into an isolation region surrounding the active region, wherein the gate extensions may at least partially surround the terminal portion of the source region. In some arrangements, the gate extensions may extend into an isolation region surrounding the active region and beyond the boundary between the isolation region and the active region. Therefore, the gate extensions may be configured to implement a resistive assembly, in some examples, which may be used to block a source-drain leakage path, wherein the isolation region overlaps with at least a portion of the terminal portion of the III-N gate layer near the source region.

[0024] In some additional and / or alternative arrangements where the III-N gate layer is contained within the active region, the gate extension can be configured (e.g., placed, arranged, etc.) to block current accumulation by suppressing parasitic current paths that may be generated in additional channel regions extending beyond the source and drain regions under the III-N gate layer. Furthermore, the formation of the gate extension can be implemented in conjunction with various source / drain contact designs (e.g., continuous contact designs, multi-contact designs, hybrid contact designs, etc.), wherein different configurations of the gate extension can be provided relative to the terminal portions of the source / drain regions in the device layout. While the examples herein may provide various structures, materials, and processes that can produce these and other beneficial effects, no particular result is required unless expressly specified in the specific claims.

[0025] Refer to the diagram. Figure 1A-1F Layouts of representative GaN devices or portions thereof according to some examples of this disclosure are depicted, wherein one or more gate extensions may be provided to suppress unwanted current paths, also known as parasitic current paths. In some examples, unwanted current paths may include leakage paths that may be generated in the device due to a deactivated (or partially activated) gate layer portion extending outside the active region of the device. In some examples, unwanted current paths may include current paths that generate current accumulation via unintended channel regions attributable to a gate layer entirely contained within the active region of the device. For the purposes of this disclosure, the terms "isolation boundary" and "active region boundary" are used interchangeably and may be defined as the interface dividing an isolation region (e.g., a region implanted with a suitable implanted species) from an active region not implanted with isolation implanted species. As will be further explained below, in some arrangements, the isolation implanted species may include species such as argon, silicon, fluorine, and nitrogen. Additionally, an isolation region may be considered as a region in which the crystallinity of the heterojunction structure of the device is impaired or disrupted. Conversely, the active region or area of ​​the device can be considered as a region in which the crystallinity of the heterojunction structure is retained, thereby promoting the formation of channels (e.g., 2DEG).

[0026] Without restrictions, Figure 1A The diagram illustrates a drain-centric bi-finger layout of a GaN device 100A, wherein a first III-N transistor 102A (also referred to as a first device finger) and a second III-N transistor 102B (also referred to as a second device finger) are formed in or above an active region or region 104 surrounded by an isolation region or region 103. As shown, an isolation boundary 179 divides the active region 104 from the isolation region 103. In some examples, the active region 104 may be formed as part of a common III-N epitaxial stack layer containing a heterojunction structure configured to support a plurality of GaN devices separated by isolation regions in a semiconductor device, but this is for illustrative purposes herein and is not required to be so. As a drain-centric design, an example III-N transistor or device finger (or simply "finger" in some examples) may include a source disposed in a source region, a drain disposed in a drain region, and a gate disposed in a gate region between the source and drain regions, wherein the III-N gate layer may be patterned to form a raceway or elongated oval structure surrounding the drain region. Thus, the source, gate, and drain regions of the III-N transistor may extend parallel to each other in the active region of the device. Furthermore, the raceway structure of the gate layer may include a first portion (e.g., a straight portion) and a second portion (e.g., a straight portion), which are coupled to each other through suitable gate segments at each end to form a closed-loop structure. In a two-finger configuration, two III-N transistors may share a common source region disposed between two corresponding raceway gate layer structures. As will be explained below, the two raceway gate layer structures of the two III-N transistors may be coupled to each other near the terminal portion of the common source region using corresponding gate bridge portions, which have suitable form factors for the purposes of some examples herein.

[0027] For example, the first III-N transistor 102A includes a drain 110A, a source 106A, and a common source 112 shared by the first and second III-N transistors 102A and 102B. Similarly, the second III-N transistor includes a drain 110B, a source 106B, and a common source 112. The gate layer 199 may be patterned to include linear gate portions 108A-1 and 108A-2 relative to the first III-N transistor 102A, and linear gate portions 108B-1 and 108B-2 relative to the second III-N transistor 102B. For some example purposes, the linear gate portions 108A-1 / 108A-2 and 108B-1 / 108B-2 may be referred to as the first, second, third, or fourth gate portions, but unless otherwise indicated, no particular order, sequence, or correspondence with a particular gate portion is implied. Although the sources 106A, 106B, drains 110A, 110B, and common source 112 are shown as corresponding consecutive contacts, this is not required. Furthermore, although the sources 106A / 106B, drains 110A / 110B, common source 112, and linear gate portions 108A-1 / 108A-2 and 108B-1 / 108B-2 of the semiconductor device 100A are located in the corresponding source region, drain region, common source region, and gate region of the active region 104, these regions are not specifically shown in the figures for clarity.

[0028] In some embodiments, gate portions 108A-1 and 108A-2 and gate portions 108B-1 and 108B-2 can be coupled to each other via corresponding gate segments 197-1 to 197-4 having, for example, an arcuate shape, thereby forming a closed loop relative to each III-N transistor 102A, 102B. In this way, gate layer 199 can form a closed-loop raceway structure surrounding the corresponding drains 110A, 110B. For the purposes of some examples, gate segments 197-1 to 197-4 may be referred to as first, second, third, or fourth gate segments, but unless otherwise indicated, no particular order, sequence, or correspondence with a particular gate segment is implied.

[0029] exist Figure 1A In the example, III-N transistors 102A and 102B are disposed in corresponding portions of the active region 104 (e.g., the first and second portions, in...). Figure 1A (Not specifically shown in the text). Regarding the first III-N transistor 102A, the corresponding portion of the active region 104 can be considered to include the following regions: a first source region having a source 106A, a first drain region having a drain 110A, and a first gate region having a gate portion 108A-1, wherein the first gate region is disposed on a first side of the first drain region. As mentioned above, the first source, first drain, and first gate regions may, for example, extend parallel to each other along the Y-axis.

[0030] Similarly, the active region 104, relative to the corresponding portion of the second III-N transistor 102B, can be considered to include the following regions: a second source region having a source 106B, a second drain region having a drain 110B, and a second gate region having a gate portion 108B-1, wherein the second gate region is disposed on a first side of the second drain region. Furthermore, the second source, second drain, and second gate regions can, for example, extend parallel to each other along the Y-axis.

[0031] Due to the closed-loop configuration of the gate layer 199, the first III-N transistor 102A further includes a third gate portion 108A-2 disposed in a third gate region, which is located on a second side (e.g., opposite to the first side) of the first drain region containing the first drain 110A. Similarly, the second III-N transistor 102B further includes a fourth gate portion 108B-2 disposed in a fourth gate region, which is located on a second side (e.g., opposite to the first side) of the second drain region containing the second drain 110B.

[0032] exist Figure 1A In the example, the isolation boundary 179 is depicted as extending across curved gate segments 197-1 to 197-4, for example, to suppress current accumulation. Therefore, curved gate segments 197-1 to 197-4 include the deactivated (or weakly activated) portion of the gate layer 199. In some additional and / or alternative arrangements, the gate layer 199 of the bi-finger GaN device 100A may be placed entirely within the active region 104, as will be further explained below. Regardless of how the III-N gate layer is arranged in a particular design, the gate layer 199 may have one or more segments, protrusions, extensions, components, etc., collectively referred to herein as gate extensions. Such gate extensions may extend (or partially enter) the isolation region 103 at appropriate locations within the GaN device 100A to block the formation of unwanted current paths, as will be explained below.

[0033] In some arrangements, gate contacts or electrodes with a continuous contact design may be formed relative to each III-N transistor 102A, 102B, wherein the gate contacts may have a width 150 and a length 195 based on the width of the III-N transistors 102A, 102B. As shown, gate contacts 109A-1 and 109A-2 are coupled to gate portions 108A-1 and 108B-2 relative to the first III-N transistor 102A, respectively. Similarly, gate contacts 109B-1 and 109B-2 are coupled to gate portions 108B-1 and 108B-2 relative to the second III-N transistor 102B, respectively. To suppress source / drain leakage current paths near the isolation boundaries 179 of the gate segments 197-1 to 197-4 (e.g., below) which are deactivated due to isolation implantation, the gate layer 199 of the GaN device 100A includes gate extensions 152-1 to 152-6 at various suitable locations. For example, gate extensions 152-1 to 152-6 can be configured as terminal portions close to the corresponding source (e.g., source contact or source region) of the GaN device 100A. In this way, the gate extensions can block parasitic current paths between the source terminal portion and the adjacent drain terminal portion, thereby providing a high-resistance region therebetween in the event that the gate extensions deplete the 2DEG below the gate extensions.

[0034] For example, a gate extension 152-1 extending from the gate portion 108B-1 to (or partially into) the isolation region 103 is formed as an extension adjacent to the terminal portion 106B-1 (which may be referred to as the source terminal portion) associated with the source 106B, which is disposed in the previously mentioned corresponding source region. The gate extension 152-1 can be used to block the leakage current path between the source terminal portion 106B-1 of the III-N transistor 102B and the corresponding adjacent terminal portion 110B-1 (which may be referred to as the drain terminal portion) associated with the drain 110B (e.g., by depleting the 2DEG under the gate extension 152-1). Similarly, a gate extension 152-2 is formed as an extension from the gate portion 108B-1 adjacent to the source terminal portion 106B-2 to block the leakage current path between the source terminal portion 106B-2 of the III-N transistor 102B and the corresponding adjacent drain terminal portion 110B-2. Similarly, gate extensions 152-5 and 152-6 extending into (or partially entering) the isolation region 103 may be formed relative to the III-N transistor 102A to suppress leakage current paths between corresponding terminal portions 106A-1, 106A-2 associated with the source 106A and corresponding adjacent terminal portions 110A-1, 110A-2 associated with the drain 110A.

[0035] Regarding the suppression of leakage current paths between the common source 112 and the drains 110A and / or 110B, some examples may be provided by gate extensions 152-3 and 152-4 extending between gate portions 108A-2 and 108B-2, also referred to herein as bridge portions. In this way, each bridge portion surrounds and electrically isolates the corresponding terminal portions 112-1, 112-2 associated with the common source 112, for example, to provide a high-resistance region near the corresponding terminal portion in the event that the bridge portion depletes the 2DEG under the bridge portion.

[0036] According to the embodiments, the shape and / or size of the gate extension according to the examples herein can vary, as long as the source terminal portion of the GaN device is blocked by a gate extension of suitable shape and / or size, wherein the gate extension extends to or overlaps with at least one edge (e.g., an isolation boundary) of the active region near the source terminal portion. For the purposes of this disclosure, the source terminal portion (or source region terminal portion) may refer to or include a terminal portion of the source contact and / or a terminal portion of the source region containing the source contact. Similarly, the drain terminal portion (or drain region terminal portion) may refer to or include a terminal portion of the drain contact and / or a terminal portion of the drain region containing the drain contact.

[0037] For example, gate extension 152-1 in Figure 1A The gate extension 152-1 is depicted as a rectangular extension relative to the source terminal portion 106B-1, extending at least along (or across) the isolation boundary 179 in a first direction of the device layout (e.g., aligned to the X-axis), but not along a second direction orthogonal to the first direction (e.g., aligned to the Y-axis) to the isolation boundary 179. In some examples, the gate extension 152-1 may have a regular quadrilateral shape (e.g., a square) that may extend in both the X and Y axes and overlap or coincide with the isolation boundary 179 along these two axes to provide stronger blocking capability. Generally, the larger the gate extension, the stronger its ability to block or suppress parasitic current paths associated with the source terminal portion (or drain terminal portion), for example, the larger the 2DEG depletion region.

[0038] Similarly, gate extensions 152-2, 152-5, and 152-6 may extend to the isolation boundary 179, respectively, near terminal portions 106B-2 (associated with source 106B) and 106A-1 and 106A-2 (associated with source 106A). Furthermore, in some arrangements, gate extensions surrounding terminal portions 112-1 and 112-2, respectively, associated with the common source 112, i.e., bridge portions 152-3 and 152-4, may also extend (e.g., along the Y direction) to overlap with the isolation boundary 179. Generally, the size and / or shape of the III-N gate extensions can vary, provided that each extension has an appropriate size and / or shape to extend to and / or overlap with the isolation boundary without violating applicable critical dimension (CD) design rules.

[0039] In some additional and / or alternative arrangements, one or more gate extensions 152-1 to 152-6 may be provided with or coupled to suitable contact structures, such as gate contacts or electrodes. Therefore, stronger blocking capability can be obtained in GaN devices by providing additional gate control. In some additional and / or alternative arrangements, the source and drain regions of the GaN device may be provided with multiple contacts or a multi-contact design, instead of... Figure 1A The continuous contact design is shown. In yet another arrangement, the entire gate layer of the GaN device may be surrounded within the active region of the GaN device, such that no gate portion or segment is exposed to the isolation implant. Therefore, in such an arrangement, the gate layer may not contain any deactivated gate portion or segment. Examples of some of the above variations are described below for the purposes of this disclosure.

[0040] Figure 1B An example two-finger layout of GaN device 100B is depicted, wherein, in addition to the gate contact associated with the corresponding III-N transistor of GaN device 100B, each gate extension is coupled with at least one additional gate contact. As shown, GaN device 100B and Figure 1AThe GaN device 100A shown is identical except for the additional gate contacts provided in the gate extensions 152-1 to 152-6. Therefore, unless otherwise mentioned herein, the description of the GaN device 100A also applies to the GaN device 100B. In addition to the gate contacts 109A-1 and 109A-2 associated with the III-N transistor 102A and the gate contacts 109B-1 and 109B-2 associated with the III-N transistor 102B, gate contacts 154-1, 154-2, 154-7, and 154-8 are also coupled to the gate extensions 152-1, 152-2, 152-5, and 152-6, respectively. Furthermore, in the example arrangement, the bridge portions 152-3 and 152-4 for blocking the parasitic current path associated with the common source 112 may each have one or more additional gate contacts, while satisfying the applicable CD design rules. Figure 1B As shown in the example, bridge portion 152-3 is coupled to two gate contacts 154-3 and 154-4, and bridge portion 152-4 is coupled to two contacts 154-5 and 154-6.

[0041] Figure 1C An example bifinite layout of a GaN device 100C, comprising a multi-contact design for both the source and drain, is depicted, wherein an enlarged gate extension may overlap with an isolation boundary and extends at least partially above the isolation region at the corresponding location. Furthermore, Figure 1C The document also illustrates a continuous gate contact structure for coupling gate contact extensions to corresponding gate extensions in the GaN device 100C. As described, unless otherwise mentioned herein, the GaN device 100C is similar to... Figure 1A The GaN device 100A is shown. Therefore, the description of the GaN device 100A above also applies to the GaN device 100C with appropriate variations as described below. For example, III-N transistors 102A and 102B each have a corresponding plurality of source contacts 106A(N), 106B(N) and a corresponding plurality of drain contacts 110A(M) and 110B(M). Similarly, in some arrangements, the GaN device 100C may include a plurality of common source contacts 112(N). Although in the example layout, the drain contacts of the III-N transistors may be located in the drain region and extend beyond the source region having the corresponding source contacts by a distance, this is not required. Furthermore, the drain contacts (e.g., drain contact 110A(M)) and source contacts (e.g., source contact 106A(N)) may include different numbers of contacts and may be arranged in various ways depending on the implementation, including in some arrangements incorporating a continuous contact design.

[0042] Similar to Figure 1B The gate extensions 152-1 to 152-6 shown are... Figure 1CThe illustrated GaN device 100C includes gate extensions 153-1 to 153-6 extending from different gate portions of the gate layer 199, but the gate extensions 153-1 to 153-6 are enlarged to extend beyond the isolation boundary 179 at appropriate locations relative to the source contacts 106B(N), 112(N), and 106A(N). Furthermore, in the example arrangement, the closed-loop continuous gate contact structure 177 includes gate contact extensions 155-1 to 155-6 coupled to the respective gate extensions 153-1 to 153-6.

[0043] Figure 1D An exemplary two-finger layout of a GaN device 100D according to the examples herein is depicted, wherein the III-N gate layer is surrounded within an isolation boundary, but the gate extension may be extended to overlap the isolation boundary at the appropriate location. Figure 1D As shown in the examples, unless otherwise mentioned herein, similar to Figure 1A In one example, the gate layer 199, comprising curved gate segments 197-1 to 197-4, is surrounded by an isolation boundary 179. In some arrangements, gate extensions 157-1 to 157-6, similar to gate extensions 152-1 to 152-6, may be provided at appropriate locations relative to the source terminal portions, as previously described. Therefore, when the GaN device 100D is turned off, there may be no leakage current path because no gate portion near the source terminal portions is deactivated by the isolation implant. However, when the GaN device 100D is under certain operating conditions, such as when the gate is turned on using a threshold voltage sufficient to establish the desired channel region exactly midway between the source and drain regions (e.g., across a channel length along the X-axis) but insufficient to form an additional channel region near the source terminal portions, the gate extensions 157-1 to 157-6 can be used to block current accumulation at the drain terminal portions.

[0044] Figure 1E and 1F Partial layouts of GaN devices 100E and 100F in a bi-finger device configuration similar to some of the examples described above are depicted. Similar to where the III-N gate layer 199 is included within the active region 104. Figure 1D Example, Figure 1E The example depicts a III-N gate layer 199' also contained within the active region 104, except for the frame-end gate segment configuration, as mentioned herein. For example, gate segments 197-2' and 197-4' connecting the linear gate portions 108A-1 and 108A-2 with the linear gate portions 108B-1 and 108B-2 are depicted as rectangular frame-end structures, rather than... Figure 1DThe curve segments 197-2 and 197-4 are shown. Furthermore, compared to GaN device 100D, the drains 110A' and 110B' of GaN device 100E extend beyond the corresponding sources 106A and 106B and the common contact 112 by a suitable distance. For example, the drain 110A' of the first III-N transistor 102A of GaN device 100E extends beyond the source 106A of the first III-N transistor 102A by a distance D1. Similarly, the drain 110B' of the second III-N transistor 102B of GaN device 100E extends beyond the source 106B of the second III-N transistor by a distance D2, which may be the same as or different from D1.

[0045] Similar to GaN device 100D, GaN device 100E also includes gate extensions 157-6' and 157-2', which extend from the straight gate portions 108A-1 and 108B-1 to (or across) the isolation boundary 179, respectively. Similarly, GaN device 100E also includes a bridge portion 157-4' disposed between the straight gate portions 108A-2 and 108B-2. Therefore, current accumulation near the drain terminal portions 110A-2' and 110B-2' is reduced in GaN device 100E, similar to GaN device 100D. Although for clarity, Figure 1E The example does not show a gate electrode or gate electrode extension, but the GaN device 100E may include gate electrodes coupled to the straight gate portions 108A-1 / 108A-2 and 108B-1 / 108B-2, and gate electrode extensions 157-6' and 157-2' coupled to the gate layer 199' and the bridge portion 157-4'. In some arrangements, the gate extensions 157-2' and 157-6' may extend along the Y-axis such that they form a single piece connected to the frame gate segments 197-4' and 197-2'.

[0046] Figure 1F The GaN device 100F shown is similar to some of the examples described above, wherein at least a portion of the gate layer may be disposed outside the active region. For example, the gate segments 197-2' and 197-4' connecting the linear gate portions 108A-1 and 108A-2 with the linear gate portions 108B-1 and 108B-2, respectively, are depicted as rectangular frame-like end structures extending over the isolation region 103, such as those similar to... Figure 1A-1C The curve segments 197-2 and 197-4 are shown. On the other hand, the drains 110A' and 110B' of the GaN device 100F are depicted extending beyond the corresponding source 106A and 106B and the common contact 112 by a suitable distance, for example, distances D1 and D2, similar to... Figure 1EExample. The gate layer 199' of GaN device 100F includes gate extensions 153-2' and 153-6' and a bridge portion 153-4', which extend beyond the isolation boundary 179, similar to Figure 1C The example shown. Therefore, the risk of a parasitic leakage path between the source and drain regions due to the deactivated (or weakly activated) gate portion in isolation region 103 can be mitigated in a similar manner by the gate extensions 153-2' and 153-6' and the bridge portion 153-4'.

[0047] Furthermore, the gate extensions 153-2' and 153-6' and the bridge portion 153-4' can also be used to reduce current accumulation near the drain terminal portions 110A-2' and 110B-2' in the GaN device 100F, similar to the GaN device 100E. Although for clarity, Figure 1F The example does not show a gate electrode or gate electrode extension, but the GaN device 100F may include gate electrodes coupled to the straight gate portions 108A-1 / 108A-2 and 108B-1 / 108B-2, and gate electrode extensions 153-2' and 153-6' coupled to the gate layer 199' and the bridge portion 153-4'.

[0048] Figure 2A Partial layouts of GaN devices in a single-finger configuration according to some other examples of this disclosure are depicted, including one or more gate extensions to mitigate parasitic current problems. As shown, an example drain-centric GaN device 200 may include an active region 204 surrounded by an isolation region 203, wherein an isolation boundary 279 is disposed between the active region 204 and the isolation region 203. The active region 204 includes a gate region (in Figure 2A The closed-loop III-N gate layer 205 (not shown) includes linear gate portions 205A and 205B joined via end cap portions 205C. A plurality of drain contacts 208(M) are disposed in the drain region surrounded by the closed-loop gate layer 205 (in...). Figure 2A (Not shown in the image). Correspondingly, multiple source contacts 206(N) are positioned in the corresponding source regions (in...). Figure 2A In the diagram (not shown), the corresponding source region extends parallel to the corresponding linear gate portions 205A, 205B (e.g., along the Y-axis).

[0049] For example, Figure 2AThe diagram shows a series of gate contacts or electrodes 210 coupled to the gate layer 205. Although, for example, the drain contact 208(M) extends beyond the source contacts 206(N) disposed along both sides of the straight gate portions 205A, 205B by a distance D3, this is not required, as previously mentioned. To suppress unwanted current accumulation paths between the source region terminal portions containing, for example, source contacts 206(1) and the drain region terminal portions containing, for example, drain contacts 208(1)-208(3) disposed beyond the terminal source contacts 206(1), gate extensions 207A, 207B are provided close to the respective source region terminal portions. In some arrangements, the gate extensions 207A, 207B may include rectangular protrusion structures extending into the isolation region 203, for example, connected to the isolation boundary 279. In some arrangements... Gate extensions 207A and 207B may extend beyond isolation boundary 279, for example, across or over at least a portion of isolation region 203. Although gate extensions 207A and 207B are shown to have the same form factor, for example, each having a length 263 (e.g., along the X-axis) and a width 261 (e.g., along the Y-axis), this is not required. Furthermore, gate extensions 207A and 207B may extend along gate layer 205 and beyond its end cap portion 205C, such that they form a single frame-type end gate extension which, in some arrangements, extends into (or partially enters) isolation region 203 in both the X and Y directions. As described above, for the purposes of some examples herein, gate extensions 207A and 207B may be arranged individually or as a single extension structure in various spatial configurations.

[0050] Despite Figure 2A The examples illustrate multi-contact designs with respect to source contact 206(N) and drain contact 208(M), respectively, where drain contact 208(M) extends beyond source contact 206(N), but this is not required, as mentioned above. Furthermore, some examples may include multiple gate contacts coupled to gate layer 205 at specific locations (e.g., in end cap portion 205C), rather than having... Figure 2A The continuous gate contact 210 is shown. Additionally, some examples may include gate contacts or gate contact extensions coupled to gate extensions 207A, 207B, as previously described. Additional and / or alternative contact layout configurations that may be combined with the examples of gate extensions taught herein can be found in U.S. Patent Application Publication 2022 / 0231156, which is incorporated herein by reference in its entirety for all purposes.

[0051] Figure 2B Depicting and Figure 2AThe layout of the GaN device 200 shown is a cross-sectional view of the GaN device along the cross-sectional plane of the straight portion 205A, 205B of the gate layer 205 excluding the gate extension. Figure 2C A cross-sectional view of the GaN device 200 along a cross-sectional plane passing through the gate extensions 207A and 207B is depicted, configured to suppress parasitic current accumulation paths, as described above. Reference Figure 2A-2C The following section provides additional details about the GaN device 200, which includes gate extensions 207A and 207B, based on some examples.

[0052] like Figure 2B and 2C As depicted herein, a GaN device 200 is formed on a portion of a semiconductor substrate 299, which may be a silicon wafer, a silicon-on-sapphire wafer, or a silicon carbide wafer, and / or a semiconductor substrate comprising a core configured to match the coefficient of thermal expansion (CTE), etc. A buffer layer 295 is formed on the substrate 299 and may comprise one or more layers of III-N semiconductor material. In some examples where the substrate 299 is implemented as a silicon wafer or a sapphire wafer, the buffer layer 295 may comprise a nucleation layer stoichiometrically containing aluminum to match the lattice constant of the substrate 299. In some examples, the buffer layer 295 may further comprise aluminum gallium nitride (AlGaN) layers / sublayers with decreasing aluminum content, and in some arrangements, unintentionally doped (UID) GaN sublayers are included. For the purposes of this example, the individual layers / sublayers of the buffer layer 295, for example, are... Figure 2B and 2C It is not specifically shown in the text.

[0053] According to the implementation scheme, the buffer layer 295 may have a thickness of about 1 micrometer (µm) to several micrometers (e.g., 3.5 µm to 7.0 µm), which can be formed by a suitable epitaxial process, such as a metal-organic vapor phase epitaxy (MOVPE) process (also known as organometallic vapor phase epitaxy (OMVPE) or metal-organic chemical vapor deposition (MOCVD)), in which several successive steps can be performed to form various constituent layers and / or sublayers. In some arrangements, the example buffer layer 295 may therefore comprise a stack of multiple layers / sublayers having the suitable materials and compositions mentioned above (e.g., GaN, AlGaN, etc.), wherein the layers / sublayers may have variable thicknesses depending on the technology and apparatus application. In some arrangements, the buffer layer 295 may comprise an AlGaN-based transition layer, an epitaxial layer with a strained layer superlattice (SLS) structure, and so on.

[0054] A buffer layer 295 can be formed on a region of the substrate 299, in which different regions such as a source region, a gate region, a drain region, and a drain access region between the gate and drain regions can be disposed relative to the GaN device 200. Due to the symmetrical nature of the drain-centric design, the gate region and the source region can be disposed on both sides of the common drain region of the GaN device 200. As depicted, source region 215A, gate region 215B, common drain region 215D, and drain access region 215C are specifically shown on one side of the GaN device 200, with corresponding regions also disposed on the other side of the common drain region 215D. Source region 215A can be considered to include the source access region (…). Figure 2B-2C (Not specifically shown), it can refer to the region between the source contact or a set of source contacts (e.g., source contact 206) and the gate region 215B, similar to the drain access region 215C. A channel layer can be provided as part of a buffer layer 295, for example, the top portion of the buffer layer 295 near the barrier layer 293. Although the channel layer may primarily comprise GaN material, in some embodiments, optional trace amounts of other Group III elements, such as aluminum or indium, may be present.

[0055] A barrier layer 293, comprising a III-N semiconductor material, is formed on top of a buffer layer 295 via a suitable epitaxial process. In an example arrangement, the barrier layer 293 may have a thickness ranging from about 1 nanometer (nm) to about 60 nm and may contain aluminum and nitrogen. In some versions of this example, the barrier layer 293 may contain gallium with an atomic percentage lower than aluminum. In some versions, the barrier layer 293 may also contain indium. In some examples, the barrier layer 293 contains an AlGaN layer.

[0056] The barrier layer 293 above the buffer layer 295 can be used as part of the heterojunction structure 297 to form a 2DEG (e.g.,) near the interface between the barrier layer 293 and the buffer layer 295. Figure 2B and 2C (As shown in 2DEG 289). In some examples, the stoichiometry and thickness of the barrier layer 293 can be configured to provide a suitable free carrier density (e.g., 3 × 10⁻⁶). 12 cm −2 Up to 2×10 13 cm −2 ) 2DEG, in order to facilitate device operation.

[0057] For the purpose of implementing the EMODE function, such as Figure 2BAs shown, a patterned p-doped III-N layer, such as gate layer 205, is formed over the barrier layer 293 in gate region 215B. In some examples, gate layer 205 may include one or more III-N material layers and may also be referred to as a p-III-N layer or a p-GaN layer, as described above. In some examples, gate layer 205 may contain approximately 1 × 10⁻⁶ g / L g. 17 From atoms per cubic centimeter to 1×10 21 The p-doped concentration is 1 atom / cm³ (e.g., Mg), and it can have a thickness of about 10 nm to 200 nm. As a result of patterning the gate layer 205 (e.g., removing a portion of the gate layer 205 outside the gate region 215B), 2DEG 289 can be formed in the channel layer outside the gate region 215B.

[0058] In some additional and / or alternative arrangements, an additional layer such as an AlGaN capping layer of about 4 nm to 10 nm (e.g., without p-doping) and / or a low-pressure chemical vapor deposition (LPCVD) silicon nitride (SiN) capping layer of about 10 nm to 20 nm may optionally be provided above the gate layer 205, which are in Figure 2A-2C It is not specifically shown in the text.

[0059] Suitable device isolation steps can be implemented to provide an isolation region relative to the GaN device 200. Depending on the embodiment, the isolation step may include implanting a suitable implant species to define a region, such as isolation region 203, where the crystallinity of the heterojunction structure 297 in isolation region 203 is impaired or otherwise damaged, resulting in increased resistance. Therefore, in isolation region 203 surrounding the active region 204 of the GaN device 200, 2DEG 289 is absent, removed, or otherwise destroyed. In some examples, argon implantation with energies between 100 keV and 300 keV can be performed, with an implantation dose of 1 × 10⁻⁶. 14 ions / cm² to 1×10⁻⁶ 16 One ion per square centimeter is used to achieve device isolation. In additional and / or alternative examples, other implanted species such as silicon, fluorine, and nitrogen can also be used as isolation implanted species.

[0060] like Figure 2B and 2CAs shown, a dielectric layer stack 291 comprising one or more dielectric layers is also formed on the heterojunction structure 297. According to embodiments, the dielectric layer stack 291 may comprise one or more SiN layers formed by LPCVD / PECVD processes, some of which may serve as surface passivation layers. In some additional and / or alternative arrangements, the dielectric layer stack 291 may comprise different materials, such as silicon dioxide (SiO2), silicon oxynitride (SiON), aluminum oxide (Al2O3), etc., and may be formed using other techniques such as ALD. The source contact 206, drain contact 208, and gate contact 210 of the GaN device 200 may be formed by a gate-before-gate process (e.g., where the source / drain contacts are formed after the gate stack is formed) or a gate-after-gate process (e.g., where the source / drain contacts are formed before the gate stack is formed).

[0061] During the formation of gate layer 205, the linear gate portions 205A and 205B and the end cap portion 205C can be appropriately patterned to form a closed-loop structure, wherein the linear gate portions 205A and 205B can be used as part of a gate stack to implement EMODE device functionality, as previously described. According to the examples herein, the patterning of gate layer 205 may also include forming Figure 2A and 2C The gate extensions 207B, 207B shown extend into the isolation region 203, wherein the gate extensions 207A, 207B are positioned close to the source region terminal portion, for example, including the source contact 206(1). Although in some arrangements (e.g., as...) Figure 2A and 2C As shown in the diagram, gate extensions 207A and 207B may not contain contact structures, but additional and / or alternative arrangements may include auxiliary or additional contact structures coupled to gate extensions 207A and 207B, such as gate contacts, gate contact extensions, etc.

[0062] Figure 3 This is a flowchart of a method 300 for manufacturing a semiconductor device including a GaN device according to some examples of this disclosure. In one arrangement, method 300 may begin by forming a III-N heterojunction structure on a semiconductor substrate, the semiconductor substrate including an active region and an isolation region surrounding the active region, wherein the active region includes a source region, a gate region, and a drain region, as illustrated at block 302. As previously stated, the source, gate, and drain regions extend parallel to each other. Furthermore, the III-N heterojunction structure includes a buffer layer on the semiconductor substrate and a barrier layer on the buffer layer. At block 304, a III-N gate layer is formed on the barrier layer, the III-N gate layer including a gate portion disposed in the gate region and a gate extension extending from the gate portion to the isolation region. In an example arrangement, the gate extension is disposed as a terminal portion adjacent to the source region.

[0063] Although various examples of this disclosure have been described above, these examples are presented by way of example only and not as limiting. Numerous changes may be made to the disclosed examples in accordance with the disclosure herein without departing from the spirit or scope of this disclosure. Therefore, the breadth and scope of this disclosure should not be limited to any of the examples described above. In fact, the scope of this disclosure should be defined by the appended claims and their equivalents.

[0064] For example, in this disclosure and the appended claims, unless otherwise stated and / or specified to the contrary, any one or more layers set forth herein may be formed in any number of suitable manners, such as using spin coating, sputtering (e.g., magnetron and / or ion beam sputtering), (thermal) growth techniques, or deposition techniques such as chemical vapor deposition (CVD), physical vapor deposition (PVD), low-pressure CVD (LPCVD), plasma-enhanced CVD (PECVD), or atomic layer deposition (ALD). As another example, silicon nitride may be silicon-rich silicon nitride or oxygen-rich silicon nitride. Silicon nitride may contain some oxygen, but not so much that the dielectric constant of the material is significantly different from that of high-purity silicon nitride.

[0065] Additionally, in at least some additional or alternative embodiments, the functions / actions described in the boxes may not occur in the order shown in the flowchart. For example, depending on the functionality / action involved, two boxes shown consecutively may actually be performed substantially simultaneously, or the boxes may sometimes be performed in reverse order. Furthermore, the functionality of a given box in a flowchart and / or block diagram may be divided into multiple boxes, and / or the functionality of two or more boxes in a flowchart and / or block diagram may be at least partially integrated. Additionally, some boxes in the flowchart may optionally be omitted. Furthermore, although some diagrams include arrows on communication paths to show the main direction of communication, it should be understood that communication may occur in the opposite direction to the depicted arrows. Finally, additional boxes may be added / inserted between the shown boxes.

[0066] The order or sequence of actions, steps, functions, components, or blocks shown in any of the flowcharts and / or block diagrams depicted in the accompanying drawings of this disclosure may be modified, altered, replaced, customized, or otherwise rearranged within a particular flowchart or block diagram, including the deletion or omission of specific actions, steps, functions, components, or blocks. Furthermore, actions, steps, functions, components, or blocks shown in a particular flowchart may be mixed with or otherwise arranged or rearranged with actions, steps, functions, components, or blocks shown in another flowchart to achieve additional changes, modifications, and configurations relative to one or more processes for the purpose of practicing the teachings of this disclosure. Similarly, although various examples have been set forth herein, not all features of a particular example are necessarily limited thereto and / or therefore necessary.

[0067] At least some of the foregoing description may contain specific directional terms such as “upper,” “lower,” “top,” “bottom,” “left,” “right,” “front,” “rear,” “vertical,” “horizontal,” etc., which may be used with reference to the orientation of some of the described figures or their illustrative elements. Since some example components may be positioned in several different orientations, the directional terms are used for illustrative purposes and are by no means limiting. Similarly, references to features referred to as “first,” “second,” etc., do not indicate any particular order, importance, etc., and such references are interchangeable depending on the context, implementation, etc. Furthermore, terms such as “above,” “below,” “under,” etc., relative to the spatial orientation of two components do not necessarily mean that one component is adjacent to or directly above another component, or that one component is adjacent to or directly below another component. Additionally, unless otherwise specifically indicated, the features and / or components of the examples described herein may be combined with each other.

[0068] Although various embodiments have been shown and described in detail, the claims are not limited to any particular embodiment or example. The specific embodiments described above should not be construed as implying that any particular component, element, step, action, or function is essential to the scope of the claims. Where phrases such as “at least one of A and B” or similar phrases are used, such phrases should be understood to mean “only A, only B, or both A and B.” Unless explicitly stated otherwise, references to singular elements are not intended to mean “one and only one,” but rather “one or more.” Similarly, depending on the context, phrases such as “a plurality” or “multiple” may mean “one or more” or “at least one.” All structural and functional equivalents of the elements of the embodiments described above are expressly incorporated herein by reference and are intended to be covered by the appended claims.

Claims

1. A semiconductor device, comprising: A semiconductor substrate includes an active region and an isolation region surrounding the active region, the active region including a source region, a gate region and a drain region, wherein the source region, the gate region and the drain region extend parallel to each other; A III-N heterojunction structure is disposed on the semiconductor substrate, the III-N heterojunction structure comprising a buffer layer on the semiconductor substrate and a barrier layer on the buffer layer; as well as A III-N gate layer, situated above the barrier layer, the III-N gate layer comprising: A gate portion, which is disposed in the gate region; as well as A gate extension that extends from the gate portion into the isolation region.

2. The semiconductor device of claim 1, wherein the gate extension is disposed as a terminal portion close to the source region.

3. The semiconductor device according to claim 1, further comprising: A gate electrode coupled to the gate portion.

4. The semiconductor device according to claim 3, further comprising: A gate electrode extension that extends from the gate electrode and is coupled to the gate extension.

5. The semiconductor device of claim 1, wherein the gate portion is a first gate portion, and the III-N gate layer further includes a second gate portion extending from the first gate portion, the first and second gate portions at least partially surrounding the terminal portion of the drain region.

6. The semiconductor device of claim 5, wherein a segment of the second gate portion is disposed over the isolation region and implanted with an isolation implantation species, including at least one of argon, silicon-fluorine, and nitrogen.

7. The semiconductor device of claim 5, wherein the second gate portion is disposed over the active region.

8. The semiconductor device of claim 1, wherein the gate extension extends over at least a portion of the isolation region.

9. The semiconductor device of claim 8, wherein a portion of the gate extension is implanted with an isolation implantation species, including at least one of argon, silicon, and nitrogen.

10. A semiconductor device, comprising: A semiconductor substrate comprising an active region and an isolation region surrounding the active region; A III-N heterojunction structure is disposed on the semiconductor substrate, the III-N heterojunction structure comprising a buffer layer on the semiconductor substrate and a barrier layer on the buffer layer; A first III-N transistor is formed in a first portion of the active region. The first III-N transistor includes a first source region, a first drain region, and a first gate region, wherein the first source region, the first drain region, and the first gate region extend parallel to each other. A second III-N transistor is formed in a second portion of the active region. The second III-N transistor includes a second source region, a second drain region, and a second gate region, wherein the second source region, the second drain region, and the second gate region extend parallel to each other. as well as A III-N gate layer is disposed above the barrier layer, the III-N gate layer comprising: A first gate portion is disposed in the first gate region; A first gate extension extends from the first gate portion to the isolation region, and the first gate extension is close to the terminal portion of the first source region; The second gate portion is disposed in the second gate region; as well as A second gate extension extends from the second gate portion to the isolation region, and the second gate extension is close to the terminal portion of the second source region.

11. The semiconductor device of claim 10, further comprising: A first gate electrode, which is coupled to the first gate portion; A first gate electrode extension extends from the first gate electrode and is coupled to the first gate extension; A second gate electrode, coupled to the second gate portion; and A second gate electrode extension extends from the second gate electrode and is coupled to the second gate extension.

12. The semiconductor device according to claim 10, wherein: The first gate is disposed on a first side of the first drain region, and the first III-N transistor further includes a third gate region disposed on a second side of the first drain region opposite to the first side; The second gate region is disposed on the first side of the second drain region, and the second III-N transistor further includes a fourth gate region disposed on the second side of the second drain region opposite to the first side; as well as The III-N gate layer further includes: The third gate portion is disposed in the third gate region; The fourth gate portion, which is disposed in the fourth gate region; and The bridge portion connects the third gate portion to the fourth gate portion.

13. The semiconductor device of claim 12, further comprising: A common source region is disposed between the third and fourth gate regions, wherein the bridge portion, the third gate portion, and the fourth gate portion at least partially surround the common source region.

14. The semiconductor device of claim 12, further comprising: A third gate electrode, which is coupled to the third gate portion; A fourth gate electrode, which is coupled to the fourth gate portion; as well as A fifth gate electrode, which is coupled to the bridge portion, wherein the fifth gate electrode connects the third gate electrode to the fourth gate electrode.

15. The semiconductor device of claim 10, wherein the III-N gate layer further comprises: A third gate portion extending from the first gate portion, the first and third gate portions at least partially surrounding the terminal portion of the first drain region; and A fourth gate portion extends from the second gate portion, and the second and fourth gate portions at least partially surround the terminal portion of the second drain region.

16. The semiconductor device according to claim 15, wherein: The third gate portion is disposed above the isolation region and implanted with an isolation implantation species, including at least one of argon, silicon, fluorine and nitrogen.

17. The semiconductor device of claim 15, wherein the third gate portion is disposed over the active region.

18. The semiconductor device of claim 10, wherein the first gate extension and the second gate extension each further extend over at least a corresponding portion of the isolation region.

19. The semiconductor device of claim 18, wherein portions of the first and second gate extensions are implanted with an isolation implantation species, including at least one of argon, silicon, fluorine, and nitrogen.

20. A method comprising: A III-N heterojunction structure is formed on a semiconductor substrate, the semiconductor substrate comprising an active region and an isolation region surrounding the active region, wherein: The active region includes a source region, a gate region, and a drain region, and the source, gate, and drain regions extend parallel to each other; and The III-N heterojunction structure includes a buffer layer on the semiconductor substrate and a barrier layer on the buffer layer; and A III-N gate layer is formed on the barrier layer, the III-N gate layer comprising: The gate portion, which is disposed in the gate region; and A gate extension that extends from the gate portion into the isolation region.

21. The method of claim 20, wherein the gate extension is disposed near a terminal portion of the source region.

22. The method of claim 20, wherein the gate extension further extends over at least a portion of the isolation region.

23. The method of claim 20, further comprising: A gate electrode is formed that is coupled to the gate portion.

24. The method of claim 23, wherein forming the gate electrode further comprises: A gate electrode extension is formed that extends from the gate electrode and is coupled to the gate extension.

25. The method of claim 20, further comprising: After forming the III-N gate layer, isolation implantation species are implanted in the isolation region, the isolation implantation species comprising at least one of argon, silicon, fluorine and nitrogen.

26. The method of claim 25, wherein: The gate portion is a first gate portion, and the III-N gate layer further includes a second gate portion extending from the gate portion. The first and second gate portions at least partially surround the terminal portion of the drain region, wherein the isolation implantation species implanted in the isolation region is included in the segment of the second gate portion located in the isolation region.

27. The method of claim 25, wherein: The gate portion is a first gate portion, and the III-N gate layer further includes a second gate portion extending from the gate portion, the first and second gate portions at least partially surrounding the terminal portion of the drain region, wherein the first and second gate portions are masked when the isolation implantation species are implanted in the isolation region.

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