Semiconductor device, method of manufacture, power module, conversion circuit and vehicle

Abstract

The application discloses a semiconductor device, a preparation method, a power module, a conversion circuit and a vehicle. The semiconductor device comprises a semiconductor body, which comprises a first region, a well region and a second region in sequence away from a first surface; the first and second regions are arranged to be of a first conductive type, and the well region is arranged to be of a second conductive type; the first surface is provided with a gate trench and a source trench located on at least one side of the gate trench; the semiconductor body further comprises a third region and a fourth region of the second conductive type, the third region is located on a side of the well region away from the first surface and is embedded in the region of the first conductive type; the fourth region extends from the first surface to the second surface to contact the third region; a gate is located in the gate trench; a source contact structure is located in the source trench; and a source is located on the first surface and contacts the first region, the fourth region and the source contact structure. The reverse recovery time of the device is reduced, and the bipolar degradation effect of the device is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device, a fabrication method, a power module, a conversion circuit, and a vehicle. Background Technology

[0002] As a representative of third-generation semiconductor materials, silicon carbide (SiC) possesses excellent physical and electrical properties. Compared to silicon, SiC has a larger bandgap and advantages such as high breakdown electric field, high thermal conductivity, high electron saturation velocity, and strong radiation resistance. Therefore, semiconductor devices fabricated using SiC can not only operate stably at higher temperatures but are also suitable for high-voltage and high-frequency applications.

[0003] SiC MOSFETs have evolved from planar to trench designs. By improving the gate structure, the current flow direction on the gate changed from planar to vertical. Trench semiconductor devices offer advantages such as small cell size and high current density. To further optimize the electric field distribution and reliability of the device, existing technologies typically use ion implantation to form a semi-enclosed P+ region (01) on one sidewall and part of the bottom of the gate trench, serving as an electric field shielding structure (see reference). Figure 1 The existing structure shown is designed to alleviate the electric field concentration problem at the bottom of the gate, thereby preventing the gate oxide layer O2 from being broken down. However, although existing trench SiC MOSFET structures (including those incorporating the aforementioned P+ shielding region) have made some progress, several key technical problems still need to be solved, such as: Long reverse recovery time (Trr): During the switching process of the device, the reverse recovery process of the body diode from the on state to the off state is relatively slow. This not only increases the switching loss, but may also cause serious voltage and current oscillations and electromagnetic interference problems in high-frequency applications. Bipolar degradation effect: When the body diode of the device is turned on during operation, the injected minority carriers may recombine at lattice defects, causing lattice defect proliferation such as basal dislocation propagation. This ultimately leads to the reliability problem of the device's on-state resistance increasing over time, which seriously restricts the long-term application reliability of SiC MOSFETs in applications requiring body diode freewheeling mode (such as inverter bridge arms).

[0004] Therefore, how to reduce the reverse recovery time of devices while improving the bipolar degradation effect has become a technical problem that urgently needs to be solved in this field. Summary of the Invention

[0005] This application provides a semiconductor device, a fabrication method, a power module, a conversion circuit, and a vehicle to reduce the reverse recovery time of the device while improving the bipolar degradation effect of the device.

[0006] According to one aspect of this application, a semiconductor device is provided, comprising: A semiconductor body, configured with a first conductivity type, includes a first surface and a second surface disposed opposite to each other. The semiconductor body further includes a well region, a first region, and a second region. The first region is configured with the first conductivity type and located on the first surface. The well region is configured with the second conductivity type and located on the side of the first region away from the first surface. The second region is configured with the first conductivity type and located on the side of the well region away from the first surface. The first conductivity type and the second conductivity type are different. The first surface is provided with a gate trench and a source trench, and the source trench is located on at least one side of the gate trench. The semiconductor body further includes a third region and a fourth region, both configured with the second conductivity type. The third region is located on the side of the well region away from the first surface and is embedded within the region of the first conductivity type in the semiconductor body. The fourth region extends from the first surface to the second surface to contact the third region. The gate is located in the gate trench; A source contact structure is located in the source trench; The source electrode is located on the first surface and is in contact with the first region, the fourth region, and the source electrode contact structure. The drain electrode is located on the second surface.

[0007] Optionally, the orthographic projection of the gate trench on the second surface extends along a first direction; The third region includes a plurality of first sub-regions extending along a first direction and spaced apart along a second direction, and a second sub-region located between and in contact with two adjacent first sub-regions; wherein the second direction is perpendicular to the first direction; In the plurality of first sub-regions, the orthographic projection of at least one first sub-region on the second surface overlaps with the orthographic projection of the slot corner of the gate trench on the second surface; and / or, the orthographic projection of at least one first sub-region on the second surface overlaps with the orthographic projection of the slot corner of the source trench on the second surface.

[0008] Optionally, the orthographic projection of the source trench on the second surface extends along the first direction; There are multiple source trenches located on the same side of the gate trench, and the multiple source trenches are spaced apart in the first direction. The fourth region extends from the first surface, through the interval between two adjacent source trenches, to the third region.

[0009] Optionally, the semiconductor body further includes: The fifth region is configured with a first conductivity type and is located at the corner of the source trench and on the side of the source trench near the second surface; at least the fifth region located on the side of the source trench near the second surface is in contact with the first sub-region; The ion concentration in the fifth region is greater than that in the second region.

[0010] Optionally, the source trench includes a first sub-trench and a second sub-trench located at the bottom of the first sub-trench, the width of the second sub-trench is smaller than the width of the first sub-trench, and the distance from the second sub-trench to the second surface is smaller than the distance from the gate trench to the second surface. The fifth region is located at the corner of the first sub-groove, the sidewall of the second sub-groove, the corner of the second sub-groove, and the side of the second sub-groove near the second surface; wherein the fifth region located at the corner of the second sub-groove and the side of the second sub-groove near the second surface is in contact with the third region; the fifth region located at the corner of the first sub-groove and the sidewall of the second sub-groove is in contact with the second region.

[0011] Optionally, the fifth region is also located on the sidewall of the first sub-groove and extends from the sidewall of the first sub-groove to the first surface.

[0012] Optionally, the semiconductor body further includes a drift region, which is configured with a first conductivity type and located on the side of the second region away from the first surface; the ion concentration in the second region is greater than the ion concentration in the drift region. The third region is located on the side of the second region away from the first surface; the surface of the third region facing the first surface is in contact with the second region and the fifth region; the surface of the third region facing the second surface is in contact with the drift region.

[0013] Optionally, the semiconductor body further includes: Substrate: The first epitaxial layer, configured with a first conductivity type, is located on one side of the substrate; The second epitaxial layer, configured as a first semiconductor type, is located on the side of the first epitaxial layer away from the substrate; The third epitaxial layer, configured as a second semiconductor type, is located on the side of the second epitaxial layer away from the substrate; The first region and the well region are disposed in the third epitaxial layer; the second region is disposed in the second epitaxial layer; the third region is disposed in the first epitaxial layer; the fourth region is disposed in the first epitaxial layer and the second epitaxial layer; the gate trench penetrates the third epitaxial layer; and the source trench penetrates the third epitaxial layer and at least a portion of the second epitaxial layer.

[0014] According to another aspect of this application, a method for fabricating a semiconductor device is provided, for fabricating the semiconductor device described in any embodiment of this application; comprising, A semiconductor body is formed, and a source trench and a gate trench are formed on a first surface of the semiconductor body. The semiconductor body is configured with a first conductivity type and includes a first surface and a second surface disposed opposite to each other. The semiconductor body also includes a well region, a first region, and a second region. The first region is configured with a first conductivity type and is located on the first surface. The well region is configured with a second conductivity type and is located on the side of the first region away from the first surface. The second region is configured with a first conductivity type and is located on the side of the well region away from the first surface. The first conductivity type and the second conductivity type are different. The first surface is provided with a gate trench and a source trench, and the source trench is located on at least one side of the gate trench. The semiconductor body also includes a third region and a fourth region, both of which are configured with a second conductivity type. The third region is located on the side of the well region away from the first surface and is embedded in the region of the semiconductor body with a first conductivity type. The fourth region extends from the first surface to the second surface to contact the third region. A gate is formed in the gate trench, and a source contact structure is formed in the source trench; A source electrode is formed on the first surface; the source electrode is in contact with the first region, the fourth region, and the source electrode contact structure. A drain electrode is formed on the second surface.

[0015] Optionally, forming a semiconductor body and forming a source trench and a gate trench on a first surface of the semiconductor body includes: Provide substrate; A first epitaxial layer is formed on one side of the substrate; the first epitaxial layer is configured with a first conductivity type; The third region is formed on the surface of the first epitaxial layer on the side away from the substrate; A second epitaxial layer is formed on the side of the first epitaxial layer away from the substrate; the second epitaxial layer is configured with a first conductivity type; A third epitaxial layer is formed on the side of the second epitaxial layer away from the substrate; the third epitaxial layer is configured with a second conductivity type; The first region and the well region are formed in the third epitaxial layer, and the fourth region is formed in the third epitaxial layer and the second epitaxial layer; The gate trench and the source trench are formed on the side of the third epitaxial layer away from the substrate.

[0016] Optionally, the source trench extends along a first direction on the first surface; there are multiple source trenches located on the same side of the gate trench, and the multiple source trenches are spaced apart in the first direction; The process of forming the first region and the well region in the third epitaxial layer, and forming the fourth region in the third epitaxial layer and the second epitaxial layer, includes: The fourth region is formed between two adjacent source trench preset positions on the same side of the gate trench preset position; A first region is formed on the surface of the third epitaxial layer on the side away from the substrate; wherein the third epitaxial layer located between the first region and the second epitaxial layer serves as the well region.

[0017] Optionally, forming the gate trench and the source trench on the side of the third epitaxial layer away from the substrate includes: A first mask layer is formed on the side of the third epitaxial layer away from the substrate, and the first mask layer is patterned; the patterned first mask layer includes a first opening, the first opening exposing a predetermined position of the source trench; Based on the patterned first mask layer, a first sub-trench of the source trench is formed on the surface of the third epitaxial layer away from the substrate, and the first sub-trench penetrates the first region and the well region. A spacer layer is formed on the sidewall of the first sub-trench, and a second sub-trench of the source trench is formed at the bottom of the first sub-trench based on the patterned first mask layer and the spacer layer. Remove the first mask layer and the spacer layer; A second mask layer is formed on the side of the third epitaxial layer away from the substrate and in the source trench, and the second mask layer is patterned; the patterned second mask layer includes a second opening, the second opening exposing a predetermined position of the gate trench; Based on the patterned second mask layer, the gate trench is formed on the surface of the third epitaxial layer away from the substrate.

[0018] Optionally, a spacer layer is formed on the sidewall of the first sub-trench, including: A first spacer layer is formed on the sidewall of the first sub-trench; A second spacer layer is formed on the side of the first spacer layer away from the sidewall of the first sub-groove; the first spacer layer and the second spacer layer are made of different materials; After forming the second sub-trench of the source trench at the bottom of the first sub-trench, the method further includes: The second spacer layer is removed, and a fifth region is formed at the exposed corner of the first sub-trench, the sidewall of the second sub-trench, the corner of the second sub-trench, and the side of the second sub-trench near the substrate; the fifth region is configured as a first conductivity type.

[0019] According to another aspect of this application, a power module is provided, including a substrate and at least one semiconductor device as described in any embodiment of this application, the substrate being used to support the semiconductor device.

[0020] According to another aspect of this application, a power conversion circuit is provided, which is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and at least one semiconductor device as described in any embodiment of this application, the semiconductor device being electrically connected to the circuit board.

[0021] According to another aspect of this application, a vehicle is provided, including a load and a power conversion circuit as described in any embodiment of this application, the power conversion circuit being used to convert alternating current to direct current, convert alternating current to alternating current, convert direct current to direct current, or convert direct current to alternating current and then input the converted direct current to the load.

[0022] The technical solution provided in this application integrates an MCD (MOS Channel Diode) in a semiconductor device by setting a source trench on at least one side of the gate trench and setting a source contact structure in the source trench. Since the barrier of the MCD is lower than that of the PN junction of the body diode, the on-state voltage drop (V_F) of the MCD is much lower than the voltage drop when the body diode (PN junction) is turned on. Therefore, during freewheeling, the MCD provides a low-resistance electron current path in parallel with the body diode, forcing the freewheeling current to mainly pass through the unipolar channel electron flow of the MCD, avoiding the injection and recombination of a large number of minority carriers (such as holes), effectively suppressing bipolar degradation. Furthermore, when the diode is turned off, almost no or only a very small number of minority carriers need to be removed, thus significantly reducing the reverse recovery time. Based on this, a third region and a fourth region are set in the semiconductor body, and both the third and fourth regions... The third region is located on the side of the well region away from the first surface and is embedded in the region of the semiconductor body with the first conductivity type. The fourth region extends from the first surface to the second surface to contact the third region. Even when the body diode (PN junction) is turned on in freewheeling mode and a large number of minority carriers (such as holes) are injected, the minority carriers can be quickly extracted and recombinated through the third region, avoiding accumulation in the drift region and effectively suppressing the bipolar degradation effect of the device. In reverse recovery, the minority carriers can also be quickly extracted and recombinated through the third region, reducing the reverse recovery time of the device.

[0023] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this application, nor is it intended to limit the scope of this application. Other features of this application will become readily apparent from the following description. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 This is a schematic diagram of the structure of a semiconductor device provided in the prior art; Figure 2 This is a top view of a third region, gate trench, and source trench in a semiconductor device provided in an embodiment of this application; Figure 3 yes Figure 2 A schematic diagram of the cross-sectional structure along line AA1 in the structure shown; Figure 4 yes Figure 2A schematic diagram of the cross-sectional structure along line BB1 ​​in the structure shown. Figure 5 This is a perspective view of a partial structure of another semiconductor device provided in the embodiments of this application; Figure 6 yes Figure 5 Top view of the third region, gate trench, and source trench in the structure shown; Figure 7 yes Figure 6 A schematic diagram of the cross-sectional structure along line CC1 in the structure shown. Figure 8 yes Figure 6 A schematic diagram of the cross-sectional structure along line DD1 in the structure shown; Figure 9 yes Figure 6 A schematic diagram of the cross-sectional structure along line EE1 in the structure shown. Figure 10 yes Figure 6 A schematic diagram of the cross-sectional structure along line FF1 in the structure shown; Figure 11 This is a schematic cross-sectional view of another semiconductor device provided in an embodiment of this application; Figure 12 This is a flowchart of a method for fabricating a semiconductor device according to an embodiment of this application; Figure 13 This is a schematic cross-sectional view of step S110 in a method for fabricating a semiconductor device according to an embodiment of this application. Figure 14 This is a top view of the third region formed in step S120 of a semiconductor device fabrication method provided in this application embodiment; Figure 15 This is a top view of a patterned third mask layer formed in a method for fabricating a semiconductor device according to an embodiment of this application; Figures 16-18 This is a schematic cross-sectional view of different positions after the third region is formed in a semiconductor device fabrication method provided in this application embodiment; Figure 19 This is a cross-sectional structural diagram corresponding to step S140 in a method for fabricating a semiconductor device provided in this application embodiment; Figure 20 This is a schematic cross-sectional view of step S1510 in a method for fabricating a semiconductor device provided in this application embodiment; Figure 21 This is a schematic cross-sectional view of step S1520 in a method for fabricating a semiconductor device provided in this application embodiment; Figure 22This is a schematic cross-sectional view of step S1620 in a method for fabricating a semiconductor device provided in this application embodiment; Figure 23 This is a schematic cross-sectional view of step S1630 in a method for fabricating a semiconductor device provided in this application embodiment; Figure 24 This is a cross-sectional structural diagram corresponding to step S1640 in a method for fabricating a semiconductor device provided in this application embodiment; Figure 25 This is a schematic cross-sectional view of the semiconductor device fabrication method provided in this application after removing the second spacer layer. Figure 26 This is a schematic cross-sectional view of the structure after the fifth region is formed in a method for fabricating a semiconductor device according to an embodiment of this application. Figure 27 This is a schematic cross-sectional view of the fifth region after it has been formed in another method for fabricating a semiconductor device according to an embodiment of this application. Figure 28 This is a cross-sectional structural diagram corresponding to step S1670 in a method for fabricating a semiconductor device provided in this application embodiment. Detailed Implementation

[0026] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0027] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0028] This application provides a semiconductor device. Figure 2This is a top view of a third region, gate trench, and source trench in a semiconductor device provided in an embodiment of this application. Figure 3 yes Figure 2 A schematic diagram of the cross-sectional structure along line AA1 in the shown structure. Figure 4 yes Figure 2 The schematic diagram of the cross-sectional structure along line BB1 ​​shown is for reference. Figures 2-4 Semiconductor devices include: The semiconductor body 1, configured with a first conductivity type, includes a first surface 11 and a second surface 12 disposed opposite to each other. The semiconductor body 1 also includes a well region QJ, a first region Q1, and a second region Q2. The first region Q1 is configured with the first conductivity type and is located on the first surface 11; the well region QJ is configured with the second conductivity type and is located on the side of the first region Q1 away from the first surface 11; the second region Q2 is configured with the first conductivity type and is located on the side of the well region QJ away from the first surface 11. The first conductivity type and the second conductivity type are different. The first surface 11 is provided with a gate trench 60 and a source trench 50, with the source trench 50 located on at least one side of the gate trench 60. The semiconductor body 1 also includes a third region Q3 and a fourth region Q4, both configured with the second conductivity type. The third region Q3 is located on the side of the well region QJ away from the first surface 11 and is embedded within a region of the first conductivity type in the semiconductor body 1. The fourth region Q4 extends from the first surface 11 to the second surface 12 to contact the third region Q3. Gate G is located in gate trench 60; The source contact structure 70 is located in the source trench 50; The source electrode S is located on the first surface 11 and is in contact with the first region Q1, the fourth region Q4 and the source electrode contact structure 70; The drain electrode D is located on the second surface 12.

[0029] The technical solution provided in this application integrates an MCD (MOS Channel Diode) in a semiconductor device by providing a source trench 50 on at least one side of a gate trench 60 and a source contact structure 70 in the source trench 50. Since the barrier of the MCD is lower than that of the PN junction of the body diode, the on-state voltage drop of the MCD is much lower than the on-state voltage drop of the body diode (PN junction). Therefore, during freewheeling, the MCD provides a low-resistance electron current path in parallel with the body diode, forcing the freewheeling current to mainly pass through the channel electron flow of the unipolar MCD, avoiding the injection and recombination of a large number of minority carriers (such as holes), effectively suppressing bipolar degradation. Furthermore, when the MCD is turned off, almost no or only a very small number of minority carriers need to be removed, thus significantly reducing the reverse recovery time. Based on this, a third region Q3 and a fourth region Q4 are provided in the semiconductor body 1. The fourth region Q4 is set to the second conductivity type; the third region Q3 is located on the side of the well region QJ away from the first surface 11 and is embedded in the region of the semiconductor body 1 where the conductivity type is the first conductivity type. The fourth region Q4 extends from the first surface 11 to the second surface 12 to contact the third region Q3. Even in freewheeling mode, when the body diode (PN junction) in the semiconductor device is turned on and a large number of minority carriers (such as holes) are injected, the minority carriers can be quickly extracted and recombinated through the third region Q3, avoiding accumulation in the drift region Q6, effectively suppressing the bipolar degradation effect of the device. In reverse recovery, the minority carriers can also be quickly extracted and recombinated through the third region Q3, reducing the reverse recovery time of the device.

[0030] The above are the core inventive points of this application. The structure of the semiconductor device will be described in detail below with reference to the accompanying drawings.

[0031] The semiconductor body 1 can be formed by a single epitaxial layer or by multiple epitaxial layers. That is, the semiconductor body 1 can be a single semiconductor epitaxial layer or a stacked structure formed by multiple semiconductor epitaxial layers. The semiconductor body 1 may also include a substrate 10, that is, the semiconductor body 1 includes a substrate 10 and at least one semiconductor epitaxial layer formed on one side of the substrate 10.

[0032] The material of the substrate 10 can be the same as the material of the semiconductor epitaxial layer, or the material of the substrate 10 can be different from the material of the semiconductor epitaxial layer. In a specific embodiment of this application, both the material of the semiconductor epitaxial layer and the material of the substrate 10 can be SiC. Compared with silicon, SiC has a larger bandgap and advantages such as high breakdown electric field, high thermal conductivity, high electron saturation velocity, and strong radiation resistance. Therefore, semiconductor devices made of SiC can not only operate stably at higher temperatures, but are also suitable for high-voltage and high-frequency applications.

[0033] The semiconductor body 1 includes a first surface 11 and a second surface 12 disposed opposite to each other. When the semiconductor body 1 includes a substrate 10 and at least one semiconductor epitaxial layer, the second surface 12 is the surface of the substrate 10 away from the semiconductor epitaxial layer, and the first surface 11 is the surface of the semiconductor epitaxial layer that is furthest from the substrate 10 away from the substrate 10.

[0034] Optional, Figure 3 and Figure 4 The semiconductor body 1 in the structure shown includes: a substrate 10; a first epitaxial layer 20, configured as a first conductivity type, located on one side of the substrate 10; a second epitaxial layer 30, configured as a first semiconductor type, located on the side of the first epitaxial layer 20 away from the substrate 10; and a third epitaxial layer 40, configured as a second semiconductor type, located on the side of the second epitaxial layer 30 away from the substrate 10. A second surface 12 is the surface of the substrate 10 away from the semiconductor epitaxial layer, and a first surface 11 is the surface of the third epitaxial layer 40 away from the substrate 10.

[0035] The first region Q1 and the well region QJ can be disposed in the third epitaxial layer 40; the second region Q2 can be disposed in the second epitaxial layer 30; the third region Q3 can be disposed in the first epitaxial layer 20; and the fourth region Q4 can be disposed in the first epitaxial layer 20 and the second epitaxial layer 30. The semiconductor body 1 also includes a drift region Q6 located on the side of the second region Q2 near the second surface 12, and the drift region Q6 is disposed in the first epitaxial layer 20. The conductivity type of the drift region Q6 is the same as that of the second region Q2, and the ion concentration of the drift region Q6 is less than or equal to the ion concentration of the second region Q2. Preferably, the ion concentration of the second region Q2 is greater than the ion concentration of the drift region Q6, so that the second region Q2 can act as a current spreader, thereby reducing the on-resistance of the semiconductor device.

[0036] In this embodiment, the first conductivity type can be N-type and the second conductivity type can be P-type; or, the first conductivity type can be P-type and the second conductivity type can be N-type. In this embodiment, the first conductivity type is N-type and the second conductivity type is P-type, so the conductivity type of the first region Q1 is set to N-type, and the first region Q1 is an N-type heavily doped region; the conductivity type of the well region QJ is set to P-type; the conductivity type of the second region Q2 is set to N-type, and the second region Q2 can also be a heavily doped region. The third region Q3 and the fourth region Q4 are both set to P-type, and at least the fourth region Q4 is a heavily doped region. The first epitaxial layer 20 is an N-type semiconductor epitaxial layer, doped with N-type dopant ions. The second epitaxial layer 30 is an N-type semiconductor epitaxial layer, doped with N-type dopant ions; the third epitaxial layer 40 is a P-type semiconductor epitaxial layer, doped with P-type dopant ions. The first region Q1 is formed by implanting N-type dopant ions into the third epitaxial layer 40; the third region Q3 is formed by implanting P-type dopant ions into the first epitaxial layer 20. The fourth region Q4 is formed by implanting P-type dopant ions into the third epitaxial layer 40 and the second epitaxial layer 30. By forming three epitaxial layers on one side of the substrate, this application can reduce the fabrication difficulty of semiconductor devices.

[0037] The gate trench 60 penetrates the third epitaxial layer 40, allowing the first region Q1 and the well region QJ to be sequentially located on the sidewalls of the gate trench 60 in the Z direction from the first surface 11 to the second surface 12. During device conduction, an inversion layer can be formed on the side of the well region QJ near the gate trench 60 using the gate voltage, thereby forming a conductive channel connecting the source S and the drain D. The source trench 50 penetrates the third epitaxial layer 40 and at least a portion of the second epitaxial layer 30, allowing the first region Q1 and the well region QJ to be sequentially located on the sidewalls of the source trench 50 in the Z direction from the first surface 11 to the second surface 12. During device freewheeling, an inversion layer can be formed on the side of the well region QJ near the source trench 50 using the source voltage, thereby ensuring the flow of freewheeling current. It should be noted that during the freewheeling phase, V DS <0, meaning the source voltage is greater than the drain voltage, the MCD can be turned on using the source voltage.

[0038] In this embodiment, the semiconductor device includes a MOSFET, a body diode, and an MCD. The MOSFET is composed of a first region Q1, a well region QJ, a second region Q2, a drift region Q6, a gate G, a source S, and a drain D within the semiconductor device. The body diode is a PN junction formed by the well region QJ and the second region Q2 within the semiconductor device. Since the P-type well region QJ is internally connected to the source S through the P-type fourth region Q4, and the N-type second region Q2 is ultimately connected to the drain D through the N-type drift region Q6, this diode appears externally as a parasitic diode from the source S to the drain D, with the anode at the source S and the cathode at the drain D. The MCD is composed of the first region Q1, the well region QJ, the second region Q2, the drift region Q6, the source contact structure 70, the source S, and the drain D within the semiconductor device, with the anode at the source S and the cathode at the drain D.

[0039] The forward conduction and reverse cutoff of the MCD and body diode depend on the operating state of the MOSFET and the source diode. The voltage polarity between the drain and gate. When the MOSFET is fully off (gate-source voltage Vo). GS When the voltage is ≤ 0, the MOSFET's conductive channel is not formed, and the current (freewheeling current) can only be conducted through the MCD. The forward conduction condition of the MCD is: when the source (S) voltage is higher than the drain (D) voltage, the body diode is forward biased, and the source voltage conducts the MCD. Because the barrier of the MCD is smaller than the barrier of the body diode's PN junction, the forward voltage drop (V_F) of the MCD is much lower than the voltage drop when the body diode (PN junction) is conducting. Therefore, during freewheeling, the MCD provides a low-resistance electron current path in parallel with the body diode, forcing the freewheeling current to mainly flow through the unipolar channel electron flow of the MCD, avoiding the injection and recombination of a large number of minority carriers (holes), and effectively suppressing bipolar degradation. Even during the freewheeling phase, due to the excessive freewheeling current, the body diode is forced to turn on due to the voltage drop, resulting in the generation of bipolar carriers and a significant increase in hole carriers. In this embodiment, the P-type third region Q3 is made to contact the surrounding N-type regions (such as the N-type second region Q2 and the N-type drift region Q6), thereby forming a built-in electric field between the P-type third region Q3 and the surrounding N-type regions, with the N-type regions pointing towards the P-type third region Q3. The built-in electric field can cause minority carriers (holes) to move towards the P-type third region Q3. The part of the P-type third region Q3 near the N-type region is an electron diffusion region, which allows minority carriers (holes) to recombine with electrons in the electron diffusion region, thereby preventing the accumulation of minority carriers (holes) in the drift region Q6 and effectively suppressing the bipolar degradation effect of the device.

[0040] The reverse cutoff condition for MCDs and body diodes: when the drain voltage is higher than the source voltage, i.e., V DS>0, MCD reverse biased, body diode reverse biased. Reverse recovery time refers to the time required for MCD and body diode to switch from forward conduction state to fully reverse cutoff state. In the embodiments of this application, if the body diode is not conducting during the freewheeling stage, only MCD is conducting; when MCD is reverse biased, almost no or only a very small number of minority carriers need to be removed, thus significantly reducing the reverse recovery time; if both the body MCD and body diode are conducting during the freewheeling stage, during reverse recovery, minority carriers can also be rapidly extracted and recombinated through the third region Q3, thereby reducing the reverse recovery time of the device.

[0041] Based on the above embodiments, optionally, the gate trench 60 extends along the first direction X on the orthographic projection of the second surface 12; the source trench 50 extends along the first direction X on the orthographic projection of the second surface 12. The third region Q3 includes a plurality of first sub-regions Q31 extending along the first direction X and spaced apart along the second direction Y, and a second sub-region Q32 located between and in contact with two adjacent first sub-regions Q31; wherein the first direction X extends perpendicular to the second direction Y and is perpendicular to the direction Z from the first surface 11 to the second surface 12. Among the plurality of first sub-regions Q31, at least one first sub-region Q31 has an overlapping region with the orthographic projection of the gate trench 60 on the second surface 12; and / or, at least one first sub-region Q31 has an overlapping region with the orthographic projection of the source trench 50 on the second surface 12.

[0042] Specifically, since the conductivity type of the first sub-region Q31 is different from that of the second region Q2 and the drift region Q6, by setting the orthographic projection of the first sub-region Q31 on the second surface 12 to overlap with the orthographic projection of the corner of the gate trench 60 on the second surface 12, the first sub-region Q31 can be used to shield the corner of the gate trench 60 with an electric field, reducing the risk of the insulating layer 81 at the corner of the gate trench 60 being broken down. Similarly, by setting the orthographic projection of the first sub-region Q31 on the second surface 12 to overlap with the orthographic projection of the corner of the source trench 50 on the second surface 12, the first sub-region Q31 can be used to shield the corner of the source trench 50 with an electric field, reducing the risk of the insulating layer 82 at the corner of the source trench 50 being broken down.

[0043] For example, Figure 2 In the structure shown, the source trench 50 is located on opposite sides of the gate trench 60, and are respectively the first source trench 51 and the second source trench 52; the third region Q3 includes four first sub-regions Q31 extending along the first direction X and spaced apart along the second direction Y, namely the first sub-region a, the first sub-region c, the first sub-region d, and the first sub-region b; combined with Figure 3 The orthographic projection of the first sub-region a on the second surface 12 overlaps with the orthographic projection of the corner of the first source trench 51 on the second surface 12, and the orthographic projection of the first sub-region a on the second surface 12 overlaps with the orthographic projection of the bottom surface of the first source trench 51 on the second surface 12; the orthographic projection of the first sub-region b on the second surface 12 overlaps with the orthographic projection of the corner of the second source trench 52 on the second surface 12, and the orthographic projection of the first sub-region b on the second surface 12 overlaps with the orthographic projection of the bottom surface of the second source trench 52 on the second surface 12; among the remaining two first sub-regions Q31, the orthographic projection of the first sub-region c on the second surface 12 overlaps with the orthographic projection of the corner of the gate trench 60 near the first source trench 51 on the second surface 12, and the orthographic projection of the first sub-region d overlaps with the orthographic projection of the corner of the gate trench 60 near the second source trench 52 on the second surface 12. In this configuration, first sub-region a and first sub-region c are connected by second sub-region e; first sub-region b and first sub-region d are connected by second sub-region f; second sub-region e and second sub-region f can be located on the same straight line, and this straight line extends along the second direction Y. First sub-region c and first sub-region d can be connected by two second sub-regions Q32, namely second sub-region g and second sub-region h.

[0044] Based on the above embodiments, optionally, there may be multiple source trenches 50 located on the same side of the gate trench 60, and the multiple source trenches 50 are spaced apart in the first direction X. The fourth region Q4 extends from the first surface 11, through the spacer region between two adjacent source trenches 50, to the third region Q3. Please continue to refer to Figure 2 , Figure 2 An exemplary diagram shows two source trenches 50 located on the same side of the gate trench 60. A fourth region Q4 extends from between the two first source trenches to the first sub-region a and contacts the first sub-region a. Another fourth region Q4 extends from between the two second source trenches to the first sub-region b and contacts the first sub-region b. Distributing the fourth region Q4 between the two source trenches 50 facilitates device miniaturization.

[0045] Based on the above embodiments, optionally, the semiconductor body 1 further includes a fifth region; the fifth region is configured with a first conductivity type and is located at the corner of the source trench 50 and on the side of the source trench 50 near the second surface 12; at least the fifth region Q5 located on the side of the source trench 50 near the second surface 12 is in contact with the first sub-region Q31. The ion concentration in the fifth region is greater than the ion concentration in the second region Q2. Utilizing the fifth region, the on-resistance of the semiconductor device (MOSFET) can be further reduced when the MOSFET is turned on.

[0046] Based on the above embodiments, Figure 5This is a perspective view of a partial structure of another semiconductor device provided in an embodiment of this application. Figure 6 yes Figure 5 The top view of the third region Q3, gate trench 60, and source trench 50 in the structure shown. Figure 7 yes Figure 6 A schematic diagram of the cross-sectional structure along line CC1 shown. Figure 8 yes Figure 6 A schematic diagram of the cross-sectional structure along line DD1 shown. Figure 9 yes Figure 6 A schematic diagram of the cross-sectional structure along line EE1 in the shown structure. Figure 10 yes Figure 6 The schematic diagram of the cross-sectional structure along line FF1 shown is for reference. Figures 5-10 Optionally, the source trench 50 includes a first sub-trench 501 and a second sub-trench 502 located at the bottom of the first sub-trench 501. The width of the second sub-trench 502 is smaller than the width of the first sub-trench 501, and the distance from the second sub-trench 502 to the second surface 12 is smaller than the distance from the gate trench 60 to the second surface 12. The fifth region Q5 is located at the corner of the first sub-groove 501, the sidewall of the second sub-groove 502, the corner of the second sub-groove 502, and the side of the second sub-groove 502 near the second surface 12; wherein, the fifth region Q5 located at the corner of the second sub-groove 502 and the side of the second sub-groove 502 near the second surface 12 is in contact with the third region Q3; the fifth region Q5 located at the corner of the first sub-groove 501 and the sidewall of the second sub-groove 502 is in contact with the second region Q2.

[0047] refer to Figure 6 In the embodiments of this application, the third region Q3 and Figure 2 Similar to the third region Q3 shown, it includes multiple first sub-regions Q31 extending along the first direction X and spaced apart along the second direction Y, and second sub-regions Q32 located between and in contact with two adjacent first sub-regions Q31. For a detailed structure, please refer to [link to relevant documentation]. Figure 2 The description of the structure shown will not be repeated here.

[0048] The technical solution provided in this application embodiment sets the source trench 50 as a two-stage trench including a first sub-trench 501 and a second sub-trench 502 located at the bottom of the first sub-trench 501. This can deepen the depth of the source trench, and the existence of the second-stage trench restricts the diffusion path of minority carriers to a local area near the source trench, reducing the diffusion distance of minority carriers and further shortening the reverse recovery time Trr.

[0049] In another embodiment of this application, reference is made to Figure 11Optionally, the fifth region Q5 can also be located on the sidewall of the first sub-trench 501 and extend from the sidewall of the first sub-trench 501 to the first surface 11. By setting the fifth region Q5 on the sidewall of the first sub-trench 501 and setting the fifth region Q5 on the sidewall of the first sub-trench 501 and the fifth region Q5 on the sidewall of the second sub-trench 502 to contact each other, the overall on-resistance of the device can be further reduced.

[0050] Based on the above embodiments, optionally, the semiconductor device further includes an interlayer insulating layer (ILD) disposed between the gate G and the source S to electrically isolate the gate G and the source S.

[0051] This application also provides a method for fabricating a semiconductor device, used to fabricate the semiconductor device described in any embodiment of this application; Figure 12 This is a flowchart of a method for fabricating a semiconductor device according to an embodiment of this application, see reference. Figure 12 The methods for fabricating semiconductor devices include: S10. A semiconductor body is formed, and a source trench and a gate trench are formed on a first surface of the semiconductor body. The semiconductor body is configured with a first conductivity type and includes a first surface and a second surface disposed opposite to each other. The semiconductor body also includes a well region, a first region, and a second region. The first region is configured with a first conductivity type and is located on the first surface. The well region is configured with a second conductivity type and is located on the side of the first region away from the first surface. The second region is configured with a first conductivity type and is located on the side of the well region away from the first surface. The first conductivity type and the second conductivity type are different. The first surface is provided with a gate trench and a source trench, and the source trench is located on at least one side of the gate trench. The semiconductor body also includes a third region and a fourth region, both of which are configured with a second conductivity type. The third region is located on the side of the well region away from the first surface and is embedded in the region of the semiconductor body with a first conductivity type. The fourth region extends from the first surface to the second surface to contact the third region.

[0052] S20. A gate is formed in the gate trench, and a source contact structure is formed in the source trench.

[0053] S30, A source electrode is formed on the first surface; the source electrode is in contact with the first region, the fourth region, and the source electrode contact structure.

[0054] S40, a drain electrode is formed on the second surface.

[0055] The technical solution provided in this application forms an MCD in a semiconductor device by forming a source trench 50 on at least one side of a gate trench 60 and a source contact structure 70 in the source trench 50. Since the barrier of the MCD is smaller than that of the PN junction of the body diode, the on-state voltage drop of the MCD is much lower than the voltage drop when the body diode (PN junction) is on. Therefore, during freewheeling, the MCD provides a low-resistance electron current path in parallel with the body diode, forcing the freewheeling current to mainly flow through the channel electrons of the unipolar MCD, avoiding the injection and recombination of a large number of minority carriers (such as holes), effectively suppressing bipolar degradation. Furthermore, when the diode in the semiconductor device is turned off, almost no or only a very small number of minority carriers need to be removed, thus significantly reducing the reverse recovery time. Based on this, A third region Q3 and a fourth region Q4 are provided in the semiconductor body 1, both of which are configured as the second conductivity type. The third region Q3 is located on the side of the well region QJ away from the first surface 11 and is embedded in the region of the semiconductor body 1 where the conductivity type is the first conductivity type. The fourth region Q4 extends from the first surface 11 to the second surface 12 to contact the third region Q3. Even when the body diode (PN junction) in the semiconductor device is turned on in freewheeling mode and a large number of minority carriers (such as holes) are injected, the minority carriers can be quickly extracted and recombinated through the third region Q3, avoiding accumulation in the drift region Q6 and effectively suppressing the bipolar degradation effect of the device. In reverse recovery, the minority carriers can also be quickly extracted and recombinated through the third region Q3, reducing the reverse recovery time of the device.

[0056] Optionally, step S10 forms a semiconductor body and forms a source trench and a gate trench on the first surface of the semiconductor body, including: S110. Provide a substrate and form a first epitaxial layer on one side of the substrate; the first epitaxial layer is configured with a first conductivity type.

[0057] For details, please refer to Figure 13 The material of the substrate 10 and the material of the first epitaxial layer 20 may be the same or different. In the embodiments of this application, the material of the substrate 10 and the material of the first epitaxial layer 20 are the same, both of which can be SiC. The conductivity type of the first epitaxial layer 20 is the same as that of the substrate 10, for example, both are N-type. The N-type first epitaxial layer 20 is used to form the drift region Q6 of the device.

[0058] S120, a third region is formed on the surface of the first epitaxial layer away from the substrate.

[0059] Specifically, the steps for forming the third region Q3 on the surface of the first epitaxial layer 20 away from the substrate 10 may include: forming a third mask layer on the surface of the first epitaxial layer 20 away from the substrate 10 and patterning the third mask layer; and implanting second conductivity type ions on the surface of the first epitaxial layer 20 away from the substrate 10 based on the patterned third mask layer to form the third region Q3.

[0060] Optionally, the third region Q3 includes a plurality of first sub-regions Q31 extending along a first direction X and spaced apart along a second direction Y, and a second sub-region Q32 located between and in contact with two adjacent first sub-regions Q31; wherein the first direction X extends perpendicularly to the second direction Y. For example, refer to... Figure 14 The third region Q3 includes four first sub-regions Q31 extending along the first direction X and spaced apart along the second direction Y, namely first sub-region a, first sub-region c, first sub-region d, and first sub-region b; wherein, first sub-region a and first sub-region c are connected by second sub-region e; first sub-region b and first sub-region d are connected by second sub-region f. First sub-region c and first sub-region d can be connected by two second sub-regions Q32, second sub-region g and second sub-region h. The corresponding patterned third mask layer 103 is as follows. Figure 15 As shown. Figures 16-18 This is a schematic cross-sectional view of different positions after the formation of the third region Q3 in a semiconductor device fabrication method provided in this application embodiment. Figure 16 After the formation of the third region Q3, Figure 14 A schematic diagram of the cross-sectional structure at the location of the LL1 line. Figure 17 After the formation of the third region Q3, Figure 14 A schematic diagram of the cross-sectional structure at the location of the MM1 line. Figure 18 After the formation of the third region Q3, Figure 14 A schematic diagram of the cross-sectional structure at the location of line NN1 in the middle.

[0061] S130, a second epitaxial layer is formed on the side of the first epitaxial layer away from the substrate; the second epitaxial layer is configured with a first conductivity type.

[0062] S140, a third epitaxial layer is formed on the side of the second epitaxial layer away from the substrate; the third epitaxial layer is configured as a second conductivity type.

[0063] For details, please refer to Figure 19The material of the second epitaxial layer 30 can be the same as or different from the material of the first epitaxial layer 20. In the embodiments of this application, the material of the second epitaxial layer 30 is the same as that of the first epitaxial layer 20, which is SiC. The conductivity type of the first epitaxial layer 20 is the same as that of the second epitaxial layer 30, and the ion concentration of the second epitaxial layer 30 is greater than that of the first epitaxial layer 20. The second epitaxial layer 30 is used to form a current diffusion region to reduce the on-resistance of the device. The material of the third epitaxial layer 40 can be the same as or different from that of the second epitaxial layer 30. In the embodiments of this application, the material of the third epitaxial layer 40 is the same as that of the second epitaxial layer 30, which is SiC. The conductivity type of the third epitaxial layer 40 is different from that of the second epitaxial layer 30; for example, the conductivity type of the second epitaxial layer 30 is N-type, and the conductivity type of the third epitaxial layer 40 is P-type.

[0064] S150. A first region and a trap region are formed in the third epitaxial layer, and a fourth region is formed in the third epitaxial layer and the second epitaxial layer.

[0065] Optionally, the source trench 50 extends along the first direction X in the orthogonal projection of the second surface 12; the number of source trenches 50 located on the same side of the gate trench 60 is multiple, and the multiple source trenches 50 are spaced apart in the first direction X. A first region Q1 and a well region QJ are formed in the third epitaxial layer 40, and a fourth region Q4 is formed in the third epitaxial layer 40 and the second epitaxial layer 30, including: S1510, A fourth region Q4 is formed between two adjacent source trench preset locations on the same side of the gate trench preset location. (Reference) Figure 20 and combined Figure 2 and Figure 6 ) S1520, a first region Q1 is formed on the surface of the third epitaxial layer 40 on the side away from the substrate 10; wherein, the third epitaxial layer 40 located between the first region Q1 and the second epitaxial layer 30 serves as a well region QJ. (Reference) Figure 21 ) S160. A gate trench and a source trench are formed on the side of the third epitaxial layer away from the substrate.

[0066] Specifically, a gate trench 60 and a source trench 50 can be formed on the side of the third epitaxial layer 40 away from the substrate 10 through an etching process. The gate trench 60 and the source trench 50 can be etched simultaneously or asynchronously. For Figure 3 and Figure 4 In the structure shown, the gate trench 60 and the source trench 50 can be etched and formed simultaneously. For Figures 7-10 The structure shown is formed by asynchronous etching of the gate trench 60 and the source trench 50.

[0067] Optional, for Figures 7-10 The structure shown includes a source trench 50 comprising a first sub-trench 501 and a second sub-trench 502 located at the bottom of the first sub-trench 501, wherein the width of the second sub-trench 502 is smaller than the width of the first sub-trench 501; the step of forming the gate trench 60 and the source trench 50 on the side of the third epitaxial layer 40 away from the substrate 10 includes: S1610, A first mask layer 101 is formed on the side of the third epitaxial layer 40 away from the substrate 10, and the first mask layer 101 is patterned; the patterned first mask layer 101 includes a first opening, and the first opening exposes a preset position of the source trench 50.

[0068] S1620. Based on the patterned first mask layer 101, a first sub-trench 501 of the source trench 50 is formed on the surface of the third epitaxial layer 40 away from the substrate 10. The first sub-trench 501 penetrates the first region Q1 and the well region QJ. (Reference) Figure 22 ) S1630, a spacer layer 90 is formed on the sidewall of the first sub-trench 501. (Reference) Figure 23 ) S1640, based on the patterned first mask layer 101 and spacer layer 90, a second sub-trench 502 of the source trench 50 is formed at the bottom of the first sub-trench 501. (Reference) Figure 24 ) Optionally, the semiconductor body 1 further includes a fifth region Q5; the fifth region Q5 is configured with a first conductivity type and is located at the corner of the source trench 50 and on the side of the source trench 50 near the second surface 12; the ion concentration of the fifth region Q5 is greater than the ion concentration of the second region Q2. Utilizing the fifth region Q5, the on-resistance of the device can be further reduced when the semiconductor device (MOSFET) is turned on. Please continue to refer to... Figure 23 Forming a spacer layer 90 on the sidewall of the first sub-trench 501 includes: forming a first spacer layer 91 on the sidewall of the first sub-trench 501; and forming a second spacer layer 92 on the side of the first spacer layer 91 away from the sidewall of the first sub-trench 501. The first spacer layer 91 and the second spacer layer 92 are made of different materials; the first spacer layer 91 can be made of silicon oxide, and the second spacer layer 92 can be made of silicon nitride, so as to prevent the first spacer layer 91 from being affected in the subsequent step of removing the second spacer layer 92.

[0069] After the second sub-trench 502 of the source trench 50 is formed at the bottom of the first sub-trench 501, the following is also included: The second spacer layer 92 is removed, and a fifth region Q5 is formed at the exposed corner of the first sub-trench 501, the sidewall of the second sub-trench 502, the corner of the second sub-trench 502, and the side of the second sub-trench 502 near the substrate 10; the fifth region Q5 is configured with a first conductivity type. (Reference) Figure 25 and Figure 26 ) Optional, for Figure 11 In the structure shown, the fifth region Q5 can also be located on the sidewall of the first sub-trench 501 and extend from the sidewall of the first sub-trench 501 to the first surface 11; then, during the formation of the first spacer layer 91, a thinner first spacer layer 91 can be formed, so that when the fifth region Q5 is formed, implanted N-type ions may be scattered to the sidewall of the first sub-trench 501, such as... Figure 27 As shown, the fifth region Q5 is then formed on the sidewall of the first sub-trench 501. The thickness of the first spacer layer 91 ranges from 100 nm to 200 nm.

[0070] S1650, Remove the first mask layer 101 and the spacer layer 90.

[0071] S1660, a second mask layer 102 is formed on the side of the third epitaxial layer 40 away from the substrate 10 and in the source trench 50, and the second mask layer 102 is patterned; the patterned second mask layer 102 includes a second opening, the second opening exposing a preset position of the gate trench 60.

[0072] S1670, based on the patterned second mask layer 102, a gate trench 60 is formed on the surface of the third epitaxial layer 40 on the side away from the substrate 10. (Reference) Figure 28 ).

[0073] Furthermore, based on the patterned second mask layer 102, after forming the gate trench 60 on the surface of the third epitaxial layer 40 away from the substrate 10, the method further includes: removing the second mask layer 102 and forming an insulating layer in the gate trench 60 and the source trench 50, wherein the material of the insulating layer may be silicon oxide.

[0074] Step S20, which involves forming a gate G in the gate trench 60 and a source contact structure 70 in the source trench 50, includes depositing polysilicon material in both the gate trench 60 and the source trench 50 to form the gate G in the gate trench 60 and the source contact structure 70 in the source trench 50. In other words, both the material of the gate G and the material of the source contact structure 70 can be polysilicon.

[0075] Embodiments of this application also provide a power module, including a substrate and at least one trench-type power device as described in any embodiment of this application, wherein the substrate is used to support the trench-type power device. It has the same technical effects and will not be described again here.

[0076] According to another aspect of this application, a power conversion circuit is provided, which is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and at least one trench-type power device as described in any embodiment of this application, wherein the trench-type power device is electrically connected to the circuit board. It has the same technical effects and will not be described again here.

[0077] Note that the above are merely preferred embodiments and the technical principles employed in this application. Those skilled in the art will understand that this application is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of this application. Therefore, although this application has been described in detail through the above embodiments, this application is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of this application, the scope of which is determined by the scope of the appended claims.

Claims

1. A semiconductor device, characterized in that, include: A semiconductor body, configured with a first conductivity type, includes a first surface and a second surface disposed opposite to each other. The semiconductor body further includes a well region, a first region, and a second region. The first region is configured with the first conductivity type and located on the first surface. The well region is configured with the second conductivity type and located on the side of the first region away from the first surface. The second region is configured with the first conductivity type and located on the side of the well region away from the first surface. The first conductivity type and the second conductivity type are different. The first surface is provided with a gate trench and a source trench, and the source trench is located on at least one side of the gate trench. The semiconductor body further includes a third region and a fourth region, both configured with the second conductivity type. The third region is located on the side of the well region away from the first surface and is embedded within the region of the first conductivity type in the semiconductor body. The fourth region extends from the first surface to the second surface to contact the third region. The gate is located in the gate trench; A source contact structure is located in the source trench; The source electrode is located on the first surface and is in contact with the first region, the fourth region, and the source electrode contact structure. The drain electrode is located on the second surface.

2. The semiconductor device according to claim 1, characterized in that, The orthographic projection of the gate trench on the second surface extends along the first direction; The third region includes a plurality of first sub-regions extending along a first direction and spaced apart along a second direction, and a second sub-region located between and in contact with two adjacent first sub-regions; wherein the second direction is perpendicular to the first direction; In the plurality of first sub-regions, the orthographic projection of at least one first sub-region on the second surface overlaps with the orthographic projection of the slot corner of the gate trench on the second surface; and / or, the orthographic projection of at least one first sub-region on the second surface overlaps with the orthographic projection of the slot corner of the source trench on the second surface.

3. The semiconductor device according to claim 2, characterized in that, The orthographic projection of the source trench on the second surface extends along the first direction; There are multiple source trenches located on the same side of the gate trench, and the multiple source trenches are spaced apart in the first direction. The fourth region extends from the first surface, through the interval between two adjacent source trenches, to the third region.

4. The semiconductor device according to claim 2, characterized in that, The semiconductor body also includes: The fifth region is configured with a first conductivity type and is located at the corner of the source trench and on the side of the source trench near the second surface; at least the fifth region located on the side of the source trench near the second surface is in contact with the first sub-region; The ion concentration in the fifth region is greater than that in the second region.

5. The semiconductor device according to claim 4, characterized in that, The source trench includes a first sub-trench and a second sub-trench located at the bottom of the first sub-trench. The width of the second sub-trench is smaller than the width of the first sub-trench, and the distance from the second sub-trench to the second surface is smaller than the distance from the gate trench to the second surface. The fifth region is located at the corner of the first sub-groove, the sidewall of the second sub-groove, the corner of the second sub-groove, and the side of the second sub-groove near the second surface; wherein the fifth region located at the corner of the second sub-groove and the side of the second sub-groove near the second surface is in contact with the third region; the fifth region located at the corner of the first sub-groove and the sidewall of the second sub-groove is in contact with the second region.

6. The semiconductor device according to claim 4, characterized in that, The fifth region is also located on the sidewall of the first sub-groove and extends from the sidewall of the first sub-groove to the first surface.

7. The semiconductor device according to claim 4, characterized in that, The semiconductor body further includes a drift region, which is configured with a first conductivity type and located on the side of the second region away from the first surface; the ion concentration in the second region is greater than the ion concentration in the drift region. The third region is located on the side of the second region away from the first surface; the surface of the third region facing the first surface is in contact with the second region and the fifth region; the surface of the third region facing the second surface is in contact with the drift region.

8. The semiconductor device according to any one of claims 1 to 7, characterized in that, The semiconductor body also includes: Substrate: The first epitaxial layer, configured with a first conductivity type, is located on one side of the substrate; The second epitaxial layer, configured as a first semiconductor type, is located on the side of the first epitaxial layer away from the substrate; The third epitaxial layer, configured as a second semiconductor type, is located on the side of the second epitaxial layer away from the substrate; The first region and the well region are disposed in the third epitaxial layer; the second region is disposed in the second epitaxial layer; the third region is disposed in the first epitaxial layer; the fourth region is disposed in the first epitaxial layer and the second epitaxial layer; the gate trench penetrates the third epitaxial layer; and the source trench penetrates the third epitaxial layer and at least a portion of the second epitaxial layer.

9. A method for fabricating a semiconductor device, characterized in that, For preparing the semiconductor device according to any one of claims 1 to 8, comprising: A semiconductor body is formed, and a source trench and a gate trench are formed on a first surface of the semiconductor body. The semiconductor body is configured with a first conductivity type and includes a first surface and a second surface disposed opposite to each other. The semiconductor body also includes a well region, a first region, and a second region. The first region is configured with a first conductivity type and is located on the first surface. The well region is configured with a second conductivity type and is located on the side of the first region away from the first surface. The second region is configured with a first conductivity type and is located on the side of the well region away from the first surface. The first conductivity type and the second conductivity type are different. The first surface is provided with a gate trench and a source trench, and the source trench is located on at least one side of the gate trench. The semiconductor body also includes a third region and a fourth region, both of which are configured with a second conductivity type. The third region is located on the side of the well region away from the first surface and is embedded in the region of the semiconductor body with a first conductivity type. The fourth region extends from the first surface to the second surface to contact the third region. A gate is formed in the gate trench, and a source contact structure is formed in the source trench; A source electrode is formed on the first surface; the source electrode is in contact with the first region, the fourth region, and the source electrode contact structure. A drain electrode is formed on the second surface.

10. The method for fabricating a semiconductor device according to claim 9, characterized in that, The process of forming a semiconductor body and forming a source trench and a gate trench on a first surface of the semiconductor body includes: Provide substrate; A first epitaxial layer is formed on one side of the substrate; the first epitaxial layer is configured with a first conductivity type; The third region is formed on the surface of the first epitaxial layer on the side away from the substrate; A second epitaxial layer is formed on the side of the first epitaxial layer away from the substrate; the second epitaxial layer is configured with a first conductivity type; A third epitaxial layer is formed on the side of the second epitaxial layer away from the substrate; the third epitaxial layer is configured with a second conductivity type; The first region and the well region are formed in the third epitaxial layer, and the fourth region is formed in the third epitaxial layer and the second epitaxial layer; The gate trench and the source trench are formed on the side of the third epitaxial layer away from the substrate.

11. The method for fabricating a semiconductor device according to claim 10, characterized in that, The source trench extends along a first direction on the first surface; there are multiple source trenches located on the same side of the gate trench, and the multiple source trenches are spaced apart in the first direction; The process of forming the first region and the well region in the third epitaxial layer, and forming the fourth region in the third epitaxial layer and the second epitaxial layer, includes: The fourth region is formed between two adjacent source trench preset positions on the same side of the gate trench preset position; A first region is formed on the surface of the third epitaxial layer on the side away from the substrate; wherein the third epitaxial layer located between the first region and the second epitaxial layer serves as the well region.

12. The method for fabricating a semiconductor device according to claim 11, characterized in that, The formation of the gate trench and the source trench on the side of the third epitaxial layer away from the substrate includes: A first mask layer is formed on the side of the third epitaxial layer away from the substrate, and the first mask layer is patterned; the patterned first mask layer includes a first opening, the first opening exposing a predetermined position of the source trench; Based on the patterned first mask layer, a first sub-trench of the source trench is formed on the surface of the third epitaxial layer away from the substrate, and the first sub-trench penetrates the first region and the well region. A spacer layer is formed on the sidewall of the first sub-trench, and a second sub-trench of the source trench is formed at the bottom of the first sub-trench based on the patterned first mask layer and the spacer layer. Remove the first mask layer and the spacer layer; A second mask layer is formed on the side of the third epitaxial layer away from the substrate and in the source trench, and the second mask layer is patterned; the patterned second mask layer includes a second opening, the second opening exposing a predetermined position of the gate trench; Based on the patterned second mask layer, the gate trench is formed on the surface of the third epitaxial layer away from the substrate.

13. The method for fabricating a semiconductor device according to claim 12, characterized in that, A spacer layer is formed on the sidewall of the first sub-trench, comprising: A first spacer layer is formed on the sidewall of the first sub-trench; A second spacer layer is formed on the side of the first spacer layer away from the sidewall of the first sub-groove; the first spacer layer and the second spacer layer are made of different materials; After forming the second sub-trench of the source trench at the bottom of the first sub-trench, the method further includes: The second spacer layer is removed, and a fifth region is formed at the exposed corner of the first sub-trench, the sidewall of the second sub-trench, the corner of the second sub-trench, and the side of the second sub-trench near the substrate; the fifth region is configured as a first conductivity type.

14. A power module, characterized in that, It includes a substrate and at least one semiconductor device as described in any one of claims 1 to 8, wherein the substrate is used to support the semiconductor device.

15. A power conversion circuit, characterized in that, The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and at least one semiconductor device as described in any one of claims 1 to 8, wherein the semiconductor device is electrically connected to the circuit board.

16. A vehicle, characterized in that, The device includes a load and a power conversion circuit as described in claim 15, the power conversion circuit being used to convert AC power to DC power, convert AC power to AC power, convert DC power to DC power, or convert DC power to AC power and then input it to the load.

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