Semiconductor structure, method of manufacturing the same, and semiconductor device

Abstract

The present disclosure provides a semiconductor structure and a preparation method thereof and a semiconductor device, and relates to the technical field of semiconductor chips, and aims to solve the problem of a large width of a channel of a semiconductor device. The semiconductor structure comprises a plurality of cell structures arranged along a first direction. The cell structure comprises a drain, a substrate, a drift layer, a first doped part, a channel part, a gate and a source. The first doped part and the channel part are arranged along the first direction, and the doping type of the first doped part is different from that of the channel part. The first doped part comprises a first part and a second part arranged along a second direction away from the drift layer, and the first part and the second part are both in contact with the channel part along the first direction. Along the first direction, the size of the second part is greater than that of the first part. The first doped part comprises first doped ions, and the doping concentration of the first doped ions in the second part is greater than or equal to the doping concentration of the first doped ions in the first part.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor chip technology, and in particular to a semiconductor structure and its preparation method, and a semiconductor device. Background Technology

[0002] The cell size of a semiconductor device affects its conductivity. Smaller cell size leads to higher channel density, resulting in lower specific on-resistance. Cell size is affected by channel width; the wider the channel, the larger the cell. Channel width is usually determined by the spacing between the gates on both sides.

[0003] Currently, the common method for fabricating vertical semiconductor devices involves etching raised pillar structures on a substrate, with these pillars serving as vertical current channels. Trenches are then etched on both sides of the pillars, and doping is implanted into the trench walls and bottom to form the gate. This means that the physical width of the pillars directly determines the channel width, making it difficult to further reduce the cell size and thus limiting further reductions in on-resistance and increases in current density. Secondly, because the channel has a relatively high carrier concentration, even small fluctuations in the pillar width during fabrication will directly lead to significant changes in the threshold voltage and breakdown voltage of the semiconductor device. Summary of the Invention

[0004] The embodiments of this disclosure provide a semiconductor structure and its fabrication method, as well as a semiconductor device, aimed at solving the problem of large channel width in semiconductor devices.

[0005] To achieve the above objectives, the embodiments of this disclosure adopt the following technical solutions: On one hand, this disclosure provides a semiconductor structure. The semiconductor structure includes a plurality of cell structures arranged along a first direction; the first direction is perpendicular to the thickness direction of the semiconductor structure, and the cell structure includes: a drain, a substrate, a drift layer, a first doped portion, a channel portion, a gate, and a source.

[0006] The drain is disposed on one side of the substrate along a second direction, which intersects with the first direction. The drift layer is disposed on the side of the substrate away from the drain. A first doped portion and a channel portion are disposed on the side of the drift layer away from the substrate, with the first doped portion surrounding the side of the channel portion; the first doped portion has a different doping type than the channel portion and also a different doping type than the drift layer. The gate is disposed on the side of the first doped portion away from the drift layer and is spaced apart from the channel portion. The source is disposed on the side of the channel portion away from the drift layer and is spaced apart from the first doped portion.

[0007] The first doped portion includes a first part and a second part arranged along a second direction away from the drift layer, and both the first part and the second part are in contact with the channel portion along the first direction. Along the first direction, the size of the second part is larger than the size of the first part; the first doped portion includes a first doped ion, and the doping concentration of the first doped ion in the second part is greater than or equal to the doping concentration of the first doped ion in the first part.

[0008] The semiconductor structure provided by the above embodiments of this disclosure has several advantages. Firstly, when the first doped portion and the channel portion are disposed on the drift layer and arranged along the first direction, the initial doped portion can be processed (e.g., ion implantation) to form the first doped portion. This eliminates the need for etching, avoiding the limitation imposed by etching on the width of the channel portion (which can be understood as the dimension along the first direction) (i.e., the physical width of the pillar in conventional processes). This allows for a narrower channel portion, effectively reducing the cell size and lowering the specific on-resistance. Secondly, when both the first and second portions are in contact with the channel portion, the presence of the second portion, which has a larger dimension and higher doping concentration along the first direction, allows at least a portion of the channel portion's width to be unrestricted by the doping depth of the first portion. This allows for a narrower channel portion, further effectively reducing the cell size and lowering the specific on-resistance. Thirdly, the second portion can be reused as a gate contact portion, reducing the gate contact resistance and improving the switching characteristics and reliability of the semiconductor device.

[0009] In some embodiments, the channel portion includes a first sub-channel portion and a second sub-channel portion arranged along a second direction and away from the drift layer. The channel portion includes second doped ions, and the doping concentration of the second doped ions in the second sub-channel portion is greater than or equal to the doping concentration of the second doped ions in the first sub-channel portion. At least a portion of the first sub-channel portion is in contact with a first portion; at least a portion of the second sub-channel portion is in contact with a second portion.

[0010] In some embodiments, along the second direction, the size of the second portion is larger than the size of the second sub-channel portion.

[0011] In some embodiments, the cell structure further includes a second doped portion. The second doped portion is disposed between the channel portion and the source. The doping type of the second doped portion is the same as that of the channel portion, and the doping concentration of the second doped portion is greater than that of the channel portion. The surface of the source near the second doped portion is further away from the drift layer than the surface of the gate near the drift layer.

[0012] In some embodiments, the cell structure further includes a dielectric portion. The dielectric portion is disposed around the second doped portion. The dielectric portion includes the portion between the second doped portion and the gate.

[0013] In some embodiments, the dielectric portion includes a first sub-dielectric portion and two second sub-dielectric portions. The first sub-dielectric portion is disposed around the second sub-dielectric portion. The second sub-dielectric portions are disposed around the second doped portion. Wherein, along a first direction, the second sub-dielectric portion includes a portion disposed between the gate and the second doped portion. The first sub-dielectric portion is disposed on the side of the gate away from the first doped portion along a second direction.

[0014] In some embodiments, along the second direction, the size of the first portion is larger than the size of the second portion.

[0015] In some embodiments, the drains of the multiple cell structures are interconnected. The substrates of the multiple cell structures are interconnected. The drift layers of the multiple cell structures are interconnected. The semiconductor structure further includes: a first interconnect and a second interconnect. The first interconnect is disposed on the side of the source of the multiple cell structures away from the channel portion; the sources of the multiple cell structures are respectively connected to the first interconnect. The second interconnect is disposed on the side of the gate of the multiple cell structures away from the first doped portion and is spaced apart from the first interconnect; the gates of the multiple cell structures are respectively connected to the second interconnect.

[0016] On the other hand, this disclosure provides a semiconductor device. The semiconductor device includes: a semiconductor structure as described in any of the preceding claims and a termination structure. The termination structure is coupled to the semiconductor structure.

[0017] In some embodiments, the terminal structure and the semiconductor structure are arranged along a first direction. The terminal structure includes a field-limiting ring. The field-limiting ring surrounds at least a portion of the semiconductor structure; the field-limiting ring and the first portion comprise the same material.

[0018] In another aspect, this disclosure provides a method for fabricating a semiconductor structure. The semiconductor structure includes a plurality of cell structures arranged along a first direction. The method for fabricating the semiconductor structure includes: forming a substrate and a drift layer to form the plurality of cell structures; stacking the substrate and the drift layer along a second direction, the second direction intersecting the first direction. On the side of the drift layer away from the substrate, a first doped portion and a channel portion of the plurality of cell structures are formed, and the first doped portion is disposed around the side of the channel portion; the doping type of the first doped portion is different from that of the channel portion and different from that of the drift layer. A gate is formed on the side of the first doped portion away from the drift layer, and the gate is spaced apart from the channel portion. A source is formed on the side of the channel portion away from the drift layer, and the source is spaced apart from the first doped portion. A drain of the plurality of cell structures is formed on the side of the substrate away from the drift layer. The first doped portion includes a first part and a second part arranged along the second direction and away from the drift layer, and both the first part and the second part are in contact with the channel portion along the first direction; along the first direction, the size of the second part is larger than the size of the first part; the first doped portion includes a first doped ion, and the doping concentration of the first doped ion in the second part is greater than or equal to the doping concentration of the first doped ion in the first part.

[0019] In some embodiments, forming a first doped portion and a channel portion with multiple cell structures includes: forming an initial channel layer on the side of the drift layer away from the substrate; performing ion implantation on a target region of the initial channel layer using a first mask layer to form first initial doped portions spaced along a third direction, wherein the first direction, the second direction, and the third direction intersect each other; and forming an initial channel portion by the portion of the initial channel layer that has not undergone ion implantation. Then, performing surface ion implantation on the first initial doped portions and the portion of the initial channel portion near the first initial doped portion using a second mask layer to form a second portion of the first doped portion; forming a first portion of the first doped portion by the portion of the first initial doped portion that has not undergone surface ion implantation, and forming a channel portion by the portion of the initial channel portion that has not undergone surface ion implantation.

[0020] In some embodiments, before forming the second portion of the first doped portion, the fabrication method further includes: forming a second initial doped portion on the side of the initial channel portion away from the drift layer, wherein the doping type of the second initial doped portion is the same as that of the channel portion, and the doping concentration of the second initial doped portion is greater than that of the channel portion. After forming the second portion of the first doped portion, the fabrication method further includes: oxidizing at least the side portion of the second initial doped portion to obtain a second sub-dielectric portion; the unoxidized portion of the second initial doped portion forms the second doped portion. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0022] Figure 1 This is a schematic diagram of the structure of an electronic device according to some embodiments; Figure 2 This is a top view of a semiconductor structure according to some embodiments; Figure 3 According to Figure 2 A cross-sectional view of a semiconductor structure along section line BB'; Figure 4 According to Figure 2 A cross-sectional view of a semiconductor structure along section line AA'; Figure 5 According to Figure 3 A cross-sectional view of a semiconductor structure along section line CC'; Figure 6 This is a schematic diagram of the structure of a semiconductor device according to some embodiments; Figure 7 This is a schematic diagram of the structure of a semiconductor device according to some other embodiments; Figure 8 This is a flowchart of a method for fabricating a semiconductor structure according to some embodiments; Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 15 , Figure 16 , Figure 17 , Figure 18 , Figure 19 , Figure 20 , Figure 21 , Figure 22 , Figure 23 and Figure 24 This is a diagram illustrating the fabrication steps of a semiconductor structure according to some embodiments; Figure 25 A simulated comparison of the cell distribution between the source and gate of a semiconductor device; Figure 26 A simulated battery distribution diagram between the source and gate of the semiconductor device of this disclosure; Figure 27 The simulation compares the transfer characteristic curves of the semiconductor devices. Figure 28 The simulation results show the transfer characteristic curves of the semiconductor device of this disclosure. Figure 29 The off-state breakdown current-voltage curves of the simulated semiconductor devices are shown in the diagram. Figure 30 The off-state breakdown current-voltage curve of the semiconductor device disclosed herein is shown in the simulation. Detailed Implementation

[0023] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0024] Unless the context requires otherwise, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description, terms such as "some embodiments," "exemplary," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0025] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0026] In describing some embodiments, the term "coupled" and its derivative expressions may be used. For example, the term "coupled" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0027] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0028] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0029] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0030] As used herein, the term "substrate" refers to a material on which subsequent layers of material can be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or sapphire substrate.

[0031] The technical terms used in the embodiments of this disclosure are explained below: Semiconductor: A semiconductor is a material whose conductivity at room temperature is between that of a conductor and an insulator; semiconductors include intrinsic semiconductors and impurity semiconductors. A pure semiconductor without impurities or defects, in which the concentration of electrons and holes is equal, is called an intrinsic semiconductor. A semiconductor doped with a certain amount of impurities is called an impurity semiconductor or an intrinsic semiconductor. Among them, when the impurities doped into an impurity semiconductor can provide a certain concentration of charge carriers (such as holes or electrons), the conductivity of the intrinsic semiconductor can be improved. Generally, the higher the charge carrier concentration, the lower the resistivity of the semiconductor and the better the conductivity. In the embodiments of this disclosure, this type of impurity semiconductor is also called a conductive semiconductor, for example, a conductive silicon carbide material doped with impurities such as nitrogen (N), boron (B), and aluminum (Al). Furthermore, when impurities doped into an impurity semiconductor can compensate for impurities, the donor electrons are just enough to fill the acceptor level, but cannot provide electrons and holes to the conduction and valence bands, resulting in a semiconductor material with a wide bandgap having a resistivity similar to that of an insulator. For example, in the embodiments of this disclosure, doping silicon carbide with transition metals achieves impurity compensation, thereby increasing the resistivity of the silicon carbide material. This type of impurity semiconductor is also called a semi-insulating semiconductor or a semi-insulator, or has semi-insulating characteristics.

[0032] It should be noted that, in this disclosure, the words "for example" and similar terms are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "for example" in this disclosure should not be construed as being more preferred or advantageous than other embodiments or design options. Specifically, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0033] The technical solutions disclosed herein can be applied to electronic devices, including various types of user equipment or terminal devices such as computers, mobile phones, tablets, wearable devices, and vehicle-mounted devices; these electronic devices can also be network equipment such as base stations. The electronic devices can also be devices such as power amplifiers used in the aforementioned electronic devices. The embodiments of this disclosure do not impose any special limitations on the specific form of the aforementioned electronic devices.

[0034] like Figure 1 As shown, this disclosure provides an electronic device 1000. The electronic device 1000 can be a fast charger, an uninterruptible power supply (UPS), a power motor, or other electronic devices.

[0035] Continue to refer to Figure 1 The electronic device 1000 includes a chip 1001 and a circuit board 1002. The chip 1001 and the circuit board 1002 are electrically connected. The circuit board 1002 converts the external power supply into the voltage or current required for the chip 1001 to operate.

[0036] For example, circuit board 1002 may include a printed circuit board (PCB) or the like.

[0037] For example, circuit board 1002 may include multiple conductive layers. The multiple conductive layers within circuit board 1002 may be separated from each other by dielectric layers.

[0038] The aforementioned chip 1001 includes a semiconductor device, which includes a semiconductor structure.

[0039] For example, the semiconductor device can be a junction field-effect transistor (JFET).

[0040] The semiconductor structure described above will be explained in detail below.

[0041] Embodiments of this disclosure provide a semiconductor structure 100. (Referring to reference...) Figures 2-5 The semiconductor structure 100 includes a plurality of cell structures T arranged along a first direction X; the first direction X is perpendicular to the thickness direction of the semiconductor structure 100, and the cell structure T includes: drain 101, substrate 103, drift layer 104, first doped portion 105, channel portion 106, gate 107 and source 102.

[0042] The drain 101 is disposed on one side of the substrate 103 along the second direction Y, which intersects the first direction X. The substrate 103 provides a mechanical support base and can serve as a channel for the vertical flow of current.

[0043] For example, the material of the substrate 103 can be silicon carbide, gallium nitride, etc.

[0044] A drift layer 104 is disposed on the side of the substrate 103 away from the drain 101. The drift layer 104 withstands voltage. When in the blocking state, the drift layer 104 withstands high voltage through depletion layer expansion; in the conducting state, the drift layer 104 serves as a path for carrier drift.

[0045] The first doped portion 105 and the channel portion 106 are disposed on the side of the drift layer 104 away from the substrate 103, and the first doped portion 105 is disposed around the side of the channel portion 106.

[0046] The first doped portion 105 has a different doping type than the channel portion 106, and also has a different doping type than the drift layer 104.

[0047] In some examples, the first doped portion 105 can be P-type doped, the channel portion 106 can be N-type doped, and the drift layer 104 can be N-type doped.

[0048] In some other examples, the first doped portion 105 can be N-type doped, the channel portion 106 can be P-type doped, and the drift layer 104 can be P-type doped.

[0049] The first doped portion 105 can improve the electric field distribution near the gate 107, prevent the gate oxide layer from breaking down due to the high electric field, or perform conductivity modulation to reduce the on-state voltage drop.

[0050] The channel portion 106 forms a conductive channel. When a voltage is applied to the gate 107, the surface of the region of the channel portion 106 will be inverted (or accumulate) to form a low-resistance channel connecting the first doped portion 105, the drift layer 104 and the source 102, thereby controlling the turn-on and turn-off of the semiconductor device.

[0051] The gate 107 is disposed on the side of the first doped portion 105 away from the drift layer 104 and spaced apart from the channel portion 106. The gate 107 is a control electrode. By applying a voltage signal, an electric field is generated in the channel portion 106, thereby controlling the concentration of charge carriers in the channel portion 106 and realizing the turn-on and turn-off of the semiconductor device (i.e., controlling the switching state).

[0052] The source 102 is located on the side of the channel portion 106 away from the drift layer 104 and is spaced apart from the first doped portion 105. The drain 101 is one of the main current output terminals of the semiconductor device. The source 102 serves as the other main current output terminal of the device and forms a vertical conductive channel with the drain 101.

[0053] The first doped portion 105 includes a first portion 51 and a second portion 52 arranged along the second direction Y and away from the drift layer 104, and both the first portion 51 and the second portion 52 are in contact with the channel portion 106 along the first direction X.

[0054] Along the first direction X, the size D2 of the second part 52 is greater than the size D1 of the first part 51; that is, D2 > D1.

[0055] The first doped portion 105 includes a first doped ion, and the doping concentration of the first doped ion in the second portion 52 is greater than or equal to the doping concentration of the first doped ion in the first portion 51.

[0056] Understandably, on the one hand, when the first doped portion 105 and the channel portion 106 are disposed on the drift layer 104 and arranged along the first direction X, the initial doped portion can be processed to form the first doped portion 105 using a non-etching method (e.g., ion implantation). This eliminates the need for etching processes, avoids the limitation on the width of the channel portion 106 (which can be understood as the dimension along the first direction X) (i.e., the physical width of the pillar in conventional processes), and allows the channel portion 106 to be narrower, thereby effectively reducing the cell size and lowering the specific on-resistance; On the one hand, when both the first portion 51 and the second portion 52 are in contact with the channel portion 106, the presence of the second portion 52, which has a larger size and higher doping concentration along the first direction X, allows the width of at least part of the channel portion 106 to be unrestricted by the doping depth of the first portion 51, making the channel portion 106 narrower, further effectively reducing the cell size and lowering the specific on-resistance; on the other hand, the second portion 52 can be reused as a contact portion of the gate 107, which can reduce the contact resistance of the gate 107 and improve the switching characteristics and reliability of the semiconductor device.

[0057] In some embodiments, the channel portion 106 includes a first sub-channel portion 61 and a second sub-channel portion 62 arranged along the second direction Y and away from the drift layer 104.

[0058] The channel portion 106 includes a second doped ion, and the doping concentration of the second doped ion in the second sub-channel portion 62 is greater than or equal to the doping concentration of the second doped ion in the first sub-channel portion 61.

[0059] Here, when the doped atoms in the first sub-channel 61 and the second sub-channel 62 are doped atoms of the same conductivity type, the doped atoms in the first sub-channel 61 and the second sub-channel 62 may be the same or different. The doping concentration in the first sub-channel 61 and the second sub-channel 62 can be obtained by comparing their respective atomic concentrations.

[0060] At least a portion of the first sub-channel portion 61 is in contact with the first portion 51; at least a portion of the second sub-channel portion 62 is in contact with the second portion 52.

[0061] Understandably, a channel with a gradually varying doping concentration is formed along the vertical direction (second direction Y). The first sub-channel region 61 with a lower doping concentration can regulate the threshold voltage; the second sub-channel region 62 with a higher doping concentration can reduce the contact resistance and provide sufficient charge carriers, thus achieving both withstand voltage characteristics and conduction performance. Moreover, the depletion layer that can be formed between the first sub-channel region 61 with a lower doping concentration and the first portion 51 allows the channel to be clamped narrower electrically without changing the physical dimensions, thereby forming a narrower effective conductive channel in the semiconductor device and improving the performance of the semiconductor device.

[0062] In some embodiments, reference Figure 3 Along the second direction Y, the size H2 of the second part 52 is greater than the size P2 of the second sub-channel part 62; that is, H2 > P2.

[0063] Understandably, the larger second portion 52 effectively creates a protective barrier in the region of the second sub-channel portion 62 near the gate 107, enabling a smoother depletion layer transition between the gate 107 and the source 102, eliminating electric field spikes, and improving the reliability and stability of the semiconductor device.

[0064] In some embodiments, the cell structure T further includes a second doped portion 108. The second doped portion 108 is disposed between the channel portion 106 and the source 102. The doping type of the second doped portion 108 is the same as the doping type of the channel portion 106, and the doping concentration of the second doped portion 108 is greater than the doping concentration of the channel portion 106.

[0065] The surface of the source 102 near the second doped portion 108 is further away from the drift layer 104 than the surface of the gate 107 near the drift layer 104.

[0066] Understandably, the surface of the source 102 is farther from the drift layer 104 than the surface of the gate 107. This means that in the second direction Y, the gate 107 and the source 102 are separated by a second doped section 108 with a higher concentration, increasing the path length between the gate 107 and the source 102. When subjected to voltage, the electric field strength is equal to the voltage divided by the distance. The increase in distance means a decrease in the average electric field strength, thereby directly increasing the breakdown voltage and preventing voltage breakdown due to the gate 107 and the source 102 being too close.

[0067] In some embodiments, the cell structure T further includes a dielectric portion 109. The dielectric portion 109 is disposed around the second doped portion 108. The dielectric portion 109 includes the portion between the second doped portion 108 and the gate 107.

[0068] Understandably, the dielectric section 109 is arranged around the second doped section 108. Since the dielectric section 109 is an insulating material, it effectively prevents electrical crosstalk caused by the lateral diffusion of charge carriers during the switching process of adjacent cell structures T, ensuring that each cell structure T works independently and improving the stability and anti-interference capability of the device array.

[0069] In some embodiments, the dielectric portion 109 includes a first sub-dielectric portion 91 and two second sub-dielectric portions 92. The first sub-dielectric portion 91 is disposed around the second sub-dielectric portions 92. The second sub-dielectric portions 92 are disposed around the second doped portion 108.

[0070] Along the first direction X, the second sub-dielectric portion 92 includes a portion disposed between the gate 107 and the second doped portion 108. The first sub-dielectric portion 91 is disposed on the side of the gate 107 away from the first doped portion 105 along the second direction Y.

[0071] Here, the materials of the first sub-dielectric section 91 and the second sub-dielectric section 92 can be the same or different; for example, both can be silicon dioxide.

[0072] Understandably, the gate 107 is surrounded by the second sub-dielectric portions 92 on both sides in the first direction X, and covered by the first sub-dielectric portion 91 in the second direction Y, forming a three-dimensional protection. This ensures that the gate 107 is completely electrically isolated from the surrounding conductive areas (such as the source 102), eliminating the risk of short circuits. Furthermore, the second sub-dielectric portions 92 can withstand the electric field in the direction between the gate 107 and the drift layer 104, preventing side breakdown of the gate. The first sub-dielectric portion 91 mainly prevents longitudinal breakdown between the metal layers of the gate 107 and the source 102. This functional partitioning allows the dielectric layer to more specifically withstand electrical stress in different directions, significantly improving the overall withstand voltage range of the gate 107.

[0073] In some embodiments, along the second direction Y, the size H1 of the first portion 51 is greater than the size H2 of the second portion 52; that is, H1 > H2.

[0074] Understandably, the larger first portion 51 can have a larger contact area and a deeper range of action with the channel portion 106, allowing the depletion layer formed by the gate 107 to extend deeper into the channel, enhancing the control efficiency of channel pinch-off, helping to achieve a lower threshold voltage and a smaller threshold fluctuation, improving the switching characteristics of the device, and increasing the breakdown voltage of the semiconductor device.

[0075] In some embodiments, the drains 101 of the plurality of cell structures T are interconnected. The substrates 103 of the plurality of cell structures T are interconnected. The drift layers 104 of the plurality of cell structures T are interconnected.

[0076] The semiconductor structure 100 further includes a first interconnect line 22 and a second interconnect line 72. The first interconnect line 22 is disposed on the side of the source 102 of the plurality of cell structures T away from the channel portion 106; the source 102 of the plurality of cell structures T are respectively connected to the first interconnect line 22.

[0077] The second interconnect line 72 is disposed on the side of the gate 107 of the plurality of cell structures T away from the first doped portion 105, and is spaced apart from the first interconnect line 22; the gate 107 of the plurality of cell structures T are respectively connected to the second interconnect line 72.

[0078] Understandably, the first interconnect 22 connects the sources 102 of all cell structures T together, realizing the leap from micro-cells to macro-power switches; the second interconnect 72 connects the gates 107 of all cell structures T together, ensuring that the control signal applied to the first interconnect 22 can reach the gate 107 of each cell simultaneously and uniformly, improving the switching speed of the semiconductor device and reducing switching losses.

[0079] On the other hand, this disclosure provides a semiconductor device 200. For example... Figure 6 and Figure 7 As shown, the semiconductor device 200 includes: a semiconductor structure 100 as described in any of the above-mentioned embodiments and a termination structure 201. The termination structure 201 is coupled to the semiconductor structure 100.

[0080] Understandably, the semiconductor structure 100 has current conduction and switching control functions. When the semiconductor device 200 is turned on, current flows from the source 102 through the channel 106, the drift layer 104, and the substrate 103 to the drain 101; when the semiconductor device 200 is turned off, part of the voltage is absorbed by the PN junction inside the semiconductor structure 100. The termination structure 201 surrounds the semiconductor structure 100 and is coupled to it, which can smooth and extend the electric field distribution at the edge of the active region, prevent premature edge breakdown, and improve the breakdown voltage performance of the semiconductor device 200.

[0081] In some embodiments, the terminal structure 201 and the semiconductor structure 100 are arranged along a first direction X. The terminal structure 201 includes a field-limiting ring 20. The field-limiting ring 20 surrounds at least a portion of the semiconductor structure 100; the field-limiting ring 20 and the first portion 51 comprise the same material.

[0082] Here, the number of field limit rings 20 can be one or more.

[0083] Understandably, the field confinement ring 20 surrounds at least a portion of the semiconductor structure 100, effectively creating a protective barrier around the semiconductor structure 100. When the depletion layer expands outwards, the field confinement ring 20 can deplete it, thereby preventing the depletion layer from reaching the dicing edge prematurely and preventing edge breakdown. This improves breakdown voltage capability. Furthermore, since the field confinement ring 20 and the first portion 51 are made of the same material, the field confinement ring 20 can be formed simultaneously with the first portion 51 in the same photolithography and implantation process, eliminating the need for additional material deposition or etching steps, significantly simplifying the process flow and reducing manufacturing costs.

[0084] Furthermore, this disclosure provides a method for fabricating a semiconductor structure 100. For example... Figure 8 As shown, the semiconductor structure 100 includes a plurality of cell structures arranged along a first direction X. The method for fabricating the semiconductor structure 100 includes steps S1 to S5.

[0085] S1: Combination Figure 5 ,refer to Figure 9 A substrate 103 and a drift layer 104 are formed to form multiple cell structures T; the substrate 103 and the drift layer 104 are stacked along the second direction Y, and the second direction Y intersects the first direction X.

[0086] Preferably, the size of the drift layer 104 along the second direction Y can be between 1 μm and 100 μm, and the doping concentration of the drift layer 104 can be 1 × 10⁻⁶. 14 cm -3 Up to 1×10 17 cm -3 between.

[0087] S2: Combination Figure 4 and Figure 5 ,refer to Figures 10-20 On the side of the drift layer 104 away from the substrate 103, a plurality of cell structures T are formed, including a first doped portion 105 and a channel portion 106, with the first doped portion 105 surrounding the side of the channel portion 106. The first doped portion 105 has a different doping type than the channel portion 106 and the drift layer 104. The first doped portion 105 includes a first portion 51 and a second portion 52 arranged along the second direction Y and away from the drift layer 104, and both the first portion 51 and the second portion 52 are in contact with the channel portion 106 along the first direction X. Along the first direction X, the size of the second portion 52 is larger than the size of the first portion 51. The first doped portion 105 includes first doped ions, and the doping concentration of the first doped ions in the second portion 52 is greater than or equal to the doping concentration of the first doped ions in the first portion 51.

[0088] In some embodiments, S2 forms a first doped portion 105 and a channel portion 106 of a plurality of cell structures, including: S2.1 to S2.3.

[0089] S2.1: Reference Figure 10 An initial channel layer 106A is formed on the side of the drift layer 104 away from the substrate 103.

[0090] For example, the initial channel layer 106A can be formed by ion implantation, and nitrogen, phosphorus or other ions can be used for ion implantation.

[0091] For example, a first initial sub-channel portion 61A and a second initial sub-channel portion 62A are formed along the second direction Y and away from the drift layer 104.

[0092] For example, the ion implantation depth of the second sub-initial channel 62A can be between 10 nm and 200 nm.

[0093] For example, the ion doping concentration of the second sub-initial channel 62A can be 1×10⁻⁶. 17 cm -3 Up to 1×10 18 cm -3 between.

[0094] For example, the ion implantation depth of the first initiator channel 61A can be between 10 nm and 200 nm.

[0095] For example, the ion doping concentration of the first initial sub-channel portion 61A can be 5 × 10⁻⁶. 16 cm -3 Up to 1×10 18 cm -3 between.

[0096] S2.2: Combination Figure 10 ,refer to Figure 11 Using the first mask layer PR1, ion implantation is performed on the target area of ​​the initial channel layer 106A to form a first initial doped portion 105A spaced along the third direction, with the first direction X and the second direction Y intersecting the third direction in pairs; the portion of the initial channel layer 106A that has not been ion implanted forms the initial channel portion 106B.

[0097] Understandably, the initial channel portion 106B includes a first intermediate sub-channel portion 61B and a second intermediate sub-channel portion 62B. The second intermediate sub-channel portion 62B is formed from the portion of the second sub-initial channel portion 62A that has not been ion implanted; the first intermediate sub-channel portion 61B is formed from the portion of the first initial sub-channel portion 61A that has not been ion implanted.

[0098] For example, ion implantation can use ions such as aluminum or boron.

[0099] For example, the size of the first initial doped portion 105A along the first direction X can be between 0.5 μm and 2 μm.

[0100] For example, the ion implantation depth of the first initial doped portion 105A can be between 100 nm and 2 μm.

[0101] For example, the ion doping concentration of the first initial doped portion 105A can be 1×10⁻⁶. 17 cm -3 Up to 1×10 19 cm -3 between.

[0102] In some examples, S2.2 includes: S2.2.1A to S2.2.2A.

[0103] S2.2.1A: Combining Figure 11 ,refer to Figure 12 Remove the first mask layer PR1, and form a second initial doped portion 108A on the side of the first initial doped portion 105A and the second sub-initial channel portion 62A away from the drift layer 104; the doping type of the second initial doped portion 108A is the same as the doping type of the channel portion 106, and the doping concentration of the second initial doped portion 108A is greater than the doping concentration of the channel portion 106.

[0104] For example, the first mask layer PR1 can be created using photolithography or etching.

[0105] For example, the ion implantation depth of the second initial doped portion 108A can be between 100 nm and 1 μm.

[0106] For example, the ion doping concentration of the second initial doped portion 108A can be 1×10⁸. 18 cm -3 Up to 1×10 20 cm -3 between.

[0107] S2.2.2A: Combining Figure 12 ,refer to Figure 13 Remove the portion where the projections of the second initial doped portion 108A and the first initial doped portion 105A overlap, and the remaining portion forms the initial second initial doped portion 108B.

[0108] In some other examples, S2.2 includes: S2.2.1B to S2.2.3B.

[0109] S2.2.1B: Combination Figure 10 ,refer to Figure 14A second initial doped portion 108A is formed on the side of the initial channel portion 106B away from the drift layer 104. The doping type of the second initial doped portion 108A is the same as that of the channel portion 106, and the doping concentration of the second initial doped portion 108A is greater than that of the channel portion 106.

[0110] S2.2.2B: Combination Figure 14 ,refer to Figure 15 Using the first mask layer PR1, ion implantation is performed on the target region of the initial channel layer 106A. The target region includes the overlapping portion of the projections of the initial channel layer 106A and the second initial doped portion 108A, so that the target region forms the initial first initial doped portion 105B.

[0111] S2.2.3B: Combination Figure 15 ,refer to Figure 16 The ion implantation region of the second initial doped region 108A is removed to obtain the first initial doped region 105A.

[0112] S2.3: Combination Figure 13 and Figure 16 ,refer to Figure 17 Using the second mask layer PR2, surface ion implantation is performed on the portion of the first initial doped portion 105A and the portion of the initial channel portion 106B near the first initial doped portion 105A to form the second portion 52 of the first doped portion 105; the portion of the first initial doped portion 105A that has not been surface ion implanted forms the first portion 51 of the first doped portion 105, and the portion of the initial channel portion 106B that has not been surface ion implanted forms the channel portion 106.

[0113] Here, the channel portion 106 includes a first sub-channel portion 61 and a second sub-channel portion 62. The portion of the first intermediate sub-channel portion 61B that has not undergone surface ion implantation forms the first sub-channel portion 61; the portion of the second intermediate sub-channel portion 62B that has not undergone surface ion implantation forms the second sub-channel portion 62.

[0114] In other embodiments, the thickness of the second mask layer PR2 is less than the thickness of the first mask layer PR1.

[0115] Understandably, the thinner thickness of the second mask layer PR2 allows for sufficient ion implantation of the first portion 51, preventing the semiconductor device 200 from being punched through by the higher voltage of the drain 101 when the implantation depth of the first portion 51 is too shallow. This would prevent the device from being reduced in size and thus from further reducing the specific on-resistance of the device.

[0116] Here, combined Figures 5-7While forming the first initial doped portion 105A, a field confinement ring 20 is formed in the terminal structure 201. The field confinement ring 20 and the first portion 51 are made of the same material.

[0117] For example, the dimensions of the second mask layer PR2 along the first direction can be between 500 nm and 1 μm.

[0118] For example, the distance between adjacent second mask layers PR2 can be between 500 nm and 1 μm.

[0119] For example, the second part 52 may be formed by ion implantation.

[0120] For example, the ion implantation depth of the second part 52 can be between 50 nm and 300 nm.

[0121] For example, the ion doping concentration of the second part 52 can be 1×10 18 cm -3 Up to 1×10 20 cm -3 between.

[0122] Here, S2.3 also includes: S2.3.1.

[0123] S2.3.1: Reference Figure 18 Remove the second mask layer PR2.

[0124] In some embodiments, after forming the second portion 52 of the first doped portion 105, the preparation method further includes: S2.4.

[0125] S2.4: Combination Figure 18 ,refer to Figure 19 and Figure 20 At least the side portion of the second initial doped portion 108A is oxidized to obtain the second sub-dielectric portion 92; the unoxidized portion of the second initial doped portion 108A forms the second doped portion 108.

[0126] Here, the second initial doped portion 108A is formed before the second portion 52 of the first doped portion 105 is formed, and the formation method can refer to the steps S2.2.1A~S2.2.2A and S2.2.1B~S2.2.3B described above.

[0127] Here, S2.4 also includes: S2.4.1.

[0128] S2.4.1: Combination Figure 19 ,refer to Figure 20 The second sub-dielectric portion 92, on the side of the second doped portion 108 away from the drift layer 104, is removed from oxidation.

[0129] For example, the material of the second initial doped portion 108A is silicon carbide. Since each crystal plane of SiC has an anisotropic thermal oxidation rate, the oxidation rate of the region located on the sidewall of the second initial doped portion 108A (crystal plane <11-20>) is the surface of the second initial doped portion 108A away from the substrate 103 (crystal plane <11-20>). <0001> The surface area is 3 to 5 times larger, causing the sidewalls of the second initial doped portion 108A to be oxidized more. This ultimately forms the second doped portion 108 and the second sub-dielectric portion 92 that encloses the second doped portion 108.

[0130] For example, the size of the second doped portion 108 along the first direction can be between 50 nm and 500 nm.

[0131] S3: Combination Figure 20 ,refer to Figure 21 A gate 107 is formed on the side of the first doped portion 105 away from the drift layer 104, and the gate 107 is disposed at a distance from the channel portion 106.

[0132] For example, the gate 107 can be formed by metal deposition followed by high-temperature annealing.

[0133] For example, the material of the gate 107 can be metals such as nickel, aluminum, titanium, and tungsten, or their alloys.

[0134] For example, the thickness of the gate 107 can be between 20 nm and 300 nm.

[0135] S4: Combination Figure 20 ,refer to Figure 21 A source electrode 102 is formed on the side of the channel portion 106 away from the drift layer 104, and the source electrode 102 is disposed at a distance from the first doped portion 105.

[0136] For example, the source electrode 102 can be formed by metal deposition followed by high-temperature annealing.

[0137] For example, the source electrode 102 can be made of metals such as nickel, aluminum, titanium, and tungsten, or their alloys.

[0138] For example, the thickness of the source 102 can be between 20 nm and 300 nm.

[0139] Here, S4 also includes: S4.1 and S4.2.

[0140] S4.1: Combination Figure 21 ,refer to Figure 22 An initial first sub-dielectric portion 91A is formed on the side of the gate 107 away from the drift layer 104, on the side of the second sub-dielectric portion 92 away from the drift layer 104, and on the sidewall of the second sub-dielectric portion 92 near the gate 107.

[0141] S4.2: Combination Figure 22 ,refer to Figure 23 The first sub-dielectric section 91A is formed by removing the second sub-dielectric section 92 and the initial first sub-dielectric section 91A on the side of the source electrode 102 away from the drift layer 104.

[0142] S5: Reference Figure 24 Multiple cell-structured drains 101 are formed on the side of substrate 103 away from drift layer 104.

[0143] For example, the drain 101 can be formed by metal deposition followed by high-temperature annealing.

[0144] For example, the material of the drain electrode 101 can be metals such as nickel, aluminum, titanium, and tungsten, or their alloys.

[0145] For example, the thickness of the drain 101 can be between 20 nm and 2 μm.

[0146] Here, after S5 or before S5, it also includes: S6.

[0147] S6: Combination Figure 6 or Figure 7 ,refer to Figure 24 A first interconnect line 22 is formed on the side of the source electrode 102 away from the channel portion 106. The sources 102 of the multiple cell structures T are respectively connected to the first interconnect line 22.

[0148] For example, the material of the first interconnect 22 can be metals such as titanium, aluminum, gold, silver, and copper and their alloys, or it can be conductive materials such as heavily doped polycrystalline silicon, titanium nitride, and indium tin oxide (ITO).

[0149] Furthermore, the above-described preparation method further includes: a second interconnect line 72. The second interconnect line 72 is disposed on the side of the gate 107 of the plurality of cell structures T away from the first doped portion 105, and is spaced apart from the first interconnect line 22; the gates 107 of the plurality of cell structures T are respectively connected to the second interconnect line 72.

[0150] For example, the material of the second interconnect 72 can be metals such as titanium, aluminum, gold, silver, and copper, or their alloys, or conductive materials such as heavily doped polycrystalline silicon, titanium nitride, and indium tin oxide (ITO).

[0151] The following specific examples further illustrate the technical solution of this disclosure.

[0152] like Figure 25 and Figure 26 As shown, Figure 25 A simulated comparison of the cell distribution between the source and gate of a semiconductor device; Figure 26The image shows a cell distribution diagram between the source (S) and gate (G) of the semiconductor device of this disclosure in a simulation. The first doped part of the semiconductor device of this disclosure is P-type doped, and the second doped part is N-type doped. The difference between the comparative semiconductor device and the semiconductor device of this disclosure is that, along the first direction X, the channel size of the comparative semiconductor device is larger than the channel size of the semiconductor device of this disclosure, that is, the channel width of the semiconductor device of this disclosure is narrower.

[0153] When the gate-source voltage is -20V, i.e., V GS At -20V, the semiconductor device is turned off. At this point, a high field (>3MV / cm) is observed between the gate and source of the comparison semiconductor device, indicating that the pn junction between the gate and source has undergone reverse breakdown. Meanwhile, at the same V... GS The electric field strength of the pn junction between the gate and source disclosed herein (<1.5MV / cm) is less than the breakdown electric field, proving that the semiconductor device disclosed herein improves the voltage range of the device gate, which is beneficial to prevent damage to high-voltage normally open semiconductor devices caused by transient gate voltage spikes.

[0154] like Figures 27-30 As shown, Figure 27 The simulation compares the transfer characteristic curves of the semiconductor devices. Figure 28 The simulation results show the transfer characteristic curves of the semiconductor device of this disclosure. Figure 29 The off-state breakdown current-voltage curves of the simulated semiconductor devices are shown in the diagram. Figure 30 The simulation output shows the off-state breakdown current-voltage curves of the semiconductor device of this disclosure; where... Figures 27-30 The horizontal axis represents the gate-source voltage in V, and the vertical axis represents the drain current in A. Along the first direction X, when the channel size varies by ±20%, in the figure, 100% indicates that the channel size is the reference size, -20% indicates that the channel size has decreased by 20%, and +20% indicates that the channel size has increased by 20%. Figure 28 In the figure, the transfer characteristic curves of semiconductor devices with channel size as the reference size, semiconductor devices with channel size reduced by 20%, and semiconductor devices with channel size increased by 20% overlap. Figure 30 In the figure, the off-state breakdown current-voltage curve of a semiconductor device with a channel size of 20% coincides with the off-state breakdown current-voltage curve of a semiconductor device with a channel size increased by 20%.

[0155] It is known that when the channel width of the semiconductor device disclosed herein is narrower, the comparative semiconductor device experiences a larger threshold voltage drift, while the threshold voltage of the semiconductor device disclosed herein remains stable at around -10V. Moreover, the off-state drain breakdown voltage of the comparative semiconductor device undergoes significant degradation, with punch-through occurring before the rated voltage, while the drain breakdown voltage of the semiconductor device disclosed herein does not undergo degradation.

[0156] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A semiconductor structure, characterized in that, This includes multiple cellular structures arranged along the first direction; The first direction is perpendicular to the thickness direction of the semiconductor structure, and the cell structure includes: Substrate; The drain electrode is disposed on one side of the substrate along a second direction, which intersects the first direction; A drift layer is disposed on the side of the substrate away from the drain electrode; The first doped portion and the channel portion are disposed on the side of the drift layer away from the substrate, and the first doped portion is disposed around the side of the channel portion; the first doped portion has a different doping type than the channel portion and a different doping type than the drift layer; The gate is disposed on the side of the first doped portion away from the drift layer and is spaced apart from the channel portion; The source electrode is located on the side of the channel portion away from the drift layer and is spaced apart from the first doped portion; The first doped portion includes a first portion and a second portion arranged along the second direction and away from the drift layer, and both the first portion and the second portion are in contact with the channel portion along the first direction; Along the first direction, the size of the second portion is larger than the size of the first portion; the first doped portion includes a first doped ion, and the doping concentration of the first doped ion in the second portion is greater than or equal to the doping concentration of the first doped ion in the first portion.

2. The semiconductor structure according to claim 1, characterized in that, The channel portion includes a first sub-channel portion and a second sub-channel portion arranged along the second direction and away from the drift layer; The channel portion includes a second doped ion, and the doping concentration of the second doped ion in the second sub-channel portion is greater than or equal to the doping concentration of the second doped ion in the first sub-channel portion. Wherein, at least a portion of the first sub-channel portion is in contact with the first portion; at least a portion of the second sub-channel portion is in contact with the second portion.

3. The semiconductor structure according to claim 2, characterized in that, Along the second direction, the size of the second portion is larger than the size of the second sub-channel portion.

4. The semiconductor structure according to claim 1, characterized in that, The cell structure further includes: a second doped portion disposed between the channel portion and the source electrode; the doping type of the second doped portion is the same as the doping type of the channel portion, and the doping concentration of the second doped portion is greater than the doping concentration of the channel portion; The surface of the source electrode near the second doped portion is further away from the drift layer than the surface of the gate electrode near the drift layer.

5. The semiconductor structure according to claim 4, characterized in that, The cellular structure also includes: A dielectric portion is disposed around the second doped portion; the dielectric portion includes a portion disposed between the second doped portion and the gate.

6. The semiconductor structure according to claim 5, characterized in that, The dielectric portion includes: a first sub-dielectric portion and a second sub-dielectric portion, wherein the first sub-dielectric portion is disposed around the second sub-dielectric portion and the second sub-dielectric portion is disposed around the second doped portion; Wherein, along the first direction, the second sub-dielectric portion includes a portion disposed between the gate and the second doped portion; the first sub-dielectric portion is disposed on the side of the gate away from the first doped portion along the second direction.

7. The semiconductor structure according to any one of claims 1 to 6, characterized in that, Along the second direction, the size of the first part is larger than the size of the second part.

8. The semiconductor structure according to any one of claims 1 to 6, characterized in that, The drains of the multiple cell structures are interconnected; The substrates of the plurality of cellular structures are interconnected; The drift layers of the plurality of cellular structures are interconnected; The semiconductor structure also includes: A first interconnect line is disposed on the side of the source electrode of the plurality of cell structures away from the channel portion; the source electrodes of the plurality of cell structures are respectively connected to the first interconnect line; The second interconnect line is disposed on the side of the gate of the plurality of cell structures away from the first doped portion and is spaced apart from the first interconnect line; the gates of the plurality of cell structures are respectively connected to the second interconnect line.

9. A semiconductor device, characterized in that, include: A semiconductor structure, as described in any one of claims 1 to 8; The terminal structure is coupled to the semiconductor structure.

10. The semiconductor device according to claim 9, characterized in that, The terminal structure and the semiconductor structure are arranged along a first direction; The terminal structure includes a field-limiting ring surrounding at least a portion of the semiconductor structure; the field-limiting ring and the first portion comprise the same material.

11. A method for fabricating a semiconductor structure, characterized in that, The semiconductor structure includes multiple cell structures arranged along a first direction; the fabrication method includes: A substrate and a drift layer are formed to form the plurality of cell structures; the substrate and the drift layer are stacked along a second direction, which intersects the first direction; On the side of the drift layer away from the substrate, a first doped portion and a channel portion of the plurality of cell structures are formed. The first doped portion is disposed around the side of the channel portion. The first doped portion has a different doping type than the channel portion and a different doping type than the drift layer. The first doped portion includes a first portion and a second portion arranged along the second direction and away from the drift layer, and both the first portion and the second portion are in contact with the channel portion along the first direction. Along the first direction, the size of the second portion is larger than the size of the first portion. The first doped portion includes a first dopant ion, and the doping concentration of the first dopant ion in the second portion is greater than or equal to the doping concentration of the first dopant ion in the first portion. A gate is formed on the side of the first doped portion away from the drift layer, and the gate is spaced apart from the channel portion; A source electrode is formed on the side of the channel portion away from the drift layer, and the source electrode is spaced apart from the first doped portion; The drain of the plurality of cell structures is formed on the side of the substrate away from the drift layer.

12. The method for preparing a semiconductor structure according to claim 11, characterized in that, The first doped portion and channel portion forming the plurality of cell structures include: An initial channel layer is formed on the side of the drift layer away from the substrate; Using a first mask layer, ion implantation is performed on the target region of the initial channel layer to form a first initial doped portion spaced along a third direction, wherein the first direction, the second direction, and the third direction intersect each other; the portion of the initial channel layer that has not been ion implanted forms an initial channel portion; Using a second mask layer, surface ion implantation is performed on the first initial doped portion and the portion of the initial channel portion near the first initial doped portion to form a second portion of the first doped portion; the portion of the first initial doped portion that has not undergone surface ion implantation forms a first portion of the first doped portion, and the portion of the initial channel portion that has not undergone surface ion implantation forms the channel portion.

13. The method for preparing a semiconductor structure according to claim 12, characterized in that, Before forming the second portion of the first doped portion, the preparation method further includes: A second initial doped portion is formed on the side of the initial channel portion away from the drift layer. The doping type of the second initial doped portion is the same as that of the channel portion, and the doping concentration of the second initial doped portion is greater than that of the channel portion. After forming the second portion of the first doped portion, the preparation method further includes: oxidizing at least the side portion of the second initial doped portion to obtain a second sub-dielectric portion; and forming the second doped portion from the unoxidized portion of the second initial doped portion.

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