A solar cell of a composite structure
By employing a composite structure of an N-type silicon substrate, a passivation layer, a nanocrystalline silicon layer, and a TCO layer in solar cells, the problems of high cutting loss and low CTM rate in heterojunction cells are solved, achieving higher cell connection efficiency and photoelectric conversion efficiency.
Patent Information
- Application Number
- CN202411732716.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-29
- Publication Date
- 2026-05-29
AI Technical Summary
Heterojunction solar cells suffer significant losses during the cutting process, and the CTM (Cellular Time Measuring) rate is low when heterojunction solar cells are combined with matrix stacked modules.
The solar cell employs a composite structure, including an N-type silicon substrate, a passivation layer, an antireflection layer, N-type and P-type nanocrystalline silicon layers, a TCO layer, and electrodes. By setting a TCO film and a low-temperature amorphous silicon layer on one side of the N-type silicon substrate, and placing all electrodes at the rear end of the cell, the structure combines heterojunction cells, Topcon cells, and IBC cells, avoiding overlap losses between cells.
It effectively reduces cutting losses, improves the CTM rate of solar cells, and enhances the reliability and photoelectric conversion efficiency of the cells.
Smart Images
Figure CN122121326A_ABST
Abstract
Description
Technical Field
[0001] This disclosure belongs to the field of solar cell technology, and specifically relates to a composite structure solar cell. Background Technology
[0002] Heterojunction solar cells typically have a multilayer thin-film structure, including silicon wafers, amorphous silicon films, and transparent conductive oxide (TCO) films. These materials expand and contract differently with temperature changes, causing stress concentration in certain areas. When the thermal stress exceeds the material's strength limit, cracking occurs, leading to structural damage and increasing the likelihood of fragmentation and cracks during cutting, thus increasing cutting losses. For example, amorphous silicon films have low hardness and are prone to cracking and breakage during cutting, resulting in decreased battery performance.
[0003] To further improve battery performance, existing technologies combine heterojunction cells with matrix stacked modules. Through the staggered arrangement of cells, a mesh-like hybrid circuit connection method is achieved, with cells connected in series vertically and in parallel horizontally. This structure has excellent resistance to dirt and microcracks. However, factors such as the welding quality between cells can significantly affect the CTM rate, resulting in a low CTP rate.
[0004] Therefore, it is necessary to propose a new type of solar cell structure to solve the problems of high cutting loss in heterojunction cells and low CTM rate when heterojunction cells are combined with matrix stacked modules. Summary of the Invention
[0005] This disclosure aims to at least address one of the technical problems existing in the prior art by providing a solar cell with a composite structure.
[0006] This disclosure proposes a composite structure solar cell, comprising:
[0007] N-type silicon substrate;
[0008] A first passivation layer is disposed on the first surface of the N-type silicon substrate;
[0009] An anti-reflection layer is disposed on the first passivation layer;
[0010] A second passivation layer is disposed on the second surface of the N-type silicon substrate;
[0011] An N-type nanocrystalline silicon layer and a P-type nanocrystalline silicon layer are disposed adjacently on the second passivation layer;
[0012] A TCO layer is disposed on the N-type nanocrystalline silicon layer and the P-type nanocrystalline silicon layer;
[0013] The first electrode and the second electrode are disposed on the TCO layer.
[0014] Optionally, the N-type nanocrystalline silicon layer includes multiple N-type nanocrystalline silicon regions, and the P-type nanocrystalline silicon layer includes multiple P-type nanocrystalline silicon regions; wherein,
[0015] Multiple N-type nanocrystalline silicon regions and multiple P-type nanocrystalline silicon regions are alternately spaced.
[0016] Optionally, the thickness of the N-type nanocrystalline silicon layer and the P-type nanocrystalline silicon layer is 20-60 nm.
[0017] Optionally, the TCO layer includes a plurality of high transmittance structures, which are spaced apart on the N-type nanocrystalline silicon layer and the P-type nanocrystalline silicon layer.
[0018] Optionally, the first passivation layer is a SiOx passivation layer.
[0019] Optionally, the thickness of the first passivation layer is 10-25 nm.
[0020] Optionally, the second passivation layer is an a-SiO:H passivation layer.
[0021] Optionally, the thickness of the second passivation layer is 5-30 nm.
[0022] Optionally, the thickness of the antireflective layer is 40-60 nm.
[0023] Optionally, the thickness of the N-type silicon substrate is 100-300 μm.
[0024] This disclosure proposes a composite solar cell comprising: an N-type silicon substrate; a first passivation layer disposed on a first surface of the N-type silicon substrate; an anti-reflection layer disposed on the first passivation layer; a second passivation layer disposed on a second surface of the N-type silicon substrate; an N-type nanocrystalline silicon layer and a P-type nanocrystalline silicon layer disposed adjacently on the second passivation layer; a TCO layer disposed on the N-type nanocrystalline silicon layer and the P-type nanocrystalline silicon layer; and a first electrode and a second electrode disposed on the TCO layer. By disposing the TCO film and the low-temperature amorphous silicon layer only on one side of the N-type silicon substrate, the problem of high cutting loss in heterojunction cells is solved. By placing both the first and second electrodes at the rear end of the cell, overlap loss between cells can be avoided, thereby improving the CTM (Cell Module Timing) rate. Attached Figure Description
[0025] Figure 1 This is a schematic diagram of a composite structure solar cell according to an embodiment of the present disclosure. Detailed Implementation
[0026] To enable those skilled in the art to better understand the technical solutions of this disclosure, the disclosure will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only used to explain this disclosure and represent a part of the embodiments of this disclosure, not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the protection scope of this disclosure.
[0027] like Figure 1 As shown, this disclosure proposes a composite structure solar cell 100, comprising: an N-type silicon substrate 110, a first passivation layer 120, an antireflection layer 130, a second passivation layer 140, an N-type nanocrystalline silicon layer 150 and a P-type nanocrystalline silicon layer 160, a TCO layer 170, a first electrode, and a second electrode; wherein, the first passivation layer 120 is disposed on a first surface of the N-type silicon substrate 110, and the antireflection layer 130 is disposed on the first passivation layer 120; the second passivation layer 140 is disposed on a second surface of the N-type silicon substrate 110; the N-type nanocrystalline silicon layer 150 and the P-type nanocrystalline silicon layer 160 are disposed adjacently on the second passivation layer 140; the TCO layer 170 is disposed on the N-type nanocrystalline silicon layer 150 and the P-type nanocrystalline silicon layer 160, and the first electrode and the second electrode are disposed on the TCO layer 170.
[0028] In this embodiment, by setting the TCO film and low-temperature amorphous silicon layer only on one side of the N-type silicon substrate, the problem of large cutting loss of heterojunction cells is solved. Secondly, by setting both the first and second electrodes of the cell on the TCO layer, which is equivalent to setting them on the rear end of the cell, the overlap loss between cells can be avoided compared with the matrix stacked module, thereby improving the CTM rate. In other words, this embodiment integrates the structures of heterojunction cell, Topcon cell and IBC cell to obtain a crystalline silicon solar cell with maximum efficiency.
[0029] It should be noted that the N-type silicon substrate in this embodiment should include a first surface and a second surface disposed opposite to each other. The first surface can be the front surface and the second surface can be the back surface. That is, a TCO film and a nanocrystalline silicon layer, as well as two electrodes, are disposed on the back surface of the N-type silicon substrate, and a passivation layer and an anti-reflection film layer are disposed on the front surface of the N-type silicon substrate, forming a structure that integrates heterojunction cell, Topcon cell and IBC cell, effectively improving cell efficiency.
[0030] Furthermore, such as Figure 1As shown, the N-type nanocrystalline silicon layer 150 includes multiple N-type nanocrystalline silicon regions (nc-Si layers), and the P-type nanocrystalline silicon layer 160 includes multiple P-type nanocrystalline silicon regions (nc-Si layers); wherein the multiple N-type nanocrystalline silicon regions and multiple P-type nanocrystalline silicon regions are alternately arranged. That is, unisolated P+ and n+ regions are arranged on the back side of the N-type silicon substrate, resulting in a resistance one order of magnitude lower than that of conventional cells. The reverse breakdown voltage of the formed PN junction is low, significantly reducing power consumption and heat generation, and improving the reliability of the device. Simultaneously, the alternating arrangement of N-type and P-type nanocrystalline silicon regions creates a built-in electric field at their interface. When light shines on the cell, the generated photogenerated carriers (electrons and holes) are rapidly separated under the influence of the built-in electric field, effectively reducing the recombination probability of carriers, improving carrier separation efficiency, increasing separation paths, improving carrier collection efficiency, and thus improving cell performance. Furthermore, the alternating spacing of the N-type and P-type nanocrystalline silicon regions allows incident light to undergo multiple reflections and scatterings within the cell. Light is reflected and refracted at the interface between different regions, which increases the propagation path of light in the battery, thereby increasing the probability of light absorption.
[0031] It should also be understood that, based on the fact that N-type nanocrystalline silicon regions and multiple P-type nanocrystalline silicon regions are located in the same layer, this structure is easy to integrate, eliminating the need for multi-layer deposition and etching processes, thus simplifying the fabrication process.
[0032] Furthermore, in this embodiment, the thickness of the N-type nanocrystalline silicon layer and the P-type nanocrystalline silicon layer is 20-60 nm, for example, preferably 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, etc. Within this thickness range, the nanocrystalline silicon layer can provide a good carrier transport channel and enhance the light absorption of the battery stack. When the thickness is too thin, the carriers may be affected by more scattering and defects, resulting in a decrease in transport efficiency; when the thickness is too thick, the carriers may experience more recombination losses during transport.
[0033] Furthermore, such as Figure 1 As shown, the TCO layer 170 includes multiple high-transmittance structures, which are spaced apart on the N-type nanocrystalline silicon layer 150 and the P-type nanocrystalline silicon layer 160. That is, a high-transmittance structure is disposed on each N-type and each P-type nanocrystalline silicon region. The spaced high-transmittance structures allow light to undergo multiple refractions and scatterings within the TCO layer, increasing the light propagation path length and helping to improve the absorption probability of light in the nanocrystalline silicon layer, thereby increasing the short-circuit current of the battery. Simultaneously, the spaced high-transmittance structures can disperse stress, reducing stress concentration caused by thermal expansion coefficient mismatch or external stress during battery fabrication and use, thus improving battery reliability and lifespan.
[0034] Furthermore, a first electrode and a second electrode are provided on the TCO layer. The first electrode can be the positive electrode of the battery, and the second electrode can be the negative electrode of the battery. Moreover, the first electrode and the second electrode can be silver electrodes, copper electrodes, gold electrodes, etc. In other words, the positive and negative electrodes of the battery are all located on the back of the battery, and there are no grid lines blocking the front. This can maximize the utilization of incident light, bring more effective power generation area, and thus improve photoelectric conversion efficiency.
[0035] Furthermore, the first passivation layer is a SiOx passivation layer, which can effectively reduce the defect state density on the silicon surface and reduce the recombination rate of charge carriers on the surface.
[0036] In some preferred embodiments, the thickness of the first passivation layer is 10-25 nm. Within this thickness range, the SiOx passivation layer can fully exert its passivation effect, reduce the defect state density on the silicon surface, reduce the recombination rate of charge carriers on the surface, and help improve the open-circuit voltage and short-circuit current of the solar cell, thereby improving the conversion efficiency of the cell.
[0037] In some other preferred embodiments, the refractive index of the first passivation layer is between 1.41 and 1.5, which matches the refractive index of the silicon substrate, which is between 3.4 and 3.5. This reduces the light reflectivity on the front side, increases the light incident rate, and increases the generation of photogenerated carriers.
[0038] Furthermore, the second passivation layer is an a-SiO:H passivation layer. The a-SiO:H passivation layer can cause light scattering on the back side of the silicon substrate, increasing the propagation path length of light inside the cell and helping to improve the light absorption efficiency.
[0039] In some preferred embodiments, the thickness of the second passivation layer is 5-30 nm, for example, 5 nm, 15 nm, 20 nm, 25 nm, 30 nm, etc. are preferred, and the thickness of the second passivation layer is about 1.45-1.55 nm.
[0040] Furthermore, the thickness of the antireflection layer is 40-60nm, for example, preferably 40nm, 50nm, 60nm, etc. Within this thickness range, the antireflection layer can effectively reduce the reflection of incident light, increase light absorption, and improve short-circuit current.
[0041] It should be noted that the antireflection layer in this embodiment can be made of silicon nitride, silicon dioxide, titanium oxide, etc. Of course, the antireflection layer can be a multilayer antireflection structure formed by combining materials with high refractive index and materials with low refractive index. For example, a double-layer antireflection film composed of TiO2 and SiO2 can achieve low reflectivity in a wider wavelength range.
[0042] Furthermore, the thickness of the N-type silicon substrate is 100-300 μm, for example, 100 μm, 200 μm, 300 μm.
[0043] It should be noted that a small amount of pentavalent elements such as phosphorus and arsenic can also be added to the N-type silicon substrate in this embodiment as impurities. The pentavalent elements provide excess electrons in the silicon crystal, making the silicon exhibit N-type conductivity.
[0044] The structure of the solar cell will be further explained below with reference to specific embodiments:
[0045] Example 1
[0046] The solar cell 100 of this embodiment with a composite structure includes: an N-type silicon substrate 110, a first passivation layer 120, an antireflection layer 130, a second passivation layer 140, an N-type nanocrystalline silicon layer 150 and a P-type nanocrystalline silicon layer 160, a TCO layer 170, a first electrode, and a second electrode; wherein, the first passivation layer 120 is disposed on the first surface of the N-type silicon substrate 110, and the antireflection layer 130 is disposed on the first passivation layer 120; the second passivation layer 140 is disposed on the second surface of the N-type silicon substrate 110; the N-type nanocrystalline silicon layer 150 and the P-type nanocrystalline silicon layer 160 are disposed adjacently on the second passivation layer 140; the TCO layer 170 is disposed on the N-type nanocrystalline silicon layer 150 and the P-type nanocrystalline silicon layer 160, and the first electrode and the second electrode are disposed on the TCO layer 170.
[0047] The N-type nanocrystalline silicon layer comprises multiple N-type nanocrystalline silicon regions, and the P-type nanocrystalline silicon layer comprises multiple P-type nanocrystalline silicon regions; wherein the multiple N-type nanocrystalline silicon regions and the multiple P-type nanocrystalline silicon regions are alternately spaced. The thickness of the N-type nanocrystalline silicon layer and the P-type nanocrystalline silicon layer is 30 nm.
[0048] Secondly, the TCO layer includes multiple high-transmittance structures, which are spaced apart on the N-type nanocrystalline silicon layer and the P-type nanocrystalline silicon layer.
[0049] Secondly, the first passivation layer is a SiOx passivation layer with a thickness of 15 nm. The second passivation layer is an a-SiO:H passivation layer with a thickness of 10 nm, the antireflection layer has a thickness of 40 nm, and the N-type silicon substrate has a thickness of 100 μm.
[0050] In this embodiment 1, the open-circuit voltage is 749.1mV, the short-time current is 42.2mA, the fill factor is 87.4%, the photoelectric conversion efficiency is 26.2%, and the power ratio at 50°C is 93.75%.
[0051] Example 2
[0052] The solar cell 100 of this embodiment with a composite structure includes: an N-type silicon substrate 110, a first passivation layer 120, an antireflection layer 130, a second passivation layer 140, an N-type nanocrystalline silicon layer 150 and a P-type nanocrystalline silicon layer 160, a TCO layer 170, a first electrode, and a second electrode; wherein, the first passivation layer 120 is disposed on the first surface of the N-type silicon substrate 110, and the antireflection layer 130 is disposed on the first passivation layer 120; the second passivation layer 140 is disposed on the second surface of the N-type silicon substrate 110; the N-type nanocrystalline silicon layer 150 and the P-type nanocrystalline silicon layer 160 are disposed adjacently on the second passivation layer 140; the TCO layer 170 is disposed on the N-type nanocrystalline silicon layer 150 and the P-type nanocrystalline silicon layer 160, and the first electrode and the second electrode are disposed on the TCO layer 170.
[0053] The N-type nanocrystalline silicon layer comprises multiple N-type nanocrystalline silicon regions, and the P-type nanocrystalline silicon layer comprises multiple P-type nanocrystalline silicon regions; wherein the multiple N-type nanocrystalline silicon regions and the multiple P-type nanocrystalline silicon regions are alternately spaced. The thickness of the N-type nanocrystalline silicon layer and the P-type nanocrystalline silicon layer is 50 nm.
[0054] Secondly, the TCO layer includes multiple high-transmittance structures, which are spaced apart on the N-type nanocrystalline silicon layer and the P-type nanocrystalline silicon layer.
[0055] Secondly, the first passivation layer is a SiOx passivation layer with a thickness of 25 nm. The second passivation layer is an a-SiO:H passivation layer with a thickness of 30 nm, the antireflection layer has a thickness of 60 nm, and the N-type silicon substrate has a thickness of 200 μm.
[0056] In this embodiment 2, the open-circuit voltage is 747.5mV, the short-time current is 40.8mA, the fill factor is 86.1%, the photoelectric conversion efficiency is 25.8%, and the power ratio at 50°C is 93.11%.
[0057] Comparative Example 1
[0058] The heterojunction solar cell of this embodiment includes: an n-type monocrystalline silicon substrate, a first hydrogenated amorphous silicon thin film, a p-type doped hydrogenated amorphous silicon thin film, a first TCO thin film and a first electrode stacked sequentially on one side of the n-type silicon wafer, and a second hydrogenated amorphous silicon thin film, an n-type doped hydrogenated amorphous silicon thin film, a second TCO thin film and a second electrode stacked sequentially on the other side of the n-type monocrystalline silicon substrate.
[0059] Secondly, the thickness of the first hydrogenated amorphous silicon film and the second hydrogenated amorphous silicon film is 60 nm. The thickness of the first TCO film and the second TCO film ranges from 120 nm. The thickness of the n-type single crystal silicon substrate is 100 μm, and the thickness of the p-type doped hydrogenated amorphous silicon film and the n-type doped hydrogenated amorphous silicon film is 20 nm.
[0060] The open-circuit voltage of Comparative Example 1 is 728.3mV, the short-time current is 33.9mA, the fill factor is 80.53%, and the photoelectric conversion efficiency is 20.8%.
[0061] It is understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of this disclosure, and this disclosure is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and substance of this disclosure, and these modifications and improvements are also considered to be within the scope of protection of this disclosure.
Claims
1. A composite solar cell, characterized in that, include: N-type silicon substrate; A first passivation layer is disposed on the first surface of the N-type silicon substrate; An anti-reflection layer is disposed on the first passivation layer; A second passivation layer is disposed on the second surface of the N-type silicon substrate; An N-type nanocrystalline silicon layer and a P-type nanocrystalline silicon layer are disposed adjacently on the second passivation layer; A TCO layer is disposed on the N-type nanocrystalline silicon layer and the P-type nanocrystalline silicon layer; The first electrode and the second electrode are disposed on the TCO layer.
2. The solar cell with a composite structure according to claim 1, characterized in that, The N-type nanocrystalline silicon layer includes multiple N-type nanocrystalline silicon regions, and the P-type nanocrystalline silicon layer includes multiple P-type nanocrystalline silicon regions; wherein... Multiple N-type nanocrystalline silicon regions and multiple P-type nanocrystalline silicon regions are alternately spaced.
3. The solar cell with a composite structure according to claim 1, characterized in that, The thickness of the N-type nanocrystalline silicon layer and the P-type nanocrystalline silicon layer is 20-60 nm.
4. The solar cell with a composite structure according to claim 1, characterized in that, The TCO layer includes multiple high-transmittance structures, which are spaced apart on the N-type nanocrystalline silicon layer and the P-type nanocrystalline silicon layer.
5. The solar cell with a composite structure according to claim 1, characterized in that, The first passivation layer is a SiOx passivation layer.
6. The solar cell with a composite structure according to claim 5, characterized in that, The thickness of the first passivation layer is 10-25 nm.
7. The solar cell with a composite structure according to claim 1, characterized in that, The second passivation layer is an a-SiO:H passivation layer.
8. The solar cell with a composite structure according to claim 7, characterized in that, The thickness of the second passivation layer is 5-30 nm.
9. The solar cell with a composite structure according to claim 1, characterized in that, The thickness of the antireflective layer is 40-60 nm.
10. The solar cell with a composite structure according to claim 1, characterized in that, The thickness of the N-type silicon substrate is 100-300 μm.