Light emitting diode and method of manufacturing the same

Abstract

The present disclosure provides a light emitting diode and a preparation method thereof, and belongs to the technical field of semiconductors. The light emitting diode comprises an n-type semiconductor layer, a multi-quantum well layer and a p-type semiconductor layer which are stacked in sequence; the p-type semiconductor layer comprises a first GaP sub-layer, a second GaP sub-layer and a third GaP sub-layer which are stacked in sequence, wherein the first GaP sub-layer is connected with the multi-quantum well layer; the doping concentration in the first GaP sub-layer, the second GaP sub-layer and the third GaP sub-layer gradually increases, and the doping concentration of the third GaP sub-layer is equal to or greater than 8.0*10 18 / cm ‑3 2 / cm . The present disclosure can reduce the working voltage of the light emitting diode.

Description

Technical Field

[0001] This disclosure belongs to the field of semiconductor technology, and specifically relates to a light-emitting diode and its fabrication method. Background Technology

[0002] The operating voltage (Vf) of a light-emitting diode (LED) chip is the driving voltage required for it to emit light normally. It is mainly used to overcome various resistances within the chip, including the bulk resistance of the semiconductor material and the contact resistance of the electrodes. Under constant driving current, the lower the Vf, the less power loss inside the chip, the higher the photoelectric conversion efficiency, and the more energy-efficient the chip.

[0003] In related technologies, light-emitting diodes (LEDs) include a multi-quantum-well layer and an n-type semiconductor layer and a p-type semiconductor layer located on either side of the multi-quantum-well layer. The p-type semiconductor layer includes a GaP window layer electrically connected to the p-electrode. To achieve good conductivity, the GaP window layer typically requires a single, high-concentration p-type doping (e.g., magnesium doping), with a typical doping concentration of 2 × 10⁻⁶. 18 / cm -3 ~5×10 18 / cm -3 .

[0004] However, excessive doping of the GaP window layer may introduce lattice defects and impurity scattering, increasing the bulk resistance of the GaP window layer. Moreover, the extremely high concentration of Mg doping in the GaP window layer may induce natural defects in the crystal (such as phosphorus vacancies). These defects may exhibit n-type characteristics, resulting in a net doping concentration that does not meet expectations, and the surface resistivity remains high. This leads to a non-ideal ohmic contact between the GaP window layer and the p-electrode, causing an increase in the chip's operating voltage, resulting in unnecessary power loss and limiting the overall energy efficiency of the chip. Summary of the Invention

[0005] This disclosure provides a light-emitting diode (LED) and its fabrication method, which can reduce the operating voltage of the LED. The technical solution is as follows: This disclosure provides a light-emitting diode (LED) comprising an n-type semiconductor layer, a multiple quantum well layer, and a p-type semiconductor layer stacked sequentially. The p-type semiconductor layer includes a first GaP sublayer, a second GaP sublayer, and a third GaP sublayer stacked sequentially, wherein the first GaP sublayer is connected to the multiple quantum well layer. The doping concentration in the first GaP sublayer, the second GaP sublayer, and the third GaP sublayer gradually increases, and the doping concentration of the third GaP sublayer is equal to or greater than 8.0 × 10⁻⁶. 18 / cm -3 .

[0006] In another implementation of this disclosure, the doping concentration of the first GaP sublayer is 5.0 × 10⁻⁶. 17 / cm -3 ~1.0×10 18 / cm -3 The thickness of the first GaP sublayer is 10nm~30nm.

[0007] In another implementation of this disclosure, the doping concentration of the second GaP sublayer is 2.0 × 10⁻⁶. 18 / cm -3 ~6.0×10 18 / cm -3 .

[0008] In another implementation of this disclosure, the doping concentration of the second GaP sublayer increases monotonically along the direction from the first GaP sublayer to the second GaP sublayer.

[0009] In another implementation of this disclosure, the thickness of the second GaP sublayer is 0.5 μm to 2.0 μm.

[0010] In another implementation of this disclosure, the doping concentration of the third GaP sublayer is less than or equal to 6.0 × 10⁻⁶. 19 / cm -3 .

[0011] In another implementation of this disclosure, the thickness of the third GaP sublayer is 50 nm to 200 nm.

[0012] On the other hand, this disclosure also provides a method for fabricating a light-emitting diode, the method comprising: forming an n-type semiconductor layer, a multiple quantum well layer, and a p-type semiconductor layer stacked sequentially; the p-type semiconductor layer comprising a first GaP sublayer, a second GaP sublayer, and a third GaP sublayer stacked sequentially, wherein the first GaP sublayer is connected to the multiple quantum well layer; the doping concentration in the first GaP sublayer, the second GaP sublayer, and the third GaP sublayer gradually increases, and the doping concentration of the third GaP sublayer is equal to or greater than 8.0 × 10⁻⁶. 18 / cm -3 The process further includes an atmosphere holding process between the formation of the first GaP sublayer and the second GaP sublayer; the atmosphere holding process includes holding the atmosphere at a temperature of 680°C to 720°C for 1 to 3 minutes under a phosphine protective atmosphere.

[0013] In another implementation of this disclosure, the first GaP sublayer is formed at a growth temperature of 600°C to 650°C and a growth rate of 0.5 nm / s to 1 nm / s.

[0014] In another implementation of this disclosure, the second GaP sublayer is formed at a growth temperature of 680°C to 720°C and a growth rate of 2.0 nm / s to 3.0 nm / s; the third GaP sublayer is formed at a growth temperature of 680°C to 720°C and a growth rate of 0 nm / s to 2.0 nm / s.

[0015] The beneficial effects of the technical solutions provided in this disclosure are: The second semiconductor layer of this light-emitting diode comprises a first GaP sublayer, a second GaP sublayer, and a third GaP sublayer stacked sequentially, with the first GaP sublayer connected to the multi-quantum-well layer. Furthermore, the doping concentration in the first, second, and third GaP sublayers gradually increases. This design allows the doping concentration of the GaP window layer to be gradual rather than uniform. Simultaneously, since the first GaP sublayer is connected to the multi-quantum-well layer, its doping concentration is the lowest. This allows for gradual lattice adjustment through the first GaP sublayer, effectively suppressing defects caused by lattice mismatch and sudden high doping, thereby reducing bulk resistance. Then, a second GaP sublayer with a moderate doping concentration sits atop the first GaP sublayer. This moderate doping concentration allows the second GaP sublayer to maintain high carrier mobility while providing sufficiently low bulk resistance. A highly doped third GaP sublayer sits atop the second GaP sublayer. This allows the GaP window layer to form a tunneling ohmic contact with the contacting metal, facilitating carriers to tunnel through the electrode-GaP window layer interface via quantum tunneling, thereby significantly reducing contact resistance. Ultimately, this reduces the operating voltage and improves electro-optical conversion efficiency at the same driving current. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of the structure of a light-emitting diode provided in an embodiment of this disclosure; Figure 2 This is a schematic diagram of another light-emitting diode structure provided in an embodiment of this disclosure; Figure 3 This is a schematic diagram of the epitaxial layer structure of a light-emitting diode provided in an embodiment of this disclosure; Figure 4This is a flowchart of a method for fabricating a light-emitting diode according to an embodiment of this disclosure; Figure 5 This is a flowchart of another method for fabricating a light-emitting diode provided in this embodiment.

[0018] The symbols in the diagram represent the following meanings: 1. n-type semiconductor layer; 12. n-type ohmic contact layer; 13. n-type current spreading layer; 14. n-type confinement layer; 15. Electrode bonding layer; 16. Roughening layer; 2. Multiple quantum well layers; 4. p-type semiconductor layer; 41. GaP window layer; 411. First GaP sublayer; 412. Second GaP sublayer; 413. Third GaP sublayer; 42. p-type confinement layer; 43. Stress transition layer; 50. Bonding substrate; 51. First electrode; 52. Second electrode; 5. Growth substrate; 6. Etching stop layer; 7. Buffer layer. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in further detail below with reference to the accompanying drawings.

[0020] This disclosure provides a light-emitting diode, such as... Figure 1 As shown, the light-emitting diode includes an n-type semiconductor layer 1, a multiple quantum well layer 2, and a p-type semiconductor layer 4 stacked sequentially.

[0021] The p-type semiconductor layer 4 includes a first GaP sublayer 411, a second GaP sublayer 412, and a third GaP sublayer 413 stacked sequentially, wherein the first GaP sublayer 411 is connected to the multi-quantum well layer 2.

[0022] The doping concentrations in the first GaP sublayer 411, the second GaP sublayer 412, and the third GaP sublayer 413 gradually increase, with the doping concentration of the third GaP sublayer 413 being equal to or greater than 8.0 × 10⁻⁶. 18 / cm -3 .

[0023] Because the p-type semiconductor layer 4 in this light-emitting diode includes a GaP window layer 41, and the GaP window layer 41 comprises a first GaP sublayer 411, a second GaP sublayer 412, and a third GaP sublayer 413 stacked sequentially, wherein the first GaP sublayer 411 is connected to the multi-quantum well layer 2. Furthermore, the doping concentration in the first GaP sublayer 411, the second GaP sublayer 412, and the third GaP sublayer 413 gradually increases. This design allows the doping concentration of the GaP window layer 41 to be gradually varied rather than a single concentration. Simultaneously, since the first GaP sublayer 411 is connected to the multi-quantum well layer 2, its doping concentration is the lowest. This allows for slow lattice adjustment through the first GaP sublayer 411, effectively suppressing defects caused by lattice mismatch and sudden high doping, thereby reducing its bulk resistance. Then, a second GaP sublayer 412 with a moderate doping concentration is placed on top of the first GaP sublayer 411. The moderate doping concentration allows the second GaP sublayer 412 to maintain high carrier mobility while providing sufficiently low bulk resistance. Above the second GaP sublayer 412 is a highly doped third GaP sublayer 413, with a doping concentration equal to or greater than 8.0 × 10⁻⁶. 18 / cm -3 This design enables charge carriers to tunnel through the interface between the electrode and the GaP window layer 41 via quantum tunneling, reducing contact resistance. Ultimately, this reduces the operating voltage and improves electro-optical conversion efficiency at the same driving current.

[0024] In this embodiment, the first GaP sublayer 411, the second GaP sublayer 412, and the third GaP sublayer 413 together form the GaP window layer 41.

[0025] Optionally, the doping concentration of the first GaP sublayer 411 is 5.0 × 10⁻⁶. 17 / cm -3 ~1.0×10 18 / cm -3 .

[0026] If the doping concentration of the first GaP sublayer 411 is too high, the introduced large number of impurity atoms will exacerbate lattice mismatch stress, inducing high-density dislocations and point defects. These defects will not only significantly reduce carrier mobility, but may also extend upwards, penetrate the active light-emitting region, and become non-radiative recombination centers, severely impairing the chip's internal quantum efficiency. Therefore, setting the first GaP sublayer 411 to low doping can achieve a smooth lattice transition and defect filtering, laying a solid foundation for the high-quality layer above that undertakes current spreading functions, thereby improving device reliability and photoelectric efficiency.

[0027] For example, the doping concentration of the first GaP sublayer 411 can be 8.0 × 10⁻⁶. 17 / cm -3 9.0×1017 / cm -3 This can effectively alleviate the problem of lattice mismatch, thereby improving device reliability and photoelectric efficiency.

[0028] Optionally, the doping concentration of the second GaP sublayer 412 is 2.0 × 10⁻⁶. 18 / cm -3 ~6.0×10 18 / cm -3 .

[0029] In the above implementation, the above settings ensure a moderate carrier concentration in the second GaP sublayer 412. Since this layer serves as the "main channel" for lateral current expansion, it needs to achieve large-area uniform conductivity at a relatively low voltage. A moderate doping concentration provides a sufficiently high doping concentration to reduce bulk resistance while avoiding lattice damage and a sharp drop in mobility due to excessive doping. This ensures that the current can spread efficiently and smoothly from below the electrode to the entire light-emitting region, suppressing the hotspot effect caused by localized current congestion and providing a low-defect-density growth basis for the top ultra-high doped layer, thus reducing the operating voltage and improving reliability.

[0030] Optionally, the doping concentration of the second GaP sublayer 412 increases monotonically along the direction from the first GaP sublayer 411 to the second GaP sublayer 412.

[0031] In the above implementation, by smoothly transitioning from a lower concentration near the first GaP sublayer 411 to a higher concentration near the third GaP sublayer 413, this design achieves dual optimization: on the one hand, the lower concentration on the lower side maintains the high crystal quality of the first GaP sublayer 411, preventing defects from extending upwards; on the other hand, the gradually increasing concentration on the upper side effectively reduces the abrupt change in doping concentration between the upper layer and the top layer of heavily doped contact layer, reducing band spikes and carrier injection barriers at the interface, allowing current to more smoothly transition from lateral expansion to vertical injection. This non-uniform concentration distribution essentially constructs a gentle slope for electrical and material properties, improving overall current expansion efficiency while maximizing the integrity of the material.

[0032] Optionally, the doping concentration of the third GaP sublayer 413 is less than or equal to 6.0 × 10⁻⁶. 19 / cm -3 .

[0033] In the above implementation, the concentration of impurity atoms (such as Mg) incorporated into the GaP crystal cannot exceed its maximum solid solubility in GaP. Exceeding this limit, the impurities will be unable to enter the lattice sites and will instead precipitate to form a second phase or clusters. These non-electroactive substances not only fail to provide more charge carriers but also become strong scattering and recombination centers, leading to a collapse in electrical performance. This setting prevents the third GaP sublayer 413 from exceeding its maximum solid solubility while simultaneously ensuring that the superior third GaP sublayer 413 is an excellent tunneling ohmic contact layer.

[0034] For example, the doping concentration of the third GaP sublayer 413 is 5.0 × 10⁻⁶. 19 / cm -3 6.0×10 19 / cm -3 This allows for tunneling between the third GaP sublayer 413 and the electrode through heavy doping, thereby reducing contact resistance.

[0035] Optionally, the thickness of the first GaP sublayer 411 is 10 nm to 30 nm.

[0036] In the above implementation, the sufficient thickness of the first GaP sublayer 411 provides enough extension space and energy dissipation distance for defects, causing them to bend, annihilate each other, or terminate within the buffer layer, thereby preventing them from penetrating upwards to the active light-emitting region. This is equivalent to establishing a "defect isolation wall," which is fundamental to improving internal quantum efficiency. If it is too thin, the transition cannot be completed, resulting in stress concentration; if it is too thick, mismatch dislocations may be generated due to stress accumulation.

[0037] For example, the thickness of the first GaP sublayer 411 is 20 nm or 25 nm. This allows the first GaP sublayer 411 to have sufficient thickness to provide enough space for defects to extend.

[0038] Optionally, the thickness of the second GaP sublayer 412 is 0.5 μm to 2.0 μm.

[0039] This thickness range ensures that after current is injected from below the electrodes, there is a sufficient vertical cross-section for low-resistance conduction (reducing bulk resistance voltage drop), while its lateral resistance is controlled within a reasonable range. This forces the current to diffuse fully and uniformly to the chip edge region, effectively suppressing local current congestion and hot spot formation. Too thin a thickness increases the spreading resistance, leading to uneven light emission; too thick a thickness increases epitaxial costs and time, and the marginal benefit to performance improvement diminishes. This thickness ensures uniform light emission over a large chip area, reducing the overall operating voltage.

[0040] For example, the thickness of the second GaP sublayer 412 is 1.0 μm or 1.5 μm. This ensures that after current is injected from below the electrode, there is a sufficient vertical cross-section for low-resistance conduction.

[0041] Optionally, the thickness of the third GaP sublayer 413 is 50 nm to 200 nm.

[0042] This thickness ensures that the third GaP sublayer 413 provides the extremely high doping concentration required for efficient tunneling, thereby reducing the contact resistance at the metal-semiconductor interface. Simultaneously, due to its extremely thin thickness, even if the material in this layer has poor crystal quality and high resistivity due to ultra-high doping, its contribution to the overall series resistance is negligible. More importantly, the thin-layer design limits the total amount of highly active dopant atoms, reducing the risk of harmful segregation or interface reactions in subsequent processes, and ensuring the long-term stability and reliability of the ohmic contact.

[0043] For example, the thickness of the third GaP sublayer 413 is 80 nm or 100 nm. This ensures that the third GaP sublayer 413 provides a sufficiently high doping concentration to achieve efficient tunneling.

[0044] Figure 2 This is a schematic diagram of another light-emitting diode structure provided in an embodiment of this disclosure, as shown below. Figure 2 As shown, the light-emitting diode also includes a bonding substrate 50, a first electrode 51 and a second electrode 52. The bonding substrate 50 is located on the side of the GaP window layer 41 away from the multiple quantum well layer 2 and is connected to the GaP window layer 41.

[0045] The first electrode 51 is located on the side of the n-type semiconductor layer 1 away from the multi-quantum well layer 2, and is electrically connected to the n-type semiconductor layer 1.

[0046] The second electrode 52 is located on the side of the bonding substrate 50 away from the GaP window layer 41 and is electrically connected to the GaP window layer 41.

[0047] In the above implementation, the bonding substrate 50 can create conditions for extracting light from the n-plane after the epitaxial growth substrate is removed, which is a prerequisite for improving the light extraction efficiency.

[0048] For example, the bonding substrate 50 can be a substrate such as silicon, copper, or conductive ceramic. This allows for efficient heat dissipation from the active region, greatly improving the chip's power handling capacity and long-term reliability. Furthermore, it provides a robust mechanical substrate, enhancing the chip's physical strength and facilitating subsequent packaging and processing.

[0049] Figure 3 This is a schematic diagram of the epitaxial layer structure of a light-emitting diode provided in an embodiment of this disclosure, as shown below. Figure 3 As shown, the n-type semiconductor layer 1 includes an n-type ohmic contact layer 12, an n-type current spreading layer 13, and an n-type confinement layer 14 stacked sequentially. The n-type confinement layer 14 is connected to the multi-quantum well layer 2.

[0050] In the above implementation, the n-type ohmic contact layer 12 is used to achieve ohmic contact. The n-type current spreading layer 13 is used to rapidly and uniformly spread the injected point or line current in the lateral direction (parallel to the surface of the substrate), enabling it to be uniformly injected into the entire light-emitting layer, thereby avoiding current congestion, achieving uniform light emission, and improving device performance and reliability. Without the n-type current spreading layer 13, the current would take the shortest path with the least resistance, resulting in a highly non-uniform current density distribution. The n-type confinement layer 14 is used to effectively confine charge carriers, thereby improving recombination efficiency.

[0051] Optionally, the n-type ohmic contact layer 12 is an n-type GaAs layer with a thickness of 30nm~80nm.

[0052] In the above implementation, the thickness of the n-type ohmic contact layer 12 is 30nm~80nm. This thickness ensures that the resistance of the n-type ohmic contact layer 12 is low, providing a sufficient and low-resistance path for charge carriers and ensuring the formation of excellent ohmic contacts. If the thickness is too thin, it may lead to excessively high series resistance, affecting current injection efficiency. On the other hand, if the thickness is too large, it may lead to crystal defects (such as dislocations), and the processing time is longer, which is not conducive to improving efficiency.

[0053] Optionally, the n-type ohmic contact layer 12 is silicon-doped, with Si2H6 as the dopant and a doping concentration of 4 × 10⁻⁶. 18 ~8×10 18 / cm 3 .

[0054] In the above implementation, a silicon source is used as the n-doping source when forming the n-type ohmic contact layer 12. Since silicon is a group IV element with four valence electrons, while group III elements only have three, there is one extra free electron. This free electron becomes the charge carrier, thus achieving n-type doping. Furthermore, the doping concentration in the n-type ohmic contact layer 12 is set to 4 × 10⁻⁶. 18 ~8×10 18 / cm 3 This indicates that within the n-type ohmic contact layer 12, there are 4 × 10⁻⁶ ohmic points per cubic centimeter of volume. 18 ~8×10 18 One free electron. This is represented by heavy doping. Through heavy doping, an extremely thin depletion region is formed on the surface of the n-type semiconductor layer, allowing electrons to easily pass through via quantum tunneling, thus forming a linear, low-resistance ohmic contact.

[0055] For example, the surface of the n-type ohmic contact layer 12 away from the multi-quantum well layer 2 (i.e., the light extraction surface) is roughened to form a micro / nano structure with a specific morphology. This effectively disrupts total internal reflection of light at the semiconductor-air interface, thereby scattering and extracting more photons trapped inside the chip, significantly improving the chip's light extraction efficiency.

[0056] Optionally, the n-type current spreading layer 13 is an n-type AlGaInP layer with a thickness of 1.5μm to 2.5μm.

[0057] In the above implementation, the n-type AlGaInP layer is chosen as the n-type current spreading layer 13 because it has a low resistivity, acting as a conductive platform to allow the current to diffuse laterally before reaching the multi-quantum well layer 2. The 1.5μm~2.5μm thick n-type current spreading layer 13 provides sufficient lateral transport paths, allowing the current to diffuse uniformly from the electrode contact point to the entire active region, avoiding current concentration below the electrode.

[0058] Optionally, the n-type confinement layer 14 is an n-type AlInP layer with a thickness of 250nm~450nm.

[0059] In the above implementation, the main function of this layer is to more tightly confine the photons generated within the multi-quantum-well layer 2, greatly suppressing photon leakage losses. Simultaneously, its sufficient thickness ensures the adequacy of the light confinement effect, ultimately significantly improving the photon extraction efficiency and output power of the device.

[0060] For example, the n-type confinement layer 14 is silicon-doped, wherein the dopant is Si2H6 and the doping concentration is 1×10⁻⁶. 18 ~4×10 18 / cm 3 .

[0061] Si₂H₆ (silyl ether) is a commonly used n-type dopant source in III-V semiconductors. After decomposition, it can stably provide Si atoms (replacing Ga / Al atoms and providing free electrons), exhibiting high doping efficiency and good uniformity. Setting the above doping concentration ensures that the conductivity of the n-type confinement layer 14 is sufficiently high (reducing current transmission losses) without increasing crystal defects due to excessive doping (defects reduce carrier mobility).

[0062] Optionally, the n-type semiconductor layer 1 further includes an electrode bonding layer 15 and a roughening layer 16, both of which are located between the n-type current spreading layer 13 and the n-type ohmic contact layer 12. The electrode bonding layer 15 is connected to the n-type ohmic contact layer 12.

[0063] In the above implementation, the electrode bonding layer 15 is used to connect with the n-type ohmic contact layer 12, and its main function is to provide excellent mechanical adhesion and thermal stability. As a robust adhesive layer, it ensures that the entire metal electrode system can withstand thermal and mechanical stresses during subsequent packaging, bonding, and long-term use, and will not peel off from the semiconductor surface.

[0064] The roughening layer 16 is used to force the current to switch from a lateral expansion mode to a vertical transport mode. Because the roughening layer 16 is a patterned structure, it physically blocks the current through its unetched regions and forces it to flow downwards through the etched windows. This design discretizes the large-area injected current into a large number of uniformly distributed injection points, working in conjunction with the lateral transport function of the n-type current expansion layer 13 to ensure that the current can be uniformly and efficiently injected vertically into the multi-quantum-well layer 2, thereby significantly improving luminescence uniformity and efficiency.

[0065] Subsequently, the electrode bonding layer 15 is an n-type GaInP layer with a thickness of 10 nm to 15 nm. The electrode bonding layer 15 is silicon-doped, with Si₂H₆ as the dopant and a doping concentration of 4 × 10⁻⁶. 18 ~8×10 18 / cm 3 .

[0066] In the above implementation, GaInP material itself possesses extremely high chemical stability and mechanical strength, effectively preventing the diffusion of electrode metal. A suitable Si doping concentration (4 × 10⁻⁶) is also crucial. 18 ~8×10 18 / cm 3 This ensures good conductivity and keeps series resistance at a low level. The thickness of 10nm~15nm provides sufficient protection and adhesion while avoiding unnecessary material consumption and stress accumulation.

[0067] Optionally, the roughening layer 16 is an n-type AlGaInP layer with a thickness of 0.5µm to 1.5µm. The roughening layer 16 is silicon-doped, with Si₂H₆ as the dopant and a doping concentration of 1×10⁻⁶. 18 ~4×10 18 / cm 3 The surface of the roughened layer 16 has random or periodic micron / nanoscale structures.

[0068] In the above implementation, the doping concentration of the roughened layer 16 is 1×10⁻⁶. 18 ~4×10 18 / cm 3This design ensures that the roughened layer 16 has good conductivity, avoiding unnecessary voltage drops. A thickness of 0.5µm to 1.5µm is sufficient to form an effective current-blocking region after etching, without excessively increasing the overall device thickness or introducing excessive growth stress, thus guaranteeing process feasibility and structural reliability. The micron / nanoscale structure on the surface of the roughened layer 16 creates a rough morphology, disrupting total internal reflection and allowing more light to escape from the chip, thereby improving chip brightness.

[0069] Optionally, the p-type semiconductor layer 4 further includes a p-type confinement layer 42 and a p-type stress transition layer 43, both of which are located between the multi-quantum well layer 2 and the GaP window layer 41. The p-type confinement layer 42 is connected to the multi-quantum well layer 2.

[0070] The p-type confinement layer 42 is used to form a bandgap difference with the multi-quantum well layer 2, thereby increasing the probability of holes and electrons meeting and recombinating within the multi-quantum well layer 2. The p-type stress transition layer 43 can effectively buffer and release the huge stress caused by lattice mismatch at the interface between different materials, greatly suppressing the generation of defects such as dislocations, and improving material quality and device reliability.

[0071] Optionally, the p-type stress transition layer 43 is a p-type AlGaInP layer. The thickness of the p-type stress transition layer 43 is 10 nm to 20 nm, the dopant is Cp₂Mg, and the doping concentration is 1 × 10⁻⁶. 18 ~2×10 18 / cm 3 .

[0072] The above thickness setting ensures the effectiveness of the p-type stress transition layer 43 and avoids excessively increasing the total thickness and series resistance of the device. If it is too thin, the gradient will be too abrupt, losing the stress buffering effect and resembling an abrupt heterojunction, which is prone to defects. Moreover, the above doping concentration can form an extremely thin depletion region at the metal-semiconductor interface, allowing carriers to be transported mainly through tunneling, thereby significantly reducing contact resistance.

[0073] Optionally, the p-type confinement layer 42 is a p-type AlInP layer. The thickness of the p-type confinement layer 42 is 250 nm to 450 nm, the dopant is Cp₂Mg, and the doping concentration is 4 × 10⁻⁶. 17 ~7×10 17 / cm 3 .

[0074] The p-type confinement layer 42 is made of AlInP material, which forms a strong barrier on the p-region side, tightly confining photons to the emitting core region and greatly suppressing photon leakage to absorption regions such as the p-type metal electrode. Simultaneously, Cp₂Mg is used for doping at a concentration of 4 × 10⁻⁶. 17~7×10 17 / cm 3 This ensures sufficient conductivity to support longitudinal current transmission while avoiding free carrier absorption losses caused by excessive doping.

[0075] See also Figure 3 Optionally, the light-emitting diode also includes a growth substrate 5, an etch stop layer 6, and a buffer layer 7. The buffer layer 7 and the etch stop layer 6 are stacked sequentially on the growth substrate 5, and the etch stop layer 6 is connected to the n-type ohmic contact layer 12.

[0076] In the above implementation, the growth substrate 5 serves as the growth platform for the entire epitaxial layer of the light-emitting diode, simultaneously undertaking core functions such as physical support, lattice matching, and thermal or electrical conduction, directly affecting the quality of the epitaxial layer and the reliability of the device. The etching stop layer 6 is used to create a difference in etching rate between the etch stop layer 6 and adjacent layers when subsequent processes (such as peeling off the growth substrate 5) require etching a certain layer, achieving "etching stops at etch stop layer 6". The buffer layer 7 serves to transition and prevent the upward propagation of lattice defects and impurities in the growth substrate 5, providing a high-quality epitaxial starting platform with a complete lattice and a clean surface for subsequent functional layers.

[0077] In this design, growth substrate 5 is a gallium arsenide (GaAs) substrate. The etching stop layer 6 is an n-type GaInP layer with a thickness of 100nm~200nm, doped with Si2H6 at a doping concentration of 1×10⁻⁶. 18 ~4×10 18 / cm 3 Buffer layer 7 is a GaAs buffer layer with a thickness of 150nm~250nm, and the dopant is Si2H6 with a doping concentration of 1×10⁻⁶. 18 ~4×10 18 / cm 3 .

[0078] This disclosure also provides a method for fabricating a light-emitting diode, such as... Figure 4 As shown, the preparation method includes: S401: Forming an n-type semiconductor layer, a multiple quantum well layer, and a p-type semiconductor layer stacked sequentially.

[0079] The p-type semiconductor layer 4 includes a first GaP sublayer 411, a second GaP sublayer 412, and a third GaP sublayer 413 stacked sequentially, wherein the first GaP sublayer 411 is connected to the multi-quantum well layer 2.

[0080] The doping concentrations in the first GaP sublayer 411, the second GaP sublayer 412, and the third GaP sublayer 413 gradually increase, with the doping concentration of the third GaP sublayer 413 being equal to or greater than 8.0 × 10⁻⁶. 18 / cm.

[0081] An atmosphere maintenance process is also included between the formation of the first GaP sublayer and the second GaP sublayer. The atmosphere holding process includes maintaining a temperature of 680℃~720℃ under a phosphine protective atmosphere for 1 to 3 minutes.

[0082] The above-mentioned LEDs have the same beneficial effects as those of the aforementioned light-emitting diodes, and will not be repeated here.

[0083] This disclosure also provides another method for fabricating a light-emitting diode, such as... Figure 5 As shown, the preparation method includes: S501: Forms a stacked n-type semiconductor layer and a multi-quantum well layer.

[0084] See Figure 3 An n-type semiconductor layer 1 and a multi-quantum well layer 2 are formed sequentially on a growth substrate 5.

[0085] The growth substrate 5 can be a GaAs substrate. The growth substrate serves as the base for epitaxial layer growth, providing physical support.

[0086] In this embodiment, a metal-organic chemical vapor deposition process is used to sequentially form an n-type semiconductor layer and a multi-quantum well layer on a growth substrate.

[0087] S502: A stacked p-type confinement layer and stress transition layer are formed on a multi-quantum well layer.

[0088] The p-type confinement layer 42 and the stress transition layer 43 are also formed using a metal-organic chemical vapor deposition process.

[0089] S503: The first GaP sublayer is formed on the stress transition layer.

[0090] The temperature of the reaction chamber was controlled at 600℃ ~ 650℃, and the growth rate was 0.5~1nm / s; simultaneously, the Mg doping concentration was controlled at 5.0×10⁻⁶. 17 / cm -3 ~1.0×10 18 / cm -3 To form a first GaP sublayer 411 with a thickness of 10nm~30nm.

[0091] According to crystal growth theory, at temperatures far below the optimal epitaxial temperature, the nucleation barrier decreases, and the nucleation density increases significantly. At this point, slow growth is employed to provide sufficient migration time for atoms, which helps to form a large number of small, uniformly distributed nuclei. The core purpose of this layer is to achieve "soft landing" epitaxy. By first growing a thin and dense first GaP sublayer at a low temperature, the stress caused by lattice mismatch between the subsequent high-temperature thick GaP layer and the underlying AlGaInP layer can be buffered. This serves as a stress transition layer, effectively preventing dislocations from extending into the active region and laying the foundation for growing a high-quality window layer. The use of moderate to low Mg doping is to ensure conductivity while avoiding damage to the initial lattice caused by high-concentration dopants.

[0092] S504: Anneal the above structure.

[0093] During annealing, the first GaP sublayer 411 is held at 680℃~720℃ for 1~3 minutes. Then, the flow of TMGa (trimethylgallium) is stopped, and the temperature is raised to 680℃~720℃ under a phosphine protective atmosphere and held for 1~3 minutes.

[0094] High temperatures provide atoms with higher kinetic energy. Following the principle of defect dynamics, point defects (such as vacancies and interstitial atoms) become active and migrate under these conditions, thus annihilating or recombinizing.

[0095] This step involves in-situ crystallization and repair of the first GaP sublayer. Firstly, annealing effectively eliminates point defects introduced by low-temperature growth, significantly reducing the density of non-radiative recombination centers. Secondly, it promotes the fusion of nucleation layer grains, forming a single-crystal transition layer with higher crystal quality. Thirdly, it activates Mg acceptors, breaks the Mg-H complex, increases the doping concentration, and creates conditions for low-resistance current transport.

[0096] S505: A second GaP sublayer is formed on the first GaP sublayer.

[0097] Controlling the Mg doping concentration from 2.0 × 10 18 / cm -3 Gradient boosted to 6.0×10 18 / cm -3 To form a second GaP sublayer 412 with a thickness of 0.5μm~2.0μm.

[0098] This stage is carried out at 680℃~720℃, with the growth rate controlled at 2.0nm / s~3.0nm / s.

[0099] High-speed growth helps suppress impurity segregation and obtain uniform crystal quality. Gradient-increasing Mg concentration utilizes the built-in electric field effect, which is naturally formed by the concentration gradient and can assist holes (majority carriers) to diffuse towards the chip edge.

[0100] This layer is the main channel for the lateral spread of current. Its core function is to achieve low-resistance bulk conductance. The uniform, high-quality crystal ensures a low defect density, while the built-in electric field generated by gradient doping accelerates hole transport. Together, these factors significantly reduce the series resistance of the window layer itself, which is the first key contribution to reducing the operating voltage.

[0101] S506: A third GaP sublayer is formed on the second GaP sublayer.

[0102] The third GaP sublayer is configured such that the GaP window layer forms a tunneling ohmic contact with the metal it contacts, thereby enabling the third GaP sublayer to...

[0103] The Mg doping concentration was controlled to be increased to 8.0 × 10⁻⁶. 18 cm -3 ~6.0×10 19 cm -3 To form a third GaP sublayer 413 with a thickness of 50nm~200nm.

[0104] Continue to maintain the reactor temperature at 680℃~720℃ and control the growth rate at 1.0nm / s~2.0nm / s.

[0105] The Mg doping concentration increased dramatically to 8.0 × 10⁻⁶. 18 cm -3 ~6.0×10 19 cm -3 According to metal-semiconductor contact theory, the ultra-high surface doping concentration makes the barrier layer extremely thin, allowing charge carriers to pass directly through via quantum tunneling, thus achieving excellent ohmic contacts. Simultaneously, reducing the growth rate and applying high temperatures promotes a shift in the growth pattern from two-dimensional layers to three-dimensional islands, based on the principles of surface diffusion and energy minimization.

[0106] This layer performs two core functions. First, through heavy Mg doping, it forms a tunneling ohmic contact at the interface with the metal electrode, which is the most effective way to reduce contact resistance and the second key contribution to reducing the operating voltage. Second, it induces the formation of a micron-scale rough structure on the surface, which disrupts total internal reflection of light at the GaP / air interface through light scattering, directly improving light extraction efficiency and achieving synergistic optimization of "voltage reduction" and "brightness enhancement".

[0107] S507: Bond the substrate to the surface of the GaP window layer away from the multi-quantum-well layer, remove the growth substrate, and fabricate the first and second electrodes.

[0108] See also Figure 2 as well as Figure 3A bonding substrate 50 is attached to the surface of the GaP window layer away from the multi-quantum-well layer (i.e., the surface of the third GaP sublayer away from the first GaP sublayer), and the growth substrate 5 is removed. The core function of the bonding substrate 50 is to achieve structural inversion and functional replacement. It is permanently bonded to the GaP window layer 41. First, after removing the original light-absorbing GaAs growth substrate, the bonding substrate 50 acts as a mechanical support, creating the prerequisite for efficient light extraction from the other side of the chip. Second, as an efficient thermal and electrical pathway, it typically uses a high thermal conductivity material (such as silicon) to quickly dissipate heat generated in the active region of the chip.

[0109] The first electrode 51 is the n-type electrical port of the chip. It is fabricated on the surface of the n-type semiconductor layer 1 (n-type layer) of the chip, forming an ohmic contact with the n-type semiconductor layer 1, and is responsible for injecting external current into the n-type region. Its position design ensures that the current must run vertically through the entire epitaxial structure, ensuring that the active region is uniformly excited. The first electrode 51 is usually designed in a grid shape to balance conductivity and light transmittance, and is a necessary endpoint for forming a complete light-emitting circuit.

[0110] The second electrode 52 serves as the chip's p-type electrical port and heat dissipation enhancer. It is fabricated on the back side of the bonding substrate 50, away from the GaP window layer 41. The p-type GaP window layer is electrically connected to the bonding substrate 50 through a conductive bonding layer. This design not only provides extremely low contact resistance and excellent lateral current spread capability, but also uses the second electrode 52 itself as a large-area heat sink, forming the shortest and most efficient heat dissipation path together with the bonding substrate 50, significantly reducing thermal resistance.

[0111] The above fabrication method allows for a reverse polarity process in chip manufacturing. The GaP window layer 41 is bonded to the bonding substrate 50 (Si) before the second electrode is fabricated. After removing the growth substrate (GaAs substrate), the surface of the n-type semiconductor layer 1 furthest from the quantum well layer 2 (i.e., the surface of the n-type ohmic contact layer 12 furthest from the quantum well layer 2) is roughened to improve light extraction efficiency. Following this, the first electrode 51 is fabricated on the n-type ohmic contact layer 12 (n-type GaAs layer), thus obtaining... Figure 2 The LED chip shown.

[0112] Under a standard test current of 200mA, the forward operating voltage (Vf) of the LED chip fabricated using this method decreased by a stable 0.10V compared to the traditional single-process method. The experimental data are shown in the table below: Table 1

[0113] Based on the table above, as the current increases, the operating voltage of the LED chip prepared by this method decreases more significantly compared to LED chips in related technologies. This directly demonstrates the superior effect of this method in reducing interface resistance, bulk resistance, and contact resistance. Moreover, thanks to the improved light extraction efficiency resulting from the roughening of the ohmic contact layer surface, the chip brightness is increased by an average of 3% while maintaining the same driving current.

[0114] The above description is merely an optional embodiment of this disclosure and is not intended to limit this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the protection scope of this disclosure.

Claims

1. A light-emitting diode, characterized in that, The light-emitting diode comprises an n-type semiconductor layer (1), a multiple quantum well layer (2), and a p-type semiconductor layer (4) stacked sequentially. The p-type semiconductor layer (4) includes a first GaP sublayer (411), a second GaP sublayer (412) and a third GaP sublayer (413) stacked sequentially, wherein the first GaP sublayer (411) is connected to the multi-quantum well layer (2); The doping concentrations in the first GaP sublayer (411), the second GaP sublayer (412), and the third GaP sublayer (413) gradually increase, with the doping concentration of the third GaP sublayer (413) being equal to or greater than 8.0 × 10⁻⁶. 18 / cm -3 .

2. The light-emitting diode according to claim 1, characterized in that, The doping concentration of the first GaP sublayer (411) is 5.0 × 10⁻⁶. 17 / cm -3 ~1.0×10 18 / cm -3 The thickness of the first GaP sublayer (411) is 10nm~30nm.

3. The light-emitting diode according to claim 1 or 2, characterized in that, The doping concentration of the second GaP sublayer (412) is 2.0 × 10⁻⁶. 18 / cm -3 ~6.0×10 18 / cm -3 .

4. The light-emitting diode according to claim 3, characterized in that, The doping concentration of the second GaP sublayer (412) increases monotonically along the direction from the first GaP sublayer (411) to the second GaP sublayer (412).

5. The light-emitting diode according to claim 1, 2 or 4, characterized in that, The thickness of the second GaP sublayer (412) is 0.5 μm to 2.0 μm.

6. The light-emitting diode according to claim 1, 2 or 4, characterized in that, The doping concentration of the third GaP sublayer (413) is less than or equal to 6.0 × 10⁻⁶. 19 / cm -3 .

7. The light-emitting diode according to claim 1, 2 or 4, characterized in that, The thickness of the third GaP sublayer (413) is 50 nm to 200 nm.

8. A method for fabricating a light-emitting diode, characterized in that, The preparation method includes: Forming an n-type semiconductor layer, a multiple quantum well layer, and a p-type semiconductor layer stacked sequentially; The p-type semiconductor layer includes a first GaP sublayer, a second GaP sublayer, and a third GaP sublayer stacked sequentially, wherein the first GaP sublayer is connected to the multiple quantum well layer; The doping concentrations in the first GaP sublayer, the second GaP sublayer, and the third GaP sublayer gradually increase, and the doping concentration of the third GaP sublayer is equal to or greater than 8.0 × 10⁻⁶. 18 / cm -3 ; An atmosphere holding process is also included between the formation of the first GaP sublayer and the second GaP sublayer. The atmosphere holding process includes maintaining a temperature of 680°C to 720°C under a phosphine protective atmosphere for 1 to 3 minutes.

9. The preparation method according to claim 8, characterized in that, The first GaP sublayer is formed at a growth temperature of 600°C to 650°C and a growth rate of 0.5 nm / s to 1 nm / s.

10. The preparation method according to claim 8, characterized in that, When forming the second GaP sublayer, the second GaP sublayer is formed at a growth temperature of 680℃~720℃ and a growth rate of 2.0nm / s~3.0nm / s. The third GaP sublayer is formed at a growth temperature of 680°C to 720°C and a growth rate of 0 nm / s to 2.0 nm / s.

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