Wafer stack structure and method of manufacturing the same

Abstract

The application discloses a wafer stacking structure and a preparation method thereof. The wafer stacking structure comprises a bearing substrate and a first spliced wafer. The bearing substrate has a first size, and the first spliced wafer is bonded to the surface of the bearing substrate and comprises a plurality of spliced structures. The plurality of spliced structures are closely arranged on the bearing substrate and jointly cover the entire surface of the bearing substrate, and a light-emitting diode structure is formed on each spliced structure. Each spliced structure is formed by cutting a growth substrate with a second size to a preset shape after an epitaxial layer is grown on the growth substrate. The first size is larger than the second size. The first spliced wafer contained in the wafer stacking structure of the application is formed by splicing the spliced structures. The spliced structures are formed by cutting a growth substrate with a small size to form an epitaxial layer, and have good growth quality. Therefore, the wafer stacking structure formed by the spliced structures also has high product quality.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, and more specifically to a wafer stacking structure and its fabrication method. Background Technology

[0002] As augmented reality / virtual reality (AR / VR) devices evolve towards ultra-high resolution, miniaturization, and lightweight design, they place extremely stringent technical requirements on the core display component, Micro LED. These requirements include: pixel density exceeding 5000 PPI, high brightness and low power consumption, and highly compact integrated packaging.

[0003] However, existing technical solutions face multiple bottlenecks in meeting the above requirements, mainly in the following aspects:

[0004] First, regarding material growth and substrate size, high-quality gallium nitride (GaN)-based epitaxial layers can typically only be obtained on 4-inch or 6-inch sapphire substrates. If direct growth is attempted on large-size silicon substrates of 12 inches or larger, the epitaxial quality will significantly decrease, the defect density will remain high, and it will be difficult to meet the crystal quality requirements of high-performance light-emitting diodes.

[0005] Secondly, in terms of mass transfer technology, the traditional "pick and place" transfer technology is inefficient for high-density Micro LED arrays, and its alignment accuracy and production capacity cannot support the large-scale mass production needs of ultra-high pixel density Micro LED displays.

[0006] Furthermore, in terms of color integration, red, green, and blue Micro LEDs are based on different semiconductor material systems (e.g., red LEDs typically use AlGaInP or GaAs, while green and blue LEDs mostly use GaN), making their epitaxial growth conditions incompatible with the substrate materials. Existing technologies often use a method of arranging the three color chips side-by-side in a plane to achieve color display. This approach greatly sacrifices the pixel density per unit area, resulting in limited display resolution.

[0007] Furthermore, existing process solutions also face problems of low wafer utilization and high manufacturing costs. Since high-quality epitaxial wafers are limited to small-sized substrates, the fabrication of large-sized display areas requires complex splicing or transfer techniques. This results in low effective utilization of small-sized GaN wafers, and the process difficulty and manufacturing costs increase dramatically during subsequent multilayer structure processing, multiple alignments, and transfers, making yield control difficult. Summary of the Invention

[0008] In view of the shortcomings of the prior art, the purpose of this invention is to provide a wafer stacking structure and its fabrication method to form a large-size, high-quality light-emitting diode epitaxial layer.

[0009] To achieve the above and other related objectives, the present invention provides a wafer stacking structure, comprising:

[0010] A carrier substrate, the carrier substrate having a first dimension;

[0011] The first splicing wafer is bonded to the surface of the carrier substrate; the first splicing wafer includes multiple splicing structures, which are closely arranged on the carrier substrate and together cover the entire surface of the carrier substrate, and each splicing structure has a light-emitting diode structure formed on it.

[0012] Each splicing structure is formed by growing an epitaxial layer on a growth substrate of size two and then cutting it to a preset shape, wherein the first size is larger than the second size.

[0013] Optionally, there are joints between multiple splicing structures, which are formed by butt joints of the edges of adjacent splicing structures, and the size of the joints does not exceed 5 μm.

[0014] Optionally, multiple light-emitting diode (LED) units are formed on the first splicing wafer, and the multiple LED units are arranged in an array. When the size of the LED unit is less than 10 mm², the splicing structure is formed as a regular hexagon, and the multiple splicing structures are arranged in a honeycomb pattern. When the size of the LED unit is between 10 mm² and 50 mm², the splicing structure is a mixture of regular hexagons and rectangles or trapezoids, with the regular hexagons set at the center of a single splicing structure, and the rectangles or trapezoids corresponding to each side of the regular hexagons set on the periphery of the regular hexagons. When the size of the LED unit is between 50 mm² and 100 mm², the shape of the splicing structure is rectangular, and the multiple splicing structures are arranged in a row and column arrangement. When the size of the LED unit is greater than 100 mm², the splicing structure is formed as a square, and the multiple splicing structures are arranged in a row and column arrangement.

[0015] Optionally, multiple splicing structures above the carrier substrate have the maximum filling efficiency. A number of light-emitting diode (LED) units separated by dicing channels are formed on the first splicing wafer. In the region of each LED unit, LED units with splicing seams are abnormal LED units, and LED units without splicing seams are normal LED units. The formula for calculating the filling efficiency is: η = N×S / [π×(D / 2)²], where N is the number of normal LED units on the first splicing wafer, S is the size of the LED unit, and D is the size of the target wafer.

[0016] Optionally, the wafer stacking structure further includes at least a second splicing wafer, which is bonded to the surface of the first splicing wafer away from the carrier substrate. The second splicing wafer includes multiple splicing structures, each splicing structure having a light-emitting diode structure formed thereon, and the light emitted by the light-emitting diode structure of the second splicing wafer is a different color than the light emitted by the light-emitting diode structure of the first splicing wafer.

[0017] Optionally, the wafer stacking structure also includes a third splicing wafer, which is bonded to the surface of the second splicing wafer away from the first splicing wafer. The third splicing wafer includes multiple splicing structures, and each splicing structure also has a light-emitting diode structure formed on it. The light emitted by the light-emitting diode structure of the second splicing wafer is a different color than the light emitted by the light-emitting diode structures on the other two splicing wafers.

[0018] Optionally, the light-emitting diode structures in the first, second, and third splicing wafers are Micro LED structures of different colors.

[0019] Optionally, the carrier substrate and the first splicing wafer are bonded using a hybrid bonding technology.

[0020] Optionally, the shape of the splicing structure on the first splicing wafer includes one or more of the following: regular hexagon, square, trapezoid, or rectangle.

[0021] Optionally, the substrate can be a bare substrate or a wafer with a functional structure.

[0022] According to one aspect of the present invention, a method for fabricating a wafer stacked structure is also provided, comprising:

[0023] S1: Obtain multiple spliced ​​structures. Each spliced ​​structure is formed by growing an epitaxial layer on a growth substrate with a size of the second dimension and then cutting it to a preset shape.

[0024] S2: A carrier substrate is provided, the carrier substrate having a first dimension, the first dimension being larger than a second dimension;

[0025] S3: Multiple splicing structures are arranged closely on the surface of the carrier substrate and together cover the entire surface of the carrier substrate.

[0026] Optionally, the step of obtaining multiple spliced ​​structures includes:

[0027] Based on the dimensions of the target wafer and the target LED unit, the optimal splicing scheme is determined, including the shape, size, and arrangement of the splicing structure.

[0028] The shape and size of the splicing structure are determined based on the optimal splicing scheme, and then it is cut.

[0029] Optionally, the step of determining the optimal splicing scheme based on the dimensions of the target splicing wafer and the dimensions of the target light-emitting diode unit includes:

[0030] Obtain the dimensions of the target splicing wafer and the dimensions of the target light-emitting diode unit;

[0031] Based on the target splicing wafer size and the target light-emitting diode unit size, the shape, size and arrangement of the target splicing structure are traversed;

[0032] The number of normal LED units on the target wafer is obtained based on the target LED unit size, the shape, size and arrangement of the target splicing structure;

[0033] The filling efficiency is calculated based on the number of normal LED units on the target wafer, the size of the target spliced ​​wafer, and the size of the target LED unit.

[0034] The optimal splicing scheme is to select the shape, size, and arrangement of the target splicing structure that corresponds to the highest filling efficiency.

[0035] Optionally, the step of calculating the fill efficiency based on the number of normal light-emitting diode units on the target splicing wafer, the target wafer size, and the target light-emitting diode unit size includes:

[0036] The filling efficiency is calculated based on the formula η = N×S / [π×(D / 2)²], where η is the filling efficiency, N is the number of normal LED units on the spliced ​​wafer, S is the size of the LED unit, and D is the size of the target wafer.

[0037] Optionally, after step S3, the method further includes:

[0038] Based on the optimal splicing scheme, multiple splicing structures are closely arranged on the surface of the supporting substrate.

[0039] Repeat steps S1 to S3 to sequentially stack the second and third splicing wafers on the first splicing wafer.

[0040] Compared with the prior art, the wafer stacking structure and its fabrication method described in this invention have at least the following beneficial effects:

[0041] The wafer stacking structure of the present invention includes a carrier substrate and a first splicing wafer. The first splicing wafer is bonded to the surface of the carrier substrate and includes multiple splicing structures. The multiple splicing structures are closely arranged on the surface of the carrier substrate and collectively cover the entire surface of the carrier substrate. Each splicing structure has a light-emitting diode structure formed on it. Each splicing structure is formed by growing an epitaxial layer on a growth substrate of a second size and then cutting it to a predetermined shape. The first size is larger than the second size. Therefore, the first splicing wafer in the wafer stacking structure of the present invention is formed by splicing structures, which are formed by growing an epitaxial layer on a small-sized growth substrate and then cutting it, resulting in better growth quality. Consequently, the wafer stacking structure composed of these splicing structures also has higher product quality.

[0042] Since each splicing structure has multiple light-emitting diode units, by transferring and bonding the splicing structures one by one to the carrier substrate, multiple light-emitting diode units can be transferred at one time, thereby improving the transfer efficiency of the light-emitting diode units.

[0043] Furthermore, a second and third splicing wafer can be stacked on the first splicing wafer of the wafer stacking structure, wherein the first, second, and third splicing wafers are red, green, and blue GaN epitaxial layers, respectively. Thus, this invention enables RGB full-color Micro-LED displays through 3D vertical integration.

[0044] The wafer stacking structure fabrication method of the present invention is used to fabricate the aforementioned wafer stacking structure and also possesses the aforementioned technical effects. Furthermore, the wafer stacking structure fabrication method of the present invention can achieve maximum filling efficiency of the spliced ​​wafers, thereby ensuring the high quality of the wafer stacking structure.

[0045] This invention provides a complete solution to the key bottlenecks in Micro LED display manufacturing: epitaxial quality, mass transfer, and RGB integration. It is especially suitable for next-generation AR / VR display devices with extremely high requirements for pixel density, display quality, and integration. Attached Figure Description

[0046] Figure 1 This is a schematic diagram of the wafer stacking structure in an embodiment of the present invention;

[0047] Figure 2 This is a structural schematic diagram illustrating the shape and arrangement of the splicing structure in an embodiment of the present invention;

[0048] Figure 3 This is a structural schematic diagram illustrating the shape and arrangement of the splicing structure in an embodiment of the present invention;

[0049] Figure 4 This is a structural schematic diagram illustrating the shape and arrangement of the splicing structure in an embodiment of the present invention;

[0050] Figure 5 This is a structural schematic diagram illustrating the shape and arrangement of the splicing structure in an embodiment of the present invention;

[0051] Figure 6 This is a flowchart illustrating the steps of the wafer stacking structure fabrication method in an embodiment of the present invention.

[0052] Figure 7 This is a schematic diagram of the splicing structure of regular hexagons in an embodiment of the present invention;

[0053] Figure 8 This is a schematic diagram of the bonding structure to the carrier substrate in an embodiment of the present invention.

[0054] Illustration of reference numerals in the attached diagram:

[0055] 100, substrate; 200, first spliced ​​wafer; 201, splicing structure; 202, splicing seam. Detailed Implementation

[0056] The following specific embodiments illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, unless otherwise specified, the following embodiments and features in the embodiments can be combined with each other.

[0057] It should be understood that the illustrations provided in the embodiments of this invention are merely schematic representations of the basic concept of the invention. Although the illustrations only show components relevant to the invention and are not drawn according to the actual number, shape, and size of components in implementation, the shape, quantity, and proportion of each component can be arbitrarily changed in actual implementation, and the component layout may also be more complex. The structures, proportions, sizes, etc., shown in the accompanying drawings are only used to complement the content disclosed in the specification for those skilled in the art to understand and read, and are not intended to limit the conditions under which this application can be implemented. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in the proportional relationships, or adjustments to the size, without affecting the effects and objectives that the invention can produce, should still fall within the scope of the technical content disclosed in this application.

[0058] This embodiment provides a wafer stacking structure, as shown in the reference. Figure 1The wafer stacking structure includes a carrier substrate 100 and a first spliced ​​wafer 200. The carrier substrate 100 can be a bare substrate that serves only as a carrier, such as a silicon substrate, glass substrate, or sapphire substrate, or it can be a wafer with a functional structure formed thereon, such as a logic wafer or a CMOS driver substrate. Optionally, the carrier substrate 100 has a first size, such as 12 inches.

[0059] The first splicing wafer 200 is bonded to the surface of the carrier substrate 100. Optionally, the first splicing wafer 200 and the carrier substrate 100 are bonded together using a hybrid bonding technology, which can achieve high-strength mechanical connection and high-density electrical interconnection. The first splicing wafer 200 includes multiple splicing structures 201. The multiple splicing structures 201 are closely arranged on the surface of the carrier substrate 100 and together cover the entire surface of the carrier substrate 100. A light-emitting diode structure is formed on each splicing structure 201. The size of the first splicing wafer 200 is the same as the size of the carrier substrate 100. There is a splicing seam 202 between the multiple splicing structures 201, which is formed by the edge butt joint of adjacent splicing structures 201. Optionally, the size of the splicing seam 202 does not exceed 5 μm, for example, it is between 2 μm and 3 μm. Each splicing structure 201 is formed by growing an epitaxial layer on a growth substrate with a second size and then cutting it to a predetermined shape, where the first size is larger than the second size. In this embodiment, the wafer stacking structure includes a first splicing wafer 200 with a first size, which is formed by a small-sized splicing structure 201. That is, the small-sized high-quality GaN epitaxial layer splicing structure is transferred to a large-sized wafer for splicing to form a large-sized, high-quality epitaxial layer, which breaks through the limitations of traditional GaN epitaxial size and improves product quality.

[0060] The first splicing wafer 200 has light-emitting diode (LED) units spaced apart by multiple dicing lines, and the multiple LED units are arranged in an array. Within each LED unit region, LED units with splicing seams 202 are abnormal LED units, and LED units without splicing seams 202 are normal LED units. The multiple splicing structures 201 above the carrier substrate 100 have the maximum filling efficiency η to ensure the light output of the first splicing wafer 200. The formula for calculating the filling efficiency η is: η = N×S / [π×(D / 2)²], where N is the number of normal LED units on the first splicing wafer 200, S is the size of the LED unit, and D is the size of the target wafer.

[0061] Optionally, refer to Figures 2-5The cutting shape of the splicing structure 201 can be hexagonal, rectangular, trapezoidal or square. The shape of the splicing structure 201 on each splicing wafer can be one or a combination of hexagonal, rectangular, trapezoidal or square to ensure the maximum filling efficiency, that is, to ensure the maximum number of normal light-emitting diode units on the first splicing wafer 200.

[0062] Reference Figure 2 When the size of the LED unit is less than 10 mm², the splicing structure 201 is formed as a regular hexagon, and multiple splicing structures 201 are arranged in a honeycomb pattern, which can be applied to high-density Miro LED arrays and micro sensors. (Refer to...) Figure 3 When the size of the LED unit is between 10 mm² and 50 mm², the splicing structure 201 is a hybrid of regular hexagons and rectangles or trapezoids. The center of each splicing structure 201 is a regular hexagon, and rectangles or trapezoids are formed around each side of the regular hexagon. This can be applied to medium-sized display modules and optoelectronic integrated chips. This embodiment uses a hybrid of regular hexagons and trapezoids as an example, but it can also be a hybrid of regular hexagons and rectangles. (Refer to...) Figure 4 When the size of the LED unit is between 50 mm² and 100 mm², the splicing structure 201 is rectangular in shape. Multiple splicing structures 201 are arranged in a row and column pattern, which can be applied to power devices and RF modules. (Refer to...) Figure 5 When the size of the light-emitting diode unit is greater than 100 mm², the splicing structure 201 is formed as a square. Multiple splicing structures 201 are arranged in a row and column pattern, which can be applied to large-size display drivers and high-performance computing chips. Optionally, the area of ​​a single splicing structure 201 is between 1 mm² and 15 mm², for example, 10 mm². In this embodiment, the shape of the splicing structure 201 is a regular hexagon. This regular hexagonal splicing structure can maximize the bonding area and reduce material waste.

[0063] The wafer stacking structure further includes at least a second splicing wafer (not shown in the figure), which is bonded to the surface of the first splicing wafer 200 away from the carrier substrate 100. The second splicing wafer includes multiple splicing structures 201, each of which has a light-emitting diode (LED) structure formed on it. The light emitted by the LED structure of the second splicing wafer is a different color than the light emitted by the LED structure of the first splicing wafer 200. Optionally, the wafer stacking structure further includes a third splicing wafer (not shown in the figure), which is bonded to the surface of the second splicing wafer away from the first splicing wafer 200. The third splicing wafer includes multiple splicing structures 201, each of which also has an LED structure formed on it. The light emitted by the LED structure of the second splicing wafer is a different color than the light emitted by the LED structures on the other two splicing wafers. Optionally, the LED structures in the first splicing wafer 200, the second splicing wafer, and the third splicing wafer are Micro LED structures of different colors. For example, the light-emitting diode structures in the first splicing wafer 200, the second splicing wafer, and the third splicing wafer radiate red light, blue light, and green light, respectively. The epitaxial layer radiating red light uses AlGaInP or GaAs material, while the epitaxial layers radiating green and blue light use GaN material.

[0064] The above-mentioned wafer stacking structure can be formed by the following wafer stacking structure fabrication method, referring to... Figure 6 The fabrication method of this wafer stacking structure includes:

[0065] S1: Obtain multiple spliced ​​structures. Each spliced ​​structure is formed by growing an epitaxial layer on a growth substrate with a size of the second dimension and then cutting it to a preset shape.

[0066] S2: A carrier substrate is provided, the carrier substrate having a first dimension, the first dimension being larger than a second dimension;

[0067] S3: Multiple splicing structures are arranged closely on the surface of the carrier substrate and together cover the entire surface of the carrier substrate.

[0068] Specifically, first execute step S1, referring to... Figure 7Multiple splicing structures 201 are obtained. In obtaining multiple splicing structures 201, the optimal splicing scheme with the highest filling efficiency needs to be selected through calculation. The splicing scheme includes the shape, size, and arrangement of the splicing structures 201. The calculation steps include: obtaining the size of the target splicing wafer and the size of the target LED unit; traversing the shape, size, and arrangement of the target splicing structures 201 based on the target splicing wafer size and the target LED unit size; obtaining the number of normal LED units on the target wafer based on the target LED unit size and the shape, size, and arrangement of the target splicing structure 201; and calculating the filling efficiency based on the number of normal LED units on the target wafer, the target splicing wafer size, and the target LED unit size. The calculation of the filling efficiency includes: calculating the filling efficiency based on the formula η = N×S / [π×(D / 2)²], where η is the filling efficiency, N is the number of normal LED units on the splicing wafer, S is the size of the LED unit, and D is the size of the target wafer. The shape and arrangement of the target splicing structure 201 corresponding to the highest filling efficiency are selected as the optimal splicing scheme. Based on the optimal splicing scheme, the shape and size of the splicing structure are obtained. Based on the shape and size of the splicing structure 201, semiconductor epitaxial wafers are cut to obtain the splicing structure 201.

[0069] The fabrication steps of the semiconductor epitaxial wafer include: First, providing multiple 4-inch or 6-inch sapphire substrates, and performing epitaxial growth on the sapphire substrates after pretreatment such as cleaning and annealing. In this embodiment, a GaN epitaxial layer is grown on the sapphire substrate using an MOCVD device to obtain the semiconductor epitaxial wafer. After obtaining the semiconductor epitaxial wafer, it is cut according to the above-mentioned optimal splicing scheme. Specifically, laser stealth dicing technology can be used for cutting to obtain the required splicing structure 201.

[0070] Execute step S2, refer to Figure 8 A carrier substrate 100 is provided, having a first size. The carrier substrate 100 can be a support substrate serving only a carrying function, such as a silicon substrate, glass substrate, or sapphire substrate, or it can be a wafer with a functional structure, such as a logic wafer. Optionally, the carrier substrate 100 has a first size, for example, 12 inches. In this embodiment, a 12-inch (300 mm) silicon substrate is provided as the carrier substrate 100, with a resistivity of 0.01 Ω·cm ~ 0.1 Ω·cm and a thickness of 775 ± 25 μm. A 200 nm thick SiO2 layer is grown on the silicon substrate as an insulating layer to electrically insulate the silicon substrate from the subsequently spliced ​​wafers. Then, a 100 nm thick TiN layer is deposited as an adhesion layer for adhesion to the subsequent splicing structure 201.

[0071] Two alignment mark systems are fabricated on the surface of the carrier substrate 100 for subsequent splicing alignment. The two alignment mark systems include global alignment marks and local fine alignment marks. In this embodiment, the global alignment marks are located at the edge of the carrier substrate 100 for coarse alignment, with a mark size of 50 × 50 μm and a depth of 200 nm. The local fine alignment marks are located at each splicing position for nanoscale fine alignment, with a mark size of 5 × 5 μm and a depth of 100 nm.

[0072] Execute step S3 and continue referring to... Figure 8 Multiple splicing structures 201 are closely arranged on the surface of the carrier substrate 100, collectively covering the entire surface of the carrier substrate 100. Specifically, a high-speed precision picking device is used to pick up and transfer the splicing structures 201, and a machine vision system is used to monitor the chip position and angle in real time to place the splicing structures 201 at the corresponding positions on the carrier substrate. Heat-release adhesive tape is used to temporarily fix the splicing structures 201 to the carrier substrate 100. After temporary bonding, an infrared alignment system is used for fine alignment, with an alignment accuracy requirement of ≤±0.5 μm. Optionally, when the thickness of the splicing structures 201 is relatively thin, temporary bonding adhesive can be used for the transfer of the splicing structures 201.

[0073] Subsequently, the splicing structure 201 will be permanently bonded to the carrier substrate 100, such as... Figure 1 As shown. In this embodiment, a hybrid bonding technology is used for the permanent bonding process. For example, SiO2-SiO2 direct bonding technology is used. During hybrid bonding, a bonding layer is first formed on the bonding interface, and the bonding surface is surface activated. Then, the hybrid bonding interfaces are brought into contact at room temperature, and preliminary bonding is performed at a low temperature. Subsequently, a stepped heating process is used to perform high-temperature annealing on the pre-bonded structure. After bonding, the interface porosity is <0.1%, the bonding strength is >1.5 J / m², and the bonding is good. After permanent bonding, insulating material is filled into the splice seam 202 to electrically isolate adjacent spliced ​​structures 201. In this embodiment, atomic layer deposition (ALD) technology is used to fill Al2O3 into the splice seam 202. The process temperature is 150°C, the number of cycles is 200, and the filling thickness is 200 nm to ensure that the seam is completely sealed and without voids. After filling, the filling surface is chemically mechanically polished to reduce surface roughness and defect density for subsequent bonding or encapsulation.

[0074] After permanent bonding, the temporary bonding adhesive is removed, and the growth substrate of the splicing structure 201 is also removed, leaving only the high-quality epitaxial layer. Optionally, the substrate on the spliced ​​wafer can be irradiated by laser lift-off, automatically separating the sapphire substrate while the GaN epitaxial layer remains on the carrier substrate 100. The peeled surface can then be cleaned with a chemical solution. Optionally, the growth substrate can also be removed using backside thinning, chemical mechanical polishing, and silicon etching processes. Optionally, after permanent bonding, refer to... Figure 8 Combination Figure 1 This also includes cutting off excess wafer portions from the splicing edges. After splicing, functional structure layers such as electrodes are fabricated on the spliced ​​wafer, and then the light-emitting diode units are cut.

[0075] Subsequently, multiple splicing wafers can be added on top of the first splicing wafer 200. For example, a second and third splicing wafer can be stacked, with the splicing steps being the same as steps S1 to S3 described above, and will not be repeated here. Optionally, the first, second, and third splicing wafers are red, green, and blue GaN epitaxial layers, respectively. Therefore, this embodiment can achieve RGB full-color Micro-LED display through 3D vertical integration.

[0076] In summary, the wafer stacking structure of the present invention includes a carrier substrate and a first splicing wafer. The first splicing wafer is bonded to the surface of the carrier substrate and includes multiple splicing structures. The multiple splicing structures are closely arranged on the carrier substrate and collectively cover the entire surface of the carrier substrate. Each splicing structure has a light-emitting diode structure formed on it. Each splicing structure is formed by growing an epitaxial layer on a growth substrate of a second size and then cutting it to a predetermined shape. The first size is larger than the second size. Therefore, the present invention overcomes the limitations of traditional GaN epitaxial size by transferring and splicing a small-size, high-quality GaN epitaxial layer onto a large-size wafer, improving product quality, achieving 3D heterogeneous integration, significantly increasing chip integration density, and is suitable for high-end AR / VR products.

[0077] Since each splicing structure has multiple light-emitting diode units, the splicing structures are transferred one by one and bonded to the carrier substrate. Through wafer-level hybrid bonding technology, efficient and high-precision mass transfer of Micro LED chips is achieved.

[0078] Furthermore, a second and third splicing wafer can be stacked on the first splicing wafer of the wafer stacking structure. The first, second, and third splicing wafers are red, green, and blue GaN epitaxial layers, respectively, enabling accurate vertical alignment. Thus, this invention can achieve RGB full-color Micro-LED display through 3D vertical integration.

[0079] The wafer stacking structure fabrication method of the present invention is used to fabricate the aforementioned wafer stacking structure, and also possesses the aforementioned technical effects. Furthermore, the wafer stacking structure fabrication method of the present invention can achieve maximum filling efficiency of the spliced ​​wafers, ensuring the product quality of the wafer stacking structure.

[0080] This invention provides key technological support for the large-scale commercialization of Micro LED displays, particularly addressing the urgent need for ultra-high pixel density, high brightness, and low power consumption micro-displays in AR / VR devices. Through 12-inch wafer-level processing, the manufacturing cost of Micro LEDs can be reduced to a commercially viable level, accelerating the widespread application of Micro LEDs in consumer electronics.

[0081] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A wafer stacking structure, characterized in that, include: A carrier substrate having a first dimension; The first splicing wafer is bonded to the surface of the carrier substrate; the first splicing wafer includes multiple splicing structures, which are closely arranged on the carrier substrate and together cover the entire surface of the carrier substrate, and each splicing structure has a light-emitting diode structure formed thereon; wherein each splicing structure is formed by growing an epitaxial layer on a growth substrate of size second size and then cutting it to a preset shape, and the first size is larger than the second size; The second splicing wafer is stacked on top of the first splicing wafer; The third splicing wafer is stacked on top of the second splicing wafer. The first, second, and third splicing wafers are used to achieve full-color display.

2. The wafer stacking structure according to claim 1, characterized in that, The plurality of splicing structures have splicing seams, which are formed by the butt joints of the edges of adjacent splicing structures, and the size of the splicing seams does not exceed 5 μm.

3. The wafer stacking structure according to claim 1, characterized in that, Multiple light-emitting diode (LED) units are formed on the first splicing wafer, and the multiple LED units are arranged in an array. When the size of the LED unit is less than 10 mm², the splicing structure is formed as a regular hexagon, and the multiple splicing structures are arranged in a honeycomb pattern. When the size of the LED unit is between 10 mm² and 50 mm², the splicing structure is a mixture of regular hexagons and rectangles or trapezoids, with the regular hexagons located at the center of a single splicing structure, and the rectangles or trapezoids corresponding to each side of the regular hexagons located on the periphery of the regular hexagons. When the size of the LED unit is between 50 mm² and 100 mm², the shape of the splicing structure is rectangular, and the multiple splicing structures are arranged in a row and column arrangement. When the size of the LED unit is greater than 100 mm², the splicing structure is formed as a square, and the multiple splicing structures are arranged in a row and column arrangement.

4. The wafer stacking structure according to claim 1, characterized in that, The first splicing wafer has a plurality of light-emitting diode (LED) units separated by dicing channels. Within each LED unit, LED units with splicing seams are considered abnormal LED units, while LED units without splicing seams are considered normal LED units. The multiple splicing structures above the carrier substrate have the maximum filling efficiency. The formula for calculating the filling efficiency is: η = N×S / [π×(D / 2)²], where N is the number of normal LED units on the first splicing wafer, S is the size of the LED unit, and D is the size of the target wafer.

5. The wafer stacking structure according to claim 1, characterized in that, The wafer stacking structure further includes at least a second splicing wafer, which is bonded to the surface of the first splicing wafer away from the carrier substrate. The second splicing wafer includes multiple splicing structures, and each splicing structure has a light-emitting diode structure formed thereon. The light emitted by the light-emitting diode structure of the second splicing wafer is a different color than the light emitted by the light-emitting diode structure of the first splicing wafer.

6. The wafer stacking structure according to claim 5, characterized in that, The wafer stacking structure also includes a third splicing wafer, which is bonded to the surface of the second splicing wafer away from the first splicing wafer. The third splicing wafer includes multiple splicing structures, and each splicing structure also has a light-emitting diode structure formed on it. The light emitted by the light-emitting diode structure of the second splicing wafer is a different color than the light emitted by the light-emitting diode structures on the other two splicing wafers.

7. The wafer stacking structure according to claim 6, characterized in that, The light-emitting diode structures in the first, second, and third splicing wafers are Micro LED structures of different colors.

8. The wafer stacking structure according to claim 1, characterized in that, The carrier substrate and the first spliced ​​wafer are bonded using a hybrid bonding technology.

9. The wafer stacking structure according to claim 1, characterized in that, The shape of the splicing structure on the first splicing wafer includes one or more of the following: regular hexagon, square, trapezoid, or rectangle.

10. The wafer stacking structure according to claim 1, characterized in that, The substrate is a bare substrate or a wafer with a functional structure.

11. A method for fabricating a wafer stacked structure, characterized in that, include: S1: Obtain multiple splicing structures, each of which is formed by growing an epitaxial layer on a growth substrate of the second size and then cutting it to a preset shape; S2: A carrier substrate is provided, the carrier substrate having a first dimension, the first dimension being larger than a second dimension; S3: The plurality of splicing structures are arranged closely on the carrier substrate and together cover the entire surface of the carrier substrate to obtain a first splicing wafer; S4: Stack the second and third splicing wafers sequentially on the first splicing wafer to achieve full-color display.

12. The preparation method according to claim 11, characterized in that, The steps for obtaining multiple spliced ​​structures include: Based on the dimensions of the target wafer and the target LED unit, the optimal splicing scheme is determined, including the shape, size, and arrangement of the splicing structure. The shape and size of the splicing structure are determined based on the optimal splicing scheme, and then it is cut.

13. The preparation method according to claim 12, characterized in that, The steps for determining the optimal splicing scheme based on the dimensions of the target wafer and the dimensions of the target LED units include: Obtain the dimensions of the target splicing wafer and the dimensions of the target light-emitting diode unit; Based on the target splicing wafer size and the target light-emitting diode unit size, the shape, size and arrangement of the target splicing structure are traversed; The number of normal LED units on the target wafer is obtained based on the target LED unit size, the shape, size and arrangement of the target splicing structure; The filling efficiency is calculated based on the number of normal LED units on the target wafer, the size of the target spliced ​​wafer, and the size of the target LED unit. The optimal splicing scheme is to select the shape, size, and arrangement of the target splicing structure that corresponds to the highest filling efficiency.

14. The preparation method according to claim 13, characterized in that, The step of calculating the fill efficiency based on the number of normal LED cells on the target spliced ​​wafer, the target wafer size, and the target LED cell size includes: The filling efficiency is calculated based on the formula η = N×S / [π×(D / 2)²], where η is the filling efficiency, N is the number of normal LED units on the spliced ​​wafer, S is the size of the LED unit, and D is the size of the target wafer.

15. The preparation method according to claim 12, characterized in that, Following step S3, the following is also included: Based on the optimal splicing scheme, the multiple splicing structures are closely arranged on the surface of the carrier substrate to obtain the first spliced ​​wafer; Repeat steps S1 to S3 to sequentially stack the second and third splicing wafers on the first splicing wafer.

Images