A chip package structure
By setting a three-dimensional heat dissipation structure on the surface and sides of the wafer layer, combined with a heat sink and coolant circulation, the problem of insufficient heat dissipation efficiency under high integration density packaging is solved, achieving efficient heat transfer and packaging performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- NINGBO SHENGRUI SEMICON TECH CO LTD
- Filing Date
- 2025-03-31
- Publication Date
- 2026-06-09
AI Technical Summary
Existing heat dissipation technologies, under 2.5D and 3D packaging architectures, struggle to simultaneously meet the demands for high integration density and high heat dissipation efficiency, especially due to bottlenecks in space constraints and material integration design.
An interlayer heat dissipation layer is set on the surface of the wafer layer, and a side heat dissipation layer is set on the side of the wafer stack structure to form an interconnected three-dimensional heat dissipation structure. Combined with the heat sink and coolant circulation, the heat transfer path is optimized.
It significantly improves the heat dissipation performance of chip packaging, while meeting the packaging requirements of high integration density and improving the efficiency of heat dissipation.
Smart Images
Figure CN224343761U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of chip packaging heat dissipation technology, and more specifically, to a chip packaging structure. Background Technology
[0002] With the rapid development of information technology, the amount of data is growing explosively, which has led to a continuous increase in the demand for computing chips. Improved performance of computing chips requires greater power consumption, making efficient heat dissipation technology crucial to ensuring the stability of their performance. Chip-level heat dissipation technology has emerged as a solution. This involves heat dissipation measures implemented on or inside the chip surface. Compared to traditional heat dissipation methods, it offers the advantage of more direct and faster heat transfer without significantly increasing the final package size.
[0003] Currently, mainstream chip-level heat dissipation technologies on the market mainly include heat pipes, vapor chambers (VC), diamond, and graphene heat dissipation technologies. Heat pipe heat dissipation technology utilizes the phase change of the working fluid inside the heat pipe to transfer heat, offering advantages such as high heat transfer efficiency and simple structure. VC vapor chamber heat dissipation technology uses vapor flow inside the vapor chamber to evenly distribute heat, effectively reducing the temperature gradient on the chip surface. Diamond and graphene heat dissipation technologies leverage the excellent thermal conductivity of these two materials to achieve efficient heat dissipation.
[0004] However, despite the excellent thermal conductivity of these materials, current heat dissipation technologies still have shortcomings. In 2.5D and 3D packaging architectures, chip integration density increases significantly, heat becomes more concentrated, and heat dissipation paths become more complex. Existing heat dissipation technologies struggle to simultaneously meet the high heat dissipation efficiency requirements of such high-integration-density packaging. For example, heat pipe and vapor chamber cooling technologies may be limited by space constraints in high-integration-density packaging, preventing them from fully realizing their heat dissipation advantages. While diamond and graphene heat dissipation technologies have high thermal conductivity, there are still some technical bottlenecks in their integration with the chip and the design of the heat dissipation structure, preventing them from fully meeting the stringent heat dissipation performance requirements of 2.5D and 3D packaging in practical applications. Utility Model Content
[0005] The purpose of this application is to provide a chip packaging structure that can form an interconnected three-dimensional heat dissipation structure between stacked wafer layers and on the sides, which can significantly improve heat dissipation performance and meet the packaging requirements of high integration density.
[0006] This application provides a chip packaging structure, including a wafer stacking structure and a three-dimensional heat dissipation structure. The wafer stacking structure includes at least two stacked wafer layers. The three-dimensional heat dissipation structure includes interlayer heat dissipation layers and side heat dissipation layers. The interlayer heat dissipation layers cover the upper surface of each wafer layer and extend at least to the peripheral edge of each wafer layer. The side heat dissipation layers cover the sides of the wafer stacking structure and connect to the interlayer heat dissipation layers.
[0007] In one feasible embodiment, the chip packaging structure further includes a heat sink covering the chip stack structure; wherein the side heat sink layer and the uppermost interlayer heat sink layer are in close contact with the inner wall of the heat sink.
[0008] In one feasible solution, the bottom of the side heat dissipation layer extends outwards to contact the bottom surface of the side wall of the heat dissipation cover.
[0009] In one feasible solution, when the heat sink covers the chip stack structure, the protruding parts of the heat sink layers between each layer are connected to each other by mechanical pressing to form a side heat sink layer, which is in close contact with the inner wall of the heat sink.
[0010] In one feasible solution, a heat dissipation unit is provided on the upper surface and / or side of the exterior of the heat sink.
[0011] In one feasible solution, the heat sink is provided with a liquid cooling channel for coolant circulation.
[0012] In one feasible approach, horizontal interconnections between adjacent wafer layers are achieved through microbumps or hybrid bonding.
[0013] In one feasible solution, a vertical conductive structure for vertical conduction is provided in the wafer layer, and an opening corresponding to the vertical conductive structure is provided in the interlayer heat dissipation layer, the size of which is larger than the size of the vertical conductive structure.
[0014] In one feasible embodiment, the wafer layer at the bottom of the wafer stacking structure is the first wafer layer, and the wafer layers above the first wafer layer are the second wafer layers.
[0015] The first wafer layer includes one or more logic wafers, and each second wafer layer includes one or more memory wafers.
[0016] In one feasible approach, the interlayer heat dissipation layer and the side heat dissipation layer are graphene films.
[0017] Compared with the prior art, the beneficial effects of this application include at least the following: In the chip packaging structure of this application, by setting an interlayer heat dissipation layer on the surface of the wafer layer and setting a side heat dissipation layer connected to the interlayer heat dissipation layer on the sidewall of the wafer stack structure, an interconnected three-dimensional heat dissipation structure can be established between the layers and the sidewall of the wafer stack structure. The interlayer heat dissipation layer transfers interlayer heat to the side heat dissipation layer, thereby significantly improving the thermal conductivity and heat dissipation performance, while also meeting the packaging requirements of high integration density. Attached Figure Description
[0018] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.
[0019] Figure 1 This is a schematic diagram illustrating a chip packaging structure according to an embodiment of this application;
[0020] Figure 2 for Figure 1 A schematic diagram of a chip packaging structure with a substrate;
[0021] Figure 3 for Figure 1 A schematic diagram of a chip package structure with a heat dissipation cover;
[0022] Figure 4 This is a schematic diagram showing the relative relationship between the vertical conductive structure and the interlayer heat dissipation layer according to an embodiment of this application;
[0023] Figure 5 This is a schematic diagram illustrating another chip packaging structure according to an embodiment of this application;
[0024] Figure 6 for Figure 5 A schematic diagram of a chip packaging structure with a substrate;
[0025] Figure 7 for Figure 6 A schematic diagram of a chip packaging structure with a heat sink.
[0026] Figure 8 This is a schematic diagram illustrating a chip packaging structure with a heat dissipation unit according to an embodiment of this application;
[0027] Figure 9 This is a schematic diagram of a chip packaging structure with a heat sink having a liquid cooling channel, according to an embodiment of this application.
[0028] Figure 10 This is a schematic diagram of a partial structure of a wafer layer and its bonding interface according to an embodiment of this application;
[0029] Figure 11 This is a schematic diagram of a partial structure at the bonding interface of another wafer layer according to an embodiment of this application.
[0030] In the figure: 10. Substrate; 1. Wafer stacking structure; 11. Wafer layer; 111. First wafer layer; 112. Second wafer layer; 12. Vertical conductive structure; 113. Bonding dielectric layer; 114. Bonding pad; 2. Three-dimensional heat dissipation structure; 21. Interlayer heat dissipation layer; 211. Opening; 22. Side heat dissipation layer; 3. Heat sink; 31. Liquid cooling channel; 32. Heat dissipation fins. Detailed Implementation
[0031] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.
[0032] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.
[0033] like Figure 1 and Figure 5 As shown in the figure, this application provides a chip packaging structure, including a wafer stacking structure 1 and a three-dimensional heat dissipation structure 2.
[0034] The wafer stacking structure 1 includes at least two stacked wafer layers 11. For example, Figure 1 The wafer stacking structure 1 in the example includes two wafer layers 11. For example, Figure 5 The wafer stacking structure 1 in the middle includes five wafer layers 11.
[0035] The three-dimensional heat dissipation structure 2 includes an interlayer heat dissipation layer 21 and a side heat dissipation layer 22. The interlayer heat dissipation layer 21 covers the upper surface of each wafer layer 11 and extends at least to the periphery of each wafer layer 11. The side heat dissipation layer 22 covers the sides of the wafer stack structure 1 and connects to each interlayer heat dissipation layer 21.
[0036] In the chip packaging structure of this application, by providing an interlayer heat dissipation layer 21 on the surface of the wafer layer 11 and a side heat dissipation layer 22 connected to the interlayer heat dissipation layer 21 on the sidewall of the wafer stack structure 1, an interconnected three-dimensional heat dissipation structure 2 can be established between the layers and on the side of the wafer stack structure 1. The interlayer heat dissipation layer 21 transfers interlayer heat to the side heat dissipation layer 22, thereby significantly improving the thermal conductivity and heat dissipation performance, while also meeting the packaging requirements of high integration density.
[0037] In one embodiment, such as Figure 2 and Figure 6 As shown, the chip packaging structure includes a substrate 10, and a wafer stack structure 1 is disposed on the substrate 10. A redistribution layer (RDL) may be disposed in the substrate 10 to optimize the circuit distribution.
[0038] In one embodiment, each wafer layer 11 may include one or more wafers.
[0039] In one embodiment, such as Figure 2 and Figure 6 As shown, the bottommost wafer layer 11 of the wafer stack structure 1 is the first wafer layer 111, and the layers above the first wafer layer 111 are the second wafer layers 112. The first wafer layer 111 may include one or more logic wafers (e.g., microprocessors, CPUs, etc.), and each second wafer layer 112 includes one or more memory wafers (e.g., SRAM wafers, DRAM wafers, MRAM wafers, other types of memory wafers, or combinations thereof).
[0040] In some embodiments, the first wafer layer 111 at the bottom generates more heat than the second wafer layer 112 at the top. The three-dimensional heat dissipation structure 2 constructed with the help of this embodiment can optimize the heat transfer and heat dissipation effect and improve performance.
[0041] In one embodiment, the interlayer heat dissipation layer 21 and the side heat dissipation layer 22 are preferably thin film structures made of graphene, which have excellent heat transfer performance and can be made very thin. For example, in this embodiment, the thickness of the interlayer heat dissipation layer 21 and the side heat dissipation layer 22 made of graphene material is preferably 1-10 micrometers, such as 1 micrometer, 2 micrometers, 3 micrometers, 5 micrometers, 8 micrometers, etc. In addition, the interlayer heat dissipation layer 21 and / or the side heat dissipation layer 22 can be fabricated by graphene deposition process.
[0042] In one embodiment, horizontal interconnection between adjacent wafer layers 11 is achieved through microbumps or hybrid bonding.
[0043] In one embodiment, such as Figure 4As shown, a vertical conductive structure 12 for vertical conduction is provided in the wafer layer 11, and an opening 211 corresponding to the vertical conductive structure 12 is provided in the interlayer heat dissipation layer 21. The size of the opening 211 is larger than the size of the vertical conductive structure 12. The vertical conductive structure 12 may include a through-silicon via (TSV) or other types of vertical conductive structures.
[0044] The vertical conductive structure 12 can be prefabricated before the wafer layer 11 is bonded, or it can be fabricated after the wafer layer 11 is bonded. Both processes have their advantages and disadvantages, and the appropriate process can be chosen flexibly according to the actual situation.
[0045] In one embodiment, such as Figure 3 and Figure 7 As shown, the chip packaging structure may further include a heat sink 3, which covers the chip stack structure 1. The side heat sink layer 22 and the uppermost interlayer heat sink layer 21 are tightly fitted to the inner wall of the heat sink 3. The heat sink 3 itself can serve as an external heat dissipation structure, or it can be connected to other external heat dissipation structures. Because the heat sink 3 is tightly fitted to the three-dimensional heat dissipation structure 2, the heat transferred by the three-dimensional heat dissipation structure 2 can be dissipated more effectively, improving heat dissipation performance.
[0046] In one embodiment, such as Figure 3 and Figure 7 As shown, the bottom of the side heat dissipation layer 22 extends outwards to contact the bottom surface of the side wall of the heat dissipation cover 3. That is, the bottom of the side wall of the heat dissipation cover 3 presses down on part of the side heat dissipation layer 22, thereby further ensuring the tight connection of the three-dimensional heat dissipation structure 2 and thus maximizing the heat dissipation performance.
[0047] It should be noted that, assuming the interlayer heat dissipation layer 21 and the side heat dissipation layer 22 are made of graphene or other conductive materials, due to their excellent conductivity, those skilled in the art need to ensure proper insulation between the heat dissipation layer and the circuit layer and conductive structure of the wafer to avoid affecting the normal functioning of the wafer. The conductive structure of the wafer can be microbumps or hybrid-bonded pads (or copper contacts for hybrid bonding).
[0048] In one embodiment, if the wafer layers 11 are connected by microbumps, during the fabrication of the interlayer heat dissipation layer 21, heat dissipation material can be deposited separately on the surface of each wafer layer 11 to form the interlayer heat dissipation layer 21 as the stacking progresses. This is equivalent to the interlayer heat dissipation layer 21 and the wafer layer 11 being independent layer structures. Simultaneously, some heat dissipation material can also be deposited on the outer edge of the wafer layer 11; this portion can be referred to as the protruding portion of the interlayer heat dissipation layer 21 extending beyond the periphery of the wafer layer 11. Furthermore, the circumferential dimension of the inner wall of the heat dissipation cover 3 is slightly larger than the circumferential dimension of the wafer stack structure 1. Preferably, the circumferential dimension of the inner wall of the heat dissipation cover 3 is 1-10 micrometers larger than the circumferential dimension of the wafer stack structure 1. Subsequently, when the heat dissipation cover 3 is installed and covers the wafer stack structure 1, the heat dissipation cover 3 will press the protruding portions of the periphery of each wafer layer 11. That is, the protruding portions of each interlayer heat dissipation layer 21 are interconnected through mechanical pressing by the heat dissipation cover 3 to form a side heat dissipation layer 22, which is in close contact with the inner wall of the heat dissipation cover 3.
[0049] Furthermore, if a graphene film is used as a heat dissipation layer in this embodiment, and the wafer layers 11 are connected by microbumps, the graphene film needs to avoid the microbump area and mainly cover the blank area (non-circuit area) of the wafer, or be embedded between the microbump arrays as an interlayer filler material. Preferably, a graphene mesh can be formed in the non-circuit area around the microbumps as an interlayer heat dissipation layer 21 to conduct heat laterally to the packaging edge.
[0050] In one embodiment, if the wafer layers 11 are connected by hybrid bonding, assuming the heat dissipation layer is a highly thermally conductive dielectric material (such as an oxide layer filled with a thermally conductive polymer), which is compatible with the hybrid bonding process, then it is not necessary to embed the interlayer heat dissipation layer 21 into the bonding interface layer of the wafer layers 11. Assuming the heat dissipation layer is made of graphene film, the interlayer heat dissipation layer 21 can be incorporated into the bonding interface layer of each wafer layer 11. For example, 10 and... Figure 11 As shown, the bonding interface layer includes a bonding dielectric layer 113 surrounding the bonding pad 114, and the interlayer heat dissipation layer 21 can be directly fabricated as part of the bonding dielectric layer 113 (see [reference]). Figure 11 ), or the surface of the bonding dielectric layer 113 covering the bonding pad 114 (see Figure 10 ).
[0051] For example, such as Figure 10 As shown, a graphene thin film layer can be formed only on the surface of the bonding dielectric layer 113; or as... Figure 11 As shown, multiple graphene film layers can be embedded in the bonding medium layer 113, which can accelerate the lateral diffusion of heat. It should be noted that regardless of the number of interlayer heat dissipation layers 21, it is ultimately necessary to ensure that the bonding pads (copper contacts) and the bonding interface layer are coplanar.
[0052] Figure 10 and Figure 11 The structural form is equivalent to incorporating the interlayer heat dissipation layer 21 as part of the bonding interface layer on the upper surface of the wafer layer 11, thereby adapting to hybrid bonding processes to meet the requirements of high-density vertical integration stacking as much as possible. The interlayer heat dissipation layer 21 can also be disposed on the surface of the bonding dielectric layer 113 on the lower surface of the wafer layer 11 or in the interlayer, but in order to improve the integration density, it is preferable to only dispose of the interlayer heat dissipation layer 21 in the bonding interface layer on the upper surface of the wafer layer 11.
[0053] Furthermore, after the hybrid bonding connection, the side heat dissipation layer 22 can still be formed by forming a heat dissipation material protrusion around the wafer layer 11 and then by mechanical pressing of the heat dissipation cover 3.
[0054] In one embodiment, a heat dissipation unit may be provided on the upper surface and / or side surface of the heat dissipation cover 3. The heat dissipation unit includes one or more combinations of heat dissipation fins, a heat spreader, and heat pipes. Figure 8 As shown, heat dissipation fins 32 can be provided on the upper surface and sides of the heat dissipation cover 3 to enhance heat dissipation performance.
[0055] In one embodiment, such as Figure 9 As shown, the heat sink 3 can be provided with a liquid cooling channel 31 for coolant circulation, which further improves heat dissipation performance.
[0056] It should be noted that the accompanying drawings are for illustrative purposes only and are not drawn to scale. Some layer structures or conductive contacts have been exaggerated to highlight structural features. Furthermore, to emphasize only the main features of the technical solution of this application, well-known protective layers, insulating layers, and other structures are not shown in the drawings. Those skilled in the art can flexibly select and design structural layers not shown in the drawings based on design requirements and experience in practical applications.
[0057] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.
Claims
1. A chip packaging structure, characterized in that, include: A wafer stacking structure (1) includes at least two wafer layers (11) stacked together. The three-dimensional heat dissipation structure (2) includes: An interlayer heat dissipation layer (21) covers the upper surface of each of the wafer layers (11) and extends at least to the periphery of each of the wafer layers (11); A side heat dissipation layer (22) covers the side of the wafer stack structure (1) and connects each of the interlayer heat dissipation layers (21).
2. The chip packaging structure according to claim 1, characterized in that, The chip packaging structure also includes a heat dissipation cover (3), which covers the chip stack structure (1). The side heat dissipation layer (22) and the uppermost interlayer heat dissipation layer (21) are closely attached to the inner wall of the heat dissipation cover (3).
3. The chip packaging structure according to claim 2, characterized in that, The bottom of the side heat dissipation layer (22) extends outwards to contact the bottom surface of the side wall of the heat dissipation cover (3).
4. The chip packaging structure according to claim 2, characterized in that, The interlayer heat dissipation layer (21) is provided with a protruding portion extending out of the periphery of the wafer layer (11). When the heat dissipation cover (3) covers the wafer stack structure (1), the protruding portions of each interlayer heat dissipation layer (21) are connected to each other by mechanical pressing to form the side heat dissipation layer (22), and are in close contact with the inner wall of the heat dissipation cover (3).
5. The chip packaging structure according to claim 2, characterized in that, The heat dissipation cover (3) has heat dissipation units provided on its upper surface and / or side surface.
6. The chip packaging structure according to claim 2, characterized in that, The heat dissipation cover (3) is provided with a liquid cooling channel (31) for coolant circulation.
7. The chip packaging structure according to claim 1, characterized in that, The adjacent wafer layers (11) are interconnected horizontally by microbumps or hybrid bonding.
8. The chip packaging structure according to claim 1, characterized in that, The wafer layer (11) is provided with a vertical conductive structure (12) for vertical conduction, and the interlayer heat dissipation layer (21) is provided with an opening (211) corresponding to the vertical conductive structure (12), the size of the opening (211) being larger than the size of the vertical conductive structure (12).
9. The chip packaging structure according to claim 1, characterized in that, The wafer layer (11) at the bottom of the wafer stack structure (1) is the first wafer layer (111), and the wafer layer above the first wafer layer (111) is the second wafer layer (112). The first wafer layer (111) includes one or more logic wafers, and each second wafer layer (112) includes one or more memory wafers.
10. The chip packaging structure according to claim 1, characterized in that, The interlayer heat dissipation layer (21) and the side heat dissipation layer (22) are graphene films.