Display panel and display device

Abstract

Embodiments of the present application provide a display panel and a display device; the display panel is provided with a light shielding layer, the light shielding layer includes a first gate of a compensation transistor, and / or the light shielding layer includes a first gate of a switching transistor, so that the compensation transistor and / or the switching transistor can still adopt a double-gate design, and the light shielding layer is away from a signal line where a first node and a second node are located compared with a first gate layer, which can reduce the parasitic capacitance of the first node and the second node to the first scan line, and / or reduce the parasitic capacitance of the second node to the second scan line, thereby reducing the total capacitance of the first node and / or the second node, improving the proportion of the first capacitance and the second capacitance, improving the threshold voltage compensation capability, and reducing the risk of screen burn-in and life deterioration.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to a display panel and a display device. Background Technology

[0002] To improve the performance of thin-film transistors (TFTs), current display devices employ LTPO (Low Temperature Polysilicon Oxide) technology. Specifically, LTPO TFTs and metal-oxide-semiconductor (MODS) TFTs are fabricated simultaneously on the same backplane, thus combining the advantages of both technologies and enhancing display device performance. Furthermore, to prevent display malfunctions caused by threshold voltage deviations in the driving transistors, current display devices store the threshold voltage of the driving transistors on capacitor plates and then compensate for it. However, due to parasitic capacitance at the gate of the driving transistor, the capacitance as a percentage of the total capacitance is relatively low, resulting in poor threshold voltage compensation capability and leading to screen burn-in and degraded lifespan.

[0003] Therefore, existing display devices suffer from a technical problem where the low proportion of capacitors in the total capacitance results in poor threshold voltage compensation capability. Summary of the Invention

[0004] This application provides a display panel and a display device to improve the technical problem that existing display devices have poor threshold voltage compensation capability due to the low proportion of capacitors in the total capacitance.

[0005] To achieve the above objectives, according to a first aspect of this application, a display panel is provided, the display panel including a pixel driving circuit and a light-emitting device electrically connected to the pixel driving circuit. The pixel driving circuit includes a driving transistor, a switching transistor, a compensation transistor, a first capacitor, and a second capacitor. A gate of the driving transistor is electrically connected to a first plate of the first capacitor and an electrode of the compensation transistor at a first node. A second plate of the first capacitor is electrically connected to a first plate of the second capacitor and an electrode of the switching transistor at a second node. A gate of the compensation transistor is electrically connected to a first scan line, and a gate of the switching transistor is electrically connected to a second scan line. The display panel includes a light-shielding layer, which includes the first gate of the compensation transistor, and / or the light-shielding layer includes the first gate of the switching transistor.

[0006] According to a second aspect of this application, a display device is provided, the display device including a display panel as described in any of the above embodiments.

[0007] This application provides a display panel and a display device. The display panel provides a light-shielding layer, which includes a first gate of a compensation transistor and / or a first gate of a switching transistor. This allows the compensation transistor and / or the switching transistor to still employ a dual-gate design. The light-shielding layer is farther away from the signal lines where the first node and the second node are located compared to the first gate layer. This reduces the parasitic capacitance between the first node and the second node and the first scan line, and / or reduces the parasitic capacitance between the second node and the second scan line. This reduces the total capacitance of the first node and / or the second node, increases the proportion of the first capacitance and the second capacitance, improves the threshold voltage compensation capability, and reduces the risk of screen burn-in and lifespan degradation.

[0008] Other features and advantages of this application will be described in detail in the following detailed description section. Attached Figure Description To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0009] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0010] Figure 1 This is a plan view of the display panel provided in an embodiment of this application.

[0011] Figure 2 This is a cross-sectional schematic diagram of the display panel provided in an embodiment of this application.

[0012] Figure 3 A circuit diagram of the pixel driving circuit of the display panel provided in an embodiment of this application.

[0013] Figure 4 A timing diagram of the pixel driving circuit of the display panel provided in an embodiment of this application.

[0014] Figure 5 This is a stacked diagram of some film layers of a display panel provided in an embodiment of this application.

[0015] Figure 6 for Figure 5 An exploded view of the light-shielding layer of the display panel.

[0016] Figure 7 for Figure 5 An exploded view of the active layer of the display panel.

[0017] Figure 8 for Figure 5 An exploded view of the first gate layer of the display panel.

[0018] Figure 9 for Figure 5 An exploded view of the second gate layer of the display panel.

[0019] Figure 10 for Figure 5 An exploded view of the semiconductor layer of the display panel.

[0020] Figure 11 for Figure 5 An exploded view of the third gate layer of the display panel.

[0021] Figure 12 for Figure 5 An exploded view of the fourth gate layer of the display panel.

[0022] Figure 13 for Figure 5 An exploded view of the fifth gate layer of the display panel.

[0023] Figure 14 for Figure 5 An exploded view of the first source-drain layer of the display panel.

[0024] Figure 15 for Figure 5 An exploded view of the second source-drain layer of the display panel.

[0025] Figure 16 for Figure 5 An exploded view of the third source-drain layer of the display panel.

[0026] Figure 17 for Figure 5 An exploded view of the first via of the display panel.

[0027] Figure 18 for Figure 5 An exploded view of the second via of the display panel.

[0028] Figure 19 for Figure 5 An exploded view of the third via in the display panel.

[0029] Figure 20 for Figure 5 An exploded view of the fourth via on the display panel.

[0030] Figure 21 for Figure 5 A stacked diagram of the light-shielding layer and active layer of the display panel.

[0031] Figure 22 for Figure 5 The stack-up diagram of the light-shielding layer, active layer, and first gate layer of the display panel.

[0032] Figure 23 for Figure 5 The stack-up diagram of the light-shielding layer, active layer, first gate layer, and second gate layer of the display panel.

[0033] Figure 24 for Figure 5 The stack-up diagram of the light-shielding layer, active layer, first gate layer, second gate layer, and semiconductor layer of the display panel.

[0034] Figure 25 for Figure 5 The stack-up diagram of the light-shielding layer, active layer, first gate layer, second gate layer, semiconductor layer, and third gate layer of the display panel.

[0035] Figure 26 for Figure 5 The stack-up diagram of the light-shielding layer, active layer, first gate layer, second gate layer, semiconductor layer, third gate layer, and fourth gate layer of the display panel.

[0036] Figure 27 for Figure 5 The stack-up diagram of the light-shielding layer, active layer, first gate layer, second gate layer, semiconductor layer, third gate layer, fourth gate layer, and fifth gate layer of the display panel.

[0037] Figure 28 for Figure 5 The stack-up diagram of the light-shielding layer, active layer, first gate layer, second gate layer, semiconductor layer, third gate layer, fourth gate layer, fifth gate layer, and first via of the display panel.

[0038] Figure 29 for Figure 5 The stack-up diagram of the light-shielding layer, active layer, first gate layer, second gate layer, semiconductor layer, third gate layer, fourth gate layer, fifth gate layer, first via, and second via of the display panel.

[0039] Figure 30 for Figure 5 The stack-up diagram of the light-shielding layer, active layer, first gate layer, second gate layer, semiconductor layer, third gate layer, fourth gate layer, fifth gate layer, first via, second via, and first source / drain layer of the display panel.

[0040] Figure 31 for Figure 5 The stack-up diagram of the light-shielding layer, active layer, first gate layer, second gate layer, semiconductor layer, third gate layer, fourth gate layer, fifth gate layer, first via, second via, first source-drain layer, and third via of the display panel.

[0041] Figure 32 for Figure 5 The stack-up diagram of the light-shielding layer, active layer, first gate layer, second gate layer, semiconductor layer, third gate layer, fourth gate layer, fifth gate layer, first via, second via, first source-drain layer, third via, and second source-drain layer of the display panel.

[0042] Figure 33 for Figure 5 The stack-up diagram of the light-shielding layer, active layer, first gate layer, second gate layer, semiconductor layer, third gate layer, fourth gate layer, fifth gate layer, first via, second via, first source-drain layer, third via, second source-drain layer, and fourth via of the display panel. Detailed Implementation

[0043] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0044] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," "joining," "electrical connection," and "electrical link" should be interpreted broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections, electrical connections, or connections that allow for communication; they can refer to direct connections or indirect connections through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0045] This application addresses the technical problem of poor threshold voltage compensation capability in existing display devices due to the low proportion of capacitors to total capacitance, by providing a display panel and a display device to improve the aforementioned technical problem.

[0046] like Figure 1 As shown, this application embodiment provides a display panel 1, which includes a display area 101 and a non-display area 102. The non-display area 102 can be disposed around the display area 101, or on one, two, or three sides of the display area 101, to... Figure 1For example, the non-display area 102 is disposed around the display area 101. The non-display area 102 includes a left side border area, a right side border area, an upper side border area, and a lower side border area. The left side border area and the right side border area can be used as gate drive circuit areas 102a. A gate drive circuit 12 is disposed in the left side border area and / or the right side border area. A bonding terminal can be disposed in the lower side border area to bond with the drive chip.

[0047] Specifically, such as Figure 1 As shown, the display area 101 is provided with a pixel unit 11, which includes a first sub-pixel unit 111, a second sub-pixel unit 112 and a third sub-pixel unit 113, and each sub-pixel unit is provided with a pixel driving circuit 13.

[0048] Specifically, Figure 1 The diagram shows that the first sub-pixel unit 111, the second sub-pixel unit 112, and the third sub-pixel unit 113 are arranged in a row and sequentially along the first direction. However, the embodiments of this application are not limited to this. The pixel arrangement can be in other ways. For example, the first sub-pixel unit 111, the second sub-pixel unit 112, and the third sub-pixel unit 113 can be located in different rows, or the first sub-pixel unit 111, the second sub-pixel unit 112, and the third sub-pixel unit 113 can be located in the same row and the same column, while the other can be located in another row and another column.

[0049] Specifically, such as Figure 2 As shown, the display panel 1 includes a substrate 21, a driving circuit layer 22, a light-emitting functional layer 23, and an encapsulation layer.

[0050] Specifically, such as Figure 2 As shown, substrate 21 includes a first flexible layer 211, a first barrier layer 212, a second flexible layer 213, and a second barrier layer 214. It is understood that... Figure 2 The illustration shows a substrate design in one embodiment of this application. The substrate 21 in this embodiment of the application may also be designed in other ways, such as having only one flexible layer.

[0051] Specifically, such as Figure 2As shown, the driving circuit layer 22 includes a light-shielding layer 221, a barrier layer 222, a buffer layer 223, an active layer 224, a first gate insulating layer 225, a first gate layer 226, a second gate insulating layer 227, a second gate layer 228, a first interlayer insulating layer 229, a semiconductor layer 231, a third gate insulating layer 232, a third gate layer 233, a fourth gate insulating layer 234, a fourth gate layer 235, a fifth gate insulating layer 236, a fifth gate layer 237, a second interlayer insulating layer 238, a first source-drain layer 239, a passivation layer 241, a first planarization layer 242, a second source-drain layer 243, a second planarization layer 244, a third source-drain layer 245, a third planarization layer 246, and a fourth planarization layer 247. It can be understood that... Figure 2 The illustration shows a design of a driving circuit layer in an embodiment of this application. The design of the driving circuit layer in this embodiment can also be other designs that can realize the normal function of the display panel, such as setting only two source-drain layers or setting only three planarization layers.

[0052] Specifically, such as Figure 2 As shown, the light-emitting functional layer 23 includes a pixel electrode layer 251, a first pixel definition layer 252, a second pixel definition layer 253, support pillars 254, a light-emitting material layer, and a common electrode layer. It can be understood that... Figure 2 The illustration shows a design of a light-emitting functional layer in an embodiment of this application. The design of the light-emitting functional layer in this embodiment can also be other designs that can realize the normal functions of the display panel. For example, the pixel definition layer in the light-emitting functional layer may include a pixel definition layer.

[0053] Specifically, the transmittance of the first pixel definition layer 252 can be less than the transmittance of the second pixel definition layer 253.

[0054] Specifically, the encapsulation layer may include a first inorganic layer, an organic layer, and a second inorganic layer arranged sequentially.

[0055] Specifically, it is understandable that Figure 2 The diagram illustrates one type of film layer structure for a display panel, but the embodiments of this application are not limited to this. The film layer structure of the display panel in the embodiments of this application can be other film layer structures. In the following embodiments, it will be referred to as... Figure 2 The following explanation uses the film layer structure of the display panel as an example. When the film layer structure of the display panel is other film layer structures, the design of the display panel can be determined accordingly.

[0056] Specifically, such as Figure 3As shown, the pixel driving circuit 13 includes a driving transistor T1, a switching transistor T2, a compensation transistor T3, an initialization transistor T4, a first light-emitting control transistor T5, a second light-emitting control transistor T6, a reset transistor T7, a first capacitor C1, and a second capacitor C2. A gate of the driving transistor T1 is electrically connected to the first plate of the first capacitor C1 at a first node Q. The second plate of the first capacitor C1 is electrically connected to the first plate of the second capacitor C2 at a second node P. The second plate of the second capacitor C2 is electrically connected to the light-emitting device LED at a third node C. A gate of the switching transistor T2 is electrically connected to the second scan line Scan2. The first electrode of the switching transistor T2 is electrically connected to the data line Data. The second electrode of the switching transistor T2 is electrically connected to the first capacitor C1 at a second node P. A gate of the compensation transistor T3 is electrically connected to the first scan line Scan1. The first electrode of the compensation transistor T3 is electrically connected to the first electrode of the driving transistor T1 at a fourth node A. The second electrode of the compensation transistor T3 is electrically connected to a gate of the driving transistor T1 at a first node Q. A gate of the initialization transistor T4 is electrically connected to the first... Scan line Scan1 is electrically connected. The first electrode of initialization transistor T4 is electrically connected to initialization signal line VI-A. The second electrode of initialization transistor T4 is electrically connected to the first capacitor C1 at the second node P. The gate of the first light-emitting control transistor T5 is electrically connected to the first light-emitting control line EM1. The first electrode of the first light-emitting control transistor T5 is electrically connected to the high-potential power line VDD. The second electrode of the first light-emitting control transistor T5 is electrically connected to the first electrode of the driving transistor T1 at the fourth node A. The gate of the second light-emitting control transistor T6 is electrically connected to the second light-emitting control line EM2. The first electrode of the second light-emitting control transistor T6 is electrically connected to the second electrode of the driving transistor T1 at the fifth node B. The second electrode of the second light-emitting control transistor T6 is electrically connected to the light-emitting device at the third node C. The gate of reset transistor T7 is electrically connected to the first light-emitting control line EM1. The first electrode of reset transistor T7 is electrically connected to initialization signal line VI-A. The second electrode of reset transistor T7 is electrically connected to the anode of the light-emitting device LED at the third node C. The cathode of the light-emitting device LED is electrically connected to the low-potential power line VSS.

[0057] It is understandable that an LED is formed by a light-emitting functional layer, with the anode of the LED being the pixel electrode of the pixel electrode layer and the cathode being the common electrode layer.

[0058] Specifically, it is understood that each sub-pixel unit emits light independently. Therefore, the data line Data may include multiple data lines corresponding to each column of sub-pixels, as illustrated in the following embodiments.

[0059] Specifically, it is understandable that some display panels use multiple high-potential power lines to adjust the light emission effect, while other display panels connect multiple high-potential power lines so that, without considering voltage drop, the signals input to the high-potential power lines in the pixel driving circuits of each sub-pixel unit are the same. This application does not limit this approach; the following embodiments will use the example of multiple high-potential power lines connected together.

[0060] Specifically, it is understandable that Figure 3 The diagram shows a pixel driving circuit 13 according to an embodiment of this application. However, the embodiments of this application are not limited to this. The pixel driving circuit can be other circuits. For example, the initialization transistor T4 and the reset transistor T7 can be connected to different initialization signal lines, or the compensation transistor T3 and the initialization transistor T4 can be connected to different scan lines, or the second plate of the second capacitor C2 can be connected to the fifth node B. In the embodiments of this application, the pixel driving circuit 13 is shown in the diagram. Figure 3 The circuit diagram shown is used as an example to explain the display panel. For other pixel driving circuits, the design of the display panel can be determined accordingly.

[0061] Specifically, such as Figure 4 As shown, for Figure 3 The operation of the pixel driving circuit 13 in the image will be explained. Figure 4As shown, the state of each transistor can be determined according to the timing sequence of the first scan line Scan1, the second scan line Scan2, the first light-emitting control line EM1, and the second light-emitting control line EM2. Specifically, in the first stage t1, the second light-emitting control transistor T6 is turned off, and the LED stops emitting light; in the second stage t2, the compensation transistor T3, the initialization transistor T4, and the first light-emitting control transistor T5 are turned on, while the switching transistor T2, the second light-emitting control transistor T6, and the reset transistor T7 are turned off. The high-potential power supply line VDD resets the first node Q, and the initialization signal line VI-A resets the second node P; in the third stage t3, the first light-emitting control transistor T5 is turned off, while the compensation transistor T3, the initialization transistor T4, and the reset transistor T7 are turned on, and the initialization... Signal line VI-A resets the third node C; in the fourth stage t4, the first light-emitting control transistor T5 is turned off, and the compensation transistor T3, initialization transistor T4, second light-emitting control transistor T6 and reset transistor T7 are turned on. The signal of the initialization signal line VI-A is written to the first node Q, completing the threshold voltage compensation; in the fifth stage t5, the compensation transistor T3 and initialization transistor T4 are turned off, and the switching transistor T2, second light-emitting control transistor T6 and reset transistor T7 are turned on. The signal of the data line Data is written to the second node P; in the sixth stage t6, the driving transistor T1, the first light-emitting control transistor T5, and the second light-emitting control transistor T6 are turned on, forming a path between the high-potential power line VDD and the low-potential power line VSS, and the light-emitting device LED emits light.

[0062] Specifically, in this embodiment, the film layer structure of the display panel is used as an example. Figure 2 The film structure shown indicates that the pixel driving circuit of the display panel is... Figure 3 The circuit shown has the following stacked structure for each film layer of the display panel: Figure 5 The display panel is described in detail using the layered structure of the film layers shown as an example. It should be understood that these are just some examples in this application. When the display panel is designed in other ways, the design of the film layer structure, the pixel driving circuit and the layered structure of each film layer can be determined accordingly.

[0063] Specifically, it can be understood that the first node Q is a virtual node, and it is not set independently. Instead, the signal of this node is transmitted through a conductive structure. In other words, the electrodes of each component are connected together to form this node, and the electrodes of each component can be regarded as this node. Therefore, the overlapping of the orthographic projection of the first connection line SL1 and the first scan line Scan1 means that the projection of the structure where the first node Q is located on the substrate overlaps with the projection of the structure where the first scan line Scan1 is located on the substrate. In this embodiment, the structure where the second electrode of the compensation transistor T3 is located is used as an example for the first connection line. However, it can be understood that the structure where the first node Q is located also includes the structure where the gate of the driving transistor is located, which can also be regarded as part of the first connection line SL1. Similarly, the meaning of the second node P and the second connection line SL2 can be determined.

[0064] Specifically, it is understood that in the embodiments of this application, since a node is a node where the electrodes or signal lines of multiple components are connected, and these electrodes and / or signal lines transmit the same signal line without considering voltage drop, a node can be any node on multiple interconnected structures. For example, the first node Q is a node where the gate of the driving transistor T1 and the second electrode of the compensation transistor are connected. Therefore, as... Figure 5 , Figure 11 , Figure 14 As shown, the first node Q can be either a node on the structure corresponding to the second electrode of the compensation transistor T3, or a node on the structure corresponding to the second gate of the driving transistor T1. This embodiment illustrates the example by marking the first node Q on the structure corresponding to the second electrode of the compensation transistor T3. Similarly, the positions of other nodes can be determined.

[0065] Specifically, it's understandable that in the circuit diagram of a pixel driving circuit, the source, drain, gate, and signal lines of each transistor are set independently. However, in actual design, to save space and reduce voltage drop, electrodes and / or signal lines connected together are actually formed using the same structure, rather than being set individually. Therefore, the same structure can be regarded as the electrodes and / or signal lines of multiple components; for example, such as Figure 14 As shown, since the second electrode T2D of the switching transistor T2 and the second electrode T4D of the initialization transistor T4 are connected to the second node P, only one structure is actually set up, with different parts of the structure serving as the second electrode T2D of the switching transistor T2, the second electrode T4D of the initialization transistor T4, and the second connection line SL2, respectively. Similarly, it can be understood that other structures can also be regarded as electrodes and / or signal lines of multiple components.

[0066] Specifically, it is understood that in some embodiments of this application, some transistors may have a first gate and a second gate. For example, the gate of reset transistor T7 includes a first gate and a second gate. In embodiments of this application, unless a specific gate is specifically designated, when a transistor has two gates, this gate refers to the first gate and the second gate of the transistor. When explicitly stated as the first gate or the second gate, it refers to either the first gate or the second gate of the transistor. For example, the gate of reset transistor T7 includes a first gate and a second gate. Unless specifically designated as the first gate or the second gate of reset transistor T7, the gate of reset transistor T7 refers to both the first gate and the second gate of reset transistor T7. For transistors where the first gate and the second gate are connected to different signals, a gate of the transistor refers to a specific gate of the transistor. For example, if the first gate and the second gate of driving transistor T1 are connected to different signal lines, then a gate of the driving transistor refers to either the first gate or the second gate of driving transistor T1. Similarly, the specific gate referred to by the gate of other transistors can be determined.

[0067] like Figures 1 to 33 As shown, this application embodiment provides a display panel 1, which includes a pixel driving circuit 13 and a light-emitting device (LED) electrically connected to the pixel driving circuit 13. The pixel driving circuit 13 includes a driving transistor T1, a switching transistor T2, a compensation transistor T3, a first capacitor C1, and a second capacitor C2. A gate of the driving transistor T1 is electrically connected to a first plate of the first capacitor C1 and an electrode of the compensation transistor T3 at a first node Q. A second plate of the first capacitor C1 is electrically connected to a first plate of the second capacitor C2 and an electrode of the switching transistor T2 at a second node P. A gate of the compensation transistor T3 is electrically connected to a first scan line Scan1, and a gate of the switching transistor T2 is electrically connected to a second scan line Scan2. The display panel 1 includes a light-shielding layer 221, which includes the first gate of the compensation transistor T3, and / or the light-shielding layer 221 includes the first gate of the switching transistor T2.

[0068] This application provides a display panel 1. The display panel 1 is provided with a light-shielding layer 221, which includes the first gate of a compensation transistor T3 and / or the first gate of a switching transistor T2. This allows the compensation transistor T3 and / or the switching transistor T2 to still adopt a dual-gate design. The light-shielding layer 221 is farther away from the signal lines where the first node Q and the second node P are located compared to the first gate layer. This can reduce the parasitic capacitance between the first node Q and the second node P and the first scan line Scan1, and / or reduce the parasitic capacitance between the second node P and the second scan line Scan2. This reduces the total capacitance of the first node Q and / or the second node P, increases the proportion of the first capacitor C1 and the second capacitor C2, improves the threshold voltage compensation capability, and reduces the risk of screen burn-in and lifespan degradation.

[0069] Specifically, when compensating for the threshold voltage of the driving transistor, a larger capacitance ratio results in better compensation. The formula for capacitance ratio is: C1*C2 / Cqtotal*Cptotal, where C1 and C2 are the capacitances of the first capacitor C1 and the second capacitor C2, respectively. Cqtotal refers to the total capacitance of the first node Q, and Cptotal refers to the total capacitance of the second node P. In this embodiment, by reducing the parasitic capacitance between the first node Q and the first scan line Scan1, and by reducing the parasitic capacitance between the second node P and the first scan line Scan1, the total capacitance of the first node Q and the second node P is reduced, thereby increasing the capacitance ratio and reducing the risk of screen burn-in and lifespan degradation.

[0070] In this embodiment, by including the first gate of the compensation transistor T3 in the light-shielding layer 221, the portion of the first scan line Scan1 located in the first gate layer is removed. Since the light-shielding layer 221 is farther away from the film layer where the first connection line SL1 is located compared to the first gate layer, the parasitic capacitance of the first connection line SL1 can be reduced, thereby increasing the capacitance ratio and reducing the risk of screen burn-in and lifespan degradation.

[0071] In this embodiment, by including the first gate of the initialization transistor T4 in the light-shielding layer 221 and removing the portion of the first scan line Scan1 located in the first gate layer, the parasitic capacitance of the second connection line SL2 can be reduced because the light-shielding layer 221 is farther away from the film layer where the second connection line SL2 is located compared to the first gate layer. This increases the capacitance ratio and reduces the risk of screen burn-in and lifespan degradation.

[0072] In this embodiment, by including the first gate of the switching transistor T2 in the light-shielding layer 221 and removing the portion of the second scan line Scan2 located in the first gate layer, the parasitic capacitance of the second connection line SL2 can be reduced because the light-shielding layer 221 is farther away from the film layer where the second connection line SL2 is located compared to the first gate layer. This increases the capacitance ratio and reduces the risk of screen burn-in and lifespan degradation.

[0073] Specifically, the first scan line Scan1 is disposed on the third gate layer 233. By disposing the first scan line Scan1 on the third gate layer 233 and removing the portion of the first scan line Scan1 located on the first gate layer, the parasitic capacitance between the first connection line SL1 and the second connection line SL2 and the first scan line Scan1 can be reduced, thereby increasing the capacitance ratio and reducing the risk of screen burn-in and lifespan degradation.

[0074] Specifically, compared to current display devices, which use a first gate layer and a third gate layer to form two parts of the first scan line Scan1 respectively, connecting the portion of the first scan line Scan1 located in the first gate layer and the portion of the first scan line Scan1 located in the third gate layer, the portion of the first scan line Scan1 located in the first gate layer corresponding to the compensation transistor T3 will serve as the first gate of the compensation transistor T3, and the portion of the first scan line Scan1 located in the third gate layer corresponding to the compensation transistor T3 will serve as the second gate of the compensation transistor T3. However, since the first connection line SL1 transmitting the signal of the first node Q is located in the first source-drain layer, and the projection of the first connection line SL1 on the substrate overlaps with the projection of the portion of the first scan line Scan1 located in the first gate layer on the substrate, and the projection of the first connection line SL1 on the substrate overlaps with the projection of the portion of the first scan line Scan1 located in the third gate layer on the substrate, the parasitic capacitance of the first connection line SL1 and the first scan line Scan1 is relatively large, resulting in a smaller capacitance ratio. This application embodiment reduces the parasitic capacitance between the first connection line SL1 and the first scan line Scan1 by removing the portion of the first scan line Scan1 located in the first gate layer, thereby increasing the capacitance ratio and reducing the risk of screen burn-in and lifespan degradation.

[0075] Specifically, the light-shielding layer 221 can include the first gate of the compensation transistor T3, so that after removing the portion of the first scan line Scan1 located in the first gate layer, the compensation transistor T3 can still adopt a dual-gate design, thereby improving the performance of the compensation transistor T3.

[0076] Specifically, compared to current display devices, where a first gate layer and a third gate layer are used to form two parts of the first scan line Scan1, and the part of the first scan line Scan1 located in the first gate layer is connected to the part of the first scan line Scan1 located in the third gate layer, the portion of the first scan line Scan1 located in the first gate layer corresponding to the initialization transistor T4 will serve as the first gate of the initialization transistor T4, and the portion of the first scan line Scan1 located in the third gate layer corresponding to the initialization transistor T4 will serve as the second gate of the initialization transistor T4. However, since the second connection line SL2, which transmits the signal of the second node P, is located in the first source-drain layer, and the projection of the second connection line SL2 on the substrate overlaps with the projection of the portion of the first scan line Scan1 located in the first gate layer on the substrate, and the projection of the first connection line SL1 on the substrate overlaps with the projection of the portion of the first scan line Scan1 located in the third gate layer on the substrate, the parasitic capacitance of the second connection line SL2 and the first scan line Scan1 is relatively large, resulting in a smaller capacitance ratio. This application embodiment reduces the parasitic capacitance between the second connection line SL2 and the first scan line Scan1 by removing the portion of the first scan line Scan1 located in the first gate layer, thereby increasing the capacitance ratio and reducing the risk of screen burn-in and lifespan degradation.

[0077] Specifically, the light-shielding layer 221 can include the first gate of the initialization transistor T4, so that after removing the portion of the first scan line Scan1 located in the first gate layer, the initialization transistor T4 can still adopt a dual-gate design, thereby improving the performance of the initialization transistor T4.

[0078] Specifically, the second scan line Scan2 is disposed on the third gate layer 233. By disposing the second scan line Scan2 on the third gate layer 233, the portion of the second scan line Scan2 located on the first gate layer is removed, which can reduce the parasitic capacitance between the second connection line SL2 and the second scan line Scan2, thereby increasing the capacitance ratio and reducing the risk of screen burn-in and lifespan degradation.

[0079] Specifically, compared to current display devices, where the first gate layer and the third gate layer are used to form two parts of the second scan line Scan2 respectively, the part of the second scan line Scan2 located in the first gate layer and the part of the second scan line Scan2 located in the third gate layer are connected. The part of the second scan line Scan2 located in the first gate layer that corresponds to the switching transistor T2 will serve as the first gate of the switching transistor T2, and the part of the second scan line Scan2 located in the third gate layer that corresponds to the switching transistor T2 will serve as the second gate of the switching transistor T2. However, since the second connection line SL2, which transmits the signal of the second node P, is located in the first source-drain layer, the switching transistor T2 will be connected to the second connection line SL2. Furthermore, the projection of the active pattern of the switching transistor T2 on the substrate will overlap with the projection of the part of the second scan line Scan2 located in the first gate layer on the substrate, and the projection of the active pattern of the switching transistor T2 on the substrate will overlap with the projection of the part of the second scan line Scan2 located in the third gate layer on the substrate. This results in a large parasitic capacitance between the second connection line SL2 and the second scan line Scan2, leading to a smaller capacitance ratio. This application embodiment reduces the parasitic capacitance between the second connection line SL2 and the second scan line Scan2 by removing the portion of the second scan line Scan2 located in the first gate layer, thereby increasing the capacitance ratio and reducing the risk of screen burn-in and lifespan degradation.

[0080] Specifically, the light-shielding layer 221 can include the first gate of the switching transistor T2, so that after removing the portion of the second scan line Scan2 located in the first gate layer, the switching transistor T2 can still adopt a dual-gate design, thereby improving the performance of the switching transistor T2.

[0081] Specifically, it is understood that although the second connection line SL2 may not overlap with the projection of the second scan line Scan2 on the substrate, the active pattern of the switching transistor will connect to the second connection line SL2. Since the active pattern of the switching transistor overlaps with the projection of the second scan line Scan2 on the substrate, parasitic capacitance will exist between the second connection line SL2 and the second scan line Scan2. In this embodiment, by removing the portion of the second scan line Scan2 located in the first gate layer, the parasitic capacitance between the second connection line SL2 and the second scan line Scan2 can be reduced, thereby increasing the capacitance ratio and reducing the risk of screen burn-in and lifespan degradation.

[0082] In some embodiments, such as Figure 5 , Figure 6As shown, the light-shielding layer 221 includes a first light-shielding line BSM1 and a second light-shielding line BSM2. The first light-shielding line BSM1 and the second light-shielding line BSM2 extend along a first direction X and are spaced apart along a second direction Y. The portion of the first light-shielding line BSM1 corresponding to the active pattern of the compensation transistor T3 is the first gate of the compensation transistor T3, and the portion of the second light-shielding line BSM2 corresponding to the active pattern of the switching transistor T2 is the first gate of the switching transistor T2. The angle between the first direction X and the second direction Y is greater than 0 and less than or equal to 90 degrees.

[0083] Specifically, such as Figure 5 , Figure 6 As shown, by making the light-shielding layer 221 include the first light-shielding light BSM1, the portion of the first light-shielding light BSM1 corresponding to the active pattern of the compensation transistor T3 is the first gate T3Ga of the compensation transistor T3. This allows the compensation transistor T3 to still adopt a dual-gate design, improving the performance of the compensation transistor T3. At the same time, the portion of the first scan line Scan1 located in the first gate layer can be removed, thereby reducing the parasitic capacitance between the first node Q and the first scan line Scan1, increasing the capacitance ratio, and reducing the risk of screen burn-in and lifespan degradation.

[0084] Specifically, the part of the first shielding light BSM1 that corresponds to the active pattern of the initialization transistor T4 is the first gate T4Ga of the initialization transistor T4.

[0085] Specifically, such as Figure 5 , Figure 6 As shown, by including a first light-shielding light source BSM1 in the light-shielding layer 221, the portion of the first light-shielding light source BSM1 corresponding to the active pattern of the initialization transistor T4 becomes the first gate T4Ga of the initialization transistor T4. This allows the initialization transistor T4 to still adopt a dual-gate design, improving the performance of the initialization transistor T4. At the same time, the portion of the first scan line Scan1 located in the first gate layer can be removed, thereby reducing the parasitic capacitance between the second node P and the first scan line Scan1, increasing the capacitance ratio, and reducing the risk of screen burn-in and lifespan degradation.

[0086] Specifically, such as Figure 5 , Figure 6As shown, by including a second light-shielding light source BSM2 in the light-shielding layer 221, the portion of the second light-shielding light source BSM2 corresponding to the active pattern of the switching transistor T2 is the first gate T2Ga of the switching transistor T2. This allows the switching transistor T2 to still adopt a dual-gate design, improving the performance of the switching transistor T2. At the same time, it can remove the portion of the second scan line Scan2 located in the first gate layer, thereby reducing the parasitic capacitance between the second node P and the second scan line Scan2, increasing the capacitance ratio, and reducing the risk of screen burn-in and lifespan degradation.

[0087] Specifically, such as Figure 5 , Figure 6 As shown, the width of the portion of the first shading light BSM1 corresponding to the active pattern of the compensation transistor T3 and the width of the portion of the first shading light BSM1 corresponding to the active pattern of the initialization transistor T4 are greater than the widths of other portions of the first shading light BSM1. This embodiment does not limit the widths of the portions of the first shading light BSM1 corresponding to the active pattern of the compensation transistor T3 and the active pattern of the initialization transistor T4.

[0088] Specifically, such as Figure 5 , Figure 6 As shown, it can be seen that the width of the active pattern portion of the second light-shielding BSM2 corresponding to the switching transistor T2 is greater than the width of the other portions of the second light-shielding BSM2.

[0089] In some embodiments, such as Figure 2 , Figure 5 , Figure 6 , Figure 11 As shown, the display panel 1 further includes a substrate 21, a first gate layer 226, a second gate layer 228, and a third gate layer 233 arranged sequentially. The light-shielding layer 221 is disposed between the substrate 21 and the first gate layer 226. The third gate layer 233 includes a first scan line Scan1 and a second scan line Scan2. The first scan line Scan1 is correspondingly disposed to the first light-shielding line BSM1, and the second scan line Scan2 is correspondingly disposed to the second light-shielding line BSM2.

[0090] Specifically, by setting the first scan line Scan1 on the third gate layer 233 and removing the portion of the first scan line Scan1 located on the first gate layer, the parasitic capacitance between the first connection line SL1 and the second connection line SL2 and the first scan line Scan1 can be reduced, thereby increasing the capacitance ratio and reducing the risk of screen burn-in and lifespan degradation.

[0091] Specifically, by setting the second scan line Scan2 on the third gate layer 233 and removing the portion of the second scan line Scan2 located on the first gate layer, the parasitic capacitance between the second connection line SL2 and the second scan line Scan2 can be reduced, thereby increasing the capacitance ratio and reducing the risk of screen burn-in and lifespan degradation.

[0092] Specifically, by setting the first scan line Scan1 to correspond with the first shielding light BSM1, the first scan line Scan1 and the first shielding light BSM1 can respectively form the second gate and the first gate of each transistor, and the first shielding light BSM1 will not occupy additional space, thereby improving the resolution of the display panel.

[0093] Specifically, by setting the second scan line Scan2 to correspond with the second shielding light BSM2, the second scan line Scan2 and the second shielding light BSM2 can respectively form the second gate and the first gate of each transistor, and the second shielding light BSM2 will not occupy additional space, thereby improving the resolution of the display panel.

[0094] In some embodiments, at least one of the first light shielding BSM1 and the second light shielding BSM2 is grounded.

[0095] Specifically, by grounding the first light-shielding element BSM1, parasitic capacitance can be further reduced, capacitance ratio can be increased, and the risk of screen burn-in and lifespan degradation can be reduced.

[0096] Specifically, by grounding the second light-shielding BSM2, parasitic capacitance can be further reduced, capacitance ratio can be increased, and the risk of screen burn-in and lifespan degradation can be reduced.

[0097] Specifically, the first light-shielding light BSM1 can block the active pattern of the compensation transistor T3; the first light-shielding light BSM1 can also block the active pattern of the initialization transistor T4. The second light-shielding light BSM2 can block the active pattern of the switching transistor T2.

[0098] Specifically, it is understood that since the first shielding light BSM1 is grounded and the distance between the first shielding light BSM1 and the active patterns of each transistor is relatively far, and no scanning signal needs to be input to it, the portion of the first shielding light BSM1 corresponding to the active patterns of each transistor has a relatively small impact on each transistor. However, since there is a potential on it, it will affect the transistor. Therefore, in this embodiment, the portion of the first shielding light BSM1 corresponding to the active patterns of each transistor is still regarded as a gate of each transistor. However, this embodiment is not limited to this, and other names can be used to refer to the portion of the first shielding light BSM1 corresponding to the active patterns of each transistor. Similarly, the function of the portion of the second shielding light BSM2 corresponding to the active patterns of each transistor can be determined.

[0099] In some embodiments, such as Figure 3 As shown, the first electrode of the switching transistor T2 is electrically connected to the data line Data, and the second electrode of the switching transistor T2 is electrically connected to the second plate of the first capacitor C1 at the second node P; the second plate of the second capacitor C2 is electrically connected to the light-emitting device LED at the third node C, and the first electrode of the driving transistor T1 is electrically connected to the first electrode of the compensation transistor T3 at the fourth node A; the pixel driving circuit 13 also includes an initialization transistor T4, a first light-emitting control transistor T5, a second light-emitting control transistor T6, and a reset transistor T7. One gate of the initialization transistor T4 is electrically connected to the first scan line Scan1, the first electrode of the initialization transistor T4 is electrically connected to the initialization signal line, and the second electrode of the initialization transistor T4 is electrically connected to the second plate of the first capacitor C1 at the second node P; The gate of the first light-emitting control transistor T5 is electrically connected to the first light-emitting control line EM1, the first electrode of the first light-emitting control transistor T5 is electrically connected to the high-potential power supply line VDD, and the second electrode of the first light-emitting control transistor T5 is electrically connected to the first electrode of the driving transistor T1 at the fourth node A; the gate of the second light-emitting control transistor T6 is electrically connected to the second light-emitting control line EM2, the first electrode of the second light-emitting control transistor T6 is electrically connected to the second electrode of the driving transistor T1 at the fifth node B, and the second electrode of the second light-emitting control transistor T6 is electrically connected to the light-emitting device at the third node C; the gate of the reset transistor T7 is electrically connected to the first light-emitting control line EM1, the first electrode of the reset transistor T7 is electrically connected to the initialization signal line VI-A, and the second electrode of the reset transistor T7 is electrically connected to the anode of the light-emitting device LED at the third node C.

[0100] In some embodiments, such as Figure 2 , Figure 5 , Figure 7 As shown, the display panel 1 includes a substrate 21 and an active layer 224. The active layer 224 is disposed on one side of the substrate 21. The active layer 224 includes an active pattern T5A of a first light-emitting control transistor T5 and an active pattern T6A of a second light-emitting control transistor T6. The active patterns T5A of the first light-emitting control transistor T5 and the active patterns T6A of the second light-emitting control transistor T6 are disposed along a first direction X. The active pattern T5A of the first light-emitting control transistor T5 extends along a second direction Y. The angle between the first direction X and the second direction Y is greater than 0 and less than or equal to 90 degrees.

[0101] Specifically, such as Figure 7 As shown, the active pattern T6A of the second light-emitting control transistor T6 includes two parts extending along the first direction X and along the second direction Y.

[0102] Specifically, such as Figure 7 As shown, the active patterns of each transistor in two adjacent sub-pixel units can be symmetrically arranged.

[0103] In some embodiments, such as Figure 2 , Figure 5 , Figure 8 As shown, the display panel 1 further includes a first gate layer 226, which is disposed on the side of the active layer 224 away from the substrate 21. The first gate layer 226 includes a first portion EM1a of a first light-emitting control line EM1 and a second light-emitting control line EM2. The first portion EM1a of the first light-emitting control line EM1 and the second light-emitting control line EM2 extend along the first direction X, and the second light-emitting control line EM2 and the first portion EM1a of the first light-emitting control line EM1 are spaced apart along the second direction Y. By including the first portion EM1a of the first light-emitting control line EM1 and the second light-emitting control line EM2 in the first gate layer, the portions of the first scan line Scan1 and the second scan line Scan2 located in the first gate layer can be removed, thereby reducing the parasitic capacitance between the first node Q and the second node P and the first scan line Scan1, reducing the parasitic capacitance between the second node P and the second scan line Scan2, thereby reducing the total capacitance of the first node Q and the second node P, increasing the proportion of the first capacitor C1 and the second capacitor C2, improving the threshold voltage compensation capability, and reducing the risk of screen burn-in and lifespan degradation.

[0104] Specifically, such as Figure 5 , Figure 8 As shown, the first part EM1a of the first light-emitting control line EM1, which corresponds to the active pattern T5A of the first light-emitting control transistor T5, can be used as the gate T5G of the first light-emitting control transistor T5. The first part EM1a of the first light-emitting control line EM1, which corresponds to the active pattern T7 of the reset transistor T7, can be used as the first gate T7Ga of the reset transistor T7. The second light-emitting control line EM2, which corresponds to the active pattern T6A of the second light-emitting control transistor T6, can be used as the gate T6G of the second light-emitting control transistor T6.

[0105] Specifically, the width of the portion of the first part EM1a of the first light-emitting control line EM1 corresponding to the active pattern of the reset transistor T7 is greater than the width of the other parts of the first part EM1a of the first light-emitting control line EM, and the width of the portion of the second light-emitting control line EM2 corresponding to the active pattern T6A of the second light-emitting control transistor T6 is greater than the width of the other parts of the second light-emitting control line EM2.

[0106] In some embodiments, such as Figure 2 , Figure 5 , Figure 9 As shown, the display panel 1 further includes a second gate layer 228, which is disposed on the side of the first gate layer 226 away from the active layer 224. The second gate layer 228 includes the first gate T1Ga of the driving transistor T1.

[0107] Specifically, the first gate T1Ga of the driving transistor T1 can be connected to the second electrode of the driving transistor T1, so that the first gate T1Ga of the driving transistor T1 is not used as its bottom gate, but as an electrode to reduce the forward bias voltage, which can achieve the effect of improving the subthreshold swing characteristic.

[0108] In some embodiments, such as Figure 2 , Figure 5 , Figure 10 As shown, the display panel 1 further includes a semiconductor layer 231, which is disposed on the side of the second gate layer 228 away from the first gate layer 226. The semiconductor layer 231 includes an active pattern T1A of a driving transistor T1, an active pattern T2A of a switching transistor T2, an active pattern T3A of a compensation transistor T3, an active pattern T4A of an initialization transistor T4, and an active pattern T7A of a reset transistor T7. The active pattern T1A of the driving transistor T1 is connected to the active pattern T3A of the compensation transistor T3. The active patterns T2A of the switching transistor T2, T4A of the initialization transistor T4, T1A of the driving transistor T1, and T7A of the reset transistor T7 are spaced apart along the second direction Y. The active patterns T3A of the compensation transistor T3 and T4A of the initialization transistor T4 are spaced apart along the first direction X.

[0109] Specifically, such as Figure 10 As shown, the active patterns T7A of the two reset transistors T7 in two adjacent sub-pixel units can be connected, and the active patterns of other transistors in two adjacent sub-pixel units can be symmetrically arranged.

[0110] In some embodiments, such as Figure 2 , Figure 5 , Figure 11As shown, the display panel 1 further includes a third gate layer 233, which is disposed on the side of the semiconductor layer 231 away from the second gate layer 228. The third gate layer 233 includes a first scan line Scan1, a second scan line Scan2, a second portion EM1b of a first light-emitting control line EM1, a second gate T1Gb of a driving transistor T1, and a first electrode C1a of a first capacitor C1. The second portion EM1b of the first light-emitting control line EM1 is connected to the first portion EM1a of the first light-emitting control line EM1. The second scan line Scan2, the first scan line Scan1, the first electrode C1a of the first capacitor C1, and the second portion EM1b of the first light-emitting control line EM1 are spaced apart along the second direction Y.

[0111] Specifically, the second part EM1b of the first light-emitting control line EM1 is connected to the first part EM1a of the first light-emitting control line EM1. It can be understood that the connection point between the second part EM1b of the first light-emitting control line EM1 and the first part EM1a of the first light-emitting control line EM1 can be located in the non-display area or at the edge of the display area.

[0112] Specifically, such as Figure 5 , Figure 11 As shown, the second part EM1b of the first light-emitting control line EM1, which corresponds to the active pattern of the reset transistor T7, can be used as the second gate T7Gb of the reset transistor T7. The part of the first scan line Scan1, which corresponds to the active pattern of the compensation transistor T3, can be used as the second gate T3Gb of the compensation transistor T3. The part of the first scan line Scan1, which corresponds to the active pattern of the initialization transistor T4, can be used as the second gate T4Gb of the initialization transistor T4. The part of the second scan line Scan2, which corresponds to the active pattern of the switching transistor T2, can be used as the second gate T2Gb of the switching transistor T2.

[0113] Specifically, the width of the portion of the second part EM1b of the first light-emitting control line EM1 corresponding to the active pattern of the reset transistor T7 is greater than the width of the other portions of the second part EM1b of the first light-emitting control line EM1. Similarly, the width of the portion of the second scan line Scan2 corresponding to the active pattern of the switching transistor T2 is greater than the width of the other portions of the second scan line Scan2. Furthermore, the widths of the portions of the first scan line Scan1 corresponding to the active pattern of the compensation transistor T3 and the active pattern of the initialization transistor T4 are greater than the widths of the other portions of the first scan line Scan1. However, this embodiment does not limit the width of the portions of the first scan line Scan1 corresponding to the active pattern of the compensation transistor T3 and the active pattern of the initialization transistor T4.

[0114] Specifically, by making the first light-emitting control line EM1 comprise two parts located in the first gate layer and the third gate layer respectively, the impedance of the first light-emitting control line EM1 can be reduced, and the gate control capability of the reset transistor can be improved.

[0115] In some embodiments, such as Figure 2 , Figure 5 , Figure 12 As shown, the display panel 1 further includes a fourth gate layer 235, which is disposed on the side of the third gate layer 233 away from the semiconductor layer 231. The fourth gate layer 235 includes a second electrode C1b of the first capacitor C1 and a first electrode C2a of the second capacitor C2, with the second electrode C1b of the first capacitor C1 corresponding to the first electrode C1a of the first capacitor C1.

[0116] Specifically, such as Figure 12 As shown, the second plate C1b of the first capacitor C1 and the first plate C2a of the second capacitor C2 can share the same structure, thereby saving space.

[0117] In some embodiments, such as Figure 2 , Figure 5 , Figure 13 As shown, the display panel 1 further includes a fifth gate layer 237, which is disposed on the side of the fourth gate layer 235 away from the third gate layer 233. The fifth gate layer 237 includes a second electrode C2b of a second capacitor C2. The second electrode C2b of the second capacitor C2 is correspondingly disposed with respect to the first electrode C2a of the second capacitor C2.

[0118] Specifically, the projection of the first scan line Scan1 on the substrate overlaps with the projection of the first connection line SL1 on the substrate, and the second plate C2b of the second capacitor C2 is located outside the overlapping area of ​​the first scan line Scan1 and the first connection line SL1.

[0119] Specifically, the projection of the first scan line Scan1 on the substrate overlaps with the projection of the second connection line SL2 on the substrate, and the second plate C2b of the second capacitor C2 is located outside the overlapping area of ​​the first scan line Scan1 and the second connection line SL2.

[0120] Specifically, the projection of the first shielding light BSM1 onto the substrate overlaps with the projection of the first connecting line SL1 onto the substrate, and the second plate C2b of the second capacitor C2 is disposed outside the overlapping area of ​​the first shielding light BSM1 and the first connecting line SL1.

[0121] Specifically, the projection of the first shielding line BSM1 onto the substrate overlaps with the projection of the second connecting line SL2 onto the substrate, and the second plate C2b of the second capacitor C2 is located outside the overlapping area of ​​the first shielding line BSM1 and the second connecting line SL2.

[0122] In some embodiments, such as Figure 2 , Figure 5 , Figure 14 As shown, the display panel 1 further includes a first source-drain layer 239, which is disposed on the side of the fifth gate layer 237 away from the fourth gate layer 235. The first source-drain layer 239 includes a first connection line SL1 for transmitting a signal of the first node Q, a second connection line SL2 for transmitting a signal of the second node P, a first electrode T1S of a driving transistor T1, a second electrode T1D of a driving transistor T1, a first electrode T2S of a switching transistor T2, a second electrode T2D of a switching transistor T2, a first electrode T3S of a compensation transistor T3, a second electrode T3D of a compensation transistor T3, a first electrode T4S of an initialization transistor T4, a second electrode T4D of an initialization transistor T4, a first electrode T5S of a first light-emitting control transistor T5, a second electrode T5D of a first light-emitting control transistor T5, a first electrode T6S of a second light-emitting control transistor T6, a second electrode T6D of a second light-emitting control transistor T6, a first electrode T7S of a reset transistor T7, and a second electrode T7D of a reset transistor T7. The first connecting line SL1 is connected to the first electrode T3S and the second electrode T3D of the compensation transistor T3, and the second connecting line SL2 is connected to the second electrode T2D of the switching transistor T2 and the second electrode T4D of the initialization transistor T4. The first connecting line SL1 and the second connecting line SL2 extend along the second direction Y.

[0123] Specifically, the first and second electrodes of each transistor are connected to the active pattern of each transistor, respectively.

[0124] In some embodiments, such as Figure 2 , Figure 5 , Figure 15 As shown, the display panel 1 further includes a second source-drain layer 243, which is disposed on the side of the first source-drain layer 239 away from the fifth gate layer 237. The second source-drain layer 243 includes two high-potential power lines VDD, an initialization signal line VI-A, a third connection line SL3, a fourth connection line SL4, and a fifth connection line SL5. The third connection line SL3, the initialization signal line VI-A, one of the high-potential power lines VDD, the fourth connection line SL4, the other high-potential power line VDD, and the fifth connection line SL5 are arranged sequentially along the second direction Y. The initialization signal line VI-A is connected to the first electrode T4S of the initialization transistor T4; a high-potential power supply line VDD is correspondingly configured with the active pattern T1A of the driving transistor T1; another high-potential power supply line VDD is connected to the first electrode T5S of the first light-emitting control transistor T5; the third connection line SL3 is connected to the first electrode T2S of the switching transistor T2; the fourth connection line SL4 is connected to the second electrode T6D of the second light-emitting control transistor T6; and the fifth connection line SL5 is connected to the first electrode T7S of the reset transistor T7.

[0125] Specifically, by setting the initialization signal line VI-A, the initialization signal line VI-A can be connected to the first electrode T4S of the initialization transistor T4, thereby enabling the initialization signal line VI-A to output a signal to the initialization transistor T4.

[0126] Specifically, by aligning a high-potential power line VDD with the active pattern T1A of the driving transistor T1, the driving transistor T1 can be shielded by the high-potential power line, preventing external light from affecting the performance of the driving transistor T1.

[0127] Specifically, by connecting another high-potential power supply line VDD to the first electrode T5S of the first light-emitting control transistor T5, the high-potential power supply line VDD can output a signal to the first light-emitting control transistor T5.

[0128] Specifically, by connecting the third connection line SL3 to the first electrode T2S of the switching transistor T2, the third connection line SL3 can connect the first electrode T2S of the switching transistor T2 and the data line Data, so that the signal of the data line Data is output to the switching transistor T2.

[0129] Specifically, by connecting the fourth connection line SL4 to the second electrode T6D of the second light-emitting control transistor T6, the fourth connection line SL4 can connect the second electrode T6D of the second light-emitting control transistor T6 and the sixth connection line SL6, thereby connecting the second electrode T6D of the second light-emitting control transistor T6 to the light-emitting device LED.

[0130] Specifically, the second source-drain layer may also include another initialization signal line, which is connected to the first electrode T7S of the reset transistor T7 via the fifth connection line SL5.

[0131] In some embodiments, such as Figure 2 , Figure 5 , Figure 16 As shown, the display panel 1 further includes a third source-drain layer 245, which is disposed on the side of the second source-drain layer 243 away from the first source-drain layer 239. The third source-drain layer 245 includes a data line Data and a sixth connection line SL6. The data line Data is connected to the third connection line SL3, and the sixth connection line SL6 is connected to the fourth connection line SL4.

[0132] Specifically, by connecting the data line Data to the third connection line SL3, the data line Data is connected to the switching transistor T2. By connecting the sixth connection line SL6 to the fourth connection line SL4, the second electrode T6D of the second light-emitting control transistor T6 is connected to the light-emitting device LED.

[0133] Specifically, the third source-drain layer may also include a high-potential power line and an initialization signal line. The high-potential power line located in the third source-drain layer may extend along the second direction and be connected to the high-potential power line located in the second source-drain layer. The initialization signal line located in the third source-drain layer may extend along the second direction and be connected to the initialization signal line located in the second source-drain layer.

[0134] Meanwhile, to illustrate the location of the vias that pass between different membrane layers, [the following is provided] Figures 17 to 20 . Figure 17 The location of the first via 311 is shown in the figure. The first via 311 refers to the via etched from the first source / drain layer to the active layer. Figure 18 The location of the second via 312 is shown. The second via 312 refers to the via etched from the first source / drain layer to the second gate layer, semiconductor layer, third gate layer, fourth gate layer and fifth gate layer. Figure 19 The location of the third via 313 is shown in the figure. The third via 313 refers to the via etched from the second source-drain layer to the first source-drain layer, and can be regarded as the via of the first planarization layer and passivation layer. Figure 20 The location of the fourth via 314 is shown in the figure. The fourth via 314 refers to the via etched from the third source-drain layer to the second source-drain layer, and can be regarded as the via of the second planarization layer.

[0135] At the same time, in order to illustrate the relative positions of each film layer, provide Figure 5 , Figures 21 to 33 To explain, from Figure 21 As can be seen, the relative positions of each structure in the light-shielding layer 221 and each structure in the active layer 224 are shown; from Figure 22 As can be seen, the relative positions of each structure in the light-shielding layer 221, the active layer 224, and the first gate layer 226 are shown; from Figure 23 The relative positions of the structures in the light-shielding layer 221, the active layer 224, the first gate layer 226, and the second gate layer 228 can be seen; from Figure 24 The relative positions of the structures in the light-shielding layer 221, active layer 224, first gate layer 226, second gate layer 228, and semiconductor layer 231 can be seen; from Figure 25 The relative positions of each structure in the light-shielding layer 221, active layer 224, first gate layer 226, second gate layer 228, semiconductor layer 231, and third gate layer 233 can be seen.

[0136] from Figure 26 The relative positions of the structures in the light-shielding layer 221, active layer 224, first gate layer 226, second gate layer 228, semiconductor layer 231, third gate layer 233, and fourth gate layer 235 can be seen; from Figure 27 The relative positions of the structures in the light-shielding layer 221, active layer 224, first gate layer 226, second gate layer 228, semiconductor layer 231, third gate layer 233, fourth gate layer 235, and fifth gate layer 237 can be seen; from Figure 28 The relative positions of the structures in the light-shielding layer 221, active layer 224, first gate layer 226, second gate layer 228, semiconductor layer 231, third gate layer 233, fourth gate layer 235, fifth gate layer 237, and first via 311 can be seen.

[0137] from Figure 29 The relative positions of the structures in the light-shielding layer 221, active layer 224, first gate layer 226, second gate layer 228, semiconductor layer 231, third gate layer 233, fourth gate layer 235, fifth gate layer 237, first via 311, and second via 312 can be seen; from Figure 30The relative positions of the structures in the light-shielding layer 221, active layer 224, first gate layer 226, second gate layer 228, semiconductor layer 231, third gate layer 233, fourth gate layer 235, fifth gate layer 237, first via 311, second via 312, and first source / drain layer 239 can be seen; from Figure 31 The relative positions of the structures in the light-shielding layer 221, active layer 224, first gate layer 226, second gate layer 228, semiconductor layer 231, third gate layer 233, fourth gate layer 235, fifth gate layer 237, first via 311, second via 312, first source / drain layer 239, and third via 313 can be seen.

[0138] from Figure 32 The relative positions of the structures in the light-shielding layer 221, active layer 224, first gate layer 226, second gate layer 228, semiconductor layer 231, third gate layer 233, fourth gate layer 235, fifth gate layer 237, first via 311, second via 312, first source / drain layer 239, third via 313, and second source / drain layer 243 can be seen; from Figure 33 The relative positions of the structures in the active layer 224, first gate layer 226, second gate layer 228, semiconductor layer 231, third gate layer 233, fourth gate layer 235, fifth gate layer 237, first via 311, second via 312, first source / drain layer 239, third via 313, second source / drain layer 243, and fourth via 314 can be seen; from Figure 5 The relative positions of each membrane layer can be seen in the image.

[0139] Specifically, in the above embodiments, the first electrode of the transistor is the source and the second electrode is the drain; or in the above embodiments, the first electrode of the transistor is the drain and the second electrode is the source.

[0140] Specifically, the active layer material includes silicon semiconductor materials, specifically low-temperature polycrystalline silicon. The semiconductor layer material includes oxide semiconductor materials, specifically metal oxide semiconductor materials, and more specifically, indium gallium zinc oxide.

[0141] Specifically, the driving transistor, switching transistor, compensation transistor, initialization transistor, and reset transistor can be N-type transistors, while the first light-emitting control transistor and the second light-emitting control transistor can be P-type transistors.

[0142] Specifically, the above embodiments have described the display panel in detail from the aspects of each circuit, each film layer, each structure and their combination. It is understood that when there is no conflict between the embodiments, the embodiments can be combined. For example, the material of the active layer includes silicon semiconductor material, and the material of the semiconductor layer includes oxide semiconductor material.

[0143] Specifically, the first sub-pixel unit, the second sub-pixel unit, and the third sub-pixel unit emit red, green, and blue light, respectively. However, the embodiments of this application are not limited to this. For example, the first sub-pixel unit, the second sub-pixel unit, and the third sub-pixel unit emit red, blue, and green light, respectively, or the first sub-pixel unit, the second sub-pixel unit, and the third sub-pixel unit emit green, red, and blue light, respectively.

[0144] Specifically, the above embodiments have described the display panel in detail from the aspects of each circuit, each film layer, each structure and their combination. It is understood that when there is no conflict between the embodiments, the embodiments can be combined. For example, the material of the active layer includes silicon semiconductor material, and the material of the semiconductor layer includes oxide semiconductor material.

[0145] Meanwhile, this application provides a display device, which includes a display panel as described in any of the above embodiments.

[0146] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0147] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0148] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0149] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A display panel, characterized in that, The device includes a pixel driving circuit and a light-emitting device electrically connected to the pixel driving circuit. The pixel driving circuit includes a driving transistor, a switching transistor, a compensation transistor, a first capacitor, and a second capacitor. A gate of the driving transistor is electrically connected to a first plate of the first capacitor and an electrode of the compensation transistor at a first node. A second plate of the first capacitor is electrically connected to a first plate of the second capacitor and an electrode of the switching transistor at a second node. A gate of the compensation transistor is electrically connected to a first scan line, and a gate of the switching transistor is electrically connected to a second scan line. The display panel includes a light-shielding layer, which includes the first gate of the compensation transistor, and / or the light-shielding layer includes the first gate of the switching transistor.

2. The display panel according to claim 1, characterized in that, The light-shielding layer includes a first light-shielding line and a second light-shielding line. The first light-shielding line and the second light-shielding line extend along a first direction and are spaced apart along a second direction. The portion of the first light-shielding line corresponding to the active pattern of the compensation transistor is the first gate of the compensation transistor, and the portion of the second light-shielding line corresponding to the active pattern of the switching transistor is the first gate of the switching transistor. The angle between the first direction and the second direction is greater than 0 and less than or equal to 90 degrees.

3. The display panel according to claim 2, characterized in that, The display panel further includes a substrate, a first gate layer, a second gate layer and a third gate layer disposed sequentially, the light-shielding layer is disposed between the substrate and the first gate layer, and the third gate layer includes a first scan line and a second scan line; The first scan line is set to correspond to the first shading line, and the second scan line is set to correspond to the second shading line.

4. The display panel according to claim 2, characterized in that, At least one of the first and second shielding lights is grounded.

5. The display panel according to any one of claims 1 to 4, characterized in that, The first electrode of the switching transistor is electrically connected to the data line, and the second electrode of the switching transistor is electrically connected to the second plate of the first capacitor at the second node; the second plate of the second capacitor is electrically connected to the light-emitting device at the third node, and the first electrode of the driving transistor is electrically connected to the first electrode of the compensation transistor at the fourth node. The pixel driving circuit also includes: An initialization transistor is formed, wherein one gate of the initialization transistor is electrically connected to the first scan line, the first electrode of the initialization transistor is electrically connected to the initialization signal line, and the second electrode of the initialization transistor is electrically connected to the second plate of the first capacitor at the second node; The first light-emitting control transistor has its gate electrically connected to the first light-emitting control line, its first electrode electrically connected to the high-potential power supply line, and its second electrode electrically connected to the first electrode of the driving transistor at the fourth node. The second light-emitting control transistor has its gate electrically connected to the second light-emitting control line, its first electrode electrically connected to the second electrode of the driving transistor at the fifth node, and its second electrode electrically connected to the light-emitting device at the third node. A reset transistor, the gate of which is electrically connected to the first light-emitting control line, the first electrode of which is connected to the initialization signal line, and the second electrode of which is connected to the second electrode of the second light-emitting control transistor at the third node.

6. The display panel according to claim 5, characterized in that, The display panel includes a substrate and an active layer. The active layer is disposed on one side of the substrate. The active layer includes an active pattern of a first light-emitting control transistor and an active pattern of a second light-emitting control transistor. The active patterns of the first light-emitting control transistor and the second light-emitting control transistor are disposed along a first direction. The active pattern of the first light-emitting control transistor extends along a second direction. The angle between the first direction and the second direction is greater than 0 and less than or equal to 90 degrees.

7. The display panel according to claim 6, characterized in that, The display panel further includes a first gate layer, which is disposed on the side of the active layer away from the substrate. The first gate layer includes a first portion of a first light-emitting control line and a second light-emitting control line. The first portion of the first light-emitting control line and the second light-emitting control line extend along the first direction, and the second light-emitting control line and the first portion of the first light-emitting control line are spaced apart along the second direction.

8. The display panel according to claim 7, characterized in that, The display panel further includes a second gate layer, which is disposed on the side of the first gate layer away from the active layer, and the second gate layer includes the first gate of the driving transistor.

9. The display panel according to claim 8, characterized in that, The display panel further includes a semiconductor layer disposed on the side of the second gate layer away from the first gate layer. The semiconductor layer includes an active pattern of a driving transistor, an active pattern of a switching transistor, an active pattern of a compensation transistor, an active pattern of an initialization transistor, and an active pattern of a reset transistor. The active pattern of the driving transistor is connected to the active pattern of the compensation transistor. The active patterns of the switching transistor, the initialization transistor, the driving transistor, and the reset transistor are spaced apart along the second direction. The active patterns of the compensation transistor and the initialization transistor are spaced apart along the first direction.

10. The display panel according to claim 9, characterized in that, The display panel further includes a third gate layer, which is disposed on the side of the semiconductor layer away from the second gate layer. The third gate layer includes a first scan line, a second scan line, a second portion of a first light-emitting control line, a second gate of a driving transistor, and a first electrode of a first capacitor. The second part of the first light-emitting control line is connected to the first part of the first light-emitting control line, and the second scan line, the first scan line, the first electrode plate of the first capacitor and the second part of the first light-emitting control line are spaced apart along the second direction.

11. The display panel according to claim 10, characterized in that, The display panel further includes a fourth gate layer, which is disposed on the side of the third gate layer away from the semiconductor layer. The fourth gate layer includes a second electrode of the first capacitor and a first electrode of the second capacitor, with the second electrode of the first capacitor corresponding to the first electrode of the first capacitor.

12. The display panel according to claim 11, characterized in that, The display panel further includes a fifth gate layer, which is disposed on the side of the fourth gate layer away from the third gate layer. The fifth gate layer includes a second plate of a second capacitor. The second plate of the second capacitor is disposed corresponding to the first plate of the second capacitor.

13. The display panel according to claim 12, characterized in that, The display panel further includes a first source-drain layer, which is disposed on the side of the fifth gate layer away from the fourth gate layer. The first source-drain layer includes a first connection line for transmitting signals of the first node, a second connection line for transmitting signals of the second node, a first electrode of a driving transistor, a second electrode of a driving transistor, a first electrode of a switching transistor, a second electrode of a switching transistor, a first electrode of a compensation transistor, a second electrode of a compensation transistor, a first electrode of an initialization transistor, a second electrode of an initialization transistor, a first electrode of a first light-emitting control transistor, a second electrode of a first light-emitting control transistor, a first electrode of a second light-emitting control transistor, a second electrode of a second light-emitting control transistor, a first electrode of a reset transistor, and a second electrode of a reset transistor. The first connecting line is connected to the first electrode of the compensation transistor and the second electrode of the compensation transistor, and the second connecting line is connected to the second electrode of the switching transistor and the second electrode of the initialization transistor. The first connecting line and the second connecting line extend along the second direction.

14. The display panel according to claim 13, characterized in that, The display panel further includes a second source-drain layer, which is disposed on the side of the first source-drain layer away from the fifth gate layer. The second source-drain layer includes two high-potential power lines, an initialization signal line, a third connection line, a fourth connection line, and a fifth connection line. The third connection line, the initialization signal line, one of the high-potential power lines, the fourth connection line, the other high-potential power line, and the fifth connection line are arranged sequentially along the second direction. The initialization signal line is connected to the first electrode of the initialization transistor, a high-potential power supply line is configured to correspond to the active pattern of the driving transistor, another high-potential power supply line is connected to the first electrode of the first light-emitting control transistor, the third connection line is connected to the first electrode of the switching transistor, the fourth connection line is connected to the second electrode of the second light-emitting control transistor, and the fifth connection line is connected to the first electrode of the reset transistor.

15. The display panel according to claim 14, characterized in that, The display panel further includes a third source-drain layer, which is disposed on the side of the second source-drain layer away from the first source-drain layer. The third source-drain layer includes a data line and a sixth connection line, wherein the data line is connected to the third connection line and the sixth connection line is connected to the fourth connection line.

16. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 15.

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