Semiconductor device and method of manufacture, power module, power conversion circuit and vehicle

Abstract

The application discloses a semiconductor device and a preparation method thereof, a power module, a power conversion circuit and a vehicle, and belongs to the technical field of semiconductors. The semiconductor device comprises a semiconductor structure, a dielectric layer located on one side of the semiconductor structure in the thickness direction, wherein the dielectric layer is provided with a first connecting hole penetrating through the dielectric layer, and the side wall of the first connecting hole is inclined away from the first connecting hole; a first conductive structure filled in the first connecting hole and electrically connected with the semiconductor structure; and a second conductive structure located on one side of the semiconductor structure in the thickness direction; wherein the inclination angle of the side wall of the first connecting hole is positively correlated with the spacing between the first connecting hole and the second conductive structure in the first direction, and the inclination angle is the included angle between the side wall and the thickness direction. The application can improve the filling effect of the first conductive structure in the first connecting hole while avoiding the risk of electric leakage, thereby improving the reliability and stability of the semiconductor device.

Description

Technical Field

[0001] This application belongs to the field of semiconductor technology, and particularly relates to a semiconductor device and its preparation method, a power module, a power conversion circuit, and a vehicle. Background Technology

[0002] In semiconductor devices, the main technology used is dry etching to form interconnects, which results in a relatively small tilt angle on the sidewalls of the interconnects. When filling the interconnects with conductive structures, the filling effect is poor, affecting the reliability and stability of the device. Summary of the Invention

[0003] This application aims to at least address one of the technical problems existing in the prior art. To this end, this application proposes a semiconductor device and its fabrication method, a power module, a power conversion circuit, and a vehicle, which can improve the filling effect of the first conductive structure in the first connection hole while avoiding the risk of leakage current, thereby improving the reliability and stability of the semiconductor device.

[0004] In a first aspect, this application provides a semiconductor device, comprising: Semiconductor structure; A dielectric layer is located on one side of the semiconductor structure in the thickness direction. A first connection hole is provided in the dielectric layer, and the sidewall of the first connection hole is inclined in the direction away from the first connection hole. A first conductive structure is filled in the first connection hole and electrically connected to the semiconductor structure; The second conductive structure is located on one side of the semiconductor structure in the thickness direction and is spaced apart from the first connecting hole along a first direction, the first direction being perpendicular to the thickness direction; The inclination angle of the sidewall of the first connection hole is positively correlated with the distance between the first connection hole and the second conductive structure in the first direction, and the inclination angle is the angle between the sidewall and the thickness direction.

[0005] According to the semiconductor device of this application, the sidewall of the first connection hole is inclined in a direction away from the first connection hole, and the inclination angle of the sidewall of the first connection hole is positively correlated with the distance between the first connection hole and the second conductive structure in the first direction. When the distance between the first connection hole and the second conductive structure in the first direction is large, the inclination angle of the sidewall of the first connection hole is increased as much as possible to facilitate the filling of the first conductive structure and improve the filling effect of the first conductive structure. When the distance between the first connection hole and the second conductive structure in the first direction is small, the inclination angle of the sidewall of the first connection hole is reduced to avoid the distance between the second conductive structure and the sidewall of the first connection hole being too small, thereby avoiding leakage between the second conductive structure and the first conductive structure and effectively improving the reliability and stability of the semiconductor device.

[0006] According to one embodiment of this application, the orthographic projection of the side of the first connection hole away from the semiconductor structure on the semiconductor structure does not overlap with the orthographic projection of the second conductive structure on the semiconductor structure.

[0007] According to one embodiment of this application, the dielectric layer is further provided with a second connecting hole penetrating the dielectric layer, and the sidewall of the second connecting hole is inclined in a direction away from the second connecting hole; The second conductive structure fills the second connection hole and is electrically connected to the semiconductor structure.

[0008] According to one embodiment of this application, the inclination angle of the sidewall of the second connecting hole is positively correlated with the distance between the first connecting hole and the second connecting hole in the first direction.

[0009] According to one embodiment of this application, the inclination angle of the first connecting hole sidewall and the inclination angle of the second connecting hole sidewall are respectively greater than or equal to 40° and less than or equal to 75°.

[0010] According to one embodiment of this application, the semiconductor structure includes: The semiconductor body includes a first surface and a second surface disposed opposite to each other in the thickness direction; The gate structure is located on the side of the semiconductor body near the first surface, or extends from the first surface into the semiconductor body; An insulating layer is located between the gate structure and the semiconductor body; The dielectric layer covers the gate structure, and the first conductive structure and the second conductive structure are respectively connected to the gate structure.

[0011] According to one embodiment of this application, the second conductive structure is located on the side of the semiconductor structure close to the dielectric layer, and the dielectric layer covers the second conductive structure and the semiconductor structure.

[0012] According to one embodiment of this application, the semiconductor structure includes: A semiconductor body includes a first surface and a second surface disposed opposite to each other in the thickness direction, and the semiconductor body further includes a first region located on the first surface; The semiconductor device further includes: An insulating layer is located on the first surface of the semiconductor body; The second conductive structure includes a gate structure located on the side of the insulating layer opposite to the semiconductor body; the dielectric layer covers the gate structure and the first region, and the first connection hole corresponds to the position of the first region; The first conductive structure includes a source electrode located on the side of the dielectric layer opposite to the semiconductor body and filling the first connection hole to connect with the first region.

[0013] According to one embodiment of this application, the inclination angle of the sidewall of the first connection hole is greater than 0° and less than or equal to 25°.

[0014] According to one embodiment of this application, the first conductive structure includes: An adhesive layer covers the surface of the first connection hole; A metal layer is filled in the first connection hole.

[0015] Secondly, this application provides a method for fabricating a semiconductor device, the method comprising: A semiconductor structure, a dielectric layer, and a second conductive structure are formed, wherein the dielectric layer and the second conductive structure are located on the same side of the thickness direction of the semiconductor structure; A first connection hole is formed penetrating the dielectric layer. The sidewall of the first connection hole is inclined in a direction away from the first connection hole, and the first connection hole and the second conductive structure are spaced apart along a first direction, which is perpendicular to the thickness direction. The inclination angle of the sidewall of the first connection hole is positively correlated with the distance between the first connection hole and the second conductive structure in the first direction, and the inclination angle is the angle between the sidewall and the thickness direction. A first conductive structure is filled into the first connection hole, and the first conductive structure is electrically connected to the semiconductor structure.

[0016] According to one embodiment of this application, forming a first connection hole penetrating the dielectric layer includes: A mask layer with a mask opening is formed on the side of the dielectric layer opposite to the semiconductor structure; A first connection hole is formed through the mask opening, penetrating the dielectric layer; the orthographic projection of the mask opening on the semiconductor structure is located within the orthographic projection of the side of the first connection hole closest to the semiconductor structure on the semiconductor structure, and the size of the side of the first connection hole opposite to the semiconductor structure is larger than the size of the mask opening; Remove the mask layer.

[0017] According to one embodiment of this application, forming a first connection hole penetrating the dielectric layer includes: Determine the target tilt angle that the sidewall of the first connecting hole needs to form; Based on the relationship between the tilt angle of the first connection hole sidewall and the etching rate of the dielectric layer, the target etching rate corresponding to the target tilt angle is determined. Based on the relationship between the etching rate and etching temperature of the dielectric layer, the target etching temperature corresponding to the target etching rate is determined; At the target etching temperature, a wet etching process is used to form a first connection hole penetrating the dielectric layer in the dielectric layer at the target etching rate, and the tilt angle of the sidewall of the first connection hole is the target tilt angle.

[0018] According to one embodiment of this application, the tilt angle of the first connection hole sidewall is positively correlated with the etching rate of the dielectric layer, and the etching rate of the dielectric layer is positively correlated with the etching temperature.

[0019] Thirdly, this application provides a power module including a substrate and a semiconductor device as described in the first aspect above, wherein the substrate is used to support the semiconductor device.

[0020] Fourthly, this application provides a power conversion circuit, which is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and a semiconductor device as described in the first aspect above, the semiconductor device being electrically connected to the circuit board.

[0021] Fifthly, this application provides a vehicle including a load and a power conversion circuit as described in the fourth aspect above, the power conversion circuit being used to convert alternating current to direct current, convert alternating current to alternating current, convert direct current to direct current, or convert direct current to alternating current and then input the converted direct current to the load.

[0022] The above-described one or more technical solutions in the embodiments of this application have at least one of the following technical effects: The sidewall of the first connecting hole is inclined in a direction away from the first connecting hole, and the inclination angle of the sidewall of the first connecting hole is positively correlated with the distance between the first connecting hole and the second conductive structure in the first direction. When the distance between the first connecting hole and the second conductive structure in the first direction is large, the inclination angle of the sidewall of the first connecting hole should be increased as much as possible to facilitate the filling of the first conductive structure and improve the filling effect of the first conductive structure. When the distance between the first connecting hole and the second conductive structure in the first direction is small, the inclination angle of the sidewall of the first connecting hole should be reduced to avoid the distance between the second conductive structure and the sidewall of the first connecting hole being too small, thereby avoiding leakage between the second conductive structure and the first conductive structure and effectively improving the reliability and stability of the semiconductor device.

[0023] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0024] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which: Figure 1 This is one of the schematic diagrams of the semiconductor device provided in the embodiments of this application; Figure 2 This is a second schematic diagram of the structure of the semiconductor device provided in the embodiments of this application; Figure 3 This is the third schematic diagram of the semiconductor device provided in the embodiments of this application; Figure 4 This is a schematic flowchart of the method for fabricating a semiconductor device provided in an embodiment of this application; Figure 5 This is one of the structural schematic diagrams in the method for fabricating a semiconductor device provided in the embodiments of this application; Figure 6 This is a second schematic diagram of the structure in the method for fabricating a semiconductor device provided in the embodiments of this application; Figure 7 This is a graph showing the relationship between etching temperature and etching rate in the semiconductor device fabrication method provided in the embodiments of this application; Figure 8 This is a graph showing the relationship between tilt angle and etching rate in the semiconductor device fabrication method provided in this application embodiment. Detailed Implementation

[0025] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0026] The following description, with reference to the accompanying drawings, describes the semiconductor device and its fabrication method, power module, power conversion circuit, and vehicle provided in embodiments of this application.

[0027] Figure 1 and Figure 2 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this application.

[0028] like Figure 1 and Figure 2 As shown, the semiconductor device provided in this application embodiment includes a semiconductor structure 1, a dielectric layer 2, a first conductive structure 3, and a second conductive structure 4.

[0029] Semiconductor structure 1 may include a single semiconductor layer or multiple semiconductor layers stacked together. The semiconductor layer may be a SiC semiconductor layer or a polycrystalline silicon (poly) semiconductor layer, etc. Semiconductor structure 1 may also include other film layers, which are not specifically limited here.

[0030] The dielectric layer 2 is located on one side of the semiconductor structure 1 in the thickness direction X. A first connection hole 21 penetrating the dielectric layer 2 is provided in the dielectric layer 2, and the sidewall of the first connection hole 21 is inclined in a direction away from the first connection hole 21. The dielectric layer 2 can be a single layer or a multilayer structure. The material of the dielectric layer 2 can include one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0031] The first connection hole 21 penetrates the dielectric layer 2 along the thickness direction X. The cross-section of the first connection hole 21 in the thickness direction X is an inverted trapezoid. The dimension of the first connection hole 21 on the side opposite to the semiconductor structure 1 (e.g.) Figure 1 The top dimension of the first connection hole 21 shown is larger than the dimension of the first connection hole 21 on the side closer to the semiconductor structure 1 (e.g., Figure 1 The bottom dimensions of the first connecting hole 21 shown are included. Dimensions may include length, width, diameter, area, etc. When the cross-section of the first connecting hole 21 in the first direction Y is circular, the dimensions of the first connecting hole 21 may include the diameter. The first direction Y is perpendicular to the thickness direction X.

[0032] The first conductive structure 3 fills the first connecting hole 21 and is electrically connected to the semiconductor structure 1. The first conductive structure 3 may only fill the first connecting hole 21, that is, the surface of the first conductive structure 3 facing away from the semiconductor structure 1 is flush with the surface of the dielectric layer 2 facing away from the semiconductor structure 1. Alternatively, the first conductive structure 3 may be located on the side of the dielectric layer 2 facing away from the semiconductor structure 1 and filled in the first connecting hole 21 and electrically connected to the semiconductor structure 1.

[0033] The second conductive structure 4 is located on one side of the semiconductor structure 1 in the thickness direction X, and is spaced apart from the first connecting hole 21 in the first direction Y. The second conductive structure 4 can be located between the semiconductor structure 1 and the dielectric layer 2, or it can be located in the dielectric layer 2. The second conductive structure 4 and the first connecting hole 21 are spaced apart in the first direction Y, that is, the second conductive structure 4 and the first connecting hole 21 do not overlap in the thickness direction X. The second conductive structure 4 and the first connecting hole 21 at least partially overlap in the first direction Y.

[0034] The tilt angle α1 of the sidewall of the first connecting hole 21 is positively correlated with the distance between the first connecting hole 21 and the second conductive structure 4 in the first direction Y. The tilt angle α1 is the angle between the sidewall and the thickness direction X. The larger the distance between the first connecting hole 21 and the second conductive structure 4 in the first direction Y, the larger the tilt angle α1 of the sidewall of the first connecting hole 21, and the larger the size of the side of the first connecting hole 21 facing away from the semiconductor structure 1. The smaller the distance between the first connecting hole 21 and the second conductive structure 4 in the first direction Y, the smaller the tilt angle α1 of the sidewall of the first connecting hole 21, and the smaller the size of the side of the first connecting hole 21 facing away from the semiconductor structure 1.

[0035] In this embodiment, when the distance between the first connecting hole 21 and the second conductive structure 4 in the first direction Y is large, the tilt angle α1 of the sidewall of the first connecting hole 21 is increased as much as possible. This allows the first conductive structure 3 to better fill the first connecting hole 21, improving the coverage of the sidewall of the first connecting hole 21 by the first conductive structure 3, thereby improving the filling effect of the first conductive structure 3. Furthermore, the larger distance between the first conductive structure 3 and the second conductive structure 4 avoids the risk of leakage. When the distance between the first connecting hole 21 and the second conductive structure 4 in the first direction Y is small, the tilt angle of the sidewall of the first connecting hole 21 is reduced to prevent the distance between the second conductive structure 4 and the sidewall of the first connecting hole 21 from being too small, thus preventing leakage between the second conductive structure 4 and the first conductive structure 3. The sidewall of the first connecting hole 21 is still tilted, effectively improving the filling effect of the first conductive structure 3.

[0036] In some embodiments, the orthographic projection of the side of the first connecting hole 21 facing away from the semiconductor structure 1 on the semiconductor structure 1 does not overlap with the orthographic projection of the second conductive structure 4 on the semiconductor structure 1, so as to ensure that the second conductive structure 4 and the sidewall of the first connecting hole 21 have a certain distance, and to avoid leakage between the second conductive structure 4 and the first conductive structure 1.

[0037] In some embodiments, such as Figure 1 As shown, the first conductive structure 3 includes an adhesive layer (i.e., the first adhesive layer 31) and a metal layer (i.e., the first metal layer 32). The first adhesive layer 31 covers the surface of the first connection hole 21 (including the sidewalls and bottom of the first connection hole 21), and the first metal layer 32 fills the first connection hole 21. The material of the first adhesive layer 31 may include TiN, etc., and the material of the first metal layer 32 may include metals such as aluminum, copper, and nickel.

[0038] In this embodiment, the sidewall of the first connecting hole 21 is inclined in a direction away from the first connecting hole 21, which can improve the coverage of the first adhesive layer 31 on the sidewall of the first connecting hole 21, improve the filling property of the first metal layer 32 in the first connecting hole 21, and thus improve the filling effect of the first conductive structure 3 in the first connecting hole 21.

[0039] In some embodiments, the dielectric layer 2 is further provided with a second connection hole 22 penetrating the dielectric layer 2. The sidewall of the second connection hole 22 is inclined in a direction away from the second connection hole 22. The second conductive structure 3 fills the second connection hole 22 and is electrically connected to the semiconductor structure 1.

[0040] The second connection hole 22 penetrates the dielectric layer 2 along the thickness direction X, and the second connection hole 22 and the first connection hole 21 are spaced apart along the first direction Y. The cross-section of the second connection hole 22 in the thickness direction X is an inverted trapezoid. The dimension of the second connection hole 22 on the side opposite to the semiconductor structure 1 (e.g.) Figure 1 The top dimension of the second connection hole 22 shown is larger than the dimension of the second connection hole 22 on the side closer to the semiconductor structure 1 (e.g., Figure 1 (The bottom dimension of the second connecting hole 22 shown). When the cross-section of the second connecting hole 22 in the first direction Y is circular, the dimension of the second connecting hole 22 may include the diameter.

[0041] It should be noted that the structures of the first connecting hole 21 and the second connecting hole 22 can be the same or different. That is, the inclination angle α2 of the sidewall of the second connecting hole 22 can be the same or different from the inclination angle α1 of the sidewall of the first connecting hole 21, the top dimension of the second connecting hole 22 can be the same or different from the top dimension of the first connecting hole 21, and the bottom dimension of the second connecting hole 22 can be the same or different from the bottom dimension of the first connecting hole 21. The first conductive structure 3 and the second conductive structure 4 can connect the same or different structures in the semiconductor structure 1.

[0042] In some embodiments, the tilt angle α1 of the sidewall of the second connecting hole 22 is positively correlated with the distance between the first connecting hole 21 and the second connecting hole 22 in the first direction Y. The larger the distance between the first connecting hole 21 and the second connecting hole 22 in the first direction Y, the larger the tilt angle α1 of the sidewall of the second connecting hole 22, and the larger the size of the second connecting hole 22 on the side away from the semiconductor structure 1; the smaller the distance between the first connecting hole 21 and the second connecting hole 22 in the first direction Y, the smaller the tilt angle α1 of the sidewall of the second connecting hole 22, and the smaller the size of the second connecting hole 22 on the side away from the semiconductor structure 1.

[0043] In this embodiment, when the distance between the first connecting hole 21 and the second connecting hole 22 in the first direction Y is large, the inclination angle α2 of the sidewall of the second connecting hole 22 is increased as much as possible. This allows the second conductive structure 4 to better fill the second connecting hole 22, improving the coverage of the second conductive structure 4 on the sidewall of the second connecting hole 22, thereby improving the filling effect of the second conductive structure 4. Furthermore, the larger distance between the first conductive structure 3 and the second conductive structure 4 avoids the risk of leakage. When the distance between the first connecting hole 21 and the second connecting hole 22 in the first direction Y is small, the inclination angle of the sidewall of the second connecting hole 22 is reduced to prevent the distance between the second connecting hole 22 and the first connecting hole 21 from being too small, thus preventing leakage between the second conductive structure 4 and the first conductive structure 3. The sidewall of the second connecting hole 22 is still inclined, effectively improving the filling effect of the second conductive structure 4.

[0044] In some embodiments, the inclination angle a1 of the sidewall of the first connecting hole 21 is greater than or equal to 40° and less than or equal to 75°. The inclination angle a2 of the sidewall of the second connecting hole 22 is greater than or equal to 40° and less than or equal to 75°. The inclination angle a1 of the sidewall of the first connecting hole 21 and the inclination angle a2 of the sidewall of the second connecting hole 22 may be the same or different.

[0045] In this embodiment, the inclination angles of the sidewalls of the first connecting hole 21 and the second connecting hole 22 are respectively set within the above-mentioned range. This can prevent leakage between the first conductive structure 3 and the second conductive structure 4 while improving the filling effect of the first connecting hole 21 and the second connecting hole 22, thereby improving the reliability and stability of the semiconductor device.

[0046] It should be noted that during the fabrication process, the first connecting hole 21 and the second connecting hole 22 are formed by etching the dielectric layer 2. The tilt angle of the sidewalls of the first connecting hole 21 and the second connecting hole 22 is positively correlated with the etching rate of the dielectric layer 2, and the etching rate of the dielectric layer 2 is positively correlated with the etching temperature. By adjusting the etching temperature, the etching rate is adjusted, thereby adjusting the tilt angle of the sidewalls of the first connecting hole 21 and the second connecting hole 22 to meet the aforementioned range requirements.

[0047] When the inclination angle α1 of the sidewall of the first connecting hole 21 is the same as the inclination angle α2 of the sidewall of the second connecting hole 22, the first connecting hole 21 and the second connecting hole 22 can be simultaneously etched in the dielectric layer 2. When the inclination angle α1 of the sidewall of the first connecting hole 21 is different from the inclination angle α2 of the sidewall of the second connecting hole 22, the first connecting hole 21 and the second connecting hole 22 can be sequentially formed in the dielectric layer 2.

[0048] In some embodiments, such as Figure 1As shown, when the second conductive structure 4 fills the second connection hole 22, the second conductive structure 4 may include a second adhesive layer 41 and a second metal layer 42. The second adhesive layer 41 covers the surface of the second connection hole 22 (including the sidewalls and bottom of the second connection hole 22), and the second metal layer 42 fills the second connection hole 22. The material of the second adhesive layer 41 may include TiN, etc., and the material of the second metal layer 42 may include metals such as aluminum, copper, and nickel.

[0049] The second adhesive layer 41 and the first adhesive layer 31 can be disposed in the same layer, that is, the second adhesive layer 41 and the first adhesive layer 31 can be formed in the same process. The second metal layer 42 and the first metal layer 32 can be disposed in the same layer, that is, the second metal layer 42 and the first metal layer 32 can be formed in the same process.

[0050] In this embodiment, the sidewall of the second connecting hole 22 is inclined in a direction away from the second connecting hole 22, which can improve the coverage of the second adhesive layer 41 on the sidewall of the second connecting hole 22, improve the filling of the second metal layer 42 in the second connecting hole 22, and thus improve the filling effect of the second conductive structure 4 in the second connecting hole 22.

[0051] In some embodiments, such as Figure 1 As shown, the semiconductor structure 1 includes a semiconductor body 10, a gate structure 12, and an insulating layer 11. The semiconductor body 10 includes a first surface and a second surface disposed opposite to each other in the thickness direction X. The gate structure 12 is located on the side of the semiconductor body 10 near the first surface, or the gate structure 12 extends from the first surface into the semiconductor body 10. The insulating layer 11 is located between the gate structure 12 and the semiconductor body 10. A dielectric layer 2 covers the gate structure 12, and a first conductive structure 3 and a second conductive structure 4 are respectively connected to the gate structure 12.

[0052] The first conductive structure 3 and the second conductive structure 4 may each include a gate connection structure to lead out the gate structure 12 and connect it to other conductive structures.

[0053] In some embodiments, such as Figure 2 As shown, the second conductive structure 4 is located on the side of the semiconductor structure 1 near the dielectric layer 2, and the dielectric layer 2 covers both the second conductive structure 4 and the semiconductor structure 1. An insulating layer 11 may be disposed between the second conductive structure 4 and the semiconductor structure 1 to isolate them. The dielectric layer 2 covers the remaining upper surface of both the second conductive structure 4 and the semiconductor structure 1. The position of the first connecting hole 21 corresponds to the position of the remaining upper surface of the semiconductor structure 1, allowing the first conductive structure 3 in the first connecting hole 21 to be electrically connected to the semiconductor structure 1.

[0054] In some embodiments, the inclination angle α1 of the sidewall of the first connection hole 21 is greater than 0° and less than or equal to 25°. When the dielectric layer 2 covers the second conductive structure 4, the distance between the second conductive structure 4 and the first connection hole 21 in the first direction Y is small, which can appropriately reduce the inclination angle α1 of the sidewall of the first connection hole 21.

[0055] In this embodiment, the tilt angle of the sidewall of the first connecting hole 21 is set within the above range, which can improve the filling effect of the first connecting hole 21 while avoiding leakage between the first conductive structure 3 and the second conductive structure 4, thereby improving the reliability and stability of the semiconductor device.

[0056] In some embodiments, the semiconductor structure 1 includes a semiconductor body, which includes a first surface and a second surface disposed opposite each other in the thickness direction. The semiconductor body also includes a first region located on the first surface. The semiconductor device further includes an insulating layer 11 located on the first surface of the semiconductor body. The second conductive structure 4 includes a gate structure located on the side of the insulating layer 11 opposite to the semiconductor body. A dielectric layer 2 covers the gate structure and the first region, and a first connection hole 21 corresponds to the position of the first region. The first conductive structure 3 includes a source located on the side of the dielectric layer 2 opposite to the semiconductor body and fills the first connection hole 21 to connect with the first region.

[0057] The semiconductor devices described in this application embodiment can be applied to MOSFET power devices.

[0058] The following describes in detail the semiconductor devices provided in the embodiments of this application, taking MOSFET power devices as an example.

[0059] like Figure 3 As shown, a semiconductor device may include a semiconductor body 10, an insulating layer 11, a gate structure 12, a gate connection structure 13, a dielectric layer 2, a source 15, and a drain 16.

[0060] The semiconductor body 10 includes a first surface S1 and a second surface S2 disposed opposite to each other in the thickness direction X. The semiconductor body 10 may include a substrate 101 and a semiconductor epitaxial layer 102 located on one side of the substrate 101 in the thickness direction X. The second surface S2 is the surface of the substrate 101 away from the semiconductor epitaxial layer 102, and the first surface S1 is the surface of the semiconductor epitaxial layer 102 away from the substrate 101.

[0061] The material of the substrate 101 and the material of the semiconductor epitaxial layer 102 can be the same or different. In some embodiments, both the material of the semiconductor epitaxial layer 102 and the material of the substrate 101 can be SiC, and the semiconductor device can be a planar SiC power device, a trench SiC power device, or other SiC semiconductor devices. SiC has excellent physical and electrical properties. Compared with silicon, SiC has a larger bandgap and advantages such as high breakdown electric field, high thermal conductivity, high electron saturation velocity, and strong radiation resistance. Therefore, semiconductor devices made of SiC can not only operate stably at higher temperatures, but are also suitable for high-voltage and high-frequency applications.

[0062] The semiconductor epitaxial layer 102 includes a well region 103, a first region 104, and a second region 105. The well region 103 extends from the first surface S1 into the semiconductor epitaxial layer 102. The first region 104 and the second region 105 extend from the first surface S1 into the well region 103, respectively.

[0063] The substrate 101, the semiconductor epitaxial layer 102, and the second region 105 are of the first conductivity type, while the well region 103 and the first region 104 are of the second conductivity type. The first conductivity type and the second conductivity type are opposite. One of the first conductivity type and the second conductivity type is P-type, and the other is N-type.

[0064] As an example, substrate 101 is an N-type substrate, semiconductor epitaxial layer 102 is an N-type epitaxial layer, and well region 103 is a P-type well region (PW). Second region 105 is an N-type doped region, also known as an N+ contact region, used as a source region. First region 104 is a P-type doped region, also known as a P+ contact region, used to provide potential for well region 103.

[0065] The insulating layer 11 may be located on the first surface S1 of the semiconductor body 10, and the insulating layer 11 does not cover the first region 104, that is, the orthogonal projection of the insulating layer 11 on the semiconductor body 10 does not overlap with the first region 104, and the gate structure 12 is located on the side of the insulating layer 11 away from the semiconductor body 10. Alternatively, the semiconductor epitaxial layer 102 may have a gate trench extending from the first surface S1 into the semiconductor epitaxial layer 102, the insulating layer 11 covering the surface of the gate trench, and the gate structure 12 filling the gate trench.

[0066] The insulating layer 11 is used to insulate the gate structure 12 from the semiconductor epitaxial layer 102. The material of the insulating layer 11 may include silicon oxide, etc., and the material of the gate structure 12 may include polysilicon, etc.

[0067] The dielectric layer 2 covers the gate structure 12 and the remaining first surface of the semiconductor body 10. The dielectric layer 2 has a first contact hole 141 and a second contact hole 142 penetrating through it. The first contact hole 141 corresponds to the position of the gate structure 12, and a gate connection structure 13 fills the first contact hole 141 and connects to the gate structure 12. There can be one or more first contact holes 141, spaced apart along a first direction Y. There can also be one or more gate connection structures 13, each corresponding to a different first contact hole 141 and connected to the gate structure 12. The second contact hole 142 corresponds to the position of the first region 104, and a source 15 is located on the side of the dielectric layer 2 away from the semiconductor body 10, filling the second contact hole 142 and connecting to the first region 104. The drain 16 is located on the second surface S2 of the semiconductor body 10.

[0068] The dielectric layer 2 is used to insulate the gate structure 12 from the source 15. The material of the dielectric layer 2 may include silicon oxide, etc., and the gate connection structure 13, the source 15 and the drain 16 may each include metals such as aluminum, copper, and nickel.

[0069] In some embodiments, the semiconductor structure 1 includes a semiconductor body 10, a gate structure 12, and an insulating layer 11. The gate structure 12 is located on the side of the semiconductor body 10 near the first surface S1, or the gate structure 12 extends from the first surface S1 into the semiconductor body 10. The insulating layer 11 is located between the gate structure 12 and the semiconductor body 10. A dielectric layer 2 covers the gate structure 12, and a first connection hole 21 and a second connection hole 22 are provided in the dielectric layer 2. A first conductive structure 3 fills the first connection hole 21 and is connected to the gate structure 12, and a second conductive structure 4 fills the second connection hole 21 and is connected to the gate structure 12. The first connection hole 12 and the second connection hole 22 respectively include the aforementioned first contact hole 141, and the first conductive structure 3 and the second conductive structure 4 respectively include the aforementioned gate connection structure 13.

[0070] The inclination angle of the sidewall of the first contact hole 141 can be greater than or equal to 40° and less than or equal to 75°.

[0071] In this embodiment, as Figure 3 As shown, the sidewall of the first contact hole 141 is inclined in a direction away from the first contact hole 141. The inclination angle of the sidewall of the first contact hole 141 is positively correlated with the distance between two adjacent first contact holes 141 in the first direction Y. This is to avoid leakage of adjacent gate connection structures 13 while improving the filling effect of the gate connection structure 13 in the first contact hole 141, thereby improving the reliability and stability of the semiconductor device.

[0072] In some embodiments, the semiconductor structure 1 includes a semiconductor body 10, which includes a first region 104 located on a first surface S1. The second conductive structure 4 includes a gate structure 12 located on the side of the semiconductor body 10 closest to the first surface S1, with an insulating layer 11 between the gate structure 12 and the semiconductor body 10. A dielectric layer 2 covers the gate structure 12 and the first region 104, and a first connection hole 21 corresponds to the position of the first region 104. The first connection hole 21 includes the aforementioned second contact hole 142. The first conductive structure 3 includes a source 15 located on the side of the dielectric layer 2 away from the semiconductor body 10 and filling the second contact hole 142, connecting to the first region 104.

[0073] In this embodiment, as Figure 3 As shown, the sidewall of the second contact hole 142 is inclined in a direction away from the second contact hole 142. The inclination angle of the sidewall of the second contact hole 142 is positively correlated with the distance between the second contact hole 142 and the gate structure 12 in the first direction Y. This is to avoid leakage between the source 15 and the gate structure 12 while improving the filling effect of the source 15 in the second contact hole 142, thereby improving the reliability and stability of the semiconductor device.

[0074] The inclination angle of the sidewall of the second contact hole 142 can be greater than 0° and less than or equal to 25°.

[0075] According to the semiconductor device provided in the embodiments of this application, the sidewall of the first connection hole 21 is inclined in a direction away from the first connection hole 21, and the inclination angle α1 of the sidewall of the first connection hole 21 is positively correlated with the distance between the first connection hole 21 and the second conductive structure 4 in the first direction Y. When the distance between the first connection hole 21 and the second conductive structure 4 in the first direction Y is large, the inclination angle α1 of the sidewall of the first connection hole 21 is increased as much as possible to facilitate the filling of the first conductive structure 3 and improve the filling effect of the first conductive structure 3. When the distance between the first connection hole 21 and the second conductive structure 4 in the first direction Y is small, the inclination angle α1 of the sidewall of the first connection hole 21 is reduced to avoid the distance between the second conductive structure 4 and the sidewall of the first connection hole 21 being too small, thereby avoiding leakage between the second conductive structure 4 and the first conductive structure 3 and effectively improving the reliability and stability of the semiconductor device.

[0076] Accordingly, this application also provides a method for fabricating a semiconductor device.

[0077] Figure 4 This is a schematic flowchart illustrating the method for fabricating a semiconductor device provided in an embodiment of this application.

[0078] like Figure 4As shown, the method for fabricating a semiconductor device provided in this application includes steps S110 to S130.

[0079] Step S110: Form a semiconductor structure, a dielectric layer, and a second conductive structure, wherein the dielectric layer and the second conductive structure are located on the same side of the thickness direction of the semiconductor structure.

[0080] First, a semiconductor structure is formed, followed by the formation of a dielectric layer and a second conductive structure. The formation of the second conductive structure can occur after or before the formation of the dielectric layer.

[0081] As an example, the formation step of the second conductive structure precedes the formation step of the dielectric layer. (Combined) Figure 2 As shown, an insulating layer 11 and a second conductive structure 4 are first formed sequentially on one side of the semiconductor structure 1 in the thickness direction X, and then a dielectric layer 2 covering the second conductive structure 4 and the semiconductor structure 1 is formed. Figure 3 As shown, the semiconductor structure 1 may include a semiconductor body 10, which may include a substrate 101 and a semiconductor epitaxial layer 102 located on one side of the substrate 101 in the thickness direction X. The semiconductor epitaxial layer 102 includes a first region 104. The second conductive structure 4 may include a gate structure 12 located on the side of the semiconductor epitaxial layer 102 facing away from the substrate 101, and an insulating layer 11 located between the gate structure 12 and the semiconductor epitaxial layer 102.

[0082] Step S120: Form a first connection hole penetrating the dielectric layer. The sidewall of the first connection hole is inclined in a direction away from the first connection hole, and the first connection hole and the second conductive structure are spaced apart along a first direction, which is perpendicular to the thickness direction. The inclination angle of the sidewall of the first connection hole is positively correlated with the distance between the first connection hole and the second conductive structure in the first direction, and the inclination angle is the angle between the sidewall and the thickness direction.

[0083] Combination Figure 2 As shown, an etching process is used to form a first interconnect 21 in the dielectric layer 2, exposing the semiconductor structure 1. Combined with... Figure 3 As shown, the first connection hole 2 may include a second contact hole 142, which exposes the first area 104.

[0084] The first connecting hole 21 and the second conductive structure 4 are spaced apart in the first direction Y. The larger the distance between the first connecting hole 21 and the second conductive structure 4 in the first direction Y, the larger the inclination angle a1 of the sidewall of the first connecting hole 21 and the larger the size of the first connecting hole 21 away from the semiconductor structure 1. The smaller the distance between the first connecting hole 21 and the second conductive structure 4 in the first direction Y, the smaller the inclination angle a1 of the sidewall of the first connecting hole 21 and the smaller the size of the first connecting hole 21 away from the semiconductor structure 1.

[0085] Step S130: Fill the first conductive structure into the first connection hole, and electrically connect the first conductive structure to the semiconductor structure.

[0086] Combination Figure 2 As shown, a thin-film deposition process is used to fill the first connecting hole 21 with a first conductive structure 3. The first conductive structure 3 may only fill the first connecting hole 21. Alternatively, the first conductive structure 3 may be located on the side of the dielectric layer 2 facing away from the semiconductor structure 1 and filled in the first connecting hole 21 for electrical connection with the semiconductor structure 1. Figure 3 As shown, the first connection hole 2 may include a second contact hole 142, and the first conductive structure 3 may include a source electrode 15. The source electrode 15 is located on the side of the dielectric layer 2 away from the semiconductor structure 1 and fills the second contact hole 142 and is connected to the first region 104.

[0087] In this embodiment, when the distance between the first connecting hole 21 and the second conductive structure 4 in the first direction Y is large, the tilt angle α1 of the sidewall of the first connecting hole 21 is increased as much as possible. This allows the first conductive structure 3 to better fill the first connecting hole 21, improving the coverage of the sidewall of the first connecting hole 21 by the first conductive structure 3, thereby improving the filling effect of the first conductive structure 3. Furthermore, the larger distance between the first conductive structure 3 and the second conductive structure 4 avoids the risk of leakage. When the distance between the first connecting hole 21 and the second conductive structure 4 in the first direction Y is small, the tilt angle of the sidewall of the first connecting hole 21 is reduced to prevent the distance between the second conductive structure 4 and the sidewall of the first connecting hole 21 from being too small, thus preventing leakage between the second conductive structure 4 and the first conductive structure 3. The sidewall of the first connecting hole 21 is still tilted, effectively improving the filling effect of the first conductive structure 3.

[0088] As another example, the formation step of the second conductive structure follows the formation step of the dielectric layer. Figure 5As shown, a semiconductor structure 1 is first formed, and then a dielectric layer 2 is formed on one side of the semiconductor structure 1 in the thickness direction X using a thin film deposition process. A second conductive structure is formed in a subsequent process. The semiconductor structure 1 may include a semiconductor body 10, an insulating layer 11, and a gate structure 12. The semiconductor body 10 may include a substrate 101 and a semiconductor epitaxial layer 102 located on one side of the substrate 101 in the thickness direction X. The insulating layer 11 is located on the side of the semiconductor epitaxial layer 102 opposite to the substrate 101, and the gate structure 12 is located on the side of the insulating layer 11 opposite to the semiconductor epitaxial layer 101. The dielectric layer 2 covers the gate structure 12. Figure 3 As shown, the dielectric layer 2 can also cover the semiconductor epitaxial layer 102.

[0089] Then, a first connection hole 21 is formed that penetrates the dielectric layer 2.

[0090] In some embodiments, forming a first connection hole through the dielectric layer includes: A mask layer with mask openings is formed on the side of the dielectric layer away from the semiconductor structure; A first connection hole is formed through the mask opening, penetrating the dielectric layer; the orthogonal projection of the mask opening on the semiconductor structure is located on the side of the first connection hole closer to the semiconductor structure and within the orthogonal projection on the semiconductor structure; the size of the side of the first connection hole away from the semiconductor structure is larger than the size of the mask opening. Remove the mask layer.

[0091] Combination Figure 5 As shown, a mask layer 5 is formed on the side of the dielectric layer 2 away from the semiconductor structure 1 using a deposition method, and a mask opening (i.e., the first mask opening 51) is formed in the mask layer 5. The mask layer 5 may include a photoresist layer, and a pattern structure can be etched on the photoresist layer by exposure and development to form the opening.

[0092] Then, combine Figure 6 As shown, a wet etching process is used to etch the dielectric layer 2 through the first mask opening 51 to form a first connection hole 21 that penetrates the dielectric layer 2.

[0093] Because wet etching is isotropic, while etching the dielectric layer 2 along the thickness direction X through the first mask opening 51, it also etches along the first direction Y, causing the first connection hole 21 formed by the etching to tilt in a direction away from the first connection hole 21. Furthermore, the orthographic projection of the first mask opening 51 onto the semiconductor structure 1 lies within the orthographic projection of the first connection hole 21 on the side of the first connection hole 21 closest to the semiconductor structure 1. The size of the side of the first connection hole 21 closest to the semiconductor structure 1 is greater than or equal to the size of the first mask opening 51, and the size of the side of the first connection hole 21 away from the semiconductor structure 1 is greater than the size of the first mask opening 51.

[0094] It should be noted that the mask layer 5 may also have a second mask opening 52. While forming the first connecting hole 21 penetrating the dielectric layer 2 through the first mask opening 51, a wet etching process is used to etch the dielectric layer 2 through the second mask opening 52 to form a second connecting hole 22 penetrating the dielectric layer 2. The second connecting hole 22 is formed simultaneously with the first connecting hole 21, and the morphology of the second connecting hole 22 and the first connecting hole 21 may be the same.

[0095] The morphology of the second connecting hole 22 can also be different from that of the first connecting hole 21. The first connecting hole 21 and the second connecting hole 22 can be formed sequentially in the dielectric layer 2 using two mask layers. The second connecting hole 22 is inclined in a direction away from the semiconductor structure 1. Furthermore, the orthographic projection of the second mask opening 52 onto the semiconductor structure 1 is located within the orthographic projection of the second connecting hole 22 on the side closest to the semiconductor structure 1. The size of the second connecting hole 22 on the side closest to the semiconductor structure 1 is greater than or equal to the size of the second mask opening 52, and the size of the second connecting hole 22 on the side away from the semiconductor structure 1 is greater than the size of the second mask opening 52.

[0096] The inclination angle of the sidewall of the first connecting hole 21 is positively correlated with the distance between the first mask opening 51 and the second mask opening 52 in the first direction Y, such that the inclination angle of the sidewall of the first connecting hole 21 is positively correlated with the distance between the first connecting hole 21 and the second connecting hole 22 in the first direction Y. Similarly, the inclination angle of the sidewall of the second connecting hole 22 is positively correlated with the distance between the first mask opening 51 and the second mask opening 52 in the first direction Y, such that the inclination angle of the sidewall of the second connecting hole 22 is positively correlated with the distance between the first connecting hole 21 and the second connecting hole 22 in the first direction Y.

[0097] The inclination angle of the sidewall of the first connecting hole 21 should not be too large or too small. If the inclination angle of the sidewall of the first connecting hole 21 is too large, it may lead to insufficient spacing between some conductive structures, posing a risk of leakage. If the inclination angle of the sidewall of the first connecting hole 21 is too small, it may lead to poor filling effect of the first connecting hole 21. In this embodiment, the inclination angle of the sidewall of the first connecting hole 21 can be set according to the spacing between the first connecting hole 21 and the second connecting hole 22, so as to improve the filling effect of the first connecting hole 21 while avoiding the risk of leakage. Similarly, the inclination angle of the sidewall of the second connecting hole 22 can also be set according to the spacing between the first connecting hole 21 and the second connecting hole 22, so as to improve the filling effect of the second connecting hole 22 while avoiding the risk of leakage.

[0098] In some embodiments, forming a first connection hole through the dielectric layer includes: Determine the target tilt angle required to form on the sidewall of the first connecting hole; Based on the relationship between the tilt angle of the first connecting hole sidewall and the etching rate of the dielectric layer, the target etching rate corresponding to the target tilt angle is determined. Based on the relationship between the etching rate and etching temperature of the dielectric layer, the target etching temperature corresponding to the target etching rate is determined. At the target etching temperature, a wet etching process is used to form a first connecting hole penetrating the dielectric layer in the dielectric layer at the target etching rate. The tilt angle of the sidewall of the first connecting hole is the target tilt angle.

[0099] The tilt angle of the via sidewall is related to the etching rate of the dielectric layer, which in turn is related to the etching temperature. Furthermore, the etching rate varies depending on the dielectric layer material. Therefore, for dielectric layers of different materials, we collected the etching rates of the dielectric layers at different temperatures and the tilt angles of the via sidewalls at different etching rates. We established a database to construct the correlation between etching rate and etching temperature for various dielectric layer materials, as well as the correlation between etching rate and tilt angle of the via sidewalls.

[0100] When forming the first connecting hole 21, the required tilt angle of the sidewall of the first connecting hole 21 is first determined as the target tilt angle. Setting the tilt angle of the sidewall of the first connecting hole 21 as the target angle avoids the risk of leakage current and improves the filling effect of the first connecting hole 21. Based on the material of the dielectric layer 2, the corresponding relationship between the etching rate and the tilt angle of the connecting hole sidewall is looked up to quickly determine the target etching rate corresponding to the target tilt angle. Then, the corresponding relationship between the etching rate and the etching temperature is looked up to quickly determine the target etching temperature corresponding to the target etching rate.

[0101] By adjusting the etching temperature of the etching machine to the target etching temperature, the dielectric layer 2 can be etched at the target etching rate. The tilt angle of the sidewall of the first connecting hole 21 formed by the etching is the target etching angle. For example, if the target etching angle is 75°, the target etching temperature is determined to be 55°. At an etching temperature of 55°, BOE etching solution is used to etch the dielectric layer 2 for 200 seconds, resulting in a tilt angle of 75° for the sidewall of the first connecting hole 21.

[0102] If a second connection hole 22 is also provided in the dielectric layer 2, similarly, the etching temperature for etching the second connection hole 22 can be determined by the same method described above, based on the required tilt angle of the sidewall of the second connection hole 22, so that the dielectric layer 2 can be etched based on the etching temperature.

[0103] In some embodiments, the tilt angle of the sidewall of the first connection hole 21 is positively correlated with the etching rate of the dielectric layer 2, and the etching rate of the dielectric layer 21 is positively correlated with the etching temperature.

[0104] For example, the dielectric layer is made of PEOX (polyethylene oxide), and the etching solution is BOE (buffered oxide etching solution, which is a mixture of hydrofluoric acid aqueous solution and ammonium fluoride aqueous solution in a ratio of 1:7). Within the etching temperature range of 25℃ to 60℃, the etching temperature is adjusted sequentially, the etching rate of the dielectric layer is collected, and the tilt angle of the sidewall of the connecting hole is also collected, as shown in Table 1.

[0105]

[0106] Table 1 Based on Table 1, establish the correlation curve between etching rate and etching temperature, such as... Figure 7 As shown, a curve relating etching rate to tilt angle is established, as follows. Figure 8 As shown, it can be seen that the higher the etching temperature, the higher the etching rate, and the larger the tilt angle of the connecting hole sidewall; the lower the etching temperature, the lower the etching rate, and the smaller the tilt angle of the connecting hole sidewall.

[0107] After determining the required tilt angle of the connector hole sidewall, the etching temperature is set according to the above correspondence to ensure that the tilt angle of the connector hole sidewall meets the requirements.

[0108] This embodiment uses a wet etching process to form connection holes in the dielectric layer 2 by setting the etching temperature. The etching effect is good, the cost of WET batch etching is lower, and the WPH (wafer throughput per hour) is higher.

[0109] After forming the first connection hole 21 in the dielectric layer 2, the bonding Figure 1 As shown, a first conductive structure 3 is filled in the first connection hole 21, and the first conductive structure 3 is electrically connected to the semiconductor structure 1. If a second connection hole 22 is also present in the dielectric layer 2, a second conductive structure 4 is filled in the second connection hole 22. The first conductive structure 3 and the second conductive structure 4 can be formed simultaneously. Figure 3 As shown, the first connection hole 12 and the second connection hole 22 each include a first contact hole 141, the first conductive structure 3 and the second conductive structure 4 each include a gate connection structure 13, the gate connection structure 13 fills the first contact hole 141 and is connected to the gate structure 12.

[0110] In some embodiments, the orthographic projection of the side of the first connecting hole 21 facing away from the semiconductor structure 1 on the semiconductor structure 1 does not overlap with the orthographic projection of the second conductive structure 4 on the semiconductor structure 1, so as to ensure that the second conductive structure 4 and the sidewall of the first connecting hole 21 have a certain distance, and to avoid leakage between the second conductive structure 4 and the first conductive structure 1.

[0111] In some embodiments, such as Figure 1 and Figure 2As shown, the first conductive structure 3 includes an adhesive layer (i.e., the first adhesive layer 31) and a metal layer (i.e., the first metal layer 32). The first adhesive layer 31 covers the surface of the first connection hole 21 (including the sidewalls and bottom of the first connection hole 21), and the first metal layer 32 fills the first connection hole 21. The material of the first adhesive layer 31 may include TiN, etc., and the material of the first metal layer 32 may include metals such as aluminum, copper, and nickel.

[0112] According to the semiconductor device fabrication method provided in this application embodiment, the sidewall of the first connection hole 21 is inclined in a direction away from the first connection hole 21, and the inclination angle α1 of the sidewall of the first connection hole 21 is positively correlated with the distance between the first connection hole 21 and the second conductive structure 4 in the first direction Y. When the distance between the first connection hole 21 and the second conductive structure 4 in the first direction Y is large, the inclination angle α1 of the sidewall of the first connection hole 21 is increased as much as possible to facilitate the filling of the first conductive structure 3 and improve the filling effect of the first conductive structure 3. When the distance between the first connection hole 21 and the second conductive structure 4 in the first direction Y is small, the inclination angle α1 of the sidewall of the first connection hole 21 is reduced to avoid the distance between the second conductive structure 4 and the sidewall of the first connection hole 21 being too small, thereby avoiding leakage between the second conductive structure 4 and the first conductive structure 3, and effectively improving the reliability and stability of the semiconductor device. Moreover, by setting the etching temperature, the first connection hole 21 is formed in the dielectric layer 2 using a wet etching process, resulting in good etching effect, lower WET batch etching cost, and higher WPH (wafer throughput per hour).

[0113] Accordingly, this application also provides a power module. The power module includes a substrate and the semiconductor device from any of the above embodiments, wherein the substrate is used to support the semiconductor device.

[0114] For example, a power module can be used as one of a power amplifier, power converter, power controller, power management module, or power regulator. A power amplifier amplifies the power of an electrical signal. A power converter converts electrical energy from one form to another; for example, a power converter can be an AC / DC converter or a DC / DC converter. A power controller is a device for controlling the flow of power. A power management module manages the power supply, ensuring that power is stably and efficiently distributed to different parts of an electronic device. A power regulator adjusts the power output to meet the needs of a specific application.

[0115] On the other hand, embodiments of this application also provide a power conversion circuit. The power conversion circuit includes a circuit board and the semiconductor device in any of the above embodiments. The semiconductor device is electrically connected to the circuit board, and the power conversion circuit can be used for current conversion, voltage conversion, or power factor correction.

[0116] For example, the power conversion circuit can be used as one of an AC / DC converter, an AC / AC converter, a DC / DC converter, a DC / AC inverter, or a power factor correction (PFC) circuit, wherein the AC / DC converter is used to convert alternating current to direct current, the AC / AC converter is used to convert alternating current to alternating current, the DC / DC converter is used to convert direct current to direct current, the DC / AC inverter is used to convert direct current to alternating current, and the power factor correction circuit is used to improve the power factor of the power supply and reduce harmonic pollution of the power grid.

[0117] On the other hand, embodiments of this application also provide a vehicle. The vehicle includes a load and the power conversion circuit described in the above embodiments. The power conversion circuit is used to convert alternating current to direct current, convert alternating current to alternating current, convert direct current to direct current, or convert direct current to alternating current and then input the converted direct current to the load to supply power to the load.

[0118] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and are not used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and are not limited in number; for example, a first object can be one or more.

[0119] In the description of this application, "multiple" means two or more.

[0120] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0121] Although embodiments of this application have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of this application, the scope of which is defined by the claims and their equivalents.

Claims

1. A semiconductor device, characterized in that, include: Semiconductor structure; A dielectric layer is located on one side of the semiconductor structure in the thickness direction. A first connection hole is provided in the dielectric layer, and the sidewall of the first connection hole is inclined in the direction away from the first connection hole. A first conductive structure is filled in the first connection hole and electrically connected to the semiconductor structure; The second conductive structure is located on one side of the semiconductor structure in the thickness direction and is spaced apart from the first connecting hole along a first direction, the first direction being perpendicular to the thickness direction; The inclination angle of the sidewall of the first connection hole is positively correlated with the distance between the first connection hole and the second conductive structure in the first direction, and the inclination angle is the angle between the sidewall and the thickness direction.

2. The semiconductor device according to claim 1, characterized in that, The orthographic projection of the side of the first connecting hole away from the semiconductor structure onto the semiconductor structure does not overlap with the orthographic projection of the second conductive structure onto the semiconductor structure.

3. The semiconductor device according to claim 1, characterized in that, The dielectric layer is further provided with a second connecting hole that penetrates the dielectric layer, and the sidewall of the second connecting hole is inclined in a direction away from the second connecting hole; The second conductive structure fills the second connection hole and is electrically connected to the semiconductor structure.

4. The semiconductor device according to claim 3, characterized in that, The inclination angle of the sidewall of the second connecting hole is positively correlated with the distance between the first connecting hole and the second connecting hole in the first direction.

5. The semiconductor device according to claim 4, characterized in that, The inclination angle of the first connecting hole sidewall and the inclination angle of the second connecting hole sidewall are both greater than or equal to 40° and less than or equal to 75°.

6. The semiconductor device according to claim 3, characterized in that, The semiconductor structure includes: The semiconductor body includes a first surface and a second surface disposed opposite to each other in the thickness direction; The gate structure is located on the side of the semiconductor body near the first surface, or extends from the first surface into the semiconductor body; An insulating layer is located between the gate structure and the semiconductor body; The dielectric layer covers the gate structure, and the first conductive structure and the second conductive structure are respectively connected to the gate structure.

7. The semiconductor device according to claim 1, characterized in that, The second conductive structure is located on the side of the semiconductor structure close to the dielectric layer, and the dielectric layer covers the second conductive structure and the semiconductor structure.

8. The semiconductor device according to claim 7, characterized in that, The semiconductor structure includes: A semiconductor body includes a first surface and a second surface disposed opposite to each other in the thickness direction, and the semiconductor body further includes a first region located on the first surface; The semiconductor device further includes: An insulating layer is located on the first surface of the semiconductor body; The second conductive structure includes a gate structure located on the side of the insulating layer opposite to the semiconductor body; the dielectric layer covers the gate structure and the first region, and the first connection hole corresponds to the position of the first region; The first conductive structure includes a source electrode located on the side of the dielectric layer opposite to the semiconductor body and filling the first connection hole to connect with the first region.

9. The semiconductor device according to claim 7, characterized in that, The inclination angle of the sidewall of the first connecting hole is greater than 0° and less than or equal to 25°.

10. The semiconductor device according to any one of claims 1-9, characterized in that, The first conductive structure includes: An adhesive layer covers the surface of the first connection hole; A metal layer is filled in the first connection hole.

11. A method for fabricating a semiconductor device, characterized in that, The method includes: A semiconductor structure, a dielectric layer, and a second conductive structure are formed, wherein the dielectric layer and the second conductive structure are located on the same side of the thickness direction of the semiconductor structure; A first connection hole is formed penetrating the dielectric layer. The sidewall of the first connection hole is inclined in a direction away from the first connection hole, and the first connection hole and the second conductive structure are spaced apart along a first direction, which is perpendicular to the thickness direction. The inclination angle of the sidewall of the first connection hole is positively correlated with the distance between the first connection hole and the second conductive structure in the first direction, and the inclination angle is the angle between the sidewall and the thickness direction. A first conductive structure is filled into the first connection hole, and the first conductive structure is electrically connected to the semiconductor structure.

12. The method for fabricating a semiconductor device according to claim 11, characterized in that, The formation of the first connection hole penetrating the dielectric layer includes: A mask layer with a mask opening is formed on the side of the dielectric layer opposite to the semiconductor structure; A first connection hole is formed through the mask opening, penetrating the dielectric layer; the orthographic projection of the mask opening on the semiconductor structure is located within the orthographic projection of the side of the first connection hole closest to the semiconductor structure on the semiconductor structure, and the size of the side of the first connection hole opposite to the semiconductor structure is larger than the size of the mask opening; Remove the mask layer.

13. The method for fabricating a semiconductor device according to claim 11, characterized in that, The formation of the first connection hole penetrating the dielectric layer includes: Determine the target tilt angle that the sidewall of the first connecting hole needs to form; Based on the relationship between the tilt angle of the first connection hole sidewall and the etching rate of the dielectric layer, the target etching rate corresponding to the target tilt angle is determined. Based on the relationship between the etching rate and etching temperature of the dielectric layer, the target etching temperature corresponding to the target etching rate is determined; At the target etching temperature, a wet etching process is used to form a first connection hole penetrating the dielectric layer in the dielectric layer at the target etching rate, and the tilt angle of the sidewall of the first connection hole is the target tilt angle.

14. The method for fabricating a semiconductor device according to claim 13, characterized in that, The tilt angle of the first connection hole sidewall is positively correlated with the etching rate of the dielectric layer, and the etching rate of the dielectric layer is positively correlated with the etching temperature.

15. A power module, characterized in that, Including a substrate and as claimed in claim 1 10. The semiconductor device described in any one of the claims, wherein the substrate is used to support the semiconductor device.

16. A power conversion circuit, characterized in that, The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and as claimed in claim 1. The semiconductor device of the 10th embodiment is electrically connected to the circuit board.

17. A vehicle, characterized in that, The device includes a load and a power conversion circuit as described in claim 16, the power conversion circuit being used to convert AC power to DC power, convert AC power to AC power, convert DC power to DC power, or convert DC power to AC power and then input it to the load.

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