Method of reducing fill trench aspect ratio
By depositing a cobalt protective layer on the surface of tungsten vias and removing the TiN hard mask layer, the trench aspect ratio is reduced, solving the filling defect problem caused by the TiN hard mask and improving the yield and reliability of semiconductor interconnects.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHANGHAI HUALI INTEGRATED CIRCUIT CORP
- Filing Date
- 2026-02-27
- Publication Date
- 2026-05-29
AI Technical Summary
In the prior art, the presence of TiN hard masks results in excessively high trench aspect ratios, leading to metal layer filling defects and affecting interconnect yield and reliability.
A cobalt protective layer is deposited on the surface of the tungsten via, and the TiN hard mask layer is removed by chemical methods to protect the tungsten via from damage, reduce the trench aspect ratio, and widen the filling window.
By reducing the trench depth-to-width ratio, filling defects are reduced, and product yield is improved.
Smart Images
Figure CN122121650A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a method for reducing the aspect ratio of filled trenches. Background Technology
[0002] In the back-end processes of integrated circuit manufacturing, metal interconnects are typically achieved using the damascus process. This process first etches trenches and / or vias in the interlayer dielectric layer, then deposits a diffusion barrier layer and a seed layer (B / S) in sequence, and finally fills the metal interconnects with copper (Cu) through electrochemical plating (ECP).
[0003] The filling capacity of the trench is highly dependent on its aspect ratio, which is the ratio of the trench's depth to its width before filling. The trench width is determined by the circuit design, while the depth is mainly determined by the thickness of the dielectric stack layer that forms the trench sidewalls. This stack layer typically includes a low-k dielectric material, a nitrogen-free anti-reflective coating (N-free DARC), and a titanium nitride (TiN) hard mask film on top.
[0004] Due to the presence of the TiN hard mask, the aspect ratio of the trench is increased before B / S deposition. The higher aspect ratio affects the filling window of subsequent B / S and ECP processes, making the metal layer more prone to filling defects, which affects the interconnect yield and reliability.
[0005] Therefore, there is an urgent need for a new method to effectively remove the TiN hard mask from the trench sidewalls in order to reduce its aspect ratio and improve the copper filling effect. Summary of the Invention
[0006] The purpose of this invention is to provide a method for reducing the depth-to-width ratio of filling trenches, so as to solve the problem that high depth-to-width ratios of existing trenches easily lead to filling defects.
[0007] To solve the above-mentioned technical problems, the present invention provides a method for reducing the depth-to-width ratio of filling trenches, comprising the following steps:
[0008] A substrate is provided, on which a first interlayer dielectric layer is formed, and tungsten vias are formed in the first interlayer dielectric layer;
[0009] A second interlayer dielectric layer and a TiN hard mask layer are sequentially formed on the first interlayer dielectric layer;
[0010] A patterned photoresist layer is formed on the TiN hard mask layer, and the TiN hard mask layer and the second interlayer dielectric layer are etched sequentially to form trenches, the bottom of the trenches exposing the tungsten vias;
[0011] A cobalt protective layer is deposited on the surface of the tungsten through-hole;
[0012] The TiN hard mask layer is cleaned and removed. A diffusion barrier layer and a seed layer are deposited sequentially in the trench, and then metal is filled.
[0013] Optionally, the thickness of the cobalt protective layer is 5~25 Å.
[0014] Optionally, the second interlayer dielectric layer includes a low-K dielectric layer and a nitrogen-free dielectric anti-reflective coating located on the low-K dielectric layer.
[0015] Optionally, before removing the TiN hard mask layer, the method further includes performing chemical mechanical polishing on the TiN hard mask layer.
[0016] Optionally, the polishing thickness of the chemical mechanical polishing is 5~20 Å.
[0017] Optionally, before depositing the cobalt protective layer, the method further includes: wet cleaning the trench.
[0018] Optionally, after performing the wet cleaning step, the method further includes: heat-treating the second interlayer dielectric layer.
[0019] Optionally, the TiN hard mask layer can be removed by wet cleaning, wherein the solution used for wet cleaning is a mixture of hydrogen peroxide and an organic chelating agent.
[0020] Optionally, the metal material filling the trench includes copper.
[0021] The present invention also provides a semiconductor structure formed using the method described in any of the preceding claims.
[0022] In summary, the present invention provides a method and semiconductor structure for reducing the aspect ratio of filled trenches, comprising the following steps: providing a substrate, wherein a first interlayer dielectric layer is formed on the substrate, and a tungsten via is formed in the first interlayer dielectric layer; sequentially forming a second interlayer dielectric layer and a TiN hard mask layer on the first interlayer dielectric layer; forming a patterned photoresist layer on the TiN hard mask layer; sequentially etching the TiN hard mask layer and the second interlayer dielectric layer to form trenches, wherein the bottom of the trenches exposes the tungsten vias; depositing a cobalt protective layer on the surface of the tungsten vias; cleaning and removing the TiN hard mask layer; sequentially depositing a diffusion barrier layer and a seed layer in the trenches; and performing metal filling.
[0023] Compared with the prior art, the technical solution provided by the present invention has the following beneficial effects:
[0024] This invention adds a cobalt protective layer deposition step and a TiN hard mask layer cleaning step before the deposition of the diffusion barrier layer and the seed layer. The cobalt protective layer protects the tungsten vias from damage during the TiN hard mask layer cleaning process. By removing the TiN hard mask layer, the aspect ratio of the trench is reduced, the filling window of the diffusion barrier layer and the seed layer is widened, filling defects are reduced, and product yield is improved. Attached Figure Description
[0025] Figure 1 This is a flowchart illustrating a method for reducing the aspect ratio of a filling trench according to an embodiment of the present invention.
[0026] Figures 2-7 for Figure 1 A structural diagram corresponding to each step in the process;
[0027] 100 - Substrate; 110 - Intermediate layer; 200 - First interlayer dielectric layer; 210 - Tungsten via; 300 - Second interlayer dielectric layer; 310 - Low-K dielectric layer; 320 - Nitrogen-free dielectric anti-reflective coating; 330 - Trench; 400 - TiN hard mask layer; 500 - Cobalt protective layer;
[0028] Those skilled in the art will understand that the accompanying drawings are provided to better understand the invention and do not constitute any limitation on the scope of the invention. Detailed Implementation
[0029] To make the objectives, advantages, and features of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention. Furthermore, the structures shown in the drawings are often part of the actual structure. In particular, different proportions are sometimes used because different drawings need to show different emphases. It should be understood that relative terms such as "above," "below," "top," and "bottom" shown in the drawings can be used to describe the relationships between various elements. These relative terms are intended to cover different orientations of elements other than those depicted in the drawings. For example, if the device is inverted relative to the view in the drawings, an element described as "above" another element will now be below that element. It should also be understood that, unless specifically stated or indicated, the terms "first," "second," "third," etc., in the specification are only used to distinguish the various components, elements, steps, etc., in the specification, and are not used to indicate logical or sequential relationships between the various components, elements, steps, etc.
[0030] In existing process flows, to reduce aspect ratio and widen the process window, an effective method is to remove the TiN hard mask film on the sidewalls via wet cleaning before B / S deposition. Currently, the TiN removal solutions used in the industry (whose main components are generally hydrogen peroxide (H₂O₂) and organic chelates) are chemically inert to cobalt (Co) and copper (Cu). Therefore, in metal layers with through-hole structures, since the bottom of the through-holes is the copper interconnect of the layer above, this solution can be safely used to remove the TiN hard mask.
[0031] However, in the fabrication of the first layer of metal interconnects in the back-end, the metal layer is usually manufactured using a single damask process. The bottom of the trench is connected to a tungsten (W) via formed in the middle process. The TiN removal solution will cause chemical damage to the tungsten. In order to protect the tungsten via, the TiN hard mask film on the sidewall has to be retained in the existing process. This results in an excessively high aspect ratio of the trench. The higher aspect ratio affects the filling window of the subsequent barrier layer, seed layer and electrochemical plating process, making the metal layer more prone to filling defects, which affects the interconnect yield and reliability.
[0032] In view of this, refer to Figure 1 As shown, this embodiment of the invention provides a method for reducing the aspect ratio of filled trenches, which can remove the TiN hard mask layer while protecting the tungsten vias from damage, including the following steps:
[0033] S1, a substrate is provided, on which a first interlayer dielectric layer is formed, and tungsten vias are formed in the first interlayer dielectric layer;
[0034] S2, a second interlayer dielectric layer and a TiN hard mask layer are sequentially formed on the first interlayer dielectric layer;
[0035] S3, a patterned photoresist layer is formed on the TiN hard mask layer, and the TiN hard mask layer and the second interlayer dielectric layer are etched sequentially to form trenches, and the bottom of the trenches exposes the tungsten vias;
[0036] S4, deposit a cobalt protective layer on the surface of the tungsten through-hole;
[0037] S5, clean and remove the TiN hard mask layer, deposit a diffusion barrier layer and a seed layer sequentially in the trench, and then fill with metal.
[0038] By using the method provided in the embodiments of the present invention, a cobalt protective layer is formed on the surface of the tungsten via, which protects the tungsten via from damage when the TiN hard mask layer is removed, reduces the trench aspect ratio, widens the process window for subsequent deposition and filling steps, reduces the generation of filling defects, and thus improves product yield.
[0039] The following combination Figures 2-7The method for reducing the depth-to-width ratio of the filling trench provided in the embodiments of the present invention will be further described.
[0040] refer to Figure 2 As shown, in step S1, a substrate 100 is provided, on which an intermediate layer 110 (which may include a lower metal interconnect structure) is formed. A first interlayer dielectric layer 200 is formed on the intermediate layer 110, and a tungsten via 210 is formed in the first interlayer dielectric layer 200. The tungsten via 210 is used to achieve electrical connection with the lower metal interconnect structure in the intermediate layer 110.
[0041] refer to Figure 3 As shown, in step S2, a low-K dielectric layer 310 and a nitrogen-free dielectric anti-reflective coating 320 are sequentially stacked on the first interlayer dielectric layer 200. The low-K dielectric layer 310 and the nitrogen-free dielectric anti-reflective coating 320 constitute the second interlayer dielectric layer 300. A TiN hard mask layer 400 is formed on the second interlayer dielectric layer 300.
[0042] refer to Figure 4 As shown, in step S3, photoresist is coated on the TiN hard mask layer 400, and then a patterned photoresist layer (not shown) is formed by photolithography. Using the patterned photoresist layer as a mask, the TiN hard mask layer 400 and the second interlayer dielectric layer 300 are etched sequentially to form a trench 330. The etching endpoint is controlled at the surface of the first interlayer dielectric layer 200 so that the bottom of the trench 330 exposes the tungsten via 210. Preferably, after etching the trench 330, the method provided in this embodiment of the invention further includes a wet cleaning step and a heat treatment step. The wet cleaning step is used to wet clean the trench 330 to remove etching residues, and the heat treatment of the second interlayer dielectric layer 300 can remove the moisture remaining from the wet cleaning and restore the low dielectric constant and chemical inertness of the surface of the interlayer dielectric layer.
[0043] refer to Figure 5 As shown, in step S4, a cobalt protective layer 500 is deposited on the surface of the tungsten via 210 exposed at the bottom of the trench 330. Preferably, in this embodiment of the invention, COCO (cobalt hexacarbonylCo2(CO)8) is used as a precursor, and the cobalt protective layer 500 is deposited using chemical vapor deposition. Because COCO is metal-selective, it has strong adsorption on metal surfaces but is difficult to adsorb on dielectric surfaces. Therefore, the COCO selectively adsorbs and decomposes into cobalt atoms on the metal surface (the surface of the tungsten via 210) to form a protective layer, while almost no cobalt is deposited on the surface of the second dielectric layer. Preferably, in this embodiment of the invention, the deposition thickness of the cobalt protective layer 500 is 5~25 Å, which is much smaller than the depth of the trench 330.
[0044] In this embodiment of the invention, during the deposition of the cobalt protective layer 500, a small amount of cobalt may be present on the surface of the TiN hard mask layer 400, as referenced. Figure 6 As shown, as a preferred embodiment, in order to prevent interference from the small amount of cobalt deposited on the TiN hard mask layer 400, the TiN hard mask layer 400 can be chemically mechanically polished before removal. Preferably, the polishing thickness of the chemically mechanical polishing is 5~20 Å.
[0045] Next, refer to Figure 7 As shown, step S5 is performed to clean and remove the TiN hard mask layer 400. Preferably, a wet cleaning method is used to remove the TiN hard mask layer 400. The solution used for wet cleaning is a mixture of hydrogen peroxide and an organic chelating agent (such as BASF R2360). This solution is chemically inert to cobalt and copper, and can effectively dissolve the TiN hard mask layer 400 without damaging the cobalt protective layer 500 and the tungsten via 210 below it. After removing the TiN hard mask layer 400, the height of the sidewalls of the trench 330 is reduced, and the aspect ratio is significantly decreased. Then, the diffusion barrier layer and the seed layer are sequentially deposited in the trench 330, and the trench 330 is filled with metal. In this embodiment, copper is used as the filler metal.
[0046] This invention also provides a semiconductor structure, which is fabricated using the method for reducing the aspect ratio of the fill trench provided in this invention.
[0047] In summary, this invention provides a method and semiconductor structure for reducing the aspect ratio of filling trenches, comprising the following steps: providing a substrate, on which a first interlayer dielectric layer is formed, and a tungsten via is formed in the first interlayer dielectric layer; sequentially forming a second interlayer dielectric layer and a TiN hard mask layer on the first interlayer dielectric layer; forming a patterned photoresist layer on the TiN hard mask layer; sequentially etching the TiN hard mask layer and the second interlayer dielectric layer to form trenches, the bottom of the trenches exposing the tungsten vias; depositing a cobalt protective layer on the surface of the tungsten vias; cleaning and removing the TiN hard mask layer; sequentially depositing a diffusion barrier layer and a seed layer in the trenches; and performing metal filling. The technical solution provided by this invention adds a TiN hard mask cleaning step, protects the tungsten vias by depositing a cobalt protective layer, reduces the aspect ratio of the trenches by removing the TiN hard mask layer, widens the process window for subsequent filling steps, reduces filling defects, and thus improves product yield.
[0048] It should be noted that the above description is only a description of the preferred embodiment of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the present invention.
Claims
1. A method for reducing the aspect ratio of a filled trench, characterized in that, Includes the following steps: A substrate is provided, on which a first interlayer dielectric layer is formed, and tungsten vias are formed in the first interlayer dielectric layer; A second interlayer dielectric layer and a TiN hard mask layer are sequentially formed on the first interlayer dielectric layer; A patterned photoresist layer is formed on the TiN hard mask layer, and the TiN hard mask layer and the second interlayer dielectric layer are etched sequentially to form trenches, the bottom of the trenches exposing the tungsten vias; A cobalt protective layer is deposited on the surface of the tungsten through-hole; The TiN hard mask layer is cleaned and removed. A diffusion barrier layer and a seed layer are deposited sequentially in the trench, and then metal is filled.
2. The method for reducing the depth-to-width ratio of a filling trench according to claim 1, characterized in that, The thickness of the cobalt protective layer is 5~25 Å.
3. The method for reducing the depth-to-width ratio of a filling trench according to claim 1, characterized in that, The second interlayer dielectric layer includes a low-K dielectric layer and a nitrogen-free dielectric anti-reflective coating located on the low-K dielectric layer.
4. The method for reducing the depth-to-width ratio of a filling trench according to claim 1, characterized in that, Before removing the TiN hard mask layer, the method further includes performing chemical mechanical polishing on the TiN hard mask layer.
5. The method for reducing the depth-to-width ratio of a filling trench according to claim 4, characterized in that, The polishing thickness of the chemical mechanical polishing is 5~20 Å.
6. The method for reducing the aspect ratio of a filling trench according to claim 1, characterized in that, Before depositing the cobalt protective layer, the method further includes: wet cleaning the trench.
7. The method for reducing the depth-to-width ratio of a filling trench according to claim 6, characterized in that, After performing the wet cleaning step, the method further includes: heat-treating the second interlayer dielectric layer.
8. The method for reducing the aspect ratio of the filling trench according to claim 1, characterized in that, The TiN hard mask layer is removed by wet cleaning, and the solution used in the wet cleaning is a mixture of hydrogen peroxide and an organic chelating agent.
9. The method for reducing the depth-to-width ratio of a filling trench according to claim 1, characterized in that, The metallic material filling the trench includes copper.
10. A semiconductor structure, characterized in that, Formed using the method described in any one of claims 1 to 9.