P3 package optimization structure based on aEASI technology and preparation method thereof

Abstract

The application discloses a P3 packaging optimization structure based on an aEASI technology and a preparation method thereof, which comprises the following steps: stamping a W-shaped lead frame with a notch, and mounting ASIC chips and optical elements on the front and back surfaces of the lead frame to realize double-sided high-density integration; then, the lead frame is cut to be unitized, and molding packaging is performed to form a packaging body; a through hole and an optical path opening are formed by laser drilling, and the precision is ensured by using the selectivity of laser on materials; a vertical interconnection conductive column is formed by filling the through hole by electroplating, and upper and lower surface copper layers are synchronously formed; then, a first fan-out conductive structure and a second fan-out conductive structure with optical windows are respectively prepared on the copper layers by patterning; finally, anti-soldering treatment is performed, BGA solder balls are arranged on one side as external connection points, and heat dissipation fins are arranged on the other side to strengthen heat dissipation. The application realizes high-density and high-reliability integration of heterogeneous chips, and effectively improves the electrical performance, heat dissipation efficiency and functional diversity of the packaging module.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor packaging technology and relates to an optimized P3 packaging structure based on aEASI (embedded active system integration) technology and its preparation method. Background Technology

[0002] As electronic devices evolve towards miniaturization, multifunctionality, and high performance, higher demands are placed on the density, performance, heat dissipation, and reliability of semiconductor packaging. Traditional packaging technologies, such as wire bonding and standard ball grid array packaging, face challenges in high-power and high-frequency applications, including excessively high parasitic resistance / inductance, insufficient heat dissipation efficiency, and size limitations.

[0003] To address these challenges, embedded packaging technology has emerged. While existing technologies, such as AT&S's ECP and TDK's SESUB, have achieved some degree of device miniaturization or performance improvement, they still have limitations in achieving a comprehensive balance between power density, electrical performance, and cost-effectiveness. Especially for applications requiring extremely high power density and excellent thermal management performance (such as 48V high-voltage systems and automotive power modules), the structural complexity and I / O capabilities of existing solutions are insufficient to meet the requirements. Summary of the Invention

[0004] The purpose of this invention is to provide an optimized P3 package structure based on aEASI technology and its preparation method, which improves the functional density, space utilization, and thermal management performance of the package.

[0005] The objective of this invention is achieved through the following technical solution: A method for fabricating an optimized P3 package structure based on aEASI technology includes the following steps: Step 1, Conductor frame forming step: Provide a copper alloy substrate and form a W-shaped conductor frame with notches through a stamping process; Step 2, Chip Mounting and Temporary Fixing: Mount the ASIC chip in the groove area of ​​the lead frame and attach a temporary substrate to the upper surface of the lead frame; Step 3, Flipping and Optical Component Assembly: Flip the assembly and attach the optical component to the protruding position on the back of the lead frame. The optical component is positioned opposite to an ASIC chip. Step 4, Cutting, Separation and Packaging: Cut the lead frame along the notch, remove the temporary substrate, and then encapsulate it with thermosetting sol to form a package, and place copper foil at the top and bottom ends of the package; Step 5, Laser Drilling Step: A CO2 laser is used to drill through the copper foil to form several through holes and optical paths corresponding to the optical elements. Step 6, Electroplating and Conductive Layer Formation Step: Electroplating is performed on the upper and lower surfaces of the package to fill the through holes and form conductive pillars, and the first copper layer and the second copper layer are formed simultaneously. Step 7, RDL fabrication and conductive structure forming steps: A temporary substrate is attached to one side of the first copper layer, and then the second copper layer is exposed, developed and etched to remove excess copper layer, retaining the portion of copper layer connected to the conductive pillar. On this basis, a redistribution layer fabrication process is used to form the first fan-out conductive structure. The first fan-out conductive structure has a notch corresponding to the position of the optical element. Step 8: Preparation of the second fan-out conductive structure: Remove the temporary substrate attached to the first copper layer and attach a new temporary substrate to the first fan-out conductive structure; then expose, develop and etch the first copper layer to remove excess copper layer and retain the portion of copper layer connected to the conductive pillars. On this basis, a redistribution layer preparation process is used to form the second fan-out conductive structure. Step 9, Solder resist treatment and terminal structure assembly steps: Apply solder resist green paint to the surfaces of the first fan-out conductive structure and the second fan-out conductive structure and set the pads; form BGA solder balls on the pads on one side of the second fan-out conductive structure, first eutecticly set a pre-formed metal layer on the pads on one side of the first fan-out conductive structure, and then attach the heat sink to the pre-formed metal layer with high thermal conductivity adhesive.

[0006] As a further improvement of the present invention, the copper alloy substrate in step 1 is a Cu-Fe-P alloy.

[0007] As a further improvement of the present invention, in step 2, the ASIC chip is mounted using eutectic bonding or conductive adhesive bonding processes; the material of the temporary substrate is glass, ceramic or polymer insulating material.

[0008] As a further improvement of the present invention, the optical element in step 3 is a vertical cavity surface-emitting laser, and is mounted using an optical alignment mounting process.

[0009] An optimized P3 package structure based on aEASI technology, fabricated using the above method, includes: Package; The lead frame, built into the package, has a W-shaped disconnect structure, allowing multiple ASIC chips to operate independently. The ASIC chip and optical components are precisely attached to the upper and lower surfaces of the lead frame, respectively. Several conductive pillars penetrate the upper and lower sides of the package and are electrically connected to the lead frame, ASIC chip and optical components; The first fan-out conductive structure and the second fan-out conductive structure are respectively disposed on the upper and lower surfaces of the package body; Solder resist green paint is applied to the surfaces of the two conductive structures and has solder pads. The pads on the second fan-out conductive structure are provided with BGA solder balls, and the pads on the first fan-out conductive structure are attached with heat sinks by high thermal conductivity adhesive.

[0010] As a further improvement of the present invention, the first fan-out conductive structure has a notch corresponding to the position of the optical element.

[0011] As a further improvement of the present invention, the lead frame is made of Cu-Fe-P alloy material.

[0012] The above technical solution has the following beneficial effects: 1. Through the innovative design of the W-shaped lead frame and double-sided mounting technology, the three-dimensional, high-density, heterogeneous integration of ASIC chips and optical components (such as VCSELs) in the same package was successfully achieved, which significantly improved the functional density and space utilization of the package. 2. The unique double-sided fan-out structure design, especially with one side dedicated to mounting a heatsink, provides an efficient thermal management path. Combined with high thermal conductivity adhesive, it can quickly conduct the heat generated by the chip to the outside, ensuring reliability and stability under high power operation; 3. Vertical conductive pillars formed through laser drilling and electroplating achieve short-path electrical interconnection, effectively reducing parasitic inductance and resistance. Simultaneously, the disconnection design of the W-shaped leadframe isolates the chips from each other, reducing electrical interference. The optical path openings and conductive structure gaps reserved for optical components ensure the pure transmission of optical signals. Attached Figure Description

[0013] To more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings in the following description are merely exemplary, and those skilled in the art can derive other embodiments based on the provided drawings without creative effort.

[0014] The structures, proportions, sizes, etc. shown in this specification are only used to complement the content disclosed in the specification for those skilled in the art to understand and read, and are not intended to limit the conditions under which the present invention can be implemented. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in the proportional relationships, or adjustments to the size, without affecting the effects and objectives that the present invention can produce, should still fall within the scope of the technical content disclosed in the present invention.

[0015] Figure 1 This is a schematic diagram of the process structure provided by the present invention.

[0016] Figure 2 This is a schematic diagram of the optimized P3 package structure provided by the present invention.

[0017] In the picture: 1. Conductor frame; 101. Notch; 2. ASIC chip; 3. Temporary substrate; 4. Optical components; 5. Package; 6. Copper foil; 71. Through hole; 72. Optical path; 81. Conductive pillar; 82. First copper layer; 83. Second copper layer; 91. First fan-out conductive structure; 92. Second fan-out conductive structure; 93. Solder resist; 94. Solder pad; 95. Heat sink; 96. High thermal conductivity adhesive. Detailed Implementation

[0018] In this invention, unless otherwise stated, directional terms such as "upper," "lower," "top," and "bottom" are generally used in relation to the direction shown in the accompanying drawings, or in relation to the vertical, perpendicular, or gravitational direction of the component itself; similarly, for ease of understanding and description, "inner" and "outer" refer to the inner and outer contours of each component itself, but the above directional terms are not intended to limit this invention.

[0019] First embodiment, such as Figure 1 As shown, a method for fabricating an optimized P3 package structure based on aEASI technology is presented, aiming to improve the integration density and reliability of the package structure and adapt to the application requirements of high-density packaging scenarios. The specific fabrication steps are as follows: Step 1, Leadframe Forming Process: A Cu-Fe-P alloy material (such as C19400 alloy) is selected as the leadframe substrate. This substrate has a copper content of approximately 97%, a softening temperature of 1250℃, and a conductivity ≥60%, effectively ensuring the conductivity and structural stability of the packaging structure. The copper substrate is processed into a W-shaped leadframe 1 using a stamping process. The stamped leadframe 1 has a pre-drilled notch 101 for subsequent cutting. The shape of the notch 101 can be rectangular, trapezoidal, or similar, as long as it meets the requirements for subsequent cutting and separation.

[0020] Step 2, Chip Mounting and Temporary Fixing: The ASIC chip 2 is precisely mounted within the recessed area of ​​the leadframe 1. Eutectic bonding can be used during mounting, relying on TLPB (Transient Liquid Phase Diffusion Bonding) technology to achieve high-strength mechanical and electrical interconnection of the ASIC chip 2. After mounting, a temporary substrate 3 is attached to the upper surface of the leadframe 1. The temporary substrate 3 can be made of glass, ceramic, or polymer insulating material, and its function is to temporarily protect and position the ASIC chip 2 and the upper structure of the leadframe 1.

[0021] Step 3, Flipping and Optical Component Assembly: The assembly with the temporary substrate 3 attached is flipped 180 degrees so that the back of the lead frame 1 faces upwards. Then, an optical component 4, which serves as the light source, is mounted on the protruding position on the back of the lead frame 1. This optical component 4 can be a vertical-cavity surface-emitting laser. The optical component 4 is positioned opposite one of the ASIC chips 2 to achieve high-density integration of the package structure. The mounting of the optical component 4 can employ an optical alignment mounting process to ensure the relative positional accuracy between it and the ASIC chip 2.

[0022] Step 4, Cutting, Separation, and Packaging: After mounting the optical component 4, cut it along the pre-reserved notch 101 on the lead frame 1. Laser cutting can be used to ensure a smooth cut surface without damaging the chip or component. Then, remove the temporary substrate 3, making the originally integrated ASIC chips 2 independent and non-interfering. Next, use thermosetting sol to encapsulate the overall structure, forming a package 5. During encapsulation, methods such as mold potting or coating can be used to ensure the integrity of the package 5. Copper foil 6 is placed at both ends of the package 5. The copper foil 6 can be fixed by pressing or other methods. After the thermosetting sol cures, it provides reliable structural protection for the internal chips, components, and lead frame, and also achieves electrical isolation between components to avoid electrical interference.

[0023] Step 5, Laser Drilling Process: A CO2 laser is used to drill through the copper foil 6 to form several through holes 71 and optical paths 72 on the upper and lower sides of the package 5. The through holes 71 are in contact with the lead frame 1, ASIC chip 2 and optical element 4, and the optical paths 72 correspond to the optical element 4 to ensure normal transmission of optical signals.

[0024] The wavelength characteristics of the CO2 laser are adapted to the requirements of this packaging process. It has a high absorption rate for the dielectric material used in the package and an extremely low absorption rate for the copper layer. This characteristic allows the laser drilling to effectively ablate and remove the dielectric material on top without damaging the lead frame 1, ultimately forming a via 71 with a copper layer at the bottom.

[0025] Step 6: Electroplating and Conductive Layer Formation: Copper is electroplated onto the top and bottom surfaces of the package 5. The conductive holes 71 are completely filled with copper through electroplating to form conductive pillars 81. The electroplating process must ensure that the conductive pillars 81 are densely filled without gaps. Simultaneously, a first copper layer 82 is formed on the upper surface of the package 5, and a second copper layer 83 is formed on the lower surface. The first copper layer 82 and the second copper layer 83 can be electroplated and formed simultaneously with the conductive pillars 81. The conductive pillars 81 provide a reliable electrical connection between the lead frame 1 and the first copper layer 82 and the second copper layer 83, ensuring the conductive continuity of the package structure.

[0026] Step 7, RDL fabrication and conductive structure forming process: A temporary substrate is attached to one side of the first copper layer 82. The temporary substrate can be made of suitable materials such as glass or polymer insulating board, and is used to protect and position the structure on the side of the first copper layer 82. Subsequently, the second copper layer 83 is exposed and developed, and excess copper layer is removed by etching process, leaving only the portion of copper layer connected to the conductive pillar 81. On this basis, conventional RDL (redistribution layer) fabrication processes in the art are used, such as sputtering, electroplating, photolithography, etc., combined with other technologies, to form the first fan-out conductive structure 91. The first fan-out conductive structure 91 has a notch corresponding to the position of the optical element 4 to ensure the normal operation and signal transmission of the optical element 4.

[0027] Step 8: Fabrication of the second fan-out conductive structure: First, remove the temporary substrate attached to the first copper layer 82, taking care to avoid damaging the first copper layer 82 and surrounding structures. Then, attach a new temporary substrate to the first fan-out conductive structure 91. This temporary substrate can be made of glass or a polymer insulating material compatible with the previous description. Next, rotate the entire structure 180 degrees and perform exposure and development on the first copper layer 82. Remove excess copper layer using an etching process, retaining only the core copper layer portion connected to the conductive pillars 81. Based on this, use equivalent techniques from conventional RDL fabrication processes in the field, such as sputtering, electroplating, and photolithography, to form the second fan-out conductive structure 92, ensuring its structural compatibility and electrical reliability with the first fan-out conductive structure 91.

[0028] Step 9, Solder resist treatment and terminal structure assembly process: On the surfaces of the first fan-out conductive structure 91 (avoiding the pre-reserved notch area above the optical element 4) and the second fan-out conductive structure 92, apply solder resist green paint 93 as needed. The coating method can be screen printing, spraying, or similar processes to ensure uniform coating. After the solder resist green paint has cured, set the pads 94 in the preset positions. Subsequently, complete the ball placement operation on the pads 94 on one side of the second fan-out conductive structure 92 to form the external contact of the BGA package; on the pads on one side of the first fan-out conductive structure 91, first melt the pre-placed metal layer (such as gold-tin) at the eutectic temperature (temperature 363℃, pressure 10-50MPa), and after cooling, form a metallurgical bond to achieve high-strength mechanical and electrical interconnection. Then, the heat sink 95 is attached using high thermal conductivity adhesive 96. High thermal conductivity adhesives such as epoxy and silicone can be used. The attachment method can be pressure curing or other means to ensure a tight fit between the heat sink 95 and the pads and conductive structures, thereby achieving efficient active heat dissipation and improving the overall heat dissipation performance of the package.

[0029] In this solution, the heat conduction area is increased and the heat dissipation efficiency is improved by optimizing the pad structure: through the design of "locally thickened pads" or "mesh-shaped heat dissipation pads".

[0030] This invention discloses an optimized P3 package structure based on aEASI technology. This structure is fabricated using the aforementioned method, resulting in a compact layout, high integration, and effective assurance of electrical performance and heat dissipation reliability. Figure 2 As shown, the package includes a package 5, which encapsulates a lead frame 1, an ASIC chip 2, and an optical element 4, forming the core functional unit of the package. The lead frame 1 is made of a Cu-Fe-P alloy or other compatible conductive materials and has two opposing upper and lower surfaces. The ASIC chip 2 and the optical element 4 are precisely attached to the upper and lower surfaces of the lead frame 1, respectively, achieving a double-sided layout of the functional components and significantly improving space utilization.

[0031] The leadframe 1 has a W-shaped disconnect structure, which is disconnected through processes such as pre-set notches, making each ASIC chip 2 independent and avoiding mutual interference during operation. The disconnect structure can also adopt trapezoidal notches, rectangular slots, or other similar structural forms. Several conductive pillars 81 are formed on the package 5 through laser drilling (CO2 laser technology can be used) and electroplating. The conductive pillars 81 reliably connect to the leadframe 1, ASIC chip 2, and optical element 4, respectively, shortening the power and signal paths. The upper and lower surfaces of the package 5 are respectively provided with a first fan-out conductive structure 91 and a second fan-out conductive structure 92. Both conductive structures are coated with solder resist 93, and pads 94 are installed at preset positions. The pads 94 on the second fan-out conductive structure 92 are ball-mounted, and the pads 94 on the first fan-out conductive structure 91 are attached to heat sinks 95 with high thermal conductivity adhesive 96, ensuring efficient heat dissipation of the package structure.

[0032] This invention possesses significant technical advantages and practical value, specifically in its structural design and manufacturing process. Structurally, through an innovative design of a W-shaped leadframe (its equivalent structure can be a W-shaped groove-type leadframe, etc.), combined with double-sided component mounting technology, it successfully achieves three-dimensional, high-density, heterogeneous integration of the ASIC chip 2 and optical components 4 (such as VCSELs, photodetectors, etc.) within the same package 5. Compared to traditional single-sided mounting structures, this significantly improves the functional density and space utilization of the package. Simultaneously, a unique double-sided fan-out conductive structure design is employed, where the first fan-out conductive structure 91 is specifically designed for mounting the heat sink 95. Combined with high thermal conductivity adhesive 96, this creates an efficient thermal management path, rapidly transferring the heat generated during chip operation to the external environment, effectively ensuring the reliability and stability of the package structure under high-power operation.

[0033] In terms of electrical performance, vertical conductive pillars 81 are formed through laser drilling (using CO2 laser technology) and electroplating to fill holes, achieving short-path electrical interconnection, effectively reducing parasitic inductance and resistance, and improving signal transmission efficiency. The disconnection design of the W-shaped leadframe (which can be effectively disconnected by cutting with notches of different shapes) isolates each ASIC chip 2 from each other, reducing electrical interference between chips. In addition, the optical path 72 and conductive structure notches reserved for optical elements 4 avoid obstruction of optical signal transmission and ensure the purity of optical signals. In terms of the fabrication method, each step is clear and well-defined, making full use of the advantages of mature processes such as CO2 laser selective ablation and electroplating to fill holes. The steps are smoothly connected, with good operability and repeatability, which can effectively improve production yield, adapt to the needs of large-scale mass production, and ensure the high reliability of the final package structure.

[0034] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0035] It should be noted that the terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in sequences other than those illustrated or described herein.

[0036] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for fabricating an optimized P3 package structure based on aEASI technology, characterized in that, Includes the following steps: Step 1, conductor frame forming step: Provide a copper alloy substrate and form a W-shaped conductor frame (1) with a notch (101) by stamping process. Step 2, Chip mounting and temporary fixing steps: ASIC chip (2) is mounted in the groove area of ​​the lead frame (1), and a temporary substrate (3) is attached to the upper surface of the lead frame (1). Step 3, Flipping and Optical Component Assembly: Flip the assembly and attach the optical component (4) to the protruding position on the back of the lead frame (1). The optical component (4) is positioned opposite to an ASIC chip (2). Step 4, Cutting, Separation and Packaging Step: Cut the lead frame (1) along the notch (101), remove the temporary substrate (3), and then encapsulate it with thermosetting sol to form a package (5), and place copper foil (6) at the upper and lower ends of the package (5). Step 5, Laser drilling step: A CO2 laser is used to drill through the copper foil (6) to form several through holes (71) and optical paths (72) corresponding to the optical elements (4). Step 6, Electroplating and Conductive Layer Formation Step: Electroplating is performed on the upper and lower surfaces of the package (5) to fill the through hole (71) to form a conductive pillar (81), and the first copper layer (82) and the second copper layer (83) are formed simultaneously. Step 7, RDL fabrication and conductive structure forming steps: A temporary substrate is attached to one side of the first copper layer (82), and then the second copper layer (83) is exposed, developed and etched to remove excess copper layer, retaining the part of the copper layer connected to the conductive pillar (81). On this basis, a redistribution layer fabrication process is used to form the first fan-out conductive structure (91). The first fan-out conductive structure (91) has a notch corresponding to the position of the optical element (4). Step 8: Preparation of the second fan-out conductive structure: Remove the temporary substrate attached to the first copper layer (82), and attach a new temporary substrate to the first fan-out conductive structure (91); then expose, develop, and etch the first copper layer (82) to remove excess copper layer, retain the portion of copper layer connected to the conductive pillar (81), and form the second fan-out conductive structure (92) using a redistribution layer preparation process. Step 9, Solder resist treatment and terminal structure assembly steps: Apply solder resist green paint (93) to the surface of the first fan-out conductive structure (91) and the second fan-out conductive structure (92) and set pads (94); form BGA solder balls on the pads on one side of the second fan-out conductive structure (92), first eutectic set a pre-formed metal layer on the pads on one side of the first fan-out conductive structure (91), and then attach heat sinks (95) to the pre-formed metal layer with high thermal conductivity adhesive (96).

2. The preparation method according to claim 1, characterized in that, The copper alloy substrate mentioned in step 1 is a Cu-Fe-P alloy.

3. The preparation method according to claim 1, characterized in that, In step 2, the ASIC chip (2) is mounted using eutectic bonding or conductive adhesive bonding processes; the temporary substrate (3) is made of glass, ceramic or polymer insulating material.

4. The preparation method according to claim 1, characterized in that, The optical element (4) mentioned in step 3 is a vertical cavity surface-emitting laser, and it is mounted using an optical alignment mounting process.

5. An optimized P3 package structure based on aEASI technology, fabricated using the method described in any one of claims 1-4, characterized in that, include: Package (5); The lead frame (1) is built into the package (5) and has a W-shaped disconnection structure, so that multiple ASIC chips (2) are independent of each other; The ASIC chip (2) and the optical element (4) are precisely attached to the upper and lower surfaces of the lead frame (1), respectively; Several conductive pillars (81) penetrate the upper and lower sides of the package (5) and are electrically connected to the lead frame (1), ASIC chip (2) and optical element (4); The first fan-out conductive structure (91) and the second fan-out conductive structure (92) are respectively disposed on the upper and lower surfaces of the package (5); Solder resist green paint (93) is applied to the surfaces of the two conductive structures and has solder pads (94). The pads on the second fan-out conductive structure (92) are provided with BGA solder balls, and the pads on the first fan-out conductive structure (91) are attached with heat sinks (95) by high thermal conductivity adhesive (96).

6. The optimized P3 package structure according to claim 55, characterized in that, The first fan-out conductive structure (91) has a notch corresponding to the position of the optical element (4).

7. The optimized P3 package structure according to claim 1, characterized in that, The conductor frame (1) is made of Cu-Fe-P alloy material.

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