Semiconductor structure and method of forming the same, package structure and method of packaging

Abstract

A semiconductor structure, a forming method thereof, a packaging structure and a packaging method, the semiconductor structure comprising: a base structure; a dielectric layer on the base structure, and a bonding surface with continuity on the top of the dielectric layer; a solder pad penetrating through the dielectric layer, the top surface of the solder pad being exposed by the bonding surface, and the top surface of the solder pad being flush with the bonding surface. Since the bonding surface has continuity, the flatness of the bonding surface is improved, the bonding strength of the bonding surface is increased accordingly, and the top surface of the solder pad is flush with the bonding surface, the flatness between the top surface of the solder pad and the bonding surface at the position of the dielectric layer is also high, thereby reducing the probability of edge collapse of the bonding surface after bonding using the semiconductor structure, and improving the packaging reliability and yield of the semiconductor structure.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same, a packaging structure, and a packaging method. Background Technology

[0002] Three-dimensional integrated circuits (3D ICs) are fabricated using advanced chip stacking technology, which stacks chips with different functions into an integrated circuit with a three-dimensional structure. Compared to two-dimensional integrated circuits, the stacking technology of 3D ICs not only shortens the signal transmission path but also increases the operating speed, thereby meeting the demands of semiconductor devices for higher performance, smaller size, lower power consumption, and more functions.

[0003] Hybrid bonding is a technique that simultaneously bonds metal pads and dielectric layers on a wafer / chip, eliminating the need for microbumps and further reducing the interconnect pitch. Therefore, hybrid bonding technology enables high-density integration and plays an irreplaceable role in 3D packaging.

[0004] However, the reliability and yield of wafer-to-wafer packaging still need to be improved. Summary of the Invention

[0005] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and its formation method, packaging structure and packaging method, which is beneficial to improving the packaging reliability and packaging yield of wafers.

[0006] To address the aforementioned problems, embodiments of the present invention provide a semiconductor structure, comprising: a substrate structure; a dielectric layer located on the substrate structure, wherein the top of the dielectric layer has a continuous bonding surface; and a solder pad penetrating the dielectric layer, wherein the top surface of the solder pad is exposed by the bonding surface and is flush with the bonding surface.

[0007] Accordingly, embodiments of the present invention also provide a method for forming a semiconductor structure, comprising: providing a substrate structure; forming a dielectric layer on the substrate structure; forming a continuous bonding surface on the top of the dielectric layer; forming an opening through the dielectric layer; and forming a bonding pad in the opening, wherein the top of the bonding pad is flush with the bonding surface.

[0008] Accordingly, embodiments of the present invention also provide a packaging structure, including: a first wafer and a second wafer stacked and bonded together, wherein one or both of the first wafer and the second wafer adopt a semiconductor structure according to any embodiment of the present invention; the bonding surfaces of the first wafer and the second wafer are disposed opposite to each other, and bonding is achieved through the bonding surfaces and the pads.

[0009] Accordingly, embodiments of the present invention also provide a packaging method, comprising: providing a first wafer and a second wafer, wherein one or both of the first wafer and the second wafer adopt a semiconductor structure according to any embodiment of the present invention; arranging the bonding surfaces of the first wafer and the second wafer opposite to each other, and arranging the pads of the first wafer and the second wafer opposite to each other; bonding the first wafer and the second wafer through the oppositely arranged bonding surfaces and the oppositely arranged pads to form a bonded wafer; and annealing the pads of the bonded wafer.

[0010] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0011] This invention provides a semiconductor structure, including: a substrate structure; a dielectric layer located on the substrate structure, wherein the top of the dielectric layer has a continuous bonding surface; and a solder pad penetrating the dielectric layer, wherein the top surface of the solder pad is exposed by the bonding surface and is flush with the bonding surface. Because the bonding surface is continuous, its flatness is improved, thereby increasing the bonding strength. Furthermore, the flushness of the top surface of the solder pad with the bonding surface and the high flatness between the top surface of the solder pad and the bonding surface at the dielectric layer location further reduce the probability of gaps appearing on the bonding surface after bonding using this semiconductor structure, thus improving the packaging reliability and yield of the semiconductor structure.

[0012] This invention provides a method for forming a semiconductor structure, comprising: providing a substrate structure; forming a dielectric layer on the substrate structure; forming a continuous bonding surface on the top of the dielectric layer; forming an opening penetrating the dielectric layer; and forming a solder pad in the opening, wherein the top of the solder pad is flush with the bonding surface. In this invention, because the formed bonding surface is continuous, the flatness of the bonding surface is improved, thereby increasing the bonding strength. Furthermore, the top surface of the solder pad is flush with the bonding surface, and the flatness between the top surface of the solder pad and the bonding surface at the dielectric layer position is also high. Therefore, after bonding using the semiconductor structure, the probability of gaps appearing on the bonding surface is reduced, thereby improving the packaging reliability and packaging yield of the semiconductor structure.

[0013] This invention provides a packaging structure including: a first wafer and a second wafer stacked and bonded together, wherein one or both of the first wafer and the second wafer employ a semiconductor structure according to any embodiment of this invention; the bonding surfaces of the first wafer and the second wafer are disposed opposite to each other, and bonding is achieved through the bonding surfaces and the bonding pads. At least one of the first wafer and the second wafer has a continuous bonding surface at the top of its dielectric layer, which correspondingly increases the bonding strength of the bonding surface, reduces the probability of gaps appearing on the bonding surface, and thus improves the packaging reliability and product yield of the semiconductor structure.

[0014] This invention provides a packaging method, comprising: providing a first wafer and a second wafer, wherein one or both of the first wafer and the second wafer employ a semiconductor structure according to any embodiment of this invention; arranging the bonding surfaces of the first wafer and the second wafer opposite to each other, and arranging the pads of the first wafer and the second wafer opposite to each other; bonding the first wafer and the second wafer together through the oppositely arranged bonding surfaces and the oppositely arranged pads to form a bonded wafer, and then annealing the pads of the bonded wafer. In the first wafer and the second wafer, at least one of them has a continuous bonding surface at the top of its dielectric layer, which correspondingly increases the bonding strength of the bonding surface, reduces the probability of gaps appearing on the bonding surface, and thus improves the packaging reliability and product yield of the semiconductor structure. Attached Figure Description

[0015] Figures 1 to 5 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0016] Figure 6 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention;

[0017] Figures 7 to 14 This is a schematic diagram of the structure corresponding to each step in one embodiment of the method for forming a semiconductor structure of the present invention;

[0018] Figure 15 This is a schematic diagram of an embodiment of the packaging structure of the present invention;

[0019] Figures 16 to 20 This is a schematic diagram of the structure corresponding to each step in one embodiment of the packaging method of the present invention. Detailed Implementation

[0020] Currently, the packaging reliability and yield of semiconductor structures still need improvement. This paper analyzes the reasons why the packaging reliability and yield of semiconductor structures need further improvement, using schematic diagrams of each step in a semiconductor structure formation method as examples. Figures 1 to 5 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0021] refer to Figure 1 A base structure 10 is provided, the base structure including a trimmed area i and a center area ii, the trimmed area i surrounding the center area ii, and the top of the base structure 10 of the trimmed area i being lower than the top of the base structure 10 of the center area ii.

[0022] refer to Figure 2 A dielectric material layer 11 is formed on the base structure 10 of the trimmed area i and the central area ii.

[0023] refer to Figure 3 A mask layer 12 is formed in the dielectric material layer 11, and the mask layer 12 is patterned to form a mask opening (not shown) located in the central region ii in the mask layer 12.

[0024] Specifically, the material of the mask layer 12 is photoresist.

[0025] refer to Figure 4 and Figure 5 Using the patterned mask layer 12 as a mask, the dielectric material layer 11 of the central region ii is patterned along the opening of the mask to form a dielectric layer 14 with an opening 13. The top surface of the dielectric layer 14 is a bonding surface 16 (e.g., ...). Figure 5 (As shown).

[0026] Continue to refer to Figure 5 The mask layer 12 is removed, and a solder pad 15 is formed in the opening 13, the top of the solder pad 15 being flush with the bonding surface 16.

[0027] Research revealed that the top of the base structure 10 of the trimmed area i is lower than the top of the base structure 10 of the central area ii, meaning that a step is formed at the junction of the trimmed area i and the central area ii of the base structure 10 (e.g., Figure 1 As shown), photoresist is typically formed using a coating process. Therefore, when the mask layer 12 is formed on the dielectric material layer 11, due to the surface tension of the fluid, photoresist accumulates at the location of the trimming area i (e.g., ...). Figures 3 to 4 As shown), in the subsequent process of removing the mask layer 12, the probability of the mask layer 12 remaining on the dielectric layer 14 is correspondingly increased (e.g., Figure 5 As shown, the top surface of the dielectric layer 14 covered by the mask layer 12 cannot serve as the bonding surface 16, which results in the bonding surface 16 at the location of the dielectric layer 14 being discontinuous, reducing the bonding strength of the bonding surface 16, and thus increasing the probability of gaps appearing on the bonding surface 16 after bonding using the semiconductor structure.

[0028] In the prior art, two methods are typically used to improve the problem of mask layer 12 residue. One method is to expose the mask layer 12 in a region at a certain distance from the edge of the substrate structure 10 through wafer edge exposure (WEE), thereby removing the mask layer 12 at the step of the substrate structure 10. However, in subsequent processes, this can damage the dielectric layer 14 at the step of the substrate structure 10. The other method is to use edge bead removal (EBR) to remove the mask layer 12 at the step of the substrate structure 10. However, since edge bead removal uses chemical cleaning solutions, it can easily damage the dielectric layer 14 at the step of the substrate structure 10.

[0029] To address the aforementioned technical problems, embodiments of the present invention provide a semiconductor structure, comprising: a substrate structure; a dielectric layer located on the substrate structure, wherein the top of the dielectric layer has a continuous bonding surface; and a solder pad penetrating the dielectric layer, wherein the top surface of the solder pad is exposed by the bonding surface and is flush with the bonding surface.

[0030] In the solution disclosed in the embodiments of the present invention, since the bonding surface formed is continuous, the flatness of the bonding surface is improved, and the bonding strength of the bonding surface is increased accordingly. Moreover, the top surface of the pad is flush with the bonding surface, and the flatness between the top surface of the pad and the bonding surface at the dielectric layer position is also high. As a result, after bonding using the semiconductor structure, the probability of gaps appearing on the bonding surface is reduced, and the packaging reliability and packaging yield of the semiconductor structure are improved.

[0031] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Figure 6 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention.

[0032] refer to Figure 6 The semiconductor structure includes: a substrate structure 100; a dielectric layer 101 located on the substrate structure 100, and the top of the dielectric layer 101 having a continuous bonding surface 102; and a solder pad 103 penetrating the dielectric layer 101, the top surface of the solder pad 103 being exposed by the bonding surface 102, and the top surface of the solder pad 103 being flush with the bonding surface 102.

[0033] Specifically, since the bonding surface 102 is continuous, the flatness of the bonding surface 102 is improved, and the bonding strength of the bonding surface 102 is increased accordingly. Moreover, the top surface of the pad 103 is flush with the bonding surface 102, and the flatness between the top surface of the pad 103 and the bonding surface 102 at the position of the dielectric layer 101 is also high. As a result, after bonding using the semiconductor structure, the probability of gaps appearing in the bonding surface 102 is reduced, and the packaging reliability and packaging yield of the semiconductor structure are improved.

[0034] The substrate structure 100 is used to provide a process platform for forming semiconductor structures.

[0035] In this embodiment, the base structure 100 includes a trimmed area I and a central area II. The trimmed area I surrounds the central area II, and the top of the base structure 100 of the trimmed area I is lower than the top of the base structure 100 of the central area II.

[0036] Trimming area I is used to trim the edges of the base structure 100.

[0037] In this embodiment, trimming area I is the area that needs to be trimmed so that the edges of the base structure 100 can be trimmed.

[0038] Central area II is used to provide a process platform for forming pad 103.

[0039] It should be noted that Central Zone II refers to all areas other than Trimmed Zone I.

[0040] It should also be noted that after the semiconductor structure is bonded to another semiconductor structure, the substrate structure 100 needs to undergo back-side thinning. Since the edges of the substrate structure 100 are usually arc-shaped, the arc-shaped edges of the remaining substrate structure 100 are prone to breakage during the back-side thinning process. Therefore, before the bonding process, the substrate structure 100 is trimmed, and a portion of the width of the substrate structure 100 is thinned along the edge of the substrate structure 100 from the bonding surface 102 side, so that the surface of the substrate structure 100 at the edge position is vertically stepped. Thus, when the back-side thinning process is performed on the substrate structure 100 to remove the portion of the substrate structure 100 that has not been trimmed, the surface of the substrate structure 100 at the edge position is vertically stepped, which helps to minimize the possibility of the substrate structure 100 breaking during the back-side thinning process.

[0041] In this embodiment, depending on the actual process, the substrate structure 100 includes a substrate (not shown) and a functional structure formed on the substrate. For example, the functional structure may include semiconductor devices such as MOS field-effect transistors or resistor structures.

[0042] As an example, the substrate is a silicon substrate. In other embodiments, the substrate material may also be one or more of germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride, or other types of substrates such as silicon-on-insulator or germanium-on-insulator.

[0043] It should be noted that the substrate can be a planar substrate or a substrate with channel protrusions.

[0044] The dielectric layer 101 is used to provide a process basis for setting up a continuous bonding surface 102, and also to achieve electrical isolation between the pads 103.

[0045] Specifically, the dielectric layer 101 is located on the substrate.

[0046] In this embodiment, the dielectric layer 101 includes: a first dielectric layer 120 located on the substrate structure 100; a second dielectric layer 121 located on top of the first dielectric layer 120; and a third dielectric layer 122 located on top of the second dielectric layer 121.

[0047] The first dielectric layer 120 is used to provide a process platform for forming the pad 103 and also to insulate adjacent pads 103 from each other.

[0048] In this embodiment, the material of the first dielectric layer 120 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxycarbide, silicon carbonitride, silicon carbonitride, low-k dielectric material (low-k dielectric material refers to dielectric material with a relative permittivity greater than or equal to 2.6 and less than or equal to 3.9) and ultra-low-k dielectric material (ultra-low-k dielectric material refers to dielectric material with a relative permittivity less than 2.6), thereby effectively reducing the parasitic capacitance between the pads 103 and thus reducing the RC delay of the device.

[0049] As an example, the first dielectric layer 120 is made of silicon oxide. In other embodiments, the first dielectric layer may also be made of a low-k dielectric material, such as black diamond (BD).

[0050] The third dielectric layer 122 is used to provide a process platform for forming the pad 103 and also to insulate adjacent pads 103 from each other.

[0051] In this embodiment, the material of the third dielectric layer 122 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxycarbide, silicon carbonitride, silicon carbonitride, low-k dielectric material (low-k dielectric material refers to dielectric material with a relative permittivity greater than or equal to 2.6 and less than or equal to 3.9) and ultra-low-k dielectric material (ultra-low-k dielectric material refers to dielectric material with a relative permittivity less than 2.6), thereby effectively reducing the parasitic capacitance between the pads 103 and thus reducing the RC delay of the device.

[0052] As an example, the material of the third dielectric layer 122 is silicon oxide. In other embodiments, the material of the third dielectric layer may also be a low-k dielectric material, for example, black diamond.

[0053] The top surface of the second dielectric layer 121 is used to define the etching stop position for etching the third dielectric layer 122.

[0054] The material of the second dielectric layer 121 is selected to have an etching selectivity ratio with that of the third dielectric layer 122, so that the top surface of the second dielectric layer 121 can define the stop position of etching the third dielectric layer 122 during the etching process. At the same time, due to the presence of the second dielectric layer 121, the opening for accommodating the solder pad 103 can be formed by all-in-one etching (AIOetch), thereby improving production efficiency and reducing production costs.

[0055] In this embodiment, the material of the second dielectric layer 121 includes silicon nitride. Specifically, there is an etching selectivity ratio between silicon nitride and the material selected for the third dielectric layer 122, and during the subsequent etching of the third dielectric layer 122, silicon nitride can define the stop position of the etching of the third dielectric layer 122.

[0056] During the subsequent bonding of the semiconductor structure, the bonding surface 102 at the location of the dielectric layer 101 is bonded to the dielectric layer of other semiconductor structures.

[0057] The pad 103 is used to bring out the electrical properties of the devices inside the substrate structure 100. Moreover, the top surface of the pad 103 is also a bonding surface. When the semiconductor structure is bonded in the subsequent process, the pad 103 contacts the pads of other semiconductor structures to achieve bonding between the semiconductor structures.

[0058] Therefore, hybrid bonding can be achieved in the bonding process through the bonding surface at the location of the solder pad 103 and the bonding surface 102 at the location of the dielectric layer 101.

[0059] Wherein, the top surface of the solder pad 103 is flush with the bonding surface 102, which means that the bonding surface at the position of the solder pad 103 is flush with the bonding surface 102 at the position of the dielectric layer 101, thereby giving the semiconductor structure a continuous bonding surface.

[0060] In this embodiment, the solder pad 103 penetrates the dielectric layer 101 located in the central region I.

[0061] In this embodiment, the material of the solder pad 103 is metal. The metal solder pad 103 can provide the main bonding strength for the bonding surface and achieve high-strength interconnection through atomic diffusion bonding.

[0062] Specifically, the material of solder pad 103 includes copper. Copper, in particular, has good electrical conductivity.

[0063] As an example, the material of the solder pad 103 includes copper. Copper has good diffusion properties, so when the solder pad 103 is heated during the subsequent bonding of the semiconductor structure, the material of the solder pad 103 is easy to diffuse, thus the bonding performance of the solder pad 103 is good during the subsequent bonding of the semiconductor structure.

[0064] The structure of the solder pad 103 can be a single damascene structure or a dual damascene structure. As an example, the structure of the solder pad 103 is a dual damascene structure.

[0065] It should be noted that the structure of the pad 103 is a double damask structure, which helps to reduce the number of planarization processes, thereby reducing the probability of depressions on the top surface of the pad 103, improving the flatness between the top surface of the pad 103 and the bonding surface 102, and correspondingly increasing the bonding strength between the semiconductor structure and the other semiconductor structure.

[0066] In this embodiment, the semiconductor structure further includes: a barrier layer (not shown) located between the pad 103 and the dielectric layer 101; and a seed layer (not shown) located between the barrier layer and the pad 103.

[0067] The barrier layer serves to prevent the diffusion of metal ions in the solder pad 103.

[0068] The barrier layer is made of one or both of tantalum nitride and tantalum. Specifically, tantalum nitride and tantalum can effectively block ion diffusion.

[0069] As an example, the barrier layer is made of tantalum nitride.

[0070] The seed layer provides a uniform starting surface for the subsequent formation of the solder pad 103, which helps to reduce the probability of defects such as voids and cracks in the subsequent formation of the solder pad 103, thereby improving the quality and reliability of the formed solder pad 103.

[0071] It should be noted that the material of the seed layer is determined by the material of the solder pad 103. In this embodiment, the seed layer is made of copper. In other embodiments, the seed layer may also be made of other metal materials suitable for the growth of solder pad materials.

[0072] In this embodiment, the semiconductor structure further includes a filling layer 104 located on the dielectric layer 101, the top surface of the filling layer 104 being the bonding surface 102, the thermal expansion coefficient of the filling layer 104 being greater than the thermal expansion coefficient of the bonding pad 103, and the thermal expansion coefficient of the filling layer 104 being greater than the thermal expansion coefficient of the dielectric layer 101.

[0073] The filling layer 104 is used to contact the bonding surfaces of other structures to achieve bonding of the semiconductor structure during subsequent bonding.

[0074] In this embodiment, since the coefficient of thermal expansion of the filling layer 104 is greater than that of the solder pad 103, and the coefficient of thermal expansion of the filling layer 104 is greater than that of the dielectric layer 101, while the coefficient of thermal expansion of the dielectric layer 101 is less than that of the solder pad 103, the filling layer 104 balances the thermal mismatch between the solder pad 103 and the dielectric layer 101. This improves the flatness between the top surface of the solder pad 103 and the bonding surface 102 at the top of the dielectric layer 101, and correspondingly reduces the probability of depressions appearing on the bonding surface 102 at the top of the dielectric layer 101. This allows the top surface of the solder pad 103 and the bonding surface 102 at the top of the dielectric layer 101 to form a continuous bonding surface, thereby improving the packaging reliability and packaging yield of the semiconductor structure.

[0075] Specifically, the thickness of the filler layer 104 should not be too large. If the thickness of the filler layer 104 is too large, during the subsequent bonding of the semiconductor structure with another semiconductor structure to form a bonded wafer, the excessive thermal expansion force of the filler layer 104 may generate a reverse force on the bonding force between the dielectric layers 101 of the bonded wafer. This can easily lead to poor results in reducing edge chipping on the bonding surface 102 of the bonded wafer, and consequently, poor results in improving the packaging reliability and packaging yield of the semiconductor structure. Therefore, in this embodiment, the thickness of the filler layer 104 is less than 10 nanometers, for example, the thickness of the filler layer 104 is 3 nanometers.

[0076] It should be noted that the coefficient of thermal expansion of the filler layer 104 should not be too large or too small. If the coefficient of thermal expansion of the filler layer 104 is too large, during the subsequent bonding of the semiconductor structure with another semiconductor structure to form a bonded wafer, the excessive thermal expansion force of the filler layer 104 may generate a reverse force on the bonding force between the dielectric layers 101 of the bonded wafer. This may result in poor performance in reducing edge chipping on the bonding surface 102 of the bonded wafer, and consequently, poor performance in improving the packaging reliability and yield of the semiconductor structure. If the coefficient of thermal expansion of the filler layer 104 is too small, its effect in balancing the thermal mismatch between the pads 103 and the dielectric layer 101 may be insignificant. Therefore, in this embodiment, the coefficient of thermal expansion of the filler layer 104 is 2 × 10⁻⁶. -5 Up to 3×10 per degree Celsius -5 Every degree Celsius.

[0077] The filler layer 104 is made of polyimide.

[0078] Specifically, the coefficient of thermal expansion of polyimide is greater than that of the solder pad 103, and the coefficient of thermal expansion of polyimide is greater than that of the dielectric layer 101. Therefore, the filler layer 104 formed by polyimide balances the thermal mismatch between the solder pad 103 and the dielectric layer 101. At the same time, the bonding strength of polyimide is greater than that of the dielectric layer 101, thereby effectively ensuring the progress of subsequent processes.

[0079] In this embodiment, the filling layer 104 is made of polyimide.

[0080] In other embodiments, the semiconductor structure may also exclude the filler layer, and correspondingly, the top surface of the dielectric layer is the bonding surface with continuity.

[0081] Accordingly, embodiments of the present invention also provide a method for forming a semiconductor structure. Figures 7 to 14 This is a schematic diagram of the structure corresponding to each step in the first embodiment of the semiconductor structure formation method of the present invention.

[0082] refer to Figure 7 Provides a base structure of 200.

[0083] The substrate structure 200 is used to provide a process platform for forming semiconductor structures.

[0084] In the step of providing the base structure 200, the base structure 200 includes a trimmed area I' and a central area II', the trimmed area I' surrounds the central area II', and the top of the base structure 200 of the trimmed area I' is lower than the top of the base structure 200 of the central area II'.

[0085] Trimming area I' is the area where the edges of the base structure 200 need to be trimmed. In this embodiment, during the step of providing the base structure 200, a base structure 200 with trimmed edges is provided. Therefore, the top of the base structure 200 in trimming area I' is lower than the top of the base structure 200 in center area II'.

[0086] Central area II' is used to provide a process platform for forming solder pads.

[0087] It should be noted that Central Area II' refers to all areas other than Border Area I'.

[0088] It should also be noted that after bonding the semiconductor structure to another semiconductor structure, the substrate structure 200 needs to undergo back-side thinning. Since the edges of the substrate structure 200 are usually arc-shaped, the arc-shaped edges of the remaining substrate structure 200 are prone to breakage during the back-side thinning process. Therefore, before the bonding process, the substrate structure 200 is trimmed, and a portion of the width of the substrate structure 200 is thinned along the edge from the bonding surface side, so that the surface of the substrate structure 200 at the edge position is vertically stepped. This ensures that when the back-side thinning process is performed on the substrate structure 200 to remove the untrimmed portion of the substrate structure 200, the surface of the substrate structure 200 at the edge position is vertically stepped, which helps to minimize the risk of breakage of the substrate structure 200 during the back-side thinning process.

[0089] In this embodiment, depending on the actual process, the substrate structure 200 includes a substrate (not shown) and a functional structure formed on the substrate. For example, the functional structure may include semiconductor devices such as MOS field-effect transistors or resistor structures.

[0090] As an example, the substrate is a silicon substrate. In other embodiments, the substrate material may also be one or more of germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride, or other types of substrates such as silicon-on-insulator or germanium-on-insulator.

[0091] It should be noted that the substrate can be a planar substrate or a substrate with channel protrusions.

[0092] Continue to refer to Figure 7 A dielectric layer 201 is formed on the substrate structure 200.

[0093] The dielectric layer 201 is used to provide a process basis for setting up a continuous bonding surface and also to achieve electrical isolation between the pads.

[0094] Specifically, the dielectric layer 201 is located on the substrate.

[0095] In this embodiment, the dielectric layer 201 includes: a first dielectric layer 230 located on the substrate structure 200; a second dielectric layer 231 located on top of the first dielectric layer 230; and a third dielectric layer 232 located on top of the second dielectric layer 231.

[0096] The first dielectric layer 230 is used to provide a process platform for forming the pad 103 and also to insulate adjacent pads 103 from each other.

[0097] In this embodiment, the material of the first dielectric layer 230 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxycarbide, silicon carbonitride, silicon carbonitride, low-k dielectric material (low-k dielectric material refers to dielectric material with a relative permittivity greater than or equal to 2.6 and less than or equal to 3.9) and ultra-low-k dielectric material (ultra-low-k dielectric material refers to dielectric material with a relative permittivity less than 2.6), thereby effectively reducing the parasitic capacitance between the solder pads and thus reducing the RC delay of the device.

[0098] As an example, the first dielectric layer 230 is made of silicon oxide. In other embodiments, the first dielectric layer may also be made of a low-k dielectric material, such as black diamond.

[0099] The third dielectric layer 232 is used to provide a process platform for forming solder pads and also to insulate adjacent solder pads from each other.

[0100] In this embodiment, the material of the third dielectric layer 232 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxycarbide, silicon carbonitride, silicon carbonitride, low-k dielectric material (low-k dielectric material refers to dielectric material with a relative permittivity greater than or equal to 2.6 and less than or equal to 3.9) and ultra-low-k dielectric material (ultra-low-k dielectric material refers to dielectric material with a relative permittivity less than 2.6), thereby effectively reducing the parasitic capacitance between the solder pads and thus reducing the RC delay of the device.

[0101] As an example, the material of the third dielectric layer 232 is silicon oxide. In other embodiments, the material of the third dielectric layer may also be a low-k dielectric material, for example, black diamond.

[0102] The top surface of the second dielectric layer 231 is used to define the etching stop position for etching the third dielectric layer 232.

[0103] The material of the second dielectric layer 231 is selected to have an etching selectivity ratio with that of the material of the third dielectric layer 232, so that the top surface of the second dielectric layer 231 can define the stop position of etching the third dielectric layer 232 during the etching process.

[0104] In this embodiment, the material of the second dielectric layer 231 includes silicon nitride. Specifically, there is an etching selectivity between silicon nitride and the material selected for the second dielectric layer 231, and silicon nitride can define the stop position for etching the third dielectric layer 232 during the subsequent etching process.

[0105] refer to Figure 8 After the dielectric layer 201 is formed on the substrate structure 200, and before the opening penetrating the dielectric layer 201 is formed, the method further includes: forming a sacrificial layer 202 on the dielectric layer 201.

[0106] The sacrificial layer 202 is used to occupy space for the filling layer that will be formed later, and also to provide a process basis for forming a continuous bonding surface.

[0107] It should be noted that the material of the sacrificial layer 202 has a removal selectivity ratio with the material of the formed solder pad, so that when the sacrificial layer 202 is removed in the future, the probability of the solder pad being damaged is reduced.

[0108] In this embodiment, in the step of forming a sacrificial layer 202 on the dielectric layer 201, the material of the sacrificial layer 202 includes silicon nitride.

[0109] Specifically, silicon nitride is easy to remove, and at the same time, silicon nitride and the material of the formed pad have a removal selectivity, thereby reducing the probability of the pad being damaged when the sacrificial layer 202 is subsequently removed.

[0110] In this embodiment, during the step of forming the sacrificial layer 202 on the dielectric layer 201, the thickness of the sacrificial layer 202 should not be too large. If the thickness of the sacrificial layer 202 is too large, the process time for removing the sacrificial layer 202 in the subsequent process will easily increase, thereby easily reducing production efficiency. Therefore, in this embodiment, the thickness of the sacrificial layer 202 is less than 10 nanometers.

[0111] refer to Figure 9 In this embodiment, after the sacrificial layer 202 is formed and before the opening is formed, the method further includes: forming a bottom anti-reflective coating 205 that conformally covers the sacrificial layer 202.

[0112] The bottom anti-reflective coating 205 is used to reduce the amount of light reflected back to the mask layer from the surface of the sacrificial layer 202 during the exposure process of forming the mask layer, so as to reduce the standing wave effect.

[0113] In this embodiment, the material of the bottom anti-reflective coating 205 includes silicon oxynitride.

[0114] refer to Figures 9 to 10 An opening 203 is formed that penetrates the dielectric layer 201.

[0115] The opening 203 is used to provide space for the subsequent formation of solder pads.

[0116] In this embodiment, in the step of forming an opening 203 through the dielectric layer 201, the opening 203 is located in the central region II'.

[0117] In this embodiment, since a sacrificial layer 202 is formed on the dielectric layer 201, an opening 203 is formed that penetrates the sacrificial layer 202 and the dielectric layer 201.

[0118] In this embodiment, a dry etching process is used to etch the sacrificial layer 202 and the dielectric layer 201 to form an opening 203.

[0119] Specifically, the dry etching process has anisotropic etching characteristics, making the etching more directional, which is beneficial for improving the morphology and dimensional accuracy of the opening 203.

[0120] It should be noted that in this embodiment, the opening 203 exposes the top of the substrate structure 200, thereby enabling the solder pads subsequently formed in the opening 203 to be electrically connected to the devices inside the substrate structure 200.

[0121] Specifically, the step of forming the opening 203 through the dielectric layer 201 includes: referring to Figure 9 A patterned mask layer 204 is formed on top of the bottom anti-reflective coating 205; Reference Figure 10 Using a patterned mask layer 204 as a mask, the bottom anti-reflective coating 205, sacrificial layer 202 and dielectric layer 201 are patterned sequentially from top to bottom to form an opening 203 that penetrates the sacrificial layer 202 and dielectric layer 201.

[0122] The patterned mask layer 204 serves as a mask for the patterned bottom anti-reflective coating 205, the sacrificial layer 202, and the dielectric layer 201. As an example, the material of the mask layer 204 includes photoresist.

[0123] Specifically, after photoresist is coated on top of the bottom anti-reflective coating 205, the photoresist is patterned through a photolithography process to form a patterned mask layer 204.

[0124] refer to Figure 11 After forming the opening 203 and before forming the solder pad 206, the process also includes: removing the mask layer 204.

[0125] refer to Figures 11 to 14 A continuous bonding surface 209 is formed on the top of the dielectric layer 201 (e.g., Figure 14 (as shown); a solder pad 206 is formed in the opening 203 (as shown). Figure 14 As shown, the top of the solder pad 206 is flush with the bonding surface 209.

[0126] The bonding surface 209 at the location of the dielectric layer 201 is used to achieve bonding.

[0127] The pad 206 is used to bring out the electrical properties of the devices inside the substrate structure 200. In addition, when the semiconductor structure is subsequently bonded to another semiconductor structure, the pad 206 is also used to contact the pads of other semiconductor structures to achieve bonding between the semiconductor structures.

[0128] It should be noted that, since the bonding surface 209 is continuous, the flatness of the bonding surface 209 is improved, and the bonding strength of the bonding surface 209 is increased accordingly. Moreover, the top surface of the pad 206 is flush with the bonding surface 209, and the flatness between the top surface of the pad 206 and the bonding surface 209 at the position of the dielectric layer 201 is also relatively high. Therefore, after bonding using the semiconductor structure, the probability of edge chipping of the bonding surface 209 is reduced, and the packaging reliability and packaging yield of the semiconductor structure are improved.

[0129] In this embodiment, the material of the solder pad 206 is metal. The metal solder pad 206 can provide the main bonding strength for the bonding surface and achieve high-strength interconnection through atomic diffusion bonding.

[0130] Specifically, the material of solder pad 206 includes copper. Copper, in particular, has good electrical conductivity.

[0131] As an example, the material of the solder pad 206 includes copper. Copper has good diffusion properties, so when the solder pad 206 is heated during the subsequent bonding of the semiconductor structure, the material of the solder pad 206 is easy to diffuse, thus the bonding performance of the solder pad 206 is good during the subsequent bonding of the semiconductor structure.

[0132] The solder pad 206 can have a single damask structure or a double damask structure. As an example, the solder pad 206 has a double damask structure.

[0133] It should be noted that in this embodiment, the structure of the solder pad 206 is a double damask structure, which helps to reduce the number of planarization processes used when forming the solder pad 206, thereby reducing the probability of depressions appearing on the top surface of the solder pad 206 and facilitating the formation of a continuous bonding surface in the future.

[0134] The steps for forming the pad 206 in the opening 203 are described in detail below with reference to the accompanying drawings.

[0135] refer to Figure 11 This forms a pad material layer 207 that fills the opening 203.

[0136] The pad material layer 207 is used to form the pad 206.

[0137] Accordingly, in this embodiment, in the step of forming the pad material layer 207 that fills the opening 203, the material of the pad material layer 207 is copper.

[0138] In this embodiment, before forming the pad material layer 207 that fills the opening 203, the method further includes: forming a conformal covering barrier material layer (not shown) on the sidewalls and bottom of the opening 203; and forming a conformal covering seed material layer (not shown) on top of the barrier material.

[0139] The barrier material layer is used for the barrier layer that is formed subsequently.

[0140] The seed material layer is used for the subsequent formation of the seed layer.

[0141] In this embodiment, after forming a pad material layer 207 that fills the opening 203, the pad material layer 207 also covers the sacrificial layer 202.

[0142] refer to Figure 12 Using the top surface of the sacrificial layer 202 as the stopping position, the pad material layer 207 is planarized, and the pad material layer 207 located in the opening 203 is retained as the pad 206.

[0143] It should be noted that planarizing the pad material layer 207 and removing the pad material layer 207 that is higher than the sacrificial layer 202 helps to reduce the unevenness of the pad 206 surface and provides a flat bonding surface for subsequent bonding processes.

[0144] In this embodiment, a chemical mechanical polishing (CMP) process is used to planarize the pad material layer 207 and remove the pad material layer 207 that is higher than the sacrificial layer 202.

[0145] Chemical mechanical polishing combines the advantages of chemical polishing and mechanical polishing, ensuring the simultaneous and efficient removal of the pad material layer 207 above the sacrificial layer 202, and obtaining a better pad 206 surface.

[0146] In this embodiment, the planarization process of the pad material layer 207 with the top surface of the sacrificial layer 202 as the stop position also includes: planarizing the barrier material layer to form a barrier layer (not shown); and planarizing the seed material layer to form a seed layer (not shown).

[0147] The barrier layer serves to prevent the diffusion of metal ions in the solder pad 206.

[0148] The barrier layer is made of one or both of tantalum nitride and tantalum. Specifically, both tantalum nitride and tantalum can effectively block ion diffusion.

[0149] As an example, the barrier layer is made of tantalum nitride.

[0150] The seed layer provides a uniform starting surface for the subsequent formation of solder pads, which helps to reduce the probability of defects such as voids and cracks in the subsequent solder pad formation, thereby improving the quality and reliability of the formed solder pads.

[0151] It should be noted that the material of the seed layer is determined by the material of the solder pad 206. In this embodiment, the seed layer is made of copper. In other embodiments, the seed layer may also be made of other metal materials suitable for the growth of solder pad materials.

[0152] refer to Figure 13 After forming the solder pad 206 in the opening 203, the forming method further includes forming a recess 208 on the side of the solder pad 206, the recess 208 being surrounded by the top of the dielectric layer 201 and the sidewall of the solder pad 206.

[0153] The recess 208 is used to provide space for the subsequent filling layer.

[0154] In this embodiment, the step of forming a recess 208 on the side of the solder pad 206 includes: removing the sacrificial layer 202.

[0155] It should be noted that the top of the base structure 200 of the trimmed area I' is lower than the top of the base structure 200 of the central area II'. That is, a step is formed at the junction of the trimmed area I' and the central area II' of the base structure 200. During the process of forming the patterned mask layer 204 on the sacrificial layer 202, when the mask layer 204 accumulates at the step, the mask layer 204 at the step can be removed at the same time by removing the sacrificial layer 202.

[0156] In this embodiment, the process of removing the sacrificial layer 202 includes a wet etching process.

[0157] Specifically, wet etching processes can easily achieve a high etching selectivity between the object being etched (sacrificial layer 202) and other film layers (e.g., dielectric layer 201, solder pad 206), thereby reducing damage to other film layers.

[0158] In this embodiment, the solution used in the wet etching process includes phosphoric acid, and the temperature of the wet etching process is 100 degrees Celsius to 200 degrees Celsius.

[0159] Specifically, phosphoric acid in the wet etching process, with a temperature range of 100°C to 200°C, has a high etching selectivity between the sacrificial layer 202 and the solder pad 206, which helps to reduce the probability of damage to the solder pad 206 during the removal of the sacrificial layer 202.

[0160] refer to Figure 14 In this embodiment, the top of the dielectric layer 201 has a bonding surface 209, and the top of the solder pad 206 also has a bonding surface (not shown), thus enabling hybrid bonding.

[0161] The bonding surface 209 is the surface for bonding semiconductor structures. After bonding between semiconductor structures is achieved, electrical connections between the circuit structure layers of the semiconductor structure can be realized, thereby realizing the normal function of the package structure.

[0162] Continue to refer to Figure 14 In this embodiment, the step of forming a continuous bonding surface 209 on the top of the dielectric layer 201 includes: forming a filler layer 210 in the recess 208, the filler layer 210 exposing the top surface of the solder pad 206 and forming a bonding surface 209 provided by the top surface of the filler layer 210, wherein the coefficient of thermal expansion of the filler layer 210 is greater than the coefficient of thermal expansion of the solder pad 206 and the coefficient of thermal expansion of the filler layer 210 is greater than the coefficient of thermal expansion of the dielectric layer 201.

[0163] In this embodiment, since the coefficient of thermal expansion of the filler layer 210 is greater than that of the solder pad 206, and the coefficient of thermal expansion of the filler layer 210 is greater than that of the dielectric layer 201, while the coefficient of thermal expansion of the dielectric layer 201 is less than that of the solder pad 206, the filler layer 210 balances the thermal mismatch between the solder pad 206 and the dielectric layer 201. This improves the flatness between the bonding surface 209 on the top of the dielectric layer 201 and the bonding surface on the top of the solder pad 206, thereby reducing the probability of depressions appearing on the bonding surface 209 on the top of the dielectric layer 201, and thus improving the packaging reliability and packaging yield of the semiconductor structure.

[0164] Specifically, the thickness of the filler layer 210 should not be too large. If the thickness of the filler layer 210 is too large, during the subsequent bonding of the semiconductor structure with another semiconductor structure to form a bonded wafer, the excessive thermal expansion force of the filler layer 210 may generate a reverse force on the bonding force between the dielectric layers 201 of the bonded wafer. This can easily lead to poor results in reducing edge chipping on the bonding surface 209 of the bonded wafer, and consequently, poor results in improving the packaging reliability and packaging yield of the semiconductor structure. Therefore, in this embodiment, the thickness of the filler layer 210 is less than 10 nanometers, for example, the thickness of the filler layer 210 is 3 nanometers.

[0165] It should be noted that the coefficient of thermal expansion of the filler layer 210 should not be too large or too small. If the coefficient of thermal expansion of the filler layer 210 is too large, during the subsequent bonding of the semiconductor structure with another semiconductor structure to form a bonded wafer, the excessive thermal expansion force of the filler layer 210 may generate a reverse force on the bonding force between the dielectric layers 201 of the bonded wafer. This may result in poor performance in reducing edge chipping on the bonding surface 209 of the bonded wafer, thereby hindering the improvement of the packaging reliability and yield of the semiconductor structure. If the coefficient of thermal expansion of the filler layer 210 is too small, its effect in balancing the thermal mismatch between the pads 206 and the dielectric layer 201 may be insignificant. Therefore, in this embodiment, the coefficient of thermal expansion of the filler layer 210 is 2 × 10⁻⁶. -5 Up to 3×10 per degree Celsius -5 Every degree Celsius.

[0166] The filler layer 210 is made of polyimide.

[0167] Specifically, the coefficient of thermal expansion of polyimide is greater than that of the solder pad 206, and the coefficient of thermal expansion of polyimide is greater than that of the dielectric layer 201. Therefore, the filler layer 210 formed by polyimide balances the thermal mismatch between the solder pad 206 and the dielectric layer 201. At the same time, the bonding strength of polyimide is greater than that of the dielectric layer 201, thereby effectively ensuring the progress of subsequent processes.

[0168] In this embodiment, the filler layer 210 is made of polyimide.

[0169] In this embodiment, the step of forming a filling layer 210 in the recess 208 includes: filling the recess 208 to form a filling material layer (not shown) covering the dielectric layer 201 and the solder pad 206; and performing a planarization process on the filling material layer until the top surface of the solder pad 206 is exposed.

[0170] The filler material layer is used as the material for filler layer 210.

[0171] In this embodiment, the filler material layer is planarized until the top surface of the solder pad 206 is exposed. This helps to reduce the unevenness of the solder pad 206 and the filler layer 210 surface, and helps to provide a flat bonding surface for subsequent bonding processes.

[0172] In this embodiment, a chemical mechanical polishing process is used to planarize the filler material layer.

[0173] Chemical mechanical polishing combines the advantages of chemical polishing and mechanical polishing, ensuring the simultaneous and efficient removal of the filler material layer and obtaining a better bonding surface 209.

[0174] In this embodiment, the top of the pad 206 is flush with the bonding surface 209 to improve the flatness between the top of the pad 206 and the bonding surface 209. When the semiconductor structure is used for bonding, it helps to reduce the probability of void defects at the bonding surface 209.

[0175] It should be noted that in other embodiments, the bonding surface may be provided solely through the top surface of the dielectric layer.

[0176] Accordingly, after forming a dielectric layer on the substrate structure and before forming an opening through the dielectric layer, the method further includes: forming a sacrificial layer on the dielectric layer; in the step of forming the opening, forming an opening through the sacrificial layer and the dielectric layer; the step of forming a continuous bonding surface on the top of the dielectric layer includes: after forming a solder pad in the opening, removing the sacrificial layer and forming a bonding surface provided by the top surface of the dielectric layer.

[0177] During the process of forming a patterned mask layer on the sacrificial layer, when the mask layer accumulates at the step, the accumulated mask layer can be removed at the same time by removing the sacrificial layer, so that the top surface of the dielectric layer is exposed, thereby providing a continuous bonding surface.

[0178] Accordingly, embodiments of the present invention also provide a packaging structure. Figure 15 This is a schematic diagram of an embodiment of the packaging structure of the present invention.

[0179] refer to Figure 15 The packaging structure includes: a first wafer 400 and a second wafer 401 stacked and bonded together, wherein one or both of the first wafer 400 and the second wafer 401 adopt the semiconductor structure of any embodiment of the present invention; the bonding surfaces 403 of the first wafer 400 and the second wafer 401 are disposed opposite to each other, and bonding is achieved through the bonding surfaces 403 and the pads 404.

[0180] It should be noted that, since at least one of the first wafer 400 and the second wafer 401 has a continuous bonding surface 403 on the top of the dielectric layer, the bonding strength of the bonding surface 403 is increased accordingly. Moreover, the top surface of the pad 404 is flush with the bonding surface 403, and the top surface of the pad 404 and the bonding surface 403 form a continuous bonding surface, which reduces the probability of gaps appearing in the bonding surface 403, thereby improving the packaging reliability and product yield of the semiconductor structure.

[0181] In this embodiment, the first wafer 400 and the second wafer 401 are both semiconductor structures of any embodiment of the present invention. For a detailed description of the first wafer 400 and the second wafer 401, please refer to the foregoing embodiments, and will not be repeated here.

[0182] The bonding surfaces 403 of the first wafer 400 and the second wafer 401 are arranged opposite to each other, and bonding is achieved through the bonding surfaces 403 and the pads 404, thereby improving the bonding strength of the first wafer 400 and the second wafer 401.

[0183] It should be noted that the dimensions of the pads 404 of the first wafer 400 and the second wafer 401 may be equal or unequal. Therefore, the pads 404 of the first wafer 400 and the second wafer 401 may overlap or partially overlap.

[0184] In this embodiment, the packaging structure further includes a filler layer 405 located on the dielectric layer 406, the top surface of the filler layer 405 being the bonding surface 403, the thermal expansion coefficient of the filler layer 405 being greater than the thermal expansion coefficient of the solder pad 404, and the thermal expansion coefficient of the filler layer 405 being greater than the thermal expansion coefficient of the dielectric layer 406.

[0185] For a description of the semiconductor structure, please refer to the relevant content in the foregoing embodiments, which will not be repeated here.

[0186] Accordingly, embodiments of the present invention also provide a packaging method. Figures 16 to 20 This is a schematic diagram of the structure corresponding to each step in one embodiment of the packaging method of the present invention.

[0187] The encapsulation method of this embodiment will be described in detail below with reference to the accompanying drawings.

[0188] refer to Figures 16 to 17 Provide the first wafer 500 (e.g.) Figure 16 (as shown) and the second wafer 501 (as shown) Figure 17 As shown), one or both of the first wafer 500 and the second wafer 501 adopt the semiconductor structure of any embodiment of the present invention.

[0189] A first wafer 500 and a second wafer 501 are provided so that the first wafer 500 and the second wafer 501 can be bonded together in the future.

[0190] In this embodiment, the first wafer 500 and the second wafer 501 are both semiconductor structures of any embodiment of the present invention. For a detailed description of the first wafer 500 and the second wafer 501 in this embodiment, please refer to the corresponding descriptions in the foregoing embodiments. This embodiment will not repeat the descriptions here.

[0191] In this embodiment, before bonding the first wafer 500 and the second wafer 501, a pre-treatment process is performed on the bonding surface 503 and the pad 504.

[0192] Specifically, pretreatment of the bonding surface 503 and the solder pad 504 helps to remove residues (e.g., organic residues) on the bonding surface 503 and the solder pad 504, thereby improving the flatness of the bonding surface 503 and thus improving the bonding strength.

[0193] As an example, the pretreatment process for the bonding surface 503 and the pad 504 includes a cleaning process.

[0194] In this embodiment, after pre-treating the bonding surface 503 and the solder pad 504, before bonding the first wafer 500 and the second wafer 501, the method further includes: performing surface activation treatment on the bonding surface 503 and the solder pad 504.

[0195] It should be noted that the bonding surface 503 is subjected to surface activation treatment to activate the surface material of the bonding surface 503 and improve the bonding strength of the bonding surface 503.

[0196] Specifically, in this embodiment, a surface activation process is used to perform surface activation treatment on the bonding surface 503 and the pad 504.

[0197] The surface activation process can activate the bonding surface 503 and the pad 504, thereby enabling better bonding of the first wafer 500 and the second wafer 501 through the bonding surface 503 and the pad 504.

[0198] refer to Figure 18 The bonding surfaces 503 of the first wafer 500 and the second wafer 501 are arranged opposite each other, and the pads 504 of the first wafer 500 and the second wafer 501 are arranged opposite each other. In subsequent bonding processes, this helps to improve the alignment accuracy of the bonding surfaces 503 and the pads 504, thereby improving the bonding strength.

[0199] refer to Figure 19 The first wafer 500 and the second wafer 501 are bonded together through the bonding surface 503 and the pad 504 that are disposed opposite to each other, forming a bonded wafer 505.

[0200] Specifically, in the semiconductor structure provided in the embodiments of the present invention, a filling layer 507 is formed on the top of the dielectric layer 506. The filling layer 507 exposes the top surface of the bonding pad 504 and forms a bonding surface 503 provided by the top surface of the filling layer 507. The coefficient of thermal expansion of the filling layer 507 is greater than that of the bonding pad 504, and the coefficient of thermal expansion of the filling layer 507 is greater than that of the dielectric layer 506.

[0201] It should be noted that, in the first wafer 500 and the second wafer 501, at least one of them has a continuous bonding surface 503 on the top of the dielectric layer, which increases the bonding strength of the bonding surface 503 and reduces the probability of edge chipping on the bonding surface 503, thereby improving the packaging reliability and product yield of the semiconductor structure.

[0202] It should also be noted that the dimensions of the pads 504 of the first wafer 500 and the second wafer 501 may be equal or unequal. Therefore, the pads 504 of the first wafer 500 and the second wafer 501 may overlap or partially overlap.

[0203] In this embodiment, the process of forming a bonding wafer from the first wafer 500 and the second wafer 501 includes a hybrid bonding process.

[0204] Specifically, in the hybrid bonding process, the bonding surfaces 503 on the side of the pad 504 are bonded to each other, and the pads 504 are bonded to each other, which increases the total bonding surface area between the first wafer 500 and the second wafer 501. Correspondingly, the bonded wafer 505 formed after the first wafer 500 and the second wafer 501 are bonded to each other is less likely to fall off.

[0205] Continue to refer to Figure 19 Annealing is performed on the bonding pads 504 of the bonding wafer 505.

[0206] It should be noted that the bonding pads 504 of the bonding wafer 505 are annealed, which causes the bonding pads 504 of the first wafer 500 and the second wafer 501 to expand, thereby promoting the bonding pads 504 of the first wafer 500 and the second wafer 501 to connect.

[0207] In this embodiment, the annealing process temperature should not be too high or too low. If the process temperature is too high, it can easily lead to drift in the electrical properties of the semiconductor device; if the process temperature is too low, it can easily result in insufficient bonding between the first wafer 500 and the second wafer 501, leading to poor fragmentation reduction during subsequent wafer thinning. Furthermore, it can also cause a decrease in the interconnect resistance between the bonding pads 504, or even interconnect failure. Therefore, in this embodiment, the annealing process temperature is between 300 and 400 degrees Celsius.

[0208] refer to Figure 20 After annealing the bonding pads 504 of the bonding wafer 505, the packaging method further includes: thinning the side of the first wafer 500 facing away from the bonding surface 503; or thinning the side of the second wafer 501 facing away from the bonding surface 503.

[0209] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: Substrate structure; A dielectric layer is located on the substrate structure, and the top of the dielectric layer has a continuous bonding surface; A solder pad penetrates the dielectric layer, the top surface of the solder pad being exposed by the bonding surface, and the top surface of the solder pad being flush with the bonding surface.

2. The semiconductor structure as described in claim 1, characterized in that, The semiconductor structure further includes: a filling layer located on the dielectric layer, the top surface of the filling layer being the bonding surface, the thermal expansion coefficient of the filling layer being greater than the thermal expansion coefficient of the bonding pad, and the thermal expansion coefficient of the filling layer being greater than the thermal expansion coefficient of the dielectric layer.

3. The semiconductor structure as described in claim 2, characterized in that, The thickness of the filling layer is less than 10 nanometers.

4. The semiconductor structure as described in claim 2, characterized in that, The coefficient of thermal expansion of the filler layer is 2×10⁻⁶. -5 Up to 3×10 per degree Celsius -5 Every degree Celsius.

5. The semiconductor structure as described in claim 2, characterized in that, The filler layer is made of polyimide.

6. The semiconductor structure as described in claim 1, characterized in that, The substrate structure includes a trimmed area and a central area, the trimmed area surrounding the central area, and the top of the substrate structure in the trimmed area being lower than the top of the substrate structure in the central area; the solder pad penetrates the dielectric layer located in the central area.

7. The semiconductor structure as described in claim 1, characterized in that, The material of the solder pad includes copper.

8. A method for forming a semiconductor structure, characterized in that, include: Provide the base structure; A dielectric layer is formed on the substrate structure; A continuous bonding surface is formed on top of the dielectric layer; An opening is formed that penetrates the dielectric layer; A solder pad is formed in the opening, with the top of the solder pad flush with the bonding surface.

9. The method for forming a semiconductor structure as described in claim 8, characterized in that, After forming a solder pad in the opening, the forming method further includes: forming a recess on the side of the solder pad, the recess being surrounded by the top of the dielectric layer and the sidewall of the solder pad; The step of forming a continuous bonding surface on top of the dielectric layer includes: forming a filler layer in the recess, the filler layer exposing the top surface of the solder pad and forming a bonding surface provided by the top surface of the filler layer, the filler layer having a thermal expansion coefficient greater than that of the solder pad and the filler layer having a thermal expansion coefficient greater than that of the dielectric layer.

10. The method for forming a semiconductor structure as described in claim 9, characterized in that, After forming a dielectric layer on the substrate structure and before forming an opening through the dielectric layer, the method further includes: forming a sacrificial layer on the dielectric layer; An opening is formed that penetrates the sacrificial layer and the dielectric layer; The step of forming a recess on the side of the solder pad includes removing the sacrificial layer.

11. The method for forming a semiconductor structure as described in claim 8, characterized in that, After forming a dielectric layer on the substrate structure and before forming an opening penetrating the dielectric layer, the method further includes: forming a sacrificial layer on the dielectric layer; An opening is formed that penetrates the sacrificial layer and the dielectric layer; The step of forming a continuous bonding surface on top of the dielectric layer includes: after forming a solder pad in the opening, removing the sacrificial layer and forming a bonding surface provided by the top surface of the dielectric layer.

12. The method for forming a semiconductor structure as described in claim 10 or 11, characterized in that, In the step of forming a sacrificial layer on the dielectric layer, the material of the sacrificial layer includes silicon nitride.

13. The method for forming a semiconductor structure as described in claim 10 or 11, characterized in that, In the step of forming a sacrificial layer on the dielectric layer, the thickness of the sacrificial layer is less than 10 nanometers.

14. The method for forming a semiconductor structure as described in claim 10 or 11, characterized in that, The step of forming the solder pad in the opening includes: forming a solder pad material layer that fills the opening; Using the top surface of the sacrificial layer as the stopping position, the pad material layer is planarized, and the pad material layer located in the opening is retained as the pad.

15. The method for forming a semiconductor structure as described in claim 10 or 11, characterized in that, The process for removing the sacrificial layer includes a wet etching process.

16. The method for forming a semiconductor structure as described in claim 9, characterized in that, The step of forming a filler layer in the recess includes: filling the recess to form a filler material layer covering the dielectric layer and the solder pad; The filler material layer is planarized until the top surface of the solder pad is exposed.

17. The method for forming a semiconductor structure as described in claim 8, characterized in that, In the step of providing a base structure, the base structure includes a trimmed area and a central area, the trimmed area surrounds the central area, and the top of the base structure in the trimmed area is lower than the top of the base structure in the central area; In the step of forming an opening through the dielectric layer, the opening is located in the central region.

18. A packaging structure, characterized in that, include: A first wafer and a second wafer are stacked and bonded, wherein one or both of the first wafer and the second wafer comprise the semiconductor structure as described in any one of claims 1 to 7; The bonding surfaces of the first wafer and the second wafer are arranged opposite to each other, and bonding is achieved through the bonding surfaces and the solder pads.

19. A packaging method, characterized in that, include: A first wafer and a second wafer are provided, wherein one or both of the first wafer and the second wafer comprise the semiconductor structure as described in any one of claims 1 to 7; The bonding surfaces of the first wafer and the second wafer are arranged opposite each other, and the pads of the first wafer and the second wafer are arranged opposite each other. The first wafer and the second wafer are bonded together through the bonding surfaces and the bonding pads that are arranged opposite to each other to form a bonded wafer; The bonding pads of the bonded wafer are annealed.

20. The packaging method as described in claim 19, characterized in that, The annealing process parameters include a process temperature of 300 degrees Celsius to 400 degrees Celsius.

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