Chip on film package structure

Abstract

A thin film flip chip package structure includes a flexible substrate, a plurality of pins, and a chip. The flexible substrate has a chip bonding region. The plurality of pins is disposed on the flexible substrate and each pin has an inner pin portion extending into the chip bonding region, wherein the plurality of pins includes a first pin, and a first inner pin portion of the first pin has an opening. The chip is disposed in the chip bonding region, wherein the chip has a plurality of bumps corresponding to the inner pin portions of the plurality of pins respectively and each having an inner pin bonding region overlapping with the inner pin portion. The plurality of bumps includes a first bump corresponding to the first inner pin portion and having a first inner pin bonding region, and a normal projection of the opening on the first bump is located in the first inner pin bonding region.

Description

Technical Field

[0001] This invention relates to a packaging structure, and more particularly to a thin-film flip-chip packaging structure. Background Technology

[0002] Generally, chip-on-film (COF) packaging structures use flip-chip bonding to attach multiple bumps on a chip to multiple pins on a flexible substrate. The bumps and pins are typically connected by thermoforming, forming a eutectic layer around the interface between the bump and the corresponding pin. However, due to specific requirements, some pins may need to be wider, such as power pins, which need to be designed to withstand higher voltages and prevent burn-out. However, as the pin width increases, the bonding strength of the eutectic layer around the bump-pin interface decreases, making the pin easier to peel off from the bump, leading to electrical abnormalities and reduced reliability of the COF packaging structure. Therefore, improving the bonding strength between the pin and the chip is a problem that needs to be addressed. Summary of the Invention

[0003] This invention relates to a thin-film flip-chip packaging structure that avoids pin stripping and improves reliability.

[0004] According to an embodiment of the present invention, a thin-film flip-chip package structure includes a flexible substrate, a plurality of pins, and a chip. The flexible substrate has a chip bonding region. The plurality of pins are disposed on the flexible substrate, and each pin has an inner pin portion extending into the chip bonding region, wherein the plurality of pins includes a first pin, and the first inner pin portion of the first pin has an opening. The chip is disposed in the chip bonding region, wherein the chip has a plurality of bumps, the plurality of bumps respectively corresponding to and connecting the inner pin portions of the plurality of pins and each having an inner pin bonding region overlapping with the inner pin portion. The plurality of bumps includes a first bump, the first bump corresponding to and connecting to the first inner pin portion and having a first inner pin bonding region, and the orthogonal projection of the opening on the first bump is located within the first inner pin bonding region.

[0005] In the thin-film flip-chip packaging structure according to an embodiment of the present invention, a metal eutectic layer is provided between the plurality of bumps and the plurality of internal pins respectively connected thereto, and the metal eutectic layer is located at least around the internal pin bonding area of ​​each bump.

[0006] In the thin-film flip-chip packaging structure according to an embodiment of the present invention, the two opposite sides of each inner pin bonding area correspond to the two opposite long sides of the inner pin portion, wherein a metal eutectic layer is formed on the sidewalls of the two opposite long sides of the inner pin portion.

[0007] In the thin-film flip-chip packaging structure according to an embodiment of the present invention, the aforementioned metal eutectic layer is further filled into the opening of the first inner lead portion and formed on the inner sidewall formed by the opening of the first inner lead portion.

[0008] In the thin-film flip-chip package structure according to an embodiment of the present invention, either side of the aforementioned opening is located within the first inner pin bonding region.

[0009] In the thin-film flip-chip package structure according to an embodiment of the present invention, the width of the opening is between 1 / 4 and 1 / 6 of the width of the first pin.

[0010] In the thin-film flip-chip packaging structure according to an embodiment of the present invention, the width of the opening is greater than or equal to 3 micrometers.

[0011] In the thin-film flip-chip packaging structure according to an embodiment of the present invention, the length of the opening is less than the length of the first bump.

[0012] In the thin-film flip-chip packaging structure according to an embodiment of the present invention, the plurality of pins further includes a plurality of second pins, wherein the width of the plurality of second pins is smaller than the width of the first pin.

[0013] In the thin-film flip-chip package structure according to an embodiment of the present invention, the width of the first pin is greater than or equal to twice the width of the plurality of second pins.

[0014] Based on the above, the thin-film flip-chip packaging structure of the present invention selectively provides an opening in the inner pin portion of the pin for pins that are prone to self-bump peeling, so that the opening is located in the inner pin bonding area of ​​the bump. In this way, the metal eutectic layer formed by the bonding of the bump and the inner pin portion can be filled into the opening, increasing the metal eutectic layer adhesion area, thereby improving the bonding strength between the pin and the corresponding bump, reducing the possibility of pin peeling off from the bump, and effectively improving the reliability of the thin-film flip-chip packaging structure. Attached Figure Description

[0015] Figure 1 This is a top view schematic diagram of a thin-film flip-chip packaging structure according to an embodiment of the present invention;

[0016] Figure 2 yes Figure 1 A top-view diagram of region R1;

[0017] Figure 3 yes Figure 2 A partial top-view diagram of region R2;

[0018] Figure 4 This is a partial cross-sectional schematic diagram of a thin-film flip-chip packaging structure according to an embodiment of the present invention. Detailed Implementation

[0019] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same component reference numerals are used in the drawings and description to denote the same or similar parts.

[0020] Figure 1 This is a top view schematic diagram of a thin-film flip-chip packaging structure according to an embodiment of the present invention. Figure 2 yes Figure 1 A top-view diagram of region R1. Figure 3 yes Figure 2 A partial top-view diagram of region R2. Figure 4 This is a partial cross-sectional schematic diagram of a thin-film flip-chip packaging structure according to an embodiment of the present invention. For clarity, Figure 1 Some components (such as chip 120 and solder mask 150) are shown in perspective. Figure 2 and Figure 3 Only pin 110 and bump 130 are shown, while other components are omitted, and bump 130 is shown in perspective. Figure 4 It can be along Figure 1 , Figure 2 A cross-sectional view of section line A-A'.

[0021] Please refer to Figures 1 to 4 The thin-film flip-chip package structure 10 includes a flexible substrate 100, a plurality of pins 110, and a chip 120. The flexible substrate 100 has a chip bonding region 100A, and the plurality of pins 110 are disposed on the flexible substrate 100, each pin 110 having an inner pin portion 110a extending into the chip bonding region 100A. The chip 120 is disposed in the chip bonding region 100A, wherein the chip 120 has a plurality of bumps 130, the plurality of bumps 130 respectively corresponding to and connecting to the inner pin portions 110a of the plurality of pins 110, and each having an inner pin bonding region 130a overlapping with the inner pin portions 110a.

[0022] In some embodiments, the flexible substrate 100 may include polyethylene terephthalate (PET), polyimide (PI), polyethersulfone (PES), polycarbonate (PC), or other suitable flexible materials. In some embodiments, the chip 120 may include a logic chip, a driver chip, a power chip, a memory chip, or other suitable chips, and the invention is not limited thereto.

[0023] In some embodiments, the thin-film flip-chip package structure 10 further includes a solder resist layer 150 disposed on the flexible substrate 100 and partially covering a plurality of pins 110 to protect the pins 110 from moisture, dust, foreign matter, etc. The solder resist layer 150 does not cover the chip bonding area 100A, exposing the inner pin portion 110a of the pins 110 for connection with the bumps 130 of the chip 120.

[0024] In some embodiments, the plurality of pins 110 includes a first pin 112 and a second pin 114. The first pin 112 may be, for example, a power supply pin, and the second pin 114 may be, for example, a signal pin, but the invention is not limited thereto. Figure 1 The diagram schematically shows a first pin 112 and a plurality of second pins 114, but is not intended to limit the invention. The number of first pins 112 and second pins 114 can be adjusted according to actual needs.

[0025] In some embodiments, the width W1 of the first pin 112 is greater than the width W2 of the second pin 114. For example, the width W1 of the first pin 112 may be greater than or equal to twice the width W2 of the second pin 114, i.e., W1 ≥ 2W2. In this document, width refers to the width measured in a direction perpendicular to the extension direction of the pin. Figure 2 For example, the first pin 112 and the second pin 114 extend in the y direction, so the widths W1 and W2 are measured in the x direction, which is perpendicular to the y direction.

[0026] In some embodiments, the first inner pin portion 112a of the first pin 112 has an opening OP, while the second inner pin portion 114a of the second pin 114 does not have an opening. The opening OP penetrates the first pin 112 and forms the inner sidewall SW1 of the first pin 112. In other words, the inner sidewall SW1 of the first pin 112 defines the opening OP. In some embodiments, the shape of the opening OP, from a top view perspective, includes a rectangle or other suitable shape, and the present invention is not limited thereto. Here, the first inner pin portion 112a and the second inner pin portion 114a are collectively referred to as inner pin portion 110a.

[0027] In some embodiments, the plurality of bumps 130 of the chip 120 include a first bump 132 and a second bump 134. The first bump 132 is correspondingly connected to a first internal pin portion 112a and has a first internal pin bonding region 132a, which is the area covered on the first bump 132 by the bonding interface between the first internal pin portion 112a and the first bump 132. The second bump 134 is correspondingly connected to a second internal pin portion 114a and has a second internal pin bonding region 134a, which is the area covered on the second bump 134 by the bonding interface between the second internal pin portion 114a and the second bump 134. Here, the first internal pin bonding region 132a and the second internal pin bonding region 134a are collectively referred to as internal pin bonding region 130a.

[0028] In some embodiments, such as Figure 3 As shown, the two opposite sides S1 and S2 (e.g., the two sides extending along the y direction) of each inner pin engagement area 130a can respectively correspond to the two opposite long sides 110s1 and 110s2 (i.e., the sides extending in the extension direction (i.e., the y direction)) of the inner pin portion 110a, while the other two opposite sides S3 and S4 (e.g., the two sides extending along the x direction) of each inner pin engagement area 130a can respectively correspond to the two opposite sides 130s1 and 130s2 of the bump 130 extending in the x direction.

[0029] In some embodiments, the width of the bump 130 is greater than the width of the corresponding pin 110. For example, the width W3 of the first bump 132 is greater than the width W1 of the first pin 112, and the width W4 of the second bump 134 is greater than the width W2 of the second pin 114.

[0030] In some embodiments, the orthographic projection of the opening OP of the first inner pin portion 112a onto the first bump 132 lies within the first inner pin engagement region 132a. That is, the first inner pin engagement region 132a of the first bump 132 covers the entire opening OP of the first inner pin portion 112a. In some embodiments, either side of the opening OP lies within the first inner pin engagement region 132a.

[0031] In some embodiments, the plurality of bumps 130 may be made of, for example, gold, but the invention is not limited thereto. In some embodiments, the plurality of pins 110 may be made of, for example, tin-plated copper, i.e., composed of a first metal layer and a second metal layer, wherein the second metal layer is located on the surface of the first metal layer, the first metal layer being copper and the second metal layer being tin-plated, but the invention is not limited thereto.

[0032] In some embodiments, a metal eutectic layer 140 is provided between the plurality of bumps 130 and the plurality of correspondingly connected inner pin portions 110a to bond the bumps 130 and the inner pin portions 110a of the pins 110. Specifically, the metal eutectic layer 140 is formed by the formation of a eutectic phenomenon between the bumps 130 and the pins 110 under high temperature and pressure. In some embodiments, the metal eutectic layer 140 is, for example, a gold-tin eutectic, but the invention is not limited thereto.

[0033] In some embodiments, the metal eutectic layer 140 is located at least around the inner pin bonding region 130a of each bump 130. That is, the metal eutectic layer 140 mainly surrounds the bonding interface between the bump 130 and the inner pin portion 110a of the pin 110.

[0034] In some embodiments, a metal eutectic layer 140 is formed on the sidewalls SW2 of the two opposing long sides 110s1 and 110s2 corresponding to the sides S1 and S2 of the inner lead portion 110a and the inner lead bonding region 130a. For example, the metal eutectic layer 140 may be located around the first inner lead bonding region 132a of the first bump 132, and on the sidewalls SW2 corresponding to the first inner lead portion 112a and the first inner lead bonding region 132a. In addition, the metal eutectic layer 140 is also located around the second inner lead bonding region 134a of the second bump 134a and the second inner lead portion 114a, and on the sidewalls SW2 corresponding to the second inner lead portion 114a and the second inner lead bonding region 134a.

[0035] In some embodiments, the metal eutectic layer 140 is also filled into the opening OP of the first inner lead portion 112a and formed on the inner sidewall SW1 of the first inner lead portion 112a. Since the first inner lead portion 112a has the opening OP, compared to the bonding between a bump and a generally unopened inner lead portion, the metal eutectic layer 140 can be formed not only on the sidewall SW2 of the first inner lead portion 112a but also on the inner sidewall SW1. This strengthens the bonding strength between the first lead 112 and the first bump 132, reducing the possibility of delamination between the first lead 112 and the first bump 132. In this way, while increasing the width of the first lead 112, the bonding strength with the first bump 132 can be strengthened by the opening OP without changing the design of the bump 130 of the chip 120.

[0036] In some embodiments, the width W5 of the aperture OP is smaller than the width W1 of the first pin 112. In some embodiments, the width W5 of the aperture OP is between 1 / 4 and 1 / 6 of the width W1 of the first pin 112. In this way, while strengthening the bonding strength between the first pin 112 and the first bump 132, the area of ​​the first inner pin portion 112a reduced due to the aperture OP does not affect the electrical performance of the first pin 112 and the first bump 132.

[0037] In some embodiments, the width W5 of the aperture OP is greater than or equal to 3 micrometers. In this way, the amount of metal eutectic layer 140 filled in the aperture OP can achieve the effect of bonding the first pin 112 and the first bump 132, thereby improving the bonding strength between the first pin 112 and the first bump 132.

[0038] In some embodiments, the length L2 of the opening OP is less than the length L1 of the first bump 132. Herein, length refers to the length measured in the extension direction of the pin. Figure 3 For example, the first pin 112 extends in the y direction, so the lengths L1 and L2 are measured in the y direction.

[0039] In some embodiments, the metal eutectic layer 140 may surround the inner sidewall SW1 formed by the opening OP, but does not completely fill the opening OP. However, the invention is not limited thereto; in other embodiments, the metal eutectic layer 140 may completely fill the opening OP without forming gaps.

[0040] In some embodiments, the thickness of the metal eutectic layer 140 on the sidewall SW2 or inner sidewall SW1 of the pin 110 gradually decreases, where the thickness of the metal eutectic layer 140 refers to the distance from the surface of the metal eutectic layer 140 to the sidewall SW2 or inner sidewall SW1 of the pin 110. Specifically, the thickness of the metal eutectic layer 140 on the sidewall SW2 or inner sidewall SW1 gradually decreases from near the interface between the bump 130 and the inner pin portion 110a to away from the interface. That is, the thickness of the metal eutectic layer 140 near the bump 130 is greater than the thickness of the metal eutectic layer 140 away from the bump 130.

[0041] In some embodiments, the thin-film flip-chip package structure 10 further includes an adhesive layer 160, which is disposed between the chip 10 and the flexible substrate 100 and covers at least a plurality of pins 110 and a plurality of bumps 130 to protect the electrical contacts of the pins 110 and bumps 130 from electrical abnormalities or damage caused by moisture or contaminants.

[0042] In summary, the thin-film flip-chip packaging structure of the present invention selectively provides an opening in the inner pin portion of the pin for pins prone to self-bump peeling, so that the opening is located within the inner pin bonding area of ​​the bump. In this way, the metal eutectic layer formed by the bonding of the bump and the inner pin portion can be filled into the opening, increasing the metal eutectic layer adhesion area, thereby improving the bonding strength between the pin and the corresponding bump, reducing the possibility of pin peeling from the bump, and effectively improving the reliability of the thin-film flip-chip packaging structure.

[0043] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A thin-film flip-chip packaging structure, characterized in that, include: Flexible substrate with chip bonding area; A plurality of pins are disposed on the flexible substrate, each pin having an inner pin portion extending into the chip bonding region, wherein the plurality of pins includes a first pin, the first inner pin portion of the first pin having an opening; and A chip is disposed in the chip bonding area, wherein the chip has a plurality of bumps, the plurality of bumps are respectively connected to the inner pin portions of the plurality of pins and each has an inner pin bonding area overlapping the inner pin portions, wherein the plurality of bumps includes a first bump, the first bump is correspondingly connected to the first inner pin portion and has a first inner pin bonding area, and the orthogonal projection of the opening on the first bump is located within the first inner pin bonding area.

2. The thin-film flip-chip packaging structure according to claim 1, characterized in that, A metal eutectic layer is provided between the plurality of bumps and the plurality of correspondingly connected inner pin portions, the metal eutectic layer being located at least around the inner pin bonding area of ​​each of the plurality of bumps.

3. The thin-film flip-chip packaging structure according to claim 2, characterized in that, The two opposite sides of each inner pin bonding area correspond to the two opposite long sides of the inner pin portion, wherein the metal eutectic layer is formed on the sidewalls of the two opposite long sides of the inner pin portion.

4. The thin-film flip-chip packaging structure according to claim 2, characterized in that, The metal eutectic layer is also filled into the opening of the first inner pin portion and formed on the inner sidewall formed by the opening of the first inner pin portion.

5. The thin-film flip-chip packaging structure according to claim 1, characterized in that, Either side of the opening is located within the first inner pin engagement area.

6. The thin-film flip-chip packaging structure according to claim 1, characterized in that, The width of the opening is between 1 / 4 and 1 / 6 of the width of the first pin.

7. The thin-film flip-chip packaging structure according to claim 1, characterized in that, The width of the opening is greater than or equal to 3 micrometers.

8. The thin-film flip-chip packaging structure according to claim 1, characterized in that, The length of the opening is less than the length of the first protrusion.

9. The thin-film flip-chip packaging structure according to claim 1, characterized in that, The plurality of pins further includes a plurality of second pins, wherein the width of the plurality of second pins is smaller than the width of the first pin.

10. The thin-film flip-chip packaging structure according to claim 9, characterized in that, The width of the first pin is greater than or equal to twice the width of the plurality of second pins.

Images