Maximize bandwidth utilization by selecting the appropriate operating mode for the PCIe card

Abstract

A computer-implemented method, system, and computer program product for maximizing bandwidth utilization of a PCIe link. Bandwidth utilization of a PCIe link involving a PCIe card is measured. Using a machine learning model trained to predict bandwidth utilization of a PCIe link, a future time bandwidth utilization of the PCIe link is predicted based on the measured bandwidth utilization of the PCIe link. If the predicted bandwidth utilization of the PCIe link exceeds a threshold, the PCIe card is configured to implement a first operational mode that utilizes more bandwidth if the first operational mode is not implemented at the future time. If the predicted bandwidth utilization of the PCIe link does not exceed the threshold, the PCIe card is configured to implement a second operational mode that utilizes less bandwidth if the second operational mode is not implemented at the future time.

Description

Technical Field

[0001] This disclosure generally relates to Peripheral Component Interconnect High Speed ​​Edition (PCIe), and more specifically to maximizing the bandwidth utilization of a PCIe link by selecting an appropriate operating mode (e.g., a high-bandwidth operating mode) for a PCIe card involving a PCIe link. Background Technology

[0002] PCI Express (PCIe), officially abbreviated as PCIe, is a high-speed serial computer expansion bus standard designed to replace the older PCI, PCI-X, and AGP bus standards. It is a universal motherboard interface for graphics cards, sound cards, hard drive host adapters, SSDs (Solid State Drives), Wi-Fi, and Ethernet hardware connections in personal computers. PCIe offers many improvements over older standards, including higher maximum system bus throughput, lower I / O pin count and smaller physical footprint, better performance expansion for bus devices, more detailed error detection and reporting mechanisms (Advanced Error Reporting, AER), and local hot-swapping capabilities. Summary of the Invention

[0003] In one embodiment of this disclosure, a computer-implemented method for maximizing bandwidth utilization of a Peripheral Component Interconnect High Speed ​​Edition (PCIe) link includes measuring the bandwidth utilization of a PCIe link involving a PCIe card. The method further includes: predicting the bandwidth utilization of the PCIe link based on the measured bandwidth utilization of the PCIe link using a machine learning model trained to predict the bandwidth utilization of the PCIe link. The method also includes: switching the operating mode of the PCIe card based on the predicted bandwidth utilization of the PCIe link.

[0004] Other forms of embodiments of the above-described computer-implemented methods are available in the system and in computer program products.

[0005] The features and technical advantages of one or more embodiments of this disclosure have been summarized in fairly general terms above in order to provide a better understanding of the detailed description of this disclosure that follows. Additional features and advantages of this disclosure, which may form the subject matter of the claims of this disclosure, will be described below. Attached Figure Description

[0006] A better understanding of this disclosure can be obtained by considering the following detailed description in conjunction with the accompanying drawings, wherein:

[0007] Figure 1 A communication system for implementing the principles of this disclosure is shown according to embodiments thereof;

[0008] Figure 2This is a schematic diagram of a software component used by a computing device according to an embodiment of the present disclosure to maximize the bandwidth utilization of a PCIe link by selecting an appropriate operating mode for a PCIe card.

[0009] Figure 3 The storage of configuration settings in the memory of a PCIe card according to an embodiment of the present disclosure is shown;

[0010] Figure 4 An embodiment of this disclosure is shown, representing a hardware configuration of a computing device for implementing the hardware environment of this disclosure;

[0011] Figure 5 This is a flowchart of a method for training a machine learning model to predict the bandwidth utilization of a PCIe link according to embodiments of the present disclosure; and

[0012] Figure 6 This is a flowchart of a method for maximizing bandwidth utilization of a PCIe link according to embodiments of the present disclosure. Detailed Implementation

[0013] As mentioned above, PCI Express (Peripheral Component Interconnect High Speed ​​Edition), formally abbreviated as PCIe, is a high-speed serial computer expansion bus standard designed to replace the older PCI, PCI-X, and AGP bus standards. It is a universal motherboard interface for graphics cards, sound cards, hard drive host adapters, SSDs (Solid State Drives), Wi-Fi, and Ethernet hardware connections in personal computers. PCIe offers many improvements over older standards, including higher maximum system bus throughput, lower I / O pin count and smaller physical footprint, better performance expansion for bus devices, more detailed error detection and reporting mechanisms (Advanced Error Reporting, AER), and local hot-swapping capabilities.

[0014] Conceptually, the PCIe bus is a high-speed serial replacement for the older PCI / PCI-X buses. One of the key differences between the PCI Express bus and the older PCI is the bus topology. PCI uses a shared parallel bus architecture, where the PCI host and all devices share a common set of address, data, and control lines. In contrast, PCI Express is based on a point-to-point topology, where a separate serial link connects each device to the root complex (the host). Due to its shared bus topology, access to the older PCI bus was adjudicated (in the case of multiple hosts) and limited to one host at a time in a single direction. Furthermore, the older PCI timing scheme limited the bus clock to the slowest peripheral on the bus (regardless of the device involved in the bus transaction). In contrast, PCIe bus links support full-duplex communication between any two endpoints, with no inherent limitations on concurrent access across multiple endpoints.

[0015] PCIe devices, such as PCIe cards, communicate via logical connections called interconnects or links. A link is a point-to-point communication channel between two PCI Express ports, allowing them to send and receive common PCI requests (configuration, I / O, or memory read / write) and interrupts (INTx, MSI, or MSI-X). At the physical layer, a link consists of one or more channels. A channel consists of two differential signaling pairs, one pair for receiving data and the other for sending. Therefore, each channel consists of four wires or signal traces. Conceptually, each channel acts as a full-duplex byte stream, simultaneously transmitting data packets in eight-bit “byte” format in both directions between the endpoints of the link. Physical PCI Express links can contain 1, 4, 8, or 16 channels.

[0016] As described above, a PCIe card communicates with a logical connection called an interconnect or link. A PCIe card is a network adapter with a PCIe interface. PCIe cards are designed to fit into PCIe-based slots (slots in the motherboard of devices such as hosts, servers, network switches, etc.). PCIe cards implement the PCIe protocol. Therefore, after a PCIe card is inserted, a logical connection (“link”) is formed between the PCIe card and the motherboard, thereby establishing a point-to-point communication channel between the two PCIe ports and allowing both to send and receive ordinary PCI requests and interrupts.

[0017] There are various generations or versions of PCIe, such as PCIe 1.0, PCIe 2.0, PCIe 3.0, PCIe 4.0, PCIe 5.0, and PCIe 6.0. Higher PCIe versions or generations utilize more power than previous generations, which had slower signaling rates. Each PCIe version supports approximately twice the bandwidth of previous versions of PCIe. Therefore, during periods of low bandwidth utilization, such higher versions or generations of PCIe have unused available bandwidth. In this case, power is wasted.

[0018] Unfortunately, there are currently no means to limit or prevent this wasted power.

[0019] Embodiments of this disclosure provide a method for limiting or preventing such wasted power by switching the operating modes of a PCIe card, such that the PCIe card switches to a less power-consuming operating mode during periods of predicted low bandwidth utilization and switches to a more power-consuming operating mode during periods of predicted high bandwidth utilization. In one embodiment, a machine learning model is built and trained to predict the bandwidth utilization of the PCIe link involving the PCIe card. When measuring the bandwidth utilization of the PCIe link involving the PCIe card, the trained machine learning model uses this measurement to predict the bandwidth utilization of the PCIe link. If the predicted measurement of the bandwidth utilization of the PCIe link exceeds a threshold, the PCIe card should operate in a first operating mode that utilizes more bandwidth (e.g., a higher version or generation of PCIe). On the other hand, if the predicted measurement of the bandwidth utilization of the PCIe link does not exceed the threshold, the PCIe card should operate in a second operating mode that utilizes less bandwidth (e.g., a lower version or generation of PCIe). By ensuring PCIe cards operate in the appropriate operating mode through predicted bandwidth utilization based on the PCIe link, the bandwidth utilization of the PCIe link is maximized and the amount of wasted power is minimized. These and other features will be discussed in further detail below.

[0020] In some embodiments of this disclosure, the disclosure includes computer-implemented methods, systems, and computer program products for maximizing bandwidth utilization of a Peripheral Component Interconnect High Speed ​​Edition (PCIe) link. In one embodiment of this disclosure, the bandwidth utilization of a PCIe link involving a PCIe card is measured. In one embodiment, such bandwidth utilization is provided as a percentage of the link transfer rate (such as 70% of the link transfer rate). In one embodiment, such bandwidth utilization is provided in bytes per second (e.g., 64 GB / s). Using a machine learning model trained to predict the bandwidth utilization of the PCIe link, the measured bandwidth utilization of the PCIe link is used to predict the bandwidth utilization of the PCIe link in the future. If the predicted bandwidth utilization of the PCIe link exceeds a threshold, the operating mode of the PCIe card is switched to implement a first operating mode (e.g., a higher version or generation of PCIe) that utilizes more bandwidth if it is not implemented in the future. If the projected bandwidth utilization of the PCIe link does not exceed a threshold, the PCIe card's operating mode is switched to a second operating mode (e.g., a lower version or generation of PCIe). If the second operating mode is not implemented in the future, it utilizes less bandwidth. In this way, the bandwidth utilization of the PCIe link is maximized and the amount of wasted power is minimized.

[0021] In the following description, numerous specific details are set forth to provide a thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without these specific details. In other instances, well-known circuits have been shown in block diagram form so as not to obscure this disclosure with unnecessary detail. In most cases, details such as considerations of timing have been omitted because such details are not essential for obtaining a full understanding of this disclosure and are within the skill of those skilled in the art.

[0022] Please refer to the attached diagram for details. Figure 1 An embodiment of the present disclosure is shown, comprising a communication system 100 for implementing the principles of the present disclosure. The communication system 100 includes a computing device 101 connected to other devices (not shown) via a network 102.

[0023] Computing device 101 can be any type of computing device (e.g., portable computing unit, personal digital assistant (PDA), laptop computer, mobile device, tablet PC, smartphone, mobile phone, navigation device, gaming unit, desktop computer system, workstation, Internet device, etc.) configured to connect to network 102 and thus communicate with other computing devices 101 and other devices (not shown). Note that both computing device 101 and its user can be identified by element number 101.

[0024] Network 102 can be, for example, a local area network (LAN), a wide area network (WAN), a wireless wide area network (WAN), a circuit-switched telephone network, a Global System for Mobile Communications (GSM) network, a Wireless Application Protocol (WAP) network, a WiFi network, an IEEE 802.11 standard network, or various combinations thereof. Without departing from the scope of this disclosure, it can also be combined with… Figure 1 System 100 uses other networks; for the sake of brevity, the description of these other networks is omitted here.

[0025] In one embodiment, computing device 101 implements the Peripheral Component Interconnect High Speed ​​Edition (PCIe) protocol for connecting various internal components (peripheral devices) within computing device 101. For example, PCIe may be used to connect peripheral devices or PCIe devices (e.g., graphics cards, network cards, memory controllers, etc.) to the motherboard 103 of computing device 101. As used herein, motherboard 103 refers to the main printed circuit board that holds and allows communication between many critical electronic components of computing device 101, such as the central processing unit (CPU) and memory, and provides connectors for other peripheral devices, such as PCIe devices.

[0026] In one embodiment, motherboard 103 includes PCIe slots of different sizes or configurations (indicated by an "x" followed by a number), referred to as "channels". Common time slot configurations include x1, x4, x8, and x16, which represent the number of data channels available for communication. A greater number of channels generally results in higher data transfer rates between the motherboard and expansion cards.

[0027] like Figure 1 As shown, computing device 101 includes PCIe cards 104A-104C (in... Figure 1 These are respectively labeled "PCIe Card A", "PCIe Card B", and "PCIe Card C". PCIe cards 104A-104C can be collectively or individually referred to as PCIe Card 104 or PCIe Card 104. Although Figure 1 A computing device 101 containing three PCIe cards 104 is shown, but the computing device 101 may contain any number of PCIe cards 104.

[0028] As used herein, PCIe card 104 is an expansion card that connects to motherboard 103 using a PCIe slot (not shown). PCIe card 104 is used to enhance the functionality of computing device 101 by adding various capabilities not integrated into motherboard 103 itself. PCIe card 104 comes in different forms, and each type is used for a specific purpose. Some common types of PCIe card 104 may include, but are not limited to, graphics cards, network interface cards, USB (Universal Serial Bus) cards, storage controller cards, sound cards, capture cards, etc.

[0029] PCIe card 104 communicates via a logical connection called an interconnect or link (referred to herein as a "PCIe link"). As used herein, a PCIe link is a point-to-point communication channel between two PCI Express ports, allowing both to send and receive common PCI requests (configuration, I / O, or memory read / write) and interrupts (INTx, MSI, or MSI-X). In other words, a PCIe link is a connection between two devices (e.g., such as...) Figure 1 The physical connection between PCIe card 104 and motherboard 103 is shown. For example, PCIe link 105A is the physical connection between PCIe card 104A and motherboard 103. PCIe link 105B is the physical connection between PCIe card 104B and motherboard 103. Furthermore, PCIe link 105C is the physical connection between PCIe card 104C and motherboard 103. PCIe links 105A-105C may be collectively or individually referred to as PCIe link 105 or PCIe link 105, respectively. Although... Figure 1 Three PCIe links 105 are shown, but computing device 101 can utilize any number of PCIe links 105.

[0030] At the physical layer, a PCIe link 105 consists of one or more channels. Each channel comprises two differential signaling pairs, one for receiving data and the other for transmitting. Therefore, each channel consists of four wires or signal traces. Conceptually, each channel acts as a full-duplex byte stream, simultaneously transmitting data packets in eight-bit “byte” format in both directions between the endpoints of the PCIe link 105. A physical PCIe link 105 can contain 1, 4, 8, or 16 channels.

[0031] A PCIe channel is a single data path within a PCIe slot or connection that provides a path for sending and receiving data, for example, between motherboard 103 and PCIe card 104. As used herein, the term "channel" refers to a set of differential signal pairs (transmit and receive) that work together to transmit data.

[0032] The number of PCIe lanes in a slot or connection determines the available bandwidth for data transfer (e.g., between motherboard 103 and PCIe card 104). More lanes generally mean higher data transfer rates and better performance. Each PCIe lane consists of multiple wires or traces designed to minimize signal interference and maintain data integrity at high speeds.

[0033] As mentioned above, there are various generations or versions of PCIe, such as PCIe 1.0, PCIe 2.0, PCIe 3.0, PCIe 4.0, PCIe 5.0, and PCIe 6.0. Higher PCIe versions or generations utilize more power than previous generations, which had slower signaling rates. Each PCIe version supports approximately twice the bandwidth of previous versions of PCIe. Therefore, during periods of low bandwidth utilization, these higher versions or generations of PCIe have unused available bandwidth. In this case, power is wasted.

[0034] Computing device 101 is configured to limit or prevent such wasted power by switching the operating mode of PCIe card 104, such that PCIe card 104 switches to a less power-consuming operating mode during periods of predicted low bandwidth utilization and switches to a more power-consuming operating mode during periods of predicted high bandwidth utilization. In other words, computing device 101 is configured to maximize bandwidth utilization by selecting an appropriate operating mode for PCIe card 104.

[0035] In one embodiment, a machine learning model is built and trained to predict the bandwidth utilization of the PCIe link 105 involving the PCIe card 104. As used herein, the PCIe link 105 refers to a point-to-point communication channel between two PCI Express ports, allowing both to send and receive common PCI requests (configuration, I / O, or memory read / write) and interrupts (INTx, MSI, or MSI-X). At the physical layer, the link consists of one or more channels. A channel consists of two differential signaling pairs, one pair for receiving data and the other for sending. Thus, each channel consists of four wires or signal traces. Conceptually, each channel acts as a full-duplex byte stream, simultaneously transmitting data packets in eight-bit “byte” format in both directions between the endpoints of the link. A physical PCI Express link can contain 1, 4, 8, or 16 channels.

[0036] In one embodiment, when measuring the bandwidth utilization of the PCIe link 105 involving the PCIe card 104, a trained machine learning model uses this measurement to predict the bandwidth utilization of the PCIe link 105. If the predicted measurement of the bandwidth utilization of the PCIe link 105 exceeds a threshold, the PCIe card 104 should operate in a first operating mode that utilizes more bandwidth (e.g., a higher version or generation of PCIe). On the other hand, if the predicted measurement of the bandwidth utilization of the PCIe link 105 does not exceed the threshold, the PCIe card 104 should operate in a second operating mode that utilizes less bandwidth (e.g., a lower version or generation of PCIe). By ensuring that the PCIe card 104 operates in an appropriate operating mode based on the predicted bandwidth utilization of the PCIe link 105, the bandwidth utilization of the PCIe link 105 is maximized and the amount of wasted power is minimized. These and other features will be discussed in further detail below.

[0037] The following is combined with Figure 2 A description is provided of the software components of a computing device 101 for maximizing the bandwidth utilization of a PCIe link 105 by selecting an appropriate operating mode for a PCIe card 104. The following description is in conjunction with... Figure 4 Further description of the hardware configuration of computing device 101 is provided.

[0038] System 100 is not limited to any particular network architecture. System 100 may include any number of computing devices 101 and networks 102.

[0039] The following is combined with Figure 2 A discussion is provided regarding the software components used by computing device 101 to maximize the bandwidth utilization of PCIe link 105 by selecting the appropriate operating mode of PCIe card 104.

[0040] Figure 2 This is a schematic diagram of a software component used by computing device 101 according to an embodiment of the present disclosure to maximize the bandwidth utilization of PCIe link 105 by selecting an appropriate operating mode for PCIe card 104.

[0041] refer to Figure 2 , combined Figure 1 The computing device 101 includes a measurement engine 201 configured to track the bandwidth utilization of each PCIe link 105 established by each PCIe card 104 over a period of time (e.g., a week, a month). As used herein, bandwidth utilization refers to the rate at which data can flow through the PCIe link 105. In one embodiment, such bandwidth utilization is provided as a percentage of the link transfer rate (e.g., 70% of the link transfer rate). In one embodiment, such bandwidth utilization is provided in bytes per second (e.g., 64 GB / s). The measurement engine 201 can utilize various tools to track the bandwidth utilization of each PCIe link 105, including but not limited to Intel® Performance Counter Monitor, 3DMark®, Libre Hardware Monitor, etc.

[0042] In one embodiment, the measurement engine 201 tracks the bandwidth utilization of the PCIe link 105 over a period of time. Such information can be used to train a machine learning model to predict the bandwidth utilization of the PCIe link 105 (e.g., at a specific future moment) based on the currently measured bandwidth utilization of the PCIe link 105, as discussed further below.

[0043] In one embodiment, measurement engine 201 measures the bandwidth utilization of PCIe link 105 (e.g., PCIe link 105A) involving PCIe card 104 (e.g., PCIe card 104A) at the current moment. In one embodiment, such bandwidth utilization is provided as a percentage of the link transfer rate (such as 70% of the link transfer rate). In one embodiment, such bandwidth utilization is provided in bytes per second (e.g., 64 GB / s). Measurement engine 201 can utilize various tools to measure the bandwidth utilization of PCIe link 105 (e.g., PCIe link 105A) at the current moment, including but not limited to Intel® Performance Counter Monitor, 3DMark®, Libre Hardware Monitor, etc.

[0044] The computing device 101 also includes a machine learning engine 202 configured to build and train a machine learning model to predict the bandwidth utilization of each PCIe link 105 at future times using the tracking bandwidth utilization of each PCIe link 105. This prediction of the bandwidth utilization of a PCIe link 105 (e.g., PCIe link 105A) is provided by the machine learning model based on currently measured bandwidth utilization of the PCIe link 105 (e.g., PCIe link 105A) as input to the trained machine learning model.

[0045] In one embodiment, a machine learning model is trained to predict the bandwidth utilization of PCIe link 105 at future times based on a sample dataset including the bandwidth utilization of PCIe link 105 tracked over a period of time. Such a sample dataset may be stored in a data structure (e.g., a table) residing in the storage device of computing device 101.

[0046] Furthermore, in one embodiment, the sample dataset discussed above is referred to herein as "training data," which is used by a machine learning algorithm to predict the bandwidth utilization of PCIe link 105. The algorithm iteratively predicts the bandwidth utilization of PCIe link 105 using the training data until the prediction reaches the expected accuracy determined by experts. Examples of such learning algorithms include nearest neighbor, Naive Bayes, decision trees, linear regression, support vector machines, and neural networks.

[0047] After training such a machine learning model, the PCIe controller 203 of computing device 101 can use the machine learning model to predict the bandwidth utilization of PCIe link 105 (e.g., PCIe link 105A) based on measured bandwidth utilization (e.g., the currently measured bandwidth utilization of PCIe link 105 (e.g., PCIe link 105A)). In one embodiment, such measured bandwidth utilization (e.g., the currently measured bandwidth utilization of PCIe link 105 (e.g., PCIe link 105A)) is input into a trained machine learning model that outputs a predicted bandwidth utilization of PCIe link 105 (e.g., PCIe link 105A) at a future time (e.g., the next hour), which may be user-specified.

[0048] In one embodiment, PCIe controller 203 is configured to determine whether the predicted bandwidth utilization of PCIe link 105 exceeds a threshold, which may be user-specified. In one embodiment, such a threshold may be based on a percentage of the link transmission rate, such as 70% of the link transmission rate. In one embodiment, such a threshold may be bytes per second (e.g., 64 Gb / s).

[0049] In one embodiment, the PCIe controller 203 determines whether the predicted bandwidth utilization of the PCIe link 105 exceeds a threshold in order to determine which operating mode the PCIe card 104 forming such a PCIe link 105 should utilize. In one embodiment, the PCIe card 104 can operate in two different operating modes, such as a high-bandwidth operating mode and a low-bandwidth operating mode. As used herein, a high-bandwidth operating mode refers to the operating mode of the PCIe card 104 involving a higher version or generation of PCIe that utilizes more bandwidth. For example, such a higher version or generation of PCIe (e.g., PCIe 6.0) may correspond to a bandwidth utilization of 128 GB / s. As used herein, a low-bandwidth operating mode refers to the operating mode of the PCIe card 104 involving a lower version or generation of PCIe that utilizes less bandwidth. For example, such a lower version or generation of PCIe, such as PCIe 4.0, may correspond to a bandwidth utilization of 32 GB / s. Although two operating modes are discussed below, it should be noted that the principles of this disclosure can utilize any number of operating modes, wherein the utilization rate of each operating mode is determined based on the predicted bandwidth utilization of the PCIe link 105 between two threshold levels / values, which can be user-specified.

[0050] In one embodiment, this operating mode of the PCIe card 104 is established by selecting appropriate configuration settings for the PCIe card 104. In one embodiment, these configuration settings are stored in the memory of the PCIe card 104 (e.g., SEEPROM (Serial Electrically Erasable Programmable Read-Only Memory)). Figure 3 As shown.

[0051] Figure 3 The storage of configuration settings in the memory (e.g., SEEPROM) of a PCIe card 104 according to an embodiment of the present disclosure is shown.

[0052] refer to Figure 3 The PCIe card 104 includes a memory 301 (e.g., SEEPROM) configured to store configuration settings 302. Examples of memory 301 may include, but are not limited to, serial electrically erasable programmable read-only memory, dynamic random access memory, synchronous dynamic random access memory, static random access memory, etc.

[0053] As used herein, configuration setting 302 refers to a set of parameters that can be changed to affect the functionality of PCIe card 104. For example, such parameters can be modified by PCIe controller 203 to implement different operating modes of PCIe card 104, such as operating in an operating mode that provides higher bandwidth and therefore uses more power than another operating mode. In another example, such parameters can be modified by PCIe controller 203 to enable PCIe card 104 to operate in an operating mode that provides lower bandwidth and therefore uses less power than the different operating modes.

[0054] In an alternative embodiment, the configuration settings 302 are stored in the storage device of the computing device 101, thereby reducing the requirement to store configuration settings on each PCIe card 104.

[0055] Return to Figure 2 , combined Figure 1 and Figure 3 In one embodiment, when determining whether the predicted bandwidth utilization of PCIe link 105 exceeds a threshold and thus determining which operating mode PCIe card 104 should operate in (e.g., at a future time), PCIe controller 203 makes a determination at that future time regarding whether the operating mode of PCIe card 104 at that future time is different from the operating mode that PCIe card 104 should operate in. For example, if the predicted bandwidth of PCIe link 105 (e.g., PCIe link 105A) exceeds the threshold, PCIe controller 203 determines that PCIe card 104 should operate in a first operating mode (e.g., PCIe 6.0) (such as an operating mode that provides higher bandwidth and uses more power) at a future time. In such a scenario, PCIe controller 203 determines whether PCIe card 104 is operating in the first operating mode when the bandwidth utilization of PCIe link 105 involving PCIe card 104 is predicted to exceed the threshold. For example, PCIe controller 203 can make such a determination when the bandwidth utilization of PCIe link 105 involving PCIe card 104 is predicted to exceed a threshold.

[0056] In another example, if the predicted bandwidth of PCIe link 105 (e.g., PCIe link 105A) does not exceed a threshold, PCIe controller 203 determines that PCIe card 104 should operate in a second operating mode (e.g., PCIe 4.0) (such as an operating mode that provides lower bandwidth and uses less power). In such a scenario, PCIe controller 203 determines whether PCIe card 104 is operating in the second operating mode when the bandwidth utilization of PCIe link 105 involving PCIe card 104 is predicted to not exceed a threshold. For example, PCIe controller 203 may make such a determination at the moment when the bandwidth utilization of PCIe link 105 involving PCIe card 104 is predicted to not exceed a threshold.

[0057] If PCIe card 104 operates in an operating mode different from the operating mode in which PCIe link 105 (e.g., PCIe 4.0) should operate when the bandwidth utilization of PCIe link 105 (e.g., PCIe 6.0) involving PCIe card 104 is predicted to exceed or not exceed a threshold, then PCIe controller 203 determines whether there is currently traffic on PCIe link 105 (e.g., PCIe link 105A) before switching the operating mode of PCIe card 104 to the operating mode in which PCIe link 105 (e.g., PCIe link 105A) involving PCIe card 104 is predicted to exceed or not exceed a threshold.

[0058] In one embodiment, traffic on PCIe link 105 (e.g., PCIe link 105A) is determined by traffic engine 204 of computing device 101. In one embodiment, traffic engine 204 determines the current traffic on PCIe link 105 (e.g., PCIe link 105A) by utilizing CATC® traces. In one implementation, CATC® traces combine uplink and downlink data paths into a single trace, even if they are parallel paths that can be active simultaneously. In one implementation, CATC® traces include several fields, such as fields indicating packet type (e.g., TLP (Transaction Layer Packet), DLLP (Data Link Layer Packet), etc.), packet payload, delay between the packet and the next packet on its data path, etc.

[0059] In one embodiment, the traffic flow engine 204 uses various software tools to determine the current traffic flow on PCIe link 105 (e.g., PCIe link 105A), and these software tools may include, but are not limited to, LogicMonitor®, Intel® VTune, etc. TMAnalyzers, ManageEngine® NetFlow® Analyzer, SolarWind® Network Performance Monitor, Paessler® Network Monitor, etc.

[0060] In response to determining that there is currently no traffic flowing on the PCIe link 105 associated with the PCIe card 104 that requires a switch in operating mode (e.g., from a second operating mode to a first operating mode), the PCIe controller 203 continues to select a configuration setting (e.g., configuration setting 302) to switch the operating mode of the PCIe card 104, for example, selecting a configuration setting (e.g., configuration setting 302) to use a first operating mode (e.g., PCIe 6.0) that provides higher bandwidth and uses more power. In another example, if it is necessary to switch the operating mode of the PCIe card 104 from the first operating mode to the second operating mode, the PCIe controller 203 continues to select a configuration setting (e.g., configuration setting 302) to switch the operating mode of the PCIe card 104, for example, selecting a configuration setting of the PCIe card 104 (e.g., configuration setting 302) to implement a second operating mode (e.g., PCIe 4.0) that provides lower bandwidth and uses less power.

[0061] If there is currently traffic flowing on PCIe link 105 associated with PCIe card 104, and the operating mode of PCIe card 104 needs to be switched (e.g., from the second operating mode to the first operating mode), then PCIe controller 203 determines whether the traffic can be temporarily routed to a different PCIe link 105, such as a PCIe link 105 that currently has no traffic.

[0062] In one embodiment, PCIe controller 203 determines whether there are currently different PCIe links 105 (e.g., PCIe link 105B) that do not display traffic. In another embodiment, PCIe controller 203 instructs traffic flow engine 204 to determine the current traffic flow on other PCIe links 105 (e.g., PCIe links 105B, 105C) to determine whether there are currently different PCIe links 105 (e.g., PCIe link 105B) that do not display traffic. Traffic flow engine 204 uses various software tools to perform this determination, including but not limited to LogicMonitor®, Intel® VTune, etc. TM Analyzers, ManageEngine® NetFlow® Analyzer, SolarWind® Network Performance Monitor, Paessler® Network Monitor, etc.

[0063] If traffic can be temporarily routed to a different PCIe link 105 (e.g., PCIe link 105B), then PCIe controller 203 will temporarily route traffic on PCIe link 105 (e.g., PCIe link 105A) of PCIe card 104 (e.g., PCIe card 104A) whose operating mode needs to be switched, to such a different PCIe link 105 (e.g., PCIe link 105B). Then, PCIe controller 203 will select a configuration setting (e.g., configuration setting 302) to switch the operating mode of PCIe card 104, for example, selecting the configuration setting of PCIe card 104 (e.g., configuration setting 302) to implement a first operating mode (e.g., PCIe 6.0) corresponding to an operating mode that provides higher bandwidth and uses more power. In another example, PCIe controller 203 selects the configuration settings of PCIe card 104 (e.g., configuration setting 302) to implement a second operating mode (e.g., PCIe 4.0) that corresponds to an operating mode that provides lower bandwidth and uses less power.

[0064] However, if a service cannot be temporarily routed to a different PCIe link 105 (e.g., PCIe link 105B), the PCIe controller 203 waits for the data transmission on the PCIe link 105 (e.g., PCIe link 105A) involving the PCIe card 104 (e.g., PCIe card 104A) whose operating mode needs to be switched to complete. Afterward, the PCIe controller 203 selects the configuration settings of the PCIe card 104 (e.g., configuration setting 302) to implement a first operating mode (e.g., PCIe 6.0) corresponding to an operating mode that provides higher bandwidth and uses more power. In another example, the PCIe controller 203 selects the configuration settings of the PCIe card 104 (e.g., configuration setting 302) to implement a second operating mode (e.g., PCIe 4.0) corresponding to an operating mode that provides lower bandwidth and uses less power.

[0065] In this way, the bandwidth utilization of PCIe link 105 is maximized and the amount of wasted power is minimized.

[0066] In one embodiment, after the configuration setting 302 of PCIe card 104 is selected to switch the operating mode of PCIe card 104, the operating mode is switched by resetting PCIe link 105 (the PCIe link 105 of the PCIe card 104 whose operating mode has been switched) and PCIe slot, and then the new operating mode of PCIe card 104 is implemented.

[0067] In one embodiment, based on the operating mode of the PCIe card 104, traffic consisting of workloads or transactions is directed via the PCIe link 105 to a specific logical partition of the hardware. For example, in one embodiment, workloads involving a marketing website or analytics platform may be directed to a first set of logical partitions of the hardware in response to the PCIe card 104 operating in a first operating mode (e.g., a high-bandwidth operating mode), and to a second set of logical partitions of the hardware in response to the PCIe card 104 operating in a second operating mode (e.g., a low-bandwidth operating mode).

[0068] In one embodiment, a data structure (e.g., a table) contains information about the set of hardware logical partitions that will be used to specify workloads or transactions based on the operating mode of the PCIe card 104. In one embodiment, the PCIe controller 203 determines the type of workload or transaction based on a classification of the workload or transaction (e.g., a classification assigned to such a workload or transaction using a Workload Management (WLM) workload classification rule published by MVS™ (Multiple Virtual Storage) Workload Management). After determining the type of workload or transaction, this classification is associated with a specific logical partition of the hardware based on the operating mode of the PCIe card 104 indicated in the data structure (e.g., the table) discussed above. In one embodiment, such a data structure resides within the storage device of the computing device 101. In one embodiment, such a data structure is populated by an expert.

[0069] The following discussion, in conjunction with methods for maximizing bandwidth utilization of PCIe links, provides a further description of these and other characteristics.

[0070] Before discussing methods for maximizing bandwidth utilization of PCIe links, let's combine... Figure 4 Provides access to computing device 101 ( Figure 1 Description of the hardware configuration.

[0071] Now for reference Figure 4 , combined Figure 1 , Figure 4 An embodiment of the hardware configuration of the present disclosure is shown, representing a hardware environment for implementing the present disclosure.

[0072] Various aspects of this disclosure are described by way of text, flowcharts, block diagrams of computer systems, and / or block diagrams of machine logic included in embodiments of a computer program product (CPP). With respect to any flowchart, depending on the technology involved, operations may be performed in a different order than that shown in a given flowchart. For example, again depending on the technology involved, two operations shown in consecutive flowchart blocks may be performed in reverse order, as a single integrated step, simultaneously, or in a manner that at least partially overlaps in time.

[0073] Computer Program Product Embodiment (“CPP Embodiment” or “CPP”) is a term used in this disclosure to describe any set of one or more storage media (also referred to as “media”) collectively included in a set of one or more storage devices that collectively include machine-readable code corresponding to instructions and / or data for performing the computer operations specified in a given CPP claim. A “storage device” is any tangible device capable of holding and storing instructions used by a computer processor. Without limitation, a computer-readable storage medium can be an electronic storage medium, a magnetic storage medium, an optical storage medium, an electromagnetic storage medium, a semiconductor storage medium, a mechanical storage medium, or any suitable combination of the foregoing. Some known types of storage devices that include these media include: magnetic disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), optical disc read-only memory (CD-ROM), digital versatile optical disc (DVD), memory sticks, floppy disks, mechanical encoding devices (e.g., punched cards or pits / platforms formed in the main surface of the disk), or any suitable combination of the foregoing. As used herein, the term computer-readable storage medium should not be construed as storage in the form of transient signals themselves, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides, optical pulses through fiber optic cables, electrical signals transmitted through wires, and / or other transmission media. As those skilled in the art will understand, data typically moves at certain incidental points in time during the normal operation of the storage device (such as during access, defragmentation, or garbage collection), but this does not render the storage device transient, as the data is not transient at the time of storage.

[0074] Computing environment 400 includes examples of environments for executing at least some computer code 401 relating to the execution of methods of the present invention, such as maximizing bandwidth utilization of a PCIe link. In addition to block 401, computing environment 400 includes, for example, computing device 101, network 102 (such as a wide area network (WAN)), end user equipment (EUD) 402, remote server 403, public cloud 404, and private cloud 405. In this embodiment, computing device 101 includes processor set 406 (including processing circuitry 407 and cache 408), communication infrastructure 409, volatile memory 410, persistent storage 411 (including operating system 412 and block 401, as described above), peripheral device set 413 (including user interface (UI) device set 414, storage 415, and Internet of Things (IoT) sensor set 416), and network module 417. Remote server 403 includes remote database 418. Public cloud 404 includes gateway 419, cloud orchestration module 420, host physical machine set 421, virtual machine set 422, and container set 423.

[0075] Computing device 101 may take the form of a desktop computer, laptop computer, tablet computer, smartphone, smartwatch or other wearable computer, mainframe computer, quantum computer, or any other form of computer or mobile device now known or to be developed in the future capable of running programs, accessing networks, or querying databases (such as remote database 418). As is well understood in the field of computer technology, and depending on the technology, the execution of computer-implemented methods may be distributed among multiple computers and / or multiple locations. On the other hand, in this presentation of computing environment 400, the detailed discussion focuses on a single computer, specifically computing device 101, to keep the presentation as simple as possible. Computing device 101 may be located in the cloud, even if it is... Figure 4 The cloud is not shown. On the other hand, the computing device 101 is not required to be in the cloud except to the extent that can be definitively indicated.

[0076] Processor set 406 includes one or more computer processors of any type now known or to be developed in the future. Processing circuitry 407 may be distributed across multiple packages, such as multiple coordinated integrated circuit chips. Processing circuitry 407 may implement multiple processor threads and / or multiple processor cores. Cache 408 is memory located within the processor chip package(s) and is typically used for data or code that should be readily accessible by the threads or cores running on processor set 406. Cache memory is typically organized into multiple levels based on its relative proximity to the processing circuitry. Alternatively, some or all of the cache used in processor set may be located “off-chip.” In some computing environments, processor set 406 may be designed to work with qubits and perform quantum computing.

[0077] Computer-readable program instructions are typically loaded onto computing device 101 to cause processor group 406 of computing device 101 to perform a series of operational steps, thereby implementing a computer-implemented method, such that the instructions thus executed instantiate the method specified in the flowcharts and / or descriptive descriptions of the computer-implemented method included in this document (collectively, the “method of the invention”). These computer-readable program instructions are stored in various types of computer-readable storage media, such as cache 408 and other storage media discussed below. The program instructions and associated data are accessed by processor group 406 to control and direct the execution of the method of the invention. In computing environment 400, at least some of the instructions for performing the method of the invention may be stored in persistent storage 411 in block 401.

[0078] Communication structure 409 is a signal transmission path that allows various components of computing device 101 to communicate with each other. Typically, this structure consists of switches and conductive paths (e.g., switches and conductive paths that form buses, bridges, physical input / output ports, etc.). Other types of signal communication paths, such as fiber optic communication paths and / or wireless communication paths, can be used.

[0079] Volatile memory 410 is any type of volatile memory now known or to be developed in the future. Examples include dynamic random access memory (RAM) or static RAM. Typically, volatile memory is characterized by random access, but this is not necessary unless explicitly indicated. In computing device 101, volatile memory 410 is located in a single package and is internal to computing device 101; however, alternatively or additionally, volatile memory may be distributed across multiple packages and / or located externally relative to computing device 101.

[0080] Persistent storage 411 is any form of non-volatile storage for a computer, now known or to be developed in the future. The non-volatility of this storage means that the stored data is maintained regardless of whether power is supplied to computing device 101 and / or directly to persistent storage 411. Persistent storage 411 may be read-only memory (ROM), but typically at least a portion of persistent storage allows data to be written, deleted, and rewritten. Some common forms of persistent storage include disks and solid-state storage devices. Operating system 412 may take several forms, such as various known proprietary operating systems or open-source portable operating system interface type operating systems employing a kernel. The code included in box 401 typically includes at least some of the computer code involved in performing the methods of the present invention.

[0081] Peripheral device set 413 includes a collection of peripheral devices for computing device 101. Data communication connections between peripheral devices and other components of computing device 101 can be implemented in various ways, such as Bluetooth connectivity, near field communication (NFC) connectivity, connections via cables (such as Universal Serial Bus (USB) type cables), plug-in connections (e.g., Secure Digital (SD) cards), connections via local area communication networks, and even connections via wide area networks such as the Internet. In various embodiments, UI device set 414 may include components such as displays, speakers, microphones, wearable devices (such as goggles and smartwatches), keyboards, mice, printers, touchpads, game controllers, and haptic devices. Storage 415 is external storage (such as external hard drives) or pluggable storage (such as SD cards). Storage 415 can be persistent and / or volatile. In some embodiments, storage 415 may take the form of a quantum computing storage device for storing data in the form of qubits. In embodiments where computing device 101 requires substantial storage (e.g., where computing device 101 locally stores and manages a large database), this storage can be provided by peripheral storage devices designed to store very large amounts of data, such as a storage area network (SAN) shared by multiple geographically distributed computers. The IoT sensor set 416 includes sensors that can be used in IoT applications. For example, one sensor could be a thermometer, while another could be a motion detector.

[0082] Network module 417 is a collection of computer software, hardware, and firmware that allows computing device 101 to communicate with other computers via WAN 102. Network module 417 may include hardware such as a modem or Wi-Fi transceiver, software for packetizing and / or unpacking data transmitted over the communication network, and / or web browser software for transmitting data over the Internet. In some embodiments, the network control and network forwarding functions of network module 417 are performed on the same physical hardware device. In other embodiments (e.g., embodiments utilizing software-defined networking (SDN), the control and forwarding functions of network module 417 are performed on physically separate devices, such that the control function manages several different network hardware devices. Computer-readable program instructions for performing the methods of the present invention can typically be downloaded to computing device 101 from an external computer or external storage device via a network adapter card or network interface included in network module 417.

[0083] WAN 102 is any wide area network (e.g., the Internet) capable of transmitting computer data over non-local distances using any technology now known or to be developed in the future for transmitting computer data. In some embodiments, a WAN may be replaced and / or supplemented by a local area network (LAN) designed to transmit data between devices located in a local area, such as a Wi-Fi network. WANs and / or LANs typically include computer hardware such as copper transmission cables, optical fiber transmissions, wireless transmissions, routers, firewalls, switches, gateway computers, and edge servers.

[0084] End User Equipment (EUD) 402 is any computer system used and controlled by an end user (e.g., a customer of the enterprise operating computing device 101) and can take any of the forms discussed above in connection with computing device 101. EUD 402 typically receives helpful and useful data from the operation of computing device 101. For example, in a hypothetical scenario where computing device 101 is designed to provide recommendations to an end user, these recommendations would typically be passed from network module 417 of computing device 101 to EUD 402 via WAN 102. In this way, EUD 402 can display or otherwise present recommendations to the end user. In some embodiments, EUD 402 can be a client device, such as a thin client, a heavy client, a mainframe computer, a desktop computer, etc.

[0085] Remote server 403 is any computer system that provides at least some data and / or functionality to computing device 101. Remote server 403 can be controlled and used by the same entity operating computing device 101. Remote server 403 represents (multiple) machines that collect and store helpful and useful data for use by other computers, such as computing device 101. For example, if computing device 101 is designed and programmed to provide recommendations based on historical data, that historical data can be provided to computing device 101 from a remote database 418 of remote server 403.

[0086] Public cloud 404 is any computer system available to multiple entities, providing on-demand availability of computer system resources and / or other computing capabilities, particularly data storage (cloud storage) and computing power, without direct active management by the user. Cloud computing typically leverages resource sharing to implement consistency and economies of scale. Direct and active management of the computing resources of public cloud 404 is performed by the computer hardware and / or software of cloud orchestration module 420. The computing resources provided by public cloud 404 are typically implemented by virtual computing environments running on various computers constituting host physical set 421, which is the universe of physical computers in and / or available to public cloud 404. Virtual computing environments typically take the form of virtual machines from virtual machine set 422 and / or containers from container set 423. It should be understood that these VCEs can be stored as images and can be transferred between various physical machine hosts as images or after the VCEs are instantiated. Cloud orchestration module 420 manages the transfer and storage of images, deploys new instantiations of VCEs, and manages the active instantiation of VCE deployments. Gateway 419 is a collection of computer software, hardware, and firmware that allows public cloud 404 to communicate via WAN 102.

[0087] Now, we will provide some further explanation of Virtualized Computing Environments (VCEs). A VCE can be stored as an "image." A new active instance of a VCE can be instantiated from an image. Two familiar types of VCEs are virtual machines and containers. A container is a VCE that uses operating system-level virtualization. This refers to an operating system feature where the kernel allows multiple isolated user-space instances, called containers, to exist. From the perspective of the programs running within them, these isolated user-space instances typically appear as real computers. Computer programs running on a regular operating system can utilize all the resources of that computer, such as connected devices, files and folders, network shares, CPU power, and quantifiable hardware capabilities. However, programs running within a container can only use the contents of the container and the devices allocated to the container; this is a feature known as containerization.

[0088] Private cloud 405 is similar to public cloud 404, except that computing resources are only available for use by a single enterprise. While private cloud 405 is depicted as communicating with WAN 102, in other embodiments, private cloud can be completely disconnected from the internet and accessible only via a local / private network. A hybrid cloud is a combination of multiple clouds of different types (e.g., private, community, or public cloud types), typically implemented by different vendors. Each of the multiple clouds remains a separate and independent entity, but the larger hybrid cloud architecture is bound together by standardization or proprietary technology that enables orchestration, management, and / or data / application portability across the multiple component clouds. In this embodiment, both public cloud 404 and private cloud 405 are part of a larger hybrid cloud.

[0089] Box 401 also includes the above combination Figures 2-3 The software components discussed are designed to maximize the bandwidth utilization of PCIe links (e.g., PCIe link 105). In one embodiment, such components may be implemented in hardware. The functions performed by these components, as discussed above, are not general-purpose computer functions. Therefore, computing device 101 is a specific machine that results from the implementation of specific, non-general-purpose computer functions.

[0090] In one embodiment, the functionality of such a software component of computing device 101 (including functionality for maximizing bandwidth utilization of PCIe links (e.g., PCIe link 105)) can be embodied in an application-specific integrated circuit.

[0091] As mentioned above, the PCIe bus is a high-speed serial replacement for the older PCI / PCI-X buses. One of the key differences between the PCI Express bus and the older PCI is the bus topology. PCI uses a shared parallel bus architecture, where the PCI host and all devices share a common set of address, data, and control lines. In contrast, PCI Express is based on a point-to-point topology, where a separate serial link connects each device to the root complex (the host). Due to its shared bus topology, access to the older PCI bus was adjudicated (in the case of multiple hosts) and limited to one host at a time in a single direction. Furthermore, the older PCI clocking scheme limited the bus clock to the slowest peripheral on the bus (regardless of the device involved in the bus transaction). In contrast, PCIe bus links support full-duplex communication between any two endpoints without inherent limitations on concurrent access across multiple endpoints. PCIe devices, such as PCIe cards, communicate via logical connections called interconnects or links. A link is a point-to-point communication channel between two PCI Express ports, allowing them to send and receive common PCI requests (configuration, I / O, or memory read / write) and interrupts (INTx, MSI, or MSI-X). At the physical layer, a link consists of one or more channels. A channel consists of two differential signaling pairs, one pair for receiving data and the other for sending. Therefore, each channel consists of four wires or signal traces. Conceptually, each channel acts as a full-duplex byte stream, simultaneously transmitting data packets in eight-bit “byte” format in both directions between the endpoints of the link. A physical PCI Express link can contain 1, 4, 8, or 16 channels. As mentioned above, a PCIe card communicates with logical connections called interconnects or links. A PCIe card is a network adapter with a PCIe interface. PCIe cards are designed to fit into PCIe-based slots, such as slots in the motherboard of devices (e.g., hosts, servers, network switches, etc.). PCIe cards implement the PCIe protocol. Therefore, after inserting a PCIe card, a logical connection (“link”) is formed between the PCIe card and the motherboard, thus implementing a point-to-point communication channel between the two PCIe ports and allowing both to send and receive ordinary PCI requests and interrupts. Various generations or versions of PCIe exist, such as PCIe 1.0, PCIe 2.0, PCIe 3.0, PCIe 4.0, PCIe 5.0, and PCIe 6.0. Higher PCIe versions or generations utilize more power than previous generations, which had slower signaling rates. Each PCIe version supports approximately twice the bandwidth of previous versions of PCIe. Therefore, during periods of low bandwidth utilization, such higher versions or generations of PCIe have unused available bandwidth. In this case, power is wasted. Unfortunately, there are currently no means to limit or prevent this wasted power.

[0092] Embodiments of this disclosure provide a means for limiting or preventing such wasted power by switching the operating mode of a PCIe card so that the PCIe card switches to a less power-consuming operating mode during predicted low bandwidth utilization periods and switches to a more power-consuming operating mode during predicted high bandwidth utilization periods, as described below. Figures 5-6 The subject of discussion. Figure 5 This is a flowchart of a method for training a machine learning model to predict the bandwidth utilization of a PCIe link (e.g., PCIe link 105). Figure 6 This is a flowchart of a method for maximizing the bandwidth utilization of a PCIe link (e.g., PCIe link 105).

[0093] As mentioned above, Figure 5 This is a flowchart of a method 500 for training a machine learning model to predict the bandwidth utilization of a PCIe link (e.g., PCIe link 105) according to embodiments of the present disclosure.

[0094] refer to Figure 5 , combined Figures 1-4 In step 501, the measurement engine 201 of the computing device 101 tracks the bandwidth utilization of each PCIe link 105 established by each PCIe card 104 over a period of time (e.g., a week, a month).

[0095] As discussed above, bandwidth utilization as used herein refers to the rate at which data can flow through PCIe link 105. In one embodiment, such bandwidth utilization is provided as a percentage of the link transfer rate (such as 70% of the link transfer rate). In one embodiment, this bandwidth utilization is provided in bytes per second (e.g., 64 GB / s). Measurement engine 201 can utilize various tools to track the bandwidth utilization of each PCIe link 105, including but not limited to Intel® Performance Counter Monitor, 3DMark®, Libre Hardware Monitor, etc.

[0096] In one embodiment, the measurement engine 201 tracks the bandwidth utilization of the PCIe link 105 over a period of time. Such information can be used to train a machine learning model to predict the bandwidth utilization of the PCIe link 105 (e.g., at a specific future moment) based on the currently measured bandwidth utilization of the PCIe link 105, as discussed further below.

[0097] In step 502, the machine learning engine 202 of computing device 101 builds and trains a machine learning model to predict the bandwidth utilization of PCIe link 105 at future times using the tracking bandwidth utilization of each PCIe link 105.

[0098] As described above, this prediction of the bandwidth utilization of PCIe link 105 (e.g., PCIe link 105A) is provided by a machine learning model based on the currently measured bandwidth utilization of PCIe link 105 (e.g., PCIe link 105A) input to a trained machine learning model.

[0099] In one embodiment, the machine learning model is trained to predict the bandwidth utilization of PCIe link 105 at future times based on a sample dataset that includes the bandwidth utilization of PCIe link 105 tracked over a period of time. Such a sample dataset may be stored in a data structure (e.g., a table) residing in a storage device (e.g., storage devices 411, 415) of computing device 101.

[0100] Furthermore, in one embodiment, the sample dataset discussed above is referred to herein as "training data," which is used by a machine learning algorithm to predict the bandwidth utilization of PCIe link 105. The algorithm iteratively predicts the bandwidth utilization of PCIe link 105 using the training data until the prediction reaches the expected accuracy determined by experts. Examples of such learning algorithms include nearest neighbor, Naive Bayes, decision trees, linear regression, support vector machines, and neural networks.

[0101] After such a machine learning model has been trained, it can be utilized by the PCIe controller 203 of computing device 101 to use the following combination Figure 6 The trained machine learning model discussed predicts the bandwidth utilization of PCIe link 105 (e.g., PCIe link 105A) based on the measured bandwidth utilization (e.g., the currently measured bandwidth utilization) of PCIe link 105 (e.g., PCIe link 105A).

[0102] Figure 6 This is a flowchart of a method 600 for maximizing bandwidth utilization of a PCIe link (e.g., PCIe link 105) according to embodiments of the present disclosure.

[0103] refer to Figure 6 , combined Figures 1-5 In step 601, the measurement engine 201 of the computing device 101 measures the bandwidth utilization of the PCIe link 105 (e.g., PCIe link 105A) involving the PCIe card 104 (e.g., PCIe card 104A) at the current moment.

[0104] As described above, in one embodiment, such bandwidth utilization is provided as a percentage of the link transfer rate (such as 70% of the link transfer rate). In one embodiment, this bandwidth utilization is provided in bytes per second (e.g., 64 GB / s). Measurement engine 201 can utilize various tools to measure the bandwidth utilization of PCIe link 105 (e.g., PCIe link 105A) at the current moment, including but not limited to Intel® Performance Counter Monitor, 3DMark®, Libre Hardware Monitor, etc.

[0105] In step 602, the PCIe controller 203 of computing device 101 uses a trained machine learning model to predict the bandwidth utilization of PCIe link 105 (e.g., PCIe link 105A) at a future time based on the measured bandwidth utilization of PCIe link 105 (e.g., the currently measured bandwidth utilization of PCIe link 105 (e.g., PCIe link 105A)). In one embodiment, such measured bandwidth utilization (e.g., the currently measured bandwidth utilization of PCIe link 105 (e.g., PCIe link 105A)) is input into a trained machine learning model that outputs a predicted bandwidth utilization of PCIe link 105 (e.g., PCIe link 105A) at a future time (e.g., the next hour), which may be user-specified.

[0106] In step 603, the PCIe controller 203 of computing device 101 determines whether the predicted bandwidth utilization of PCIe link 105 at a future time exceeds a threshold, which may be user-specified. In one embodiment, such a threshold may be based on a percentage of the link transmission rate, such as 70% of the link transmission rate. In one embodiment, such a threshold may be bytes per second (e.g., 64 Gb / s).

[0107] As described above, in one embodiment, the PCIe controller 203 determines whether the predicted bandwidth utilization of the PCIe link 105 at a future time exceeds a threshold to determine which operating mode the PCIe card 104 forming such a PCIe link 105 should use. In one embodiment, the PCIe card 104 can operate in two different operating modes, such as a high-bandwidth operating mode and a low-bandwidth operating mode. As used herein, a high-bandwidth operating mode refers to the operating mode of the PCIe card 104 involving a higher version or generation of PCIe that utilizes more bandwidth. For example, such a higher version or generation of PCIe (e.g., PCIe 6.0) may correspond to a bandwidth utilization of 128 GB / s. As used herein, a low-bandwidth operating mode refers to the operating mode of the PCIe card 104 involving a lower version or generation of PCIe that utilizes less bandwidth. For example, such a lower version or generation of PCIe, such as PCIe 4.0, may correspond to a bandwidth utilization of 32 GB / s. Although two operating modes are discussed below, it should be noted that the principles of this disclosure can utilize any number of operating modes, wherein the utilization rate of each operating mode is determined based on the predicted bandwidth utilization of the PCIe link 105 between two threshold levels / values, which can be user-specified.

[0108] In one embodiment, this operating mode of the PCIe card 104 is established by selecting appropriate configuration settings for the PCIe card 104. In one embodiment, these configuration settings are stored in the memory of the PCIe card 104 (e.g., SEEPROM (Serial Electrically Erasable Programmable Read-Only Memory)). Figure 3 As shown.

[0109] refer to Figure 3 The PCIe card 104 includes a memory 301 (e.g., SEEPROM) configured to store configuration settings 302. Examples of memory 301 may include, but are not limited to, serial electrically erasable programmable read-only memory, dynamic random access memory, synchronous dynamic random access memory, static random access memory, etc.

[0110] As used herein, configuration setting 302 refers to a set of parameters that can be changed to affect the functionality of PCIe card 104. For example, such parameters can be modified by PCIe controller 203 to implement different operating modes of PCIe card 104, such as operating in an operating mode that provides higher bandwidth and therefore uses more power than another operating mode. In another example, such parameters can be modified by PCIe controller 203 to enable PCIe card 104 to operate in an operating mode that provides lower bandwidth and therefore uses less power than in the different operating modes.

[0111] In an alternative embodiment, the configuration settings 302 are stored in the storage device of the computing device 101 (e.g., storage devices 411, 415), thereby reducing the requirement to store configuration settings on each PCIe card 104.

[0112] If the predicted bandwidth utilization of PCIe link 105 in the future exceeds a threshold, then PCIe card 104 should operate in a first operating mode (e.g., PCIe 6.0), such as an operating mode that provides higher bandwidth and uses more power. In such a scenario, in step 604, the PCIe controller 203 of computing device 101 determines whether the operating mode of PCIe card 104 in the future is different from the operating mode that PCIe card 104 should operate in (e.g., the first operating mode). For example, if the predicted bandwidth of PCIe link 105 (e.g., PCIe link 105A) exceeds a threshold, then PCIe controller 203 determines whether PCIe card 104 is operating in the first operating mode when the bandwidth utilization of PCIe link 105 involving PCIe card 104 is predicted to exceed the threshold. For example, PCIe controller 203 may make such a determination at the moment when the bandwidth utilization of PCIe link 105 involving PCIe card 104 is predicted to exceed the threshold.

[0113] If PCIe card 104 operates in a first operating mode when the bandwidth utilization of PCIe link 105 involving PCIe card 104 is predicted to exceed a threshold, then PCIe card 104 continues to operate in the first operating mode, and the measurement engine 201 of calculation device 101 measures the bandwidth utilization of the same or different PCIe link 105 (e.g., PCIe link 105A) involving PCIe card 104 (e.g., PCIe card 104A) at the current moment in step 601.

[0114] If PCIe card 104 is not operating in the first operating mode (e.g., operating in the second operating mode) when the bandwidth utilization of PCIe link 105 involving PCIe card 104 is predicted to exceed a threshold, then in step 605, the PCIe controller 203 of computing device 101 determines whether there is currently traffic on PCIe link 105 (e.g., PCIe link 105A, whose predicted bandwidth utilization exceeds the threshold) before switching the operating mode of PCIe card 104 to operate in the first operating mode.

[0115] As described above, in one embodiment, traffic on PCIe link 105 (e.g., PCIe link 105A) is determined by traffic engine 204 of computing device 101. In one embodiment, traffic engine 204 determines the current traffic on PCIe link 105 (e.g., PCIe link 105A) by utilizing CATC® traces. In one implementation, CATC® traces combine uplink and downlink data paths into a single trace, even if they are parallel paths that can be active simultaneously. In one implementation, CATC® traces include several fields, such as fields indicating packet type (e.g., TLP (Transaction Layer Packet), DLLP (Data Link Layer Packet), etc.), packet payload, delay between the packet and the next packet on its data path, etc.

[0116] In one embodiment, the traffic flow engine 204 uses various software tools to determine the current traffic flow on PCIe link 105 (e.g., PCIe link 105A), and these software tools may include, but are not limited to, LogicMonitor®, Intel® VTune, etc. TM Analyzers, ManageEngine® NetFlow® Analyzer, SolarWind® Network Performance Monitor, Paessler® Network Monitor, etc.

[0117] If there is currently no traffic on PCIe link 105 (e.g., PCIe link 105A with predicted bandwidth utilization exceeding a threshold) before switching the operating mode of PCIe card 104 to the first operating mode, then in step 606, the PCIe controller 203 of computing device 101 selects the configuration settings (e.g., configuration settings 302) of PCIe card 104 to implement the first operating mode (e.g., PCIe 6.0) that corresponds to the operating mode that provides higher bandwidth and uses more power.

[0118] However, if there is currently traffic on PCIe link 105 (e.g., PCIe link 105A whose predicted bandwidth utilization exceeds a threshold) before switching the operating mode of PCIe card 104 to the first operating mode, then in step 607, the PCIe controller 203 of computing device 101 determines whether the traffic can be temporarily routed to a different PCIe link 105, such as a PCIe link 105 that currently has no traffic.

[0119] As described above, in one embodiment, the PCIe controller 203 determines whether there are currently different PCIe links 105 (e.g., PCIe link 105B) that do not display traffic. In one embodiment, the PCIe controller 203 instructs the traffic flow engine 204 to determine the current traffic flow on other PCIe links 105 (e.g., PCIe links 105B, 105C) to determine whether there are currently different PCIe links 105 (e.g., PCIe link 105B) that do not display traffic. The traffic flow engine 204 uses various software tools to perform this determination, including but not limited to LogicMonitor®, Intel® VTune, etc. TM Analyzers, ManageEngine® NetFlow® Analyzer, SolarWind® Network Performance Monitor, Paessler® Network Monitor, etc.

[0120] If traffic can be temporarily routed to a different PCIe link 105 (e.g., PCIe link 105B), then in step 608, the PCIe controller 203 of the computing device 101 routes the traffic to the different PCIe link 105 (e.g., PCIe link 105B). Afterwards, the PCIe controller 203 selects the configuration settings of the PCIe card 104 (e.g., configuration setting 302) to implement a first operating mode (e.g., PCIe 6.0) corresponding to an operating mode that provides higher bandwidth and uses more power.

[0121] However, if the service cannot be temporarily routed to a different PCIe link 105 (e.g., PCIe link 105B), then in step 609, the PCIe controller 203 of the computing device 101 waits for the data transmission on the PCIe link 105 (e.g., PCIe link 105A) of the PCIe card 104 (e.g., PCIe card 104A) whose operating mode needs to be switched to complete. Afterward, the PCIe controller 203 selects the configuration settings of the PCIe card 104 (e.g., configuration setting 302) to implement a first operating mode (e.g., PCIe 6.0) corresponding to an operating mode that provides higher bandwidth and uses more power.

[0122] In this way, the bandwidth utilization of PCIe link 105 is maximized and the amount of wasted power is minimized.

[0123] Returning to step 603, however, if the predicted bandwidth utilization of PCIe link 105 at a future time does not exceed a threshold (which may be user-specified), then PCIe card 104 should operate in a second operating mode (e.g., PCIe 4.0) (such as an operating mode that provides lower bandwidth and uses less power). In such a scenario, in step 610, the PCIe controller 203 of computing device 101 determines whether the operating mode of PCIe card 104 at a future time is different from the operating mode that PCIe card 104 should operate in (e.g., the second operating mode). For example, if the predicted bandwidth of PCIe link 105 (e.g., PCIe link 105A) does not exceed the threshold, then PCIe controller 203 determines whether PCIe card 104 is operating in the second operating mode when the bandwidth utilization of PCIe link 105 involving PCIe card 104 is predicted to not exceed the threshold. For example, PCIe controller 203 may make such a determination at the moment when the bandwidth utilization of PCIe link 105 involving PCIe card 104 is predicted to not exceed the threshold.

[0124] If PCIe card 104 is operating in a second operating mode when the bandwidth utilization of PCIe link 105 involving PCIe card 104 is predicted to not exceed a threshold, then PCIe card 104 continues to operate in the second operating mode, and the measurement engine 201 of calculation device 101 measures the bandwidth utilization of the same or different PCIe link 105 (e.g., PCIe link 105A) involving PCIe card 104 (e.g., PCIe card 104A) at the current moment in step 601.

[0125] If PCIe card 104 is not operating in the second operating mode (e.g., operating in the first operating mode) when the bandwidth utilization of PCIe link 105 involving PCIe card 104 is predicted to not exceed a threshold, then in step 611, the PCIe controller 203 of computing device 101 determines whether there is currently traffic on PCIe link 105 (e.g., PCIe link 105A, whose predicted bandwidth utilization does not exceed the threshold) before switching the operating mode of PCIe card 104 to operate in the second operating mode.

[0126] As described above, in one embodiment, traffic on PCIe link 105 (e.g., PCIe link 105A) is determined by traffic engine 204 of computing device 101. In one embodiment, traffic engine 204 determines the current traffic on PCIe link 105 (e.g., PCIe link 105A) by utilizing CATC® traces. In one implementation, CATC® traces combine uplink and downlink data paths into a single trace, even if they are parallel paths that can be active simultaneously. In one implementation, CATC® traces include several fields, such as fields indicating packet type (e.g., TLP (Transaction Layer Packet), DLLP (Data Link Layer Packet), etc.), packet payload, delay between the packet and the next packet on its data path, etc.

[0127] In one embodiment, the traffic flow engine 204 uses various software tools to determine the current traffic flow on PCIe link 105 (e.g., PCIe link 105A), and these software tools may include, but are not limited to, LogicMonitor®, Intel® VTune, etc. TM Analyzers, ManageEngine® NetFlow® Analyzer, SolarWind® Network Performance Monitor, Paessler® Network Monitor, etc.

[0128] If there is currently no traffic on PCIe link 105 (e.g., PCIe link 105A whose predicted bandwidth utilization does not exceed a threshold) before switching the operating mode of PCIe card 104 to the second operating mode, then in step 612, the PCIe controller 203 of computing device 101 selects the configuration settings of PCIe card 104 (e.g., configuration settings 302) to implement the second operating mode (e.g., PCIe 4.0) that corresponds to the operating mode that provides lower bandwidth and uses less power.

[0129] However, if there is currently traffic on PCIe link 105 (e.g., PCIe link 105A whose predicted bandwidth utilization does not exceed a threshold) before switching the operating mode of PCIe card 104 to the second operating mode, then in step 613, the PCIe controller 203 of computing device 101 determines whether the traffic can be temporarily routed to a different PCIe link 105, such as a PCIe link 105 that currently has no traffic.

[0130] As described above, in one embodiment, the PCIe controller 203 determines whether there are currently different PCIe links 105 (e.g., PCIe link 105B) that do not display traffic. In one embodiment, the PCIe controller 203 instructs the traffic flow engine 204 to determine the current traffic flow on other PCIe links 105 (e.g., PCIe links 105B, 105C) to determine whether there are currently different PCIe links 105 (e.g., PCIe link 105B) that do not display traffic. The traffic flow engine 204 uses various software tools to perform this determination, including but not limited to LogicMonitor®, Intel® VTune, etc. TM Analyzers, ManageEngine® NetFlow® Analyzer, SolarWind® Network Performance Monitor, Paessler® Network Monitor, etc.

[0131] If traffic can be temporarily routed to a different PCIe link 105 (e.g., PCIe link 105B), then in step 614, the PCIe controller 203 of computing device 101 routes the traffic to the different PCIe link 105 (e.g., PCIe link 105B). Afterwards, the PCIe controller 203 selects the configuration settings of the PCIe card 104 (e.g., configuration setting 302) to implement a second operating mode (e.g., PCIe 4.0) corresponding to an operating mode that provides lower bandwidth and uses less power.

[0132] However, if the service cannot be temporarily routed to a different PCIe link 105 (e.g., PCIe link 105B), in step 615, the PCIe controller 203 of the computing device 101 waits for the data transmission on the PCIe link 105 (e.g., PCIe link 105A) of the PCIe card 104 (e.g., PCIe card 104A) whose operating mode needs to be switched to complete. Afterward, the PCIe controller 203 selects the configuration settings (e.g., configuration setting 302) of the PCIe card 104 to implement a second operating mode (e.g., PCIe 4.0) corresponding to an operating mode that provides lower bandwidth and uses less power.

[0133] In this way, the bandwidth utilization of PCIe link 105 is maximized and the amount of wasted power is minimized.

[0134] In one embodiment, in conjunction with selecting the configuration setting 302 of PCIe card 104 as described above to switch the operating mode of PCIe card 104, the operating mode is switched by resetting PCIe link 105 (the PCIe link 105 of the PCIe card 104 whose operating mode is switched) and PCIe slot, and then the new operating mode of PCIe card 104 is implemented.

[0135] In one embodiment, based on the operating mode of the PCIe card 104, traffic consisting of workloads or transactions is directed via the PCIe link 105 to a specific logical partition of the hardware. For example, in one embodiment, workloads involving a marketing website or analytics platform may be directed to a first set of logical partitions of the hardware in response to the PCIe card 104 operating in a first operating mode (e.g., a high-bandwidth operating mode), and to a second set of logical partitions of the hardware in response to the PCIe card 104 operating in a second operating mode (e.g., a low-bandwidth operating mode).

[0136] In one embodiment, a data structure (e.g., a table) contains information about the set of hardware logical partitions that will be used to specify workloads or transactions based on the operating mode of the PCIe card 104. In one embodiment, the PCIe controller 203 determines the type of workload or transaction based on a classification of the workload or transaction (e.g., a classification assigned to such a workload or transaction using a Workload Management (WLM) workload classification rule published by MVS™ (Multiple Virtual Storage) Workload Management). After determining the type of workload or transaction, this classification is associated with a specific logical partition of the hardware based on the operating mode of the PCIe card 104 indicated in the data structure (e.g., the table) discussed above. In one embodiment, such a data structure resides within a storage device (e.g., storage devices 411, 415) of the computing device 101. In one embodiment, such a data structure is populated by an expert.

[0137] In summary, the principles of this disclosure provide a method for limiting or preventing wasted power by switching the operating modes of a PCIe card, such that the PCIe card switches to an operating mode that uses less power during periods of predicted low bandwidth utilization of the PCIe link involving the PCIe card, and switches to an operating mode that uses more power during periods of predicted high bandwidth utilization of the PCIe link involving the PCIe card.

[0138] Furthermore, the principles of this disclosure improve upon the technology or technical field involving Peripheral Component Interconnect High Speed ​​Edition (PCIe).

[0139] As described above, a power supply system may include a power module that provides physical housing for several power components such as switching regulators (e.g., DC-DC switching regulators) and low-dropout (LDO) regulators. A switching regulator, such as a DC-DC switching regulator, converts an input DC voltage to the desired DC voltage. An LDO regulator is a DC linear voltage regulator that regulates the output voltage even when the input voltage is very close to the output voltage. Multiple regulators (such as switching regulators and LDO regulators) can be placed close to the processor chip or module to meet the processor's point-of-load (POL) requirements (e.g., low noise margin, high inrush current, etc.). Point-of-load (POL) power supplies address the challenges of high peak current requirements and low noise margins required by high-performance semiconductors (e.g., microcontrollers or ASICs) by placing individual power regulators (linear or DC-DC) near their point of use. To implement a high-current power supply system to power high-power multi-voltage systems, the power module of the power supply system needs to utilize multiple regulators, such as those discussed above, to implement a POL for power distribution, saving space for multiple power supplies and enabling system portability. In some cases, power supply modules in a power system need to handle current surges (referred to herein as "inrush currents") caused by a sudden increase in workload, such as in high-power multi-voltage systems. These current surges may not be handled by the power supply module alone. For example, decoupling capacitors (capacitors used to decouple one part of a circuit from another) may fail to maintain the correct voltage level to power the load. Furthermore, inrush currents can cause malfunctions in power supply modules, such as for switching regulators (e.g., DC-DC switching regulators), due to inductor saturation or power switch failure. Additionally, a failure of a switching regulator (e.g., a DC-DC switching regulator) can lead to operational problems for an LDO regulator because the input voltage and current are supplied by such a switching regulator. Unfortunately, there is currently no effective method to handle these current surges (inrush currents) in a power supply module caused by a sudden increase in operating load.

[0140] Embodiments of this disclosure improve this technology by measuring the bandwidth utilization of the PCIe link involving the PCIe card. In one embodiment, such bandwidth utilization is provided as a percentage of the link transmission rate (such as 70% of the link transmission rate). In another embodiment, such bandwidth utilization is provided in bytes per second (e.g., 64 GB / s). Using a machine learning model trained to predict the bandwidth utilization of the PCIe link, the bandwidth utilization of the PCIe link in the future is predicted based on the measured bandwidth utilization. If the predicted bandwidth utilization of the PCIe link exceeds a threshold, the operating mode of the PCIe card is switched to implement a first operating mode (e.g., a higher version or generation of PCIe), which utilizes more bandwidth if it is not implemented in the future. If the predicted bandwidth utilization of the PCIe link does not exceed the threshold, the operating mode of the PCIe card is switched to implement a second operating mode (e.g., a lower version or generation of PCIe), which utilizes less bandwidth if it is not implemented in the future. In this way, the bandwidth utilization of the PCIe link is maximized and the amount of wasted power is minimized. Furthermore, this approach represents an improvement in the field of peripheral component interconnect (PCIe) technology.

[0141] The technical solutions provided in this disclosure cannot be executed in the human mind, nor can they be executed by humans using pen and paper. In other words, the technical solutions provided in this disclosure cannot be expected to be completed in the human mind or by humans using pen and paper in any reasonable time with any reasonable accuracy without the use of a computer.

[0142] Various embodiments of this disclosure have been described for illustrative purposes, but are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein has been chosen to best explain the principles of the embodiments, their practical application, or technical improvements to technologies found in the market, or to enable those skilled in the art to understand the embodiments disclosed herein.

Claims

1. A computer-implemented method for maximizing bandwidth utilization of a Peripheral Component Interconnect High Speed ​​Edition (PCIe) link, the method comprising: Measure the bandwidth utilization of the PCIe link involving the PCIe card; The bandwidth utilization of the PCIe link is predicted based on the measured bandwidth utilization of the PCIe link using a machine learning model trained to predict the bandwidth utilization of the PCIe link. as well as The operating mode of the PCIe card is switched based on the predicted bandwidth utilization of the PCIe link.

2. The method according to claim 1, further comprising: In response to the predicted bandwidth utilization of the PCIe link exceeding a threshold, the PCIe card configuration is selected to implement a first operating mode, wherein the first operating mode is a later PCIe version than a second operating mode.

3. The method according to claim 1, further comprising: In response to the predicted bandwidth utilization of the PCIe link not exceeding a threshold, the configuration settings of the PCIe card are selected to implement a second operating mode, wherein the second operating mode is an earlier PCIe version than the first operating mode.

4. The method according to claim 1, further comprising: In response to the predicted bandwidth utilization of the PCIe link exceeding a threshold, it is determined whether the current operating mode of the PCIe card is the first operating mode. as well as In response to the PCIe card's current operating mode being in a second operating mode, it is determined whether there is currently traffic on the PCIe link involving the PCIe card.

5. The method according to claim 4, further comprising: In response to the presence of traffic on the PCIe link involving the PCIe card, the traffic is routed to a different PCIe link; as well as The PCIe card is configured to implement the first operating mode when routing traffic to the different PCIe links.

6. The method according to claim 1, further comprising: In response to the predicted bandwidth utilization of the PCIe link not exceeding a threshold, it is determined whether the current operating mode of the PCIe card is the second operating mode. as well as In response to the PCIe card's current operating mode being in a first operating mode, it is determined whether there is currently traffic on the PCIe link involving the PCIe card.

7. The method according to claim 6, further comprising: In response to the presence of traffic on the PCIe link involving the PCIe card, the traffic is routed to a different PCIe link; as well as The PCIe card is configured to implement the second operating mode when routing traffic to the different PCIe links.

8. A computer program product for maximizing bandwidth utilization of a Peripheral Component Interconnect High Speed ​​Edition (PCIe) link, the computer program product comprising one or more computer-readable storage media having program code embodied therein, the program code including programming instructions for: Measure the bandwidth utilization of the PCIe link involving the PCIe card; The bandwidth utilization of the PCIe link is predicted based on the measured bandwidth utilization of the PCIe link using a machine learning model trained to predict the bandwidth utilization of the PCIe link. as well as The operating mode of the PCIe card is switched based on the predicted bandwidth utilization of the PCIe link.

9. The computer program product according to claim 8, wherein, The program code also includes programming instructions for the following operations: In response to the predicted bandwidth utilization of the PCIe link exceeding a threshold, the PCIe card configuration is selected to implement a first operating mode, wherein the first operating mode is a later PCIe version than a second operating mode.

10. The computer program product according to claim 8, wherein, The program code also includes programming instructions for the following operations: In response to the predicted bandwidth utilization of the PCIe link not exceeding a threshold, the configuration settings of the PCIe card are selected to implement a second operating mode, wherein the second operating mode is an earlier PCIe version than the first operating mode.

11. The computer program product according to claim 8, wherein, The program code also includes programming instructions for the following operations: In response to the predicted bandwidth utilization of the PCIe link exceeding a threshold, it is determined whether the current operating mode of the PCIe card is a first operating mode; and In response to the PCIe card's current operating mode being in a second operating mode, it is determined whether there is currently traffic on the PCIe link involving the PCIe card.

12. The computer program product according to claim 11, wherein, The program code also includes programming instructions for the following operations: In response to the presence of traffic on the PCIe link involving the PCIe card, the traffic is routed to a different PCIe link; as well as The PCIe card is configured to implement the first operating mode when routing traffic to the different PCIe links.

13. The computer program product according to claim 8, wherein, The program code also includes programming instructions for the following operations: In response to the predicted bandwidth utilization of the PCIe link not exceeding a threshold, it is determined whether the current operating mode of the PCIe card is the second operating mode. as well as In response to the PCIe card's current operating mode being in a first operating mode, it is determined whether there is currently traffic on the PCIe link involving the PCIe card.

14. The computer program product according to claim 13, wherein, The program code also includes programming instructions for the following operations: In response to the presence of traffic on the PCIe link involving the PCIe card, the traffic is routed to a different PCIe link; as well as The PCIe card is configured to implement the second operating mode when routing traffic to the different PCIe links.

15. A system comprising: Memory is used to store computer programs for maximizing bandwidth utilization of the PCIe (Peripheral Component Interconnect) link. as well as A processor connected to the memory, wherein the processor is configured to execute program instructions of the computer program, the program instructions including: Measure the bandwidth utilization of the PCIe link involving the PCIe card; Using a machine learning model trained to predict the bandwidth utilization of a PCIe link, the bandwidth utilization of the PCIe link is predicted based on the measured bandwidth utilization of the PCIe link; and The operating mode of the PCIe card is switched based on the predicted bandwidth utilization of the PCIe link.

16. The system of claim 15, wherein the program instructions of the computer program further include: In response to the predicted bandwidth utilization of the PCIe link exceeding a threshold, the PCIe card configuration is selected to implement a first operating mode, wherein the first operating mode is a later PCIe version than a second operating mode.

17. The system of claim 15, wherein the program instructions of the computer program further include: In response to the predicted bandwidth utilization of the PCIe link not exceeding a threshold, the configuration settings of the PCIe card are selected to implement a second operating mode, wherein the second operating mode is an earlier PCIe version than the first operating mode.

18. The system of claim 15, wherein the program instructions of the computer program further include: In response to the predicted bandwidth utilization of the PCIe link exceeding a threshold, it is determined whether the current operating mode of the PCIe card is the first operating mode. as well as In response to the PCIe card's current operating mode being in a second operating mode, it is determined whether there is currently traffic on the PCIe link involving the PCIe card.

19. The system of claim 18, wherein the program instructions of the computer program further include: In response to the presence of traffic on the PCIe link involving the PCIe card, the traffic is routed to a different PCIe link; as well as The PCIe card is configured to implement the first operating mode when routing traffic to the different PCIe links.

20. The system of claim 15, wherein the program instructions of the computer program further include: In response to the predicted bandwidth utilization of the PCIe link not exceeding a threshold, it is determined whether the current operating mode of the PCIe card is the second operating mode. as well as In response to the PCIe card's current operating mode being in a first operating mode, it is determined whether there is currently traffic on the PCIe link involving the PCIe card.

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