Optimization for mitigating frequency crowding in multi-qubit processors

Abstract

A plurality of qubit collision types and a plurality of constraints are defined. For a set of qubits, a computerized mixed integer programming solver is used to iteratively minimize collisions under the constraints by minimizing a sum of a product of a number of collisions of each collision type given a constraint multiplied by a weight. A frequency tuning plan for the set of qubits is output based on the iterative minimization. The physical qubits are facilitated to be tuned in accordance with the frequency tuning plan.

Description

Background Technology

[0001] This invention relates to the fields of electrical, electronic and computer technology, and more specifically, to the computer-aided design of quantum computing systems.

[0002] Quantum computers utilize quantum mechanics; that is, the fact that matter exhibits both particle and wave properties at small scales. Quantum computers use qubits, similar to bits in conventional digital computing.

[0003] Qubits can be implemented using many modes. Some common modes include superconducting qubits based on circuit quantum electrodynamics (cQED) architecture, ion trap qubits, spin qubits, and neutral atom or photon qubits. The most common mode is the superconducting qubit. Superconducting qubit modes require cooling to extremely low temperatures using cryostats, dilution refrigerators, etc. A relevant example of a superconducting qubit is a fixed-frequency transmon. Quantum computers operate through quantum logic gates between qubits. Such gates can be implemented using, for example, microwave-activated coupling, fast-tunable coupling, or parametric coupling between the qubits forming the gate.

[0004] A major challenge in scaling up fixed-frequency architectures is mitigating errors caused by lattice frequency collisions. LASIQ (Laser Annealing of Randomly Damaged Qubits) technology has been developed to increase the collision-free yield of transmon lattices by selectively tuning (i.e., tuning) the frequency of individual qubits through laser thermal annealing. Qubits can be addressed using a unique frequency; however, undesirable collisions can occur when the frequencies of two nearest or second-nearest neighbor qubits become too close, or, for example, when the frequency spacing between adjacent qubits is in a similar range to the qubit anharmonicity. Other variations of such frequency collisions can occur, and their precise definitions will depend on the type of gate used in the quantum processor. Generally, care should be taken in qubit frequency allocation to ensure that frequency collision regions are avoided, as frequency congestion is a pervasive and industry-wide problem affecting gate fidelity. Summary of the Invention

[0005] The principles of this invention provide optimized techniques for mitigating frequency congestion in multi-qubit processors. In one aspect, an exemplary method includes the steps of: defining a plurality of qubit collision types and a plurality of constraints; for a qubit group, using a computerized mixed-integer programming solver to iteratively minimize collisions under the constraints by minimizing the sum of the products of the number of frequency collisions multiplied by weights for a given constraint in each of the collision types; outputting a frequency tuning plan for the qubit group based on the iterative minimization; and facilitating the tuning of physical qubits according to the frequency tuning plan.

[0006] Optionally, the method further includes, after iteratively minimizing collisions, using the computerized mixed-integer programming solver to iteratively maximize the frequency margin under the constraints for the qubit set.

[0007] In another aspect, an exemplary computer program product includes a computer-readable storage medium having program instructions embodied thereon. The program instructions are executable by a processor to cause the processor to perform a method comprising the steps of: defining a plurality of qubit collision types and a plurality of constraints; for a qubit group, using a computerized mixed-integer programming solver to iteratively minimize collisions under the constraints by minimizing the sum of the products of the number of frequency collisions multiplied by weights for a given constraint in each of the collision types; outputting a frequency tuning plan for the qubit group based on the iterative minimization; and facilitating the tuning of physical qubits according to the frequency tuning plan.

[0008] In another aspect, an exemplary device includes: a memory; and at least one processor coupled to the memory and operated to: define a plurality of qubit collision types and a plurality of constraints; for a qubit group, iteratively minimize collisions under the constraints by using a computerized mixed-integer programming solver to minimize the sum of the products of the number of frequency collisions multiplied by weights for a given constraint in each of the collision types; output a frequency tuning plan for the qubit group based on the iterative minimization; and facilitate the tuning of physical qubits according to the frequency tuning plan.

[0009] Optionally, the at least one processor is also operated to control the LASIQ tuning machine to tune the chip according to the plan.

[0010] As used herein, "facilitating" an action includes performing an action, making an action easier, assisting in performing an action, or causing an action to be performed. Therefore, by way of example only and not limitation, instructions executing on a processor can facilitate an action performed by instructions executing on the LASIQ tool or on a remote processor controlling the LASIQ tool by sending appropriate data or commands to cause or assist in performing that action. To avoid confusion, when an actor facilitates an action in a manner other than performing an action, the action is still performed by an entity or combination of entities.

[0011] One or more embodiments of the present invention or elements thereof may be implemented as a computer program product comprising a computer-readable storage medium having computer-usable program code for performing the indicated method steps. Furthermore, one or more embodiments of the present invention or elements thereof may be implemented as a system (or apparatus) including a memory and at least one processor coupled to the memory and configured to perform the exemplary method steps. Further still, in another aspect, one or more embodiments of the present invention or elements thereof may be implemented as an apparatus for performing one or more method steps described herein; the apparatus may include (i) a hardware module, (ii) a software module stored in a computer-readable storage medium (or multiple such media) and implemented on a hardware processor, or (iii) a combination of (i) and (ii); any of (i)-(iii) implements the specific techniques set forth herein.

[0012] The techniques disclosed herein can provide significantly beneficial technical effects. Some embodiments may not have these potential advantages, and these potential advantages are not necessarily required in all embodiments. One or more embodiments may provide one or more of the following, by way of example only and without limitation:

[0013] Technological processes for improving the computer-aided design of quantum computing systems by enhancing tuning precision and / or tuning accuracy.

[0014] The technical process of improving the computer-aided design of quantum computing systems by increasing tuning yield compared to existing technology systems;

[0015] Improve the performance of a quantum computing system designed according to an exemplary embodiment by increasing tuning accuracy compared to existing technology systems;

[0016] Technological processes for improving the computer-aided design of quantum systems can be enhanced by increasing the speed of frequency tuning scheme generation for multi-qubit and / or modular processors.

[0017] The yield of available processors and / or modular processors is significantly increased. As used herein, “yield” refers to the proportion of a quantum processor, a chip within a modular processor, or a qubit within a chip whose frequency can be set to eliminate frequency collisions and / or minimize gate errors. Yield metrics can take into account the frequency shifts or other random variations expected to occur after tuning. These variations can be statistically evaluated using Monte Carlo models or other known probabilistic or statistical modeling methods. In the context of quantum processors, availability can be understood as an advantage in terms of gate speed, gate fidelity, low collision count, or any other metric that can be used to improve the quality of quantum computing;

[0018] Fewer collisions can lead to a reduction in the time required to run quantum algorithms and the supporting CPU (classical computation and corresponding computational energy); that is, it saves CPU time for the computer running the design algorithm.

[0019] These and other features and advantages of the invention will become clear from the following detailed description of exemplary embodiments, which should be read in conjunction with the accompanying drawings. Attached Figure Description

[0020] Figure 1 A rendering depicting the regular spacing of a "heavy hexagonal" fixed-frequency transmon qubit lattice of an exemplary chip that can be tuned according to various aspects of the present invention;

[0021] Figure 2-5 An exemplary sublattice is shown according to various aspects of the present invention;

[0022] Figure 6 and 7 Collision definitions for 1.0% door error and 0.5% door error according to various aspects of the present invention are shown respectively;

[0023] Figure 8 and 9 Optimization models for minimizing collisions and maximizing margins for a 0.5% gate error are shown respectively according to various aspects of the present invention;

[0024] Figure 10 An exemplary workflow for a frequency tuning scheme according to various aspects of the present invention is shown;

[0025] Figure 11 An exemplary tuning scheme generation according to various aspects of the present invention is illustrated;

[0026] Figure 12 An exemplary feedback process is shown, according to various aspects of the present invention, for achieving in-situ yield improvement by regenerating a new tuning schedule as tuning progresses;

[0027] Figure 13 The iterative tuning cycles according to various aspects of the present invention are described;

[0028] Figure 14 Exemplary yield assessments according to various aspects of the present invention are described;

[0029] Figure 15-18 Exemplary results for LASIQ tuning to optimization schemes according to various aspects of the present invention are shown;

[0030] Figure 19 A computing environment according to an embodiment of the present invention is described. Detailed Implementation

[0031] LASIQ tuning is the process of progressively changing the resistance of a Josephson junction. For this purpose, LASIQ can be used to tune any quantum element that includes one or more Josephson junctions. For example, a fixed-frequency transmon qubit includes a Josephson junction shunted by a capacitor, whereby the Josephson junction behaves as a nonlinear inductive element, allowing the qubit to exhibit non-uniform energy spacing between successive energy levels (i.e., the qubit exhibits anharmonicity, which allows for a uniquely addressable ground state and first excited state). By performing LASIQ on these fixed-frequency transmon qubits, the Josephson junction resistance can be modified post-fabrication, and the transmon qubit frequency can be modified accordingly. In this case, LASIQ can therefore be used as a post-fabrication frequency adjustment tool to design the qubit frequency to conform to the desired frequency pattern.

[0032] Transmon qubits with fixed frequencies are typically fabricated using lattice geometries (e.g., heavy hexagonal lattices, square lattices, etc.). Furthermore, qubits are known to suffer from frequency congestion, caused by energy level degeneracy between adjacent and second-nearest neighbor qubits, and even higher-order connectivity can be considered. This frequency congestion can be quantized by the number of collisions exhibited by the multi-qubit lattice. Each collision type can be defined by frequency bounds that qubit pairs or triplets are forbidden from entering. Similarly, other undesirable adjacent, second-nearest neighbor, or more distant neighbor interactions can be enumerated, and frequency bounds can be similarly defined as needed. If these bounds are violated, high gate errors will be observed, leading to low gate fidelity. LASIQ, a laser annealing method, uses a series of annealing "pulses" to iteratively tune the Josephson junction resistance to gradually and monotonically approach their respective target resistances, thereby designing the qubit frequencies to desired values, levels, modes, etc.

[0033] As used herein, the term "pulse" refers to a laser annealing operation performed by applying laser power to a target element (e.g., a Josephson junction) for a specified duration (annealing time) to tune the target element. In the context of the exemplary embodiments of this disclosure discussed herein, a laser tuning method is provided to tune the junction resistance of a Josephson junction in a stepwise and incremental manner, wherein multiple "pulses" are applied to a given Josephson junction to tune its junction resistance to a target junction resistance.

[0034] The term "annealing iteration," as used herein and in the context of laser annealing processing, refers to a process involving a single laser pulse and associated control, measurement, and calculation by a LASIQ computer system and apparatus to determine the required annealing time and power for the annealing pulse. Therefore, laser annealing iteration or LASIQ iteration refers to the entire process by which the Josephson junction is measured, the annealing power and time are determined, and the annealing pulse is executed. In this sense, an iteration involves the entire sequence of laser annealing systems and apparatuses, as it corresponds to a step toward a resistance target for a Josephson junction. Tuning a junction to completion (i.e., reaching its resistance target) can be described as proceeding in an "iterative" manner. The term "iterative process," as used herein, generally refers to a set of iterations, such as those applicable to one or more qubit devices or the like (including Josephson junctions), whereby the one or more qubit devices are tuned toward their respective targets.

[0035] The term "round" or "annealing round" as used herein and in the context of laser annealing processing refers to a tuning process in which all qubits on a multi-qubit device undergo laser annealing sequentially, and which may be followed by another round or a series of rounds. Such rounds can be performed continuously until all qubits on the multi-qubit device have reached their respective goals. For example, a monolithic quantum chip may include multiple qubit devices comprising Josephson junctions (e.g., 100 qubits, denoted as Q1, Q2, Q3, ..., Q100). In an exemplary embodiment of the tuning method, Q1 is first tuned with one or more annealing iterations, as desired. The process continues to Q2, where one or more annealing iterations may be performed, as desired. The process then continues to Q3, and so on, until finally Q100 is tuned with one or more annealing iterations, as desired. The entire process from Q1 to Q100 is defined as one round. After this first round, the process may return to Q1 and will be repeated again until Q100 is reached. The continuous polling process can provide timing control and delay between iterations or iteration groups, allowing Josephson junctions to relax to their final resistance before the next annealing iteration or iteration group.

[0036] The term "optimization iteration," as used in this paper and in the context of the frequency scheme generated by the optimization routine, refers to the process of solving a frequency pattern covering the entire lattice using an optimization routine based on a mixed-integer programming routine. This frequency pattern assigns an operating frequency to each qubit in the lattice, aiming to mitigate collisions with nearest-neighbor, second-nearest-neighbor, or any other n-degree neighboring qubits, with the goal of maximizing single-qubit and multi-qubit gate fidelity. During each optimization iteration, a frequency scheme is generated for the entire lattice at a time by tiling a series of sublattices, which may include qubits overlapping with adjacent sublattices. Note that many sublattices will typically be identical; however, some sublattices are often dissimilar, for example, around the corners of a heavy hexagonal lattice (sublattices around corners may not have complete qubits consisting of H-shapes or rings). After a given optimization iteration is completed, another iteration can be subsequently implemented to remove any remaining collisions. Therefore, in the process of continuous optimization iterations, increasingly improved solutions can be achieved, resulting in a gradually decreasing collision count, and the desired number of optimization iterations can be specified by a skilled operator in the art (e.g., heuristically based on the teachings of this paper), or can be automated using a yield metric that specifies, for example, that the solution must exceed a target gate fidelity that is accepted and for which the LASIQ tuning process subsequently begins.

[0037] During LASIQ tuning, the frequency typically approaches the target monotonically and iteratively, where a resistance target or equivalent frequency target is determined by a frequency tuning scheduler. This iterative approach is based on successive laser “pulses” that asymptotically move the qubit frequency toward the target frequency. This asymptotic and incremental tuning approach reduces the risk of overshoot or undershoot in junction resistance. To ensure this asymptotic approach, various calibration structures can be used to determine the typical tuning rate and range of the Josephson junction, using dedicated test structures that may be interleaved and / or located on unused areas of the chip (e.g., chip “kerfs,” which are unused areas that physically separate two adjacent dies on a wafer, or test pieces), or using “sister” chips that have undergone the same process steps during manufacturing. However, despite these measures to avoid overshoot or undershoot, the statistical probability of such anomalies increases and becomes virtually unavoidable as quantum chips scale to hundreds or thousands of qubits and beyond. In other words, given the massive scale of modern quantum processors, it is essentially impossible to successfully achieve the target frequency for all qubits as designed in the initial tuning plan. This is detrimental to chip yield (e.g., by collision-free probability assessment), leading to chip discarding (e.g., due to the expected high gate error rate). The net effect involves a significant reduction in the number of usable processors obtained given a batch of chips to be tuned. One or more embodiments provide techniques for in-situ and adaptive target modification to correct these tuning errors and defects to improve quantum processor yield.

[0038] Yield metrics for quantum processors can be evaluated using deterministic and statistical analysis or similar methods. For example, a common yield metric could include the number of collisions in a tuned chip, or a comparison of the number of collisions before and after LASIQ tuning. However, more sophisticated methods can be implemented to determine the expected number of collisions achievable after the quantum processor has been completed and cooled in a cryostat. These methods are applicable to single-chip processors and to both within and across each chip in modular devices. This can be accomplished, for example, by using Monte Carlo methods or similar approaches, whereby the predicted frequencies undergo a random scattering whose amplitude is defined by frequency precision intervals (e.g., 20 MHz), and the impact of the scattering on the expected number of collisions is quantitatively assessed. Equivalently, the expected probability of a zero-collision chip on non-modular or modular devices can be calculated. Another metric that can be used is the prediction of gate error rate, gate fidelity, and / or gate speed. Such models, in addition to considering the qubit frequency after LASIQ tuning, can also consider, for example, the qubit coherence time. These models depend on the architecture. However, one or more embodiments for adaptive and in-situ modifications of such tuning schemes are not limited to any particular tuning scheme generation method or multi-qubit architecture. Rather, given a known lattice architecture and qubit coupling mechanism, as well as acceptable yield metrics, one or more embodiments can be implemented to significantly improve the overall proportion of acceptable chips. Once the multi-qubit chip is successfully tuned, these yield metrics can be used to select desired candidates for further cryogenic screening, whereby the multi-qubit processor can be cooled to cryogenic temperatures and further characterized, for example, by measuring qubit frequencies and comparing them to predicted frequency targets, quantizing qubit coherence, measuring single-qubit and multi-qubit gate fidelity, etc.

[0039] As described above, LASIQ (Laser Annealing of Randomly Damaged Qubits) technology has been developed to increase the collision-free yield of transmon lattices by selectively adjusting (i.e., tuning) the frequency of individual qubits through laser thermal annealing. LASIQ tuning can be used in one or more exemplary embodiments. However, it is to be understood that the embodiments described herein that require frequency tuning (e.g., functional qubits, quantum logic structures, quantum coupling structures, or any general element including one or more Josephson junctions) are not limited to using only LASIQ tuning, but can utilize any frequency tuning capability of Josephson junction-based qubits and / or elements to meet the frequency tuning requirements required for successfully realizing a quantum device including one or more interconnected processors, which may occur in modular devices (i.e., various embodiments apply to both modular and non-modular systems). In one exemplary embodiment, a LASIQ tool is used to perform laser annealing of Josephson junctions of fixed-frequency transmon qubits connected in a heavy hexagonal lattice structure, thereby taking into account nearest-neighbor and second-nearest-neighbor collisions.

[0040] In some cases, microwave-tunable superconducting qubit architectures, such as flux-tunable architectures, can be employed. In one or more embodiments, techniques for selectively tuning the frequencies of individual qubits based on Josephson junctions and various components can be used to achieve significant yield improvements, which can be part of a microwave-tunable superconducting qubit architecture.

[0041] Frequency tunability achieved through laser annealing (e.g., the LASIQ process) can be evaluated, for example, using calibration methods described elsewhere herein, in which a set of test junctions are laser-annealed to determine the tuning rate and tuning range, as well as any other functional parameters deemed necessary to tune the junction to completion. Specifically, in one or more embodiments, the tuning rate is used to estimate the laser annealing duration required to substantially tune the junction to completion, and the tuning range (i.e., the maximum tuning limit) is used to constrain the generation of a tuning schedule for the qubit frequencies (as used herein, “substantially tuned the junction to completion” means the tuning required to tune the junction to a target completion band, which may be 0.3% of the target resistance in a non-limiting example as discussed elsewhere herein. The 0.3% figure is exemplary and can be modified by those skilled in the art based on heuristics as needed, depending on the field of interest and application). As an example, the tuning schedule may include a fixed number of multiple frequency levels, and each qubit should be located at one of these levels and may also be tuned to these levels. The latter condition is determined by calibration of similar junctions, whereby these similar junctions are tuned to observe how far their resistance can shift. By appropriately assigning each qubit to a frequency level and within tunability constraints, energy level degeneracy that could lead to unwanted crosstalk (i.e., collisions) and thus low gate fidelity can be avoided. Other examples of methods for generating tuning schemes may include fixed-frequency schemes, or optimized protocols where each qubit can reside within a frequency range (constrained by collision boundaries) that depends on the frequency values ​​of neighboring or second-nearest neighbor qubits. The exemplary methods mentioned for generating tuning schemes are not intended to be exhaustive, but rather to serve as illustrative examples of methods that can generate tuning schemes given a lattice topology, such as in the case of a superconducting qubit lattice. Generally, any other tuning scheme generator that sufficiently mitigates frequency collisions will be considered acceptable, as will be readily apparent to those skilled in the art from the teachings herein. Such tuning schemes that extend beyond fixed-frequency modes and optimized protocols are referred to herein as “ad-hoc” schemes. This paper describes optimized protocols for generating frequency tuning schemes for multi-qubit processors, where optimized routines based on mixed-integer programming problems have been shown to generate tuning schemes that can potentially mitigate frequency collisions successfully. However, the adaptive method described in this paper is not limited to any specific tuning schedule generation method, but can be universally applied to any frequency tuning schedule generator, whether ad hoc or similar.

[0042] When determining the yield of a tuned chip, frequency collision analysis and collision-free yield are likely important metrics to consider. Collision boundaries for a given quantum processor architecture can be derived using known empirical and / or first-principles gate error models for the tuned superconducting qubit architecture. As an illustrative example, fixed-frequency transmon qubit pairs can be modeled as undergoing ZX interactions used to implement CNOT (controlled-not-intercept) gates. High-fidelity gates typically require controlling this interaction by assigning appropriate boundaries to the relative frequency difference between nearest-neighbor and second-nearest-neighbor transmon qubit pairs. Therefore, gate error modeling should take into account this interaction, as well as various noise sources; for example, noise from static ZZ interactions between qubits. In one or more exemplary methods, gate error modeling, and thus frequency collision boundaries, can be performed by empirically measuring the device frequency and the corresponding gate fidelity achievable on a given architecture.

[0043] In light of the teachings herein, those skilled in the art can adapt known tuning scheme generators to implement one or more embodiments. Nominally, after tuning, the junction resistance increases, and therefore the qubit frequency decreases. Thus, for example, if a qubit or group of qubits is under-scored in terms of resistance (i.e., reaches its tuning limit before it can reach its target), then one or more embodiments generate a new tuning scheme subject to the constraint that the under-scored qubits should no longer be moved, since there is no longer any remaining tuning range among these qubits. On the other hand, for example, if a qubit or group of qubits is over-scored, then one or more embodiments generate a scheme that allows them to continue tuning, provided they have not yet reached their estimated maximum range. In some embodiments, the qubits are bidirectionally tuned. In this respect, they can be tuned up and down within the tuning range limits as needed. The nature and directionality of the tuning can be determined based on a calibration test junction that will undergo laser annealing at various combinations of laser power and time.

[0044] The current vision envisions future quantum computers (Condor processors with >1000 qubits) utilizing cross-resonance technology from IBM in Armonk, New York, employing fixed-frequency transmon qubits, which requires post-fabrication frequency tuning using LASIQ. Through modeling, we identified collision regions (7 collision types) that should be avoided to ensure high gate fidelity, and ideally, fixed-frequency modes (e.g., 3-frequency (3f) modes) would help to efficiently avoid all collision types. As fabricated, large initial tuning spreads can exist on the qubits (corresponding to frequency spreads greater than 200 MHz for resistances up to 5%). Due to such large spreads, controlling the number of collisions in fabricated multi-qubit processors is impractical. The LASIQ process can be used to control this to a frequency accuracy of approximately 20 MHz, providing an order of magnitude improvement in frequency control. However, due to the limited tuning range (approximately 15% for resistances), obtaining the ideal 3f mode using current laser annealing techniques is generally not feasible. One or more embodiments described herein mitigate frequency congestion. One or more embodiments advantageously provide an alternative frequency scheduler that operates within tuning range and collision boundary constraints to generate an appropriate tuning schedule for a given processor prior to entering the LASIQ process. Such constraints may include, for example, tuning range limitations, such that the alternative frequency scheduler can meet yield requirements.

[0045] One or more embodiments provide techniques for generating frequency tuning schemes for lattices of fixed-frequency transmon qubits, based on optimization routines that treat tuning scheme generation as an optimization problem of mixed-integer programming with collision boundary constraints and an objective of minimizing the total number of collisions (defined by an objective function). Mixed-integer programming problems are generally not solvable in polynomial time, and solving a full heavy hexagonal lattice (e.g., IBM's Eagle 127-qubit system, or, for example, IBM's 433-qubit Osprey system) can be extremely slow. At the scale of 1,121 qubits (e.g., IBM's Condor system), such optimization is essentially impractical, requiring enormous computational resources to adequately solve the optimization problem.

[0046] One or more embodiments overcome these problems and demonstrate computational efficiency by using a “tiling solution” in which the lattice is divided into unit cell lattices, each sublattice is then optimized, and boundary collisions between tilings are resolved in subsequent iterations. One or more embodiments weight the importance of collisions by increasing or decreasing collision boundaries (or equivalently, frequency avoidance regions) or by changing their relative importance in the objective function. In one or more embodiments, the tuning scheme configuration can be changed by varying the tuning range. We found that this tuning scheme generator can be used to tune 127-qubit-scale processors, and the yield metrics quantized on the resulting post-LASIQ tuned processor are close to the desired tuning scheme. Our results demonstrate the effectiveness of using the tuning scheme generated by our computationally efficient optimization routine for LASIQ tuning of 127-qubit-scale processors. Different embodiments may use different tiling schemes. In some embodiments, a large amount of computational resources may be used to solve the entire lattice without tiling. In some embodiments, the tuning scheme may be reused during LASIQ to compensate for tuning defects.

[0047] This document provides examples for heavy hexagonal lattices, but aspects of the invention can be applied to any interconnected lattice, including modularly connected multi-qubit processors, where elements on multi-qubit and modular processors include functional qubits, quantum logic structures, quantum coupling structures, or any general element including one or more Josephson junctions. Typically, LASIQ tuning processes can be used to frequency control any structure containing a Josephson junction whose tunneling barrier is easily tunable by laser annealing. Such structures can include various types of qubits, or SQUIDs (superconducting quantum interference devices), or single Josephson junctions, or other combinations of Josephson junctions, capacitors, and inductors. They can be linked to a neighboring structure current ground, inductive ground, or capacitive ground on the chip. Functional structures can contain Josephson junctions designed or constructed differently from those in quantum coupling structures. Typically, several types of Josephson junctions undergo calibration to determine their response to laser power and exposure time. These individual calibrations determine the tuning range and tuning rate specific to the functional structure and quantum coupling structure. Typically, given frequency constraints (i.e., collision boundaries) and tuning constraints (e.g., tuning range), suitable objective functions and lattice tiling can be defined to achieve computationally efficient optimization routines.

[0048] Figure 1A regularly spaced rendering of a single 127-qubit 'heavy hexagonal' fixed-frequency transmon qubit lattice of an example chip (i.e., the IBM 'Eagle' quantum processor) is shown. Other lattice geometries are possible. One or more embodiments seek to mitigate 'collisions' and distribute the frequency detuning of nearest and second-nearest neighbor qubits to low gate error regions; for example, in a lattice with fixed-frequency qubits having seven collision types. Advantageously, at least some embodiments use an ideal 3-frequency pattern to avoid all seven collision types. However, achieving such an ideal 3-frequency pattern can be challenging given the tuning range constraints (typically 15% resistance) and the post-fabrication spread (4-5% resistance). In cases where an ideal 3-frequency pattern is not achievable due to tuning range constraints, one or more embodiments can use computationally efficient optimization methods as described herein, by utilizing a sublattice tiling scheme, whereby subsets of larger lattices can be solved sequentially and 'tiled' across larger lattices to obtain a global solution. In this way, the computational problem can be transformed into a problem that scales linearly with the lattice size, thereby significantly improving the throughput of the optimization routine and allowing for real-time adaptive solving during LASIQ tuning. Such an adaptive solution advantageously accommodates situations where individual qubits may overshoot or undershoot, and new schemes must be generated in situ to avoid unnecessary collisions that could lead to low gate fidelity.

[0049] Now consider sublattice tiling according to aspects of the invention. One or more embodiments optimize the frequency scheme by dividing the entire qubit lattice into a set of small sublattices (such that each qubit is covered by at least one sublattice (sublattices may overlap each other)) and optimizing the frequency scheme of all sublattices individually. Figure 2-5 As shown, there are many different variations in the sublattice shape. Figure 2 In the "per-qubit" sublattice method shown, each qubit (called the target qubit) is enumerated, and a set of qubits including the target qubit and its neighboring qubits forms a sublattice. This "per-qubit" method is independent of qubit layout because it can be used in any general lattice layout, regardless of connectivity. Figure 2 In each qubit sublattice, S0 comprises Q0 and its neighboring qubits (Q1 and Q14). Also considered... Figure 3-5 In the target Figure 1 The specific tiling scheme of the hexagonal lattice shown is illustrated. For example, 9 ( Figure 3 ) or 11 ( Figure 4 The "H-shaped" sublattice of qubits, wherein each sublattice comprises a pair of 4 or 5 qubit lines and an intermediate qubit. Another possibility is... Figure 5The 12-qubit "ring" sublattice shown: a ring sublattice of 12 qubits. Due to the degree 2 and degree 3 connectivity required for tiling "H-shaped" or "ring" sublattices, therefore Figure 3-5 The specific embodiments of sublattice tiling listed herein can only be implemented in a heavy hexagonal lattice. Note that one or more embodiments use a subset of the sublattice shape near the corners of the qubit lattice, and... Figure 2-5 In this paper, only a portion of the sublattice is depicted. In other embodiments using multi-qubit lattices other than heavy hexagonal ones, it should be understood that the methods described herein can be applied using any sublattice tiling scheme, thereby allowing the entire lattice to be tiled with overlapping qubits in neighboring sublattices. The optimization method used herein minimizes collisions in each sublattice while taking into account the frequency distribution of overlapping qubits in the tiling of neighboring sublattices. Once all sublattices have been optimized in this way, the optimization method can be repeated a specified number of times over the entire lattice to eliminate residual collisions created during the tiling process.

[0050] In one exemplary workflow, an initial guess for the frequency scheme is set (e.g., using a lower or upper boundary of the tuning range / frequency offset, or by randomly selecting numbers within the range); this is repeated (iterated) several times to optimize the frequency scheme for all sublattices. Note that, as previously stated, the optimization iteration optimizes all sublattices once. The optimization of each sublattice can be performed sequentially or in parallel. In one or more embodiments, the number of optimization iterations is specified as the input parameter “num_repetitions”, which represents how many times the lattice solution is repeated across all sublattice tiles. In one non-limiting exemplary embodiment, two optimization iterations are used, in which all sublattice tiles are solved in the first optimization iteration, and in a subsequent (i.e., second) optimization iteration, the solver is repeated across all sublattices to minimize residual collisions. One or more embodiments may use a single sublattice tiling scheme (e.g., an “H-shaped” sublattice). In other embodiments, different tiling solutions may be implemented on successive optimization iterations. One or more embodiments employ a mixed-integer programming model to optimize the frequency scheme for the sublattices.

[0051] Therefore, one or more embodiments can employ various sublattice variants. Figure 3 and 4 The "H" option in the code is essentially an H-shape rotated 90 degrees. In one or more instances, the entire lattice is divided into sublattices, with the constraint that each qubit should be covered by at least one sublattice. Figure 4 In the case of 11 qubits, H5 and H6 overlap, so several qubits are covered by more than one sublattice. On the other hand, in Figure 3 In the case of 9 qubits, H5 and H6 do not overlap. Figure 3 and4 The "H-shaped" configuration and Figure 5 The toroidal sublattice configurations are all focused on heavy hexagonal lattices. The "per qubit" sublattice (its value for...) Figure 2 Each individual target qubit (consisting of a three-qubit or four-qubit sublattice) is more suitable for different types of lattices, where each target qubit typically has two or more nearest neighbors. Therefore, Figure 2 Each sublattice in the array comprises the target qubit and its neighbors, and each qubit is covered by at least its own sublattice. Different tile shapes can be mixed based on the constraint that each qubit is covered by at least one sublattice (e.g., Figure 2-5 (any one of them).

[0052] One or more embodiments use the IBM® ILOG® CPLEX® Optimizer (a registered trademark of IBM, Inc., Armonk, NY, USA) to solve the optimization model. Based on the teachings herein, those skilled in the art will be able to implement the embodiments using other mixed-integer programming solvers such as the Gurobi product available from GUROBI OPTIMIZATION, LLC, Beaverton, Oregon, USA, and the FICO® Xpress Optimization product available from FICO, Bozeman, Montana, USA. Generally, any solver capable of implementing a mixed-integer programming solver can be used to perform optimization iterations and is not limited to any of the solvers listed herein.

[0053] Now consider the objective function and constraints, and how to identify a frequency tuning scheme for each sublattice. In one or more instances, each qubit has several frequencies. In one or more embodiments, the inputs include:

[0054] The entire qubit lattice and the target sublattice

[0055] For each quantum bit i in the entire crystal lattice (The frequency of |0>→|1>, corresponding to the quantum bit transition frequency) and (Aharmonicity) (f) 12 =f 01 +anh, or equivalently, f 02 =2*f 01 +anh, or f 02 / 2=f 01 +anh / 2)

[0056] Frequency scheme outside the target sublattice ( )

[0057] Assuming the default cross resonance direction: if Then control j and target k.

[0058] In one or more embodiments, the decision variables include:

[0059] The frequency shift of qubit i in the target sublattice. In this respect, let It is the frequency of the offset qubit i. , and Defined in a similar manner. Furthermore, the sublattice exterior... It is given as input and processed as a constant.

[0060] : Margin between the collision boundary and the target boundary.

[0061] : 0 if the default control and target direction are used, and 1 if the opposite direction is used.

[0062] : The number of frequency collisions of the nth constraint of collision type i in the sublattice.

[0063] The relevant parameters include:

[0064] : Minimum margin

[0065] , Frequency offset of quantum bit i lower and upper boundaries

[0066] : Collision type weights (i=1,…,7)

[0067] : Scaling factor of the collision boundary (i=1,…,7).

[0068] Possible objective functions include:

[0069] Minimize the sum of (weighted) frequency collisions

[0070] If there is no collision, maximize the margin. .

[0071] Therefore, based on each qubit i of the entire lattice (the frequency at which the state transitions from ground state 0 to the first excited state 1) and (Aharmonicity) allows for the calculation of other frequencies, such as f. 12 =f 01+anh、f 02 =2*f 01 +anh、f 02 / 2=f 01 +anh / 2, these frequencies are necessary to determine whether nearest-neighbor or second-nearest-neighbor collisions exist. In one or more embodiments, these quantities are used to define a collision, and the optimization model computes them during optimization. In one or more embodiments, it is assumed that the frequency schedule outside the target sublattice is fixed. In the example, subscript j refers to the control, and subscript k refers to the target. One or more embodiments maximize the margin in the absence of collisions. In an exemplary embodiment, margin It is maximized to the collision boundary to achieve the maximum effect of collision mitigation.

[0072] Now for reference Figure 6 and Figure 7 In one or more embodiments, the constraints include avoiding all seven frequency collision types. This list of nearest and second nearest neighbor collisions pertains to the lattice of a fixed-frequency transmon qubit; however, other embodiments with different multi-qubit lattice geometries and qubit architectures may include subsets or supersets of this collision list. Therefore, by defining corresponding collision constraints and boundaries, the optimization iterations described herein can be similarly implemented for various types of lattice geometries and qubit architectures.

[0073] Typically, we will now consider frequency collision type and boundaries. We find that in one or more embodiments, there are seven types of collisions, defined depending on the target gate error. Figure 6 The table shows the definition of a 1.0% gate error. Figure 7 The table shows the definition for a 0.5% gate error, where the collision boundary is increased accordingly for each collision type. Typically, collision avoidance constraints can be represented as linear constraints or indicator constraints. One or more embodiments are weighted... and scaling factor The importance of controlling collision type is determined in the objective function. Multiply by the collision amount of type i. Larger weights. This will increase the relative importance of collision type i. Scaling factor Multiply by the boundary of collision type i. For example, to achieve a 0.5% gate error, for example, b1=1 is implemented to use precisely, such as Figure 7 The collision boundaries are listed in the table. To increase the boundary of Type-1 collisions (and thus obtain a solution for Type-1 collisions that mitigates the gate error boundary beyond 0.5%), b1=2.0 results in a 40*2.0=80MHz boundary.

[0074] Now for reference Figure 8 and Figure 9 An optimized model for a gate error of 0.5% to minimize collisions (Example A) Figure 8 ) and maximizing margin (Example B) Figure 9 As those skilled in the art will appreciate, in light of the teachings herein, for a given lattice connectivity, an optimization model can be formulated in a similar manner for any gate error and any number of collisions. Note that the optimization model considers constraints involving one or more qubits in the target sublattice. One or more embodiments apply a mixed-integer programming solver to optimize model A( Figure 8 ) and Model B Figure 9 Some solvers (such as CPLEX) can directly handle indicator constraints. The indicator constraints and absolute value functions (|f...|) can be converted into linear constraints when using solvers that cannot directly handle them. One or more embodiments provide a workflow for optimizing a frequency schedule for a target sublattice. It is assumed that the frequencies outside the target sublattice are constant. A specified number of optimization iterations are used to solve model A( Figure 8 If the final solution contains some collisions, return the frequency scheme. If the solution has no collisions, then model B can be solved separately. Figure 9 ), to further mitigate collisions and return to the frequency plan. In some cases, Model B ( Figure 9 Model B can be omitted as an option; users can omit it by omitting model B. Figure 9 And faster runtime is expected. Note that regarding indicator constraints, if the variable... Then certain specific constraints should be satisfied. The indicator constraint "variable_x = constant_c → constraint_y" means "if variable_x is a constant_c, then constraint_y is satisfied". For example, model A has the constraint " (Default CR direction) means "if If it is 0, then the constraint is... The constraint should be satisfied. Otherwise, the constraint may not be satisfied.

[0075] Model A ( Figure 8 The objective function is defined. It is minimized under the constraints of the conditions defined in the subsequent definitions and inequalities. For example, avoiding type 1 collisions requires satisfying the condition... , where j and k are adjacent qubits, such that ,and and These are the tuned qubits i and j. As defined, the boundary for type 1 collisions is given by 40 MHz, while the multiplication scaling b1 provides beyond... Figure 7Additional boundaries for the 0.5% gate error boundary defined in [the document / reference]. This effectively quantifies the contribution to type 1 collisions. Combined with the objective function described above, it can be achieved through a weighted function. The contribution is weighted, and this weighting function can be modified to emphasize or weaken the Type 1 collision contribution. The importance of this in the objective function. Similarly, a corresponding definition is made for each collision type. The contributions to the objective function include consideration of 3-neighbor collisions (bystander collisions), which are enumerated by types 5-7. Model A can be solved over multiple optimization iterations using a tiling solution, and thus a tuning frequency schedule can be generated.

[0076] After generating a frequency schedule using Model A, the resulting residual collisions can be evaluated, and if deemed practically feasible, further implementation of Model B can proceed. Figure 9 In one exemplary embodiment, for example, if the result of model A produces a collision-free frequency solution, model B can be run. Figure 9 In this case, Model B will maximize the margin to the collision frequency boundary (i.e., the relative qubit detuning distance between the nearest and second nearest neighbors), thereby minimizing the statistical probability of a collision occurring after the LASIQ tuning process. This is similar to Model A. Figure 8 The approach involves introducing sublattice tiling and repeatedly solving the problem over multiple optimization iterations to run model B. Figure 9 To ensure an acceptable solution is obtained, model A is implemented in this way. Figure 8 ) and Model B Figure 9 The optimizer routine determines a collision-free solution while minimizing the likelihood of post-tuning collisions caused by processes such as tuning defects and frequency dispersion due to junction drift and aging. The probability of collisions can be quantified using statistical methods such as Monte Carlo yield modeling, in which a set of frequency deviations of random amplitude (constrained by a frequency dispersion parameter) is applied to the qubit frequency, and the number of collisions generated is calculated. By repeating this process a certain number of times, the expected number of total collisions under the assumption of a given frequency dispersion can be determined. However, any other collision and / or yield evaluation methods can be performed, as long as the output produces a yield metric reflecting the functional availability of the chip.

[0077] Furthermore, in this regard, Figure 10 An example workflow for a frequency tuning scheme is shown. In box 1001, relevant initial parameters are defined, including collision boundaries 1003, collision type 1005, maximum and minimum tuning ranges 1007, and collision weights. 1009. Collision scaling factor 1011 and any other relevant parameters 1013, such as minimum margin, etc. Based on the input, an initial guess for the frequency tuning scheme is generated in 1015. In step 1017, a sublattice is generated based on the input including the qubit lattice 1019 and the sublattice shape 1021. In step 1023, based on the initial guess from step 1015 and the sublattice generated in step 1017, optimization iteration begins to optimize all sublattices. In step 1025, a target sublattice is selected. In step 1027, model A is solved for the target sublattice. Figure 8 To minimize collisions, and optionally, in step 1029, to solve model B for the target sublattice. Figure 9 To maximize the margin from the collision boundary. In decision box 1031, determine whether all sublattices have been optimized in the current optimization iteration. If not, the logic flow returns to step 1025. If yes, the logic flow proceeds to decision box 1033. In decision box 1033, determine whether the number of optimization iterations has reached the maximum value specified at 1037. If not, the logic flow returns to step 1023 and a new optimization iteration begins. If yes, the logic flow proceeds to 1035 to output the frequency tuning plan for the LASIQ tuning process.

[0078] Now go to Figure 11Considering aspects of tuning plan generation, in one or more embodiments, an optimizer is used to generate a tuning plan in step 1101, and the tuning plan is based on tuning range constraints 1107, collision type 1103, and frequency collision boundaries 1105 for each collision type. Yield modeling is performed in step 1111 (based on the tuning plan and database records 1109); for example, Monte Carlo, gamma calculator (i.e., estimated overhead of probabilistic error cancellation as known from the IBM research paper “Probabilistic error cancellation with sparse Pauli-Lindblad models on noisy quantum processors” by Ewout van den Berg et al., May 8, 2023: 1–6), gate error modeling, and if determined to be acceptable in decision box 1113, the chip is tuned in step 1115; otherwise, a new chip may be selected for tuning in step 1117. For example, database record 1109 can be correlated with historical frequency dispersion, which is typically around 20 MHz. That is, the frequency of the qubit can be determined with an accuracy of approximately 20 MHz using room-temperature junction resistance data, where this dispersion includes contributions from the frequency prediction accuracy as well as junction aging before cooling and measurement. For example, the collision boundary could be a 1% gate error or a 0.5% gate error, such as... Figure 6 and Figure 7 As shown. In one or more embodiments, in step 1107, the maximum and minimum available tuning ranges of the qubit to be tuned are defined; this can be obtained from calibration run on a set of test junctions having similar or identical properties to the junction being tuned. Database records 1109 can be obtained from empirical observations of multiple devices that have been cooled to determine what type of frequency dispersion can be expected; when input into statistical yield model 1111, at least some possible defects can be determined. Database records 1109 may include, for example, statistical and measurement results from previous devices and expected random variations after tuning.

[0079] Note that gamma is an expression for the overhead of how many computer runs / computation time must be performed, and it increases with the corresponding improvement in qubit coherence and the reduction in collisions. By reducing this runtime overhead, a larger number of qubits can be run at greater circuit depth, enabling the realization of deeper quantum circuits, for example, in the case of probabilistic error correction.

[0080] Figure 12An exemplary feedback process is shown to improve in-situ yield by regenerating a new tuning schedule as tuning progresses. In fact, Figure 12 The feedback during tuning is illustrated. In step 1201, preliminary screening is performed. In step 1203, a tuning plan is generated. In step 1205, predictive yield analysis (e.g., Monte Carlo analysis) and collision analysis are performed in situ during LASIQ tuning. In decision box 1207, it is determined whether the yield is acceptable. If so (the "yes" branch), the plan target is assigned to the lattice in step 1209, and then proceeds to LASIQ tuning in step 1211. On the other hand, if the yield is unacceptable (the "no" branch of decision box 1207), proceeding to decision box 1213, it is determined whether there are possible alternative constraints. For example, alternative constraints may involve new acceptable collision-free allowed frequency bands for each qubit based on the new tuning plan. For example, alternative frequency constraints may also be based on the ability of the qubit to tune in the negative frequency direction or bidirectionally. In this case, new frequency tuning constraints can be implemented on the existing qubit set to allow in-situ correction of defects originating from qubit frequency overshoot or undershoot. We found that the regenerated tuning plan is often very different from the original tuning plan. In this sense, each chip at any given time can be considered a completely new chip, only its boundary conditions are different from its previous tuning rounds. If this is not the case (No branch in box 1213), the process terminates at 1215 and a new chip is selected for screening. If an alternative frequency constraint exists (Yes branch), a new frequency constraint is selected in step 1217 and the process returns to step 1203 to generate a new tuning plan. Predictive yield analysis 1205 is performed, and if satisfactory in decision box 1207, a new plan target is assigned at 1209. After LASIQ tuning in step 1211, it is determined in decision box 1219 whether tuning is complete. If not complete (No branch), the logic flow returns to step 1205 to evaluate the quality of the tuning round. On the other hand, if tuning is complete (Yes branch), the process proceeds to the LASIQ post-analysis in step 1221.

[0081] therefore, Figure 12This involves tuning plan generation and tuning flow. In one or more embodiments, each time a tuning plan is generated at 1203, a predictive analysis (e.g., Monte Carlo) is run at 1205. If the yield is unacceptable, constraints can be modified, for example, increasing the tuning range or changing the collision weights / boundaries. This process iterates until a good tuning plan is found, and then a LASIQ tuning round is performed at 1211. After each round, the tuning is checked at 1207 to ensure the yield is still acceptable; otherwise, the constraints can be modified again to generate a new tuning plan. In one or more embodiments, each qubit is tuned iteratively. A tuning round means tuning all qubits on the chip in a previously defined round-robin format. Possible alternative constraints include different collision boundaries, different frequency tuning limits, acceptable operating frequencies for the qubits, etc.

[0082] Figure 13 The iterative tuning rounds are described. The tuning process begins in step 1301. In step 1303, the process moves to the initial Josephson junction. In step 1305, a specified time delay is waited for. This time delay can be, for example, a fixed time delay, or it can be a variable time delay to allow the junction time to stabilize from previous tuning rounds. In step 1307, the Josephson junction is focused and aligned. In step 1309, the resistance of the Josephson junction is measured. In decision block 1311, it is determined whether the tuning of a particular qubit is complete. If not, the process proceeds to step 1313 and the annealing time and power are determined. Then, in step 1315, laser annealing is performed with the appropriate time and power. In step 1317, the process moves to the next Josephson junction. In decision block 1321, it is determined whether the tuning of this junction has been marked as complete. If not, the logic proceeds to step 1305. If yes, the logic proceeds to decision block 1323. If no more junctions remain to be tuned, the tuning process ends at 1325. If more junctions remain to be tuned, the process moves to the next junction in step 1317. In decision box 1311, if the tuning of a particular qubit is complete, the qubit is marked as complete in step 1319, and the process moves to the next junction in step 1317.

[0083] Therefore, one or more embodiments perform multiple tuning rounds for each junction using an iterative approach to approximate the resistance target until tuning is considered complete. A delay can be implemented to allow the resistance to relax before the next annealing iteration on the qubit. Regarding measuring the resistance of the Josephson junction at 1309 and determining whether qubit tuning is complete in decision box 1311, in one or more embodiments, the distance between the junction resistance and the target resistance is checked. If qubit tuning is not complete, then the distance to the target can be used to determine the required annealing time and power at 1313.

[0084] The tuning process in 1311 determines the currently measured junction resistance (expressed as) of a given Josephson junction. Whether it is at or near the target junction resistance (expressed as) of a given Josephson junction. In some embodiments, when the measured junction resistance With the target junction resistance The absolute difference between them is in the target junction resistance Within certain specified threshold percentages, i.e. At that time, a given Josephson junction will be considered to be at its target junction resistance. In some embodiments, (or 0.3%). For example, suppose a given Josephson junction has a target junction resistance. =10K ohms, when measuring junction resistance In the range of approximately 9,970 ohms to approximately 10,030 ohms (i.e., in...) Around + / - 30 ohms, a given Josephson junction will be considered at its target junction resistance. .

[0085] If the measured junction resistance of a given Josephson junction is determined... The target junction resistance is not at or near a given Josephson junction. (The negative judgment in box 204) then the tuning process continues to determine the annealing time and laser power for laser annealing of the given Josephson junction in a given iteration based on the junction resistance measured in 1309. Specifically, the tuning process will be based on the currently measured junction resistance. To determine the target junction resistance to achieve a given Josephson junction. Required residual resistance offset (expressed as) ),in At least in part based on The pulse time for a given laser annealing iteration is determined by a function of the laser and the total annealing time spent on the previous “pulse” in the previous tuning iteration performed for a given Josephson junction.

[0086] Figure 14 The yield assessment aspects are described. In step 1401, assuming all other junctions are tuned to the target, based on input 1403 (a set of current junction resistances {R... J,1 R J,2 , ...R J,N}) and 1405 (a set of target junction resistors {R T,1 R T,2 , ...RT,N}), to obtain the predicted quantum bit frequency {f 01,1 f 01,2 , ...f 01,N In step 1407, collision analysis is performed using nearest neighbor (NN) and second nearest neighbor (NNN) degeneracy. In step 1409, statistical analysis (e.g., Monte Carlo) is performed to identify the expected number of collisions for a given frequency prediction inaccuracy or a set of frequency prediction inaccuracies (e.g., a range from 0 MHz to 40 MHz). In step 1411, the zero-collision probability (collision yield) is obtained. In decision box 1413, it is determined whether the yield is below an acceptance threshold. If so, tuning continues at 1415; otherwise, a new tuning plan is generated in step 1417. Returning to step 1401, in a path parallel to steps 1407-1411, in step 1419, gate error analysis is performed to estimate gate fidelity (error yield).

[0087] Therefore, advantageously, the progress of tuning can be quantified by quantifying the collision and zero-collision probabilities and the gate fidelity and defining an acceptance threshold; in one or more embodiments, this can occur in situ during tuning. Figure 14 Yield assessment and Figure 12 The collision, yield, and predictive analysis box 1205 is related, and also to the statistical yield modeling box 1111 (in one or more embodiments, boxes 1205 and 1111 are substantially the same). This can be targeted at, for example... Figure 6 and Figure 7 Collision analysis is performed on data in tables such as the 0.5% and 1% gate error boundaries. In one or more embodiments, a statistical analysis (e.g., Monte Carlo) is performed in step 1409 to identify the expected number of collisions at a given frequency prediction inaccuracy (e.g., 20 MHz) or a set of frequency prediction inaccuracies (e.g., a band range from 0 MHz to 40 MHz). Regarding the step of generating a new tuning plan in 1417, if no new tuning plan is available, then choosing a different chip is appropriate. Yield assessment can be used on the tuning plan, or it can be performed separately in situ during tuning. There are two alternative approaches from step 1401 to decision box 1413. Branches 1407-1409-1411 themselves do not provide a gate fidelity number, but rather assess the expected number of collisions for a given scatter, thereby quantifying the probability of obtaining a high gate fidelity. The branch through step 1419 estimates the actual gate fidelity based on a gate error model and can be similarly used to define an acceptance threshold for a tuned quantum processor.

[0088] Now for reference Figure 15-18Consider an exemplary LASIQ tuning of the optimization plan. This is an example of tuning towards a target frequency. In this example, the tuning residual is 7 MHz based on the deviation between the predicted frequency and the target frequency. One or more embodiments use the iterative tuning method described above to adaptively approach the frequency target. Figure 15 and Figure 16 The data in this paper is based on actual experimental data from an IBM Eagle chip using the iterative method discussed above. In each case, the X-axis represents the desired target frequency. It can be seen that very precise tuning can be achieved using the LASIQ tuning process. Figure 15 In the diagram, the residual is displayed on the Y-axis and corresponds to the deviation of the final predicted frequency (after LASIQ tuning) from the desired target frequency. This residual corresponds to an equivalent frequency accuracy of 7 MHz. This accuracy is based on resistance measurement estimation. Figure 16 It shows the target f relative to the desired target 01 Actual predicted LASIQ post-frequency f 01 The relationship demonstrates excellent linear correlation and is evidence of the effectiveness of the exemplary LASIQ tuning process for frequency control according to aspects of the present invention. In other words, by using... Figure 8 and Figure 9 The objective function and constraints outlined in the document generate a tuning plan, which can be successfully implemented using the LASIQ tuning process.

[0089] Figure 17 The table shows the post-tuned collision analysis (after LASIQ) compared to the target. From Figure 17 It can be seen that the initial LASIQ pre-collision is significant, with 113 collisions of types 1 to 7. After generating the tuning plan and completing the LASIQ tuning process, Figure 17 The second column shows a significant reduction in total collisions, particularly Type 1 collisions that severely impair the fidelity of two-qubit gates. In this specific example, Model A( Figure 8 ) was used in the frequency tuning program, but Model B ( Figure 9 Although not used in this example due to remaining collisions, it could optionally be used to further increase the margin from the collision boundary. Figure 17 The third column shows the tuning plan collisions, and it is clear that the total LASIQ post-collision count is very similar to the target collision count, again demonstrating the effectiveness of the LASIQ tuning process in achieving the desired tuning plan.

[0090] Figure 18 It shows the relationship with Figure 17The Eagle processor in the example corresponds to Monte Carlo analysis with a frequency dispersion ranging from 0 MHz (i.e., perfect low-temperature frequency accuracy) to 40 MHz. Two curves are depicted in this example: the curve with circular data points is the target, and the curve with square data points is the result after LASIQ. Each point on the curve is the result of the average collision count obtained by introducing a random dispersion corresponding to the value on the X-axis. In this example, the LASIQ-post-Monte Carlo is essentially the same as the tuning scheme Monte Carlo, indicating that the tuning results according to one or more embodiments are as good as the generated tuning scheme. Therefore, these figures illustrate the effectiveness of exemplary embodiments in removing collisions and achieving the desired results. In the exemplary tuning scheme, types 1, 3, and 4 have the highest weights, and types 2, 5, 6, and 7 have the lowest weights. In non-limiting exemplary embodiments, typical relative weights... Including: Type 1:8, Type 2:1, Type 3:4, Type 4:4, and Types 5 to 7:1.

[0091] therefore, Figure 17 and Figure 18 The relevant metrics corresponding to Monte Carlo boxes 1111 and 1409 are shown. Figure 18 This is a Monte Carlo analysis of both the target and the achieved frequency (after LASIQ). It can be seen that the curves are close to each other; the tuning is generally commensurate with the planned quality. The X-axis represents frequency dispersion. When there is a large frequency dispersion, the collision count is expected to increase. Considering that a plan has been generated, but the tuning of that plan is not entirely perfect, and there is some frequency dispersion and / or some frequency scrambling once the chip cools down, this will lead to more collisions. This type of curve is an effective way to evaluate yield; that is, to determine whether the total number of collisions is at the expected level. Again considering relative weights, in one or more embodiments, there are two methods to control which collisions should be avoided more strongly. One is to control the weights... This increases or decreases the relative importance of a specific collision type i. Another is a scaling factor that directly controls the collision boundary. , This expands the avoidance zone for each collision.

[0092] One or more embodiments provide a method comprising: generating an optimized tuning schedule for a quantum computing device based on an objective function and constraints, wherein the objective is to minimize collisions under collision types and boundaries; and determining whether yield is acceptable based on screening analysis (e.g., Monte Carlo or gate error modeling). Furthermore, one or more embodiments provide a tuning schedule optimizer comprising a sublattice tiling scheme thereby enabling rapid generation of a tuning schedule; an objective function that aims to minimize total collisions or a subset of collisions; constraints based on collision type, collision boundaries, tuning range, and collision weights; a collision weighting scheme that prioritizes collisions based on collision weights; and a scaling factor to increase / decrease collision boundaries by type.

[0093] One or more embodiments employ tuning methods, including iterative and adaptive approaches, to accurately and precisely approach a target qubit frequency. One or more embodiments employ tuning devices, including a laser tuning system and a processor, to perform tuning planning and screening analysis.

[0094] It is worth noting that, in Figure 11 In the middle, step 1101 is Figure 10 The result of 1035. Figure 13 The actual physical tuning process is shown, for example, it can be performed using a LASIQ machine. Figure 14 One way to implement step 1111 is shown. Figure 10 In 1005, elements 1009 and 1011 correspond to Figure 6 and Figure 7 Elements 1003, 1007, and 1013 include constraints that can be set by those skilled in the art using heuristic methods or other techniques based on the teachings herein. Step 1015 may include selecting a lower boundary or an upper boundary, or a random selection, as discussed elsewhere herein. The qubit lattice 1019 includes, for example, a data structure defining connectivity. Element 1021 includes, for example, data from... Figure 2-5 The shape. In 1017, the sublattice can be generated manually or using a deterministic step algorithm. Elements 1023 and 1025 may include, for example, setting indexes / counters. Elements 1027 and 1029 can be based on... Figure 8 and Figure 9 Implementation. Element 1037 may include a limit on the number of iterations determined heuristically or as discussed elsewhere in this document; in a non-limiting example, such as 2-10 iterations. Boxes 1031 and 1033 may be comparison statements in a high-level programming language. Element 1035 may be a data structure for maintaining the tuning schedule. Figure 12 An exemplary feedback process for in-situ yield improvement according to aspects of the present invention is illustrated by regenerating a new tuning schedule as tuning progresses; for example, it can be combined with... Figure 10The generated tuning plan is used together. Generally, for any element or step not described in detail, those skilled in the art can implement them by adapting known techniques implemented in the software based on the teachings herein.

[0095] Regarding the initial screening in section 1201, screening is used to ensure that all candidate chips assigned for tuning have sufficiently high predicted post-tuning quality that they should be included in the LASIQ tuning queue. In section 1203, the generation of the tuning plan can be achieved using various tuning plan generators that can satisfy frequency constraints and achieve the target gate fidelity. Such tuning plans include fixed-frequency patterns, fixed-frequency hierarchies, optimizer solutions involving significant computational requirements, ad hoc plans, etc.

[0096] The relevant inputs for the statistical analysis will be any expected random variations in the qubit frequency between the LASIQ tuning moment and the moment the chip is cooled and operated in the cryostat. These can be estimated from records of past devices previously measured and stored in database 1109 accessed by the statistical yield modeling algorithm 1111. Additionally, there is material relaxation in the Josephson junction that occurs after annealing, where the junction resistance relaxes and stabilizes to its final value, and this relaxation can be compensated for and / or adapted using an appropriate time delay between the LASIQ and the cryogenic frequency measurement, as shown in step 1305.

[0097] Further regarding tuning plan generators (optimizers), the IBM CPLEX optimizer (available from IBM in Armonk, NY) provides a software solution for linear programming optimization problems, broadly applicable to the types of problems described in this paper (e.g., generating frequency tuning plans given frequency collision constraints). Other algorithms may, for example, attempt to optimize the practicality of a quantum processor by computing the longest possible collision-free chain, loop, or other such conformation under constraints on tunability, collision boundaries, and lattice geometry. Optimizers using stochastic plan generators or ad hoc generators can also be used, for example, in the case of a Monte Carlo tuning plan generator, where a large number of frequency patterns are tried to sample the solution space. Other algorithms, such as collision avoidance algorithms, can iterate between different topologies to find the number of collision-free (or collision-reduced) qubits in a chosen evaluation topology by incrementally shifting the qubit frequencies by a parameterized amount until convergence is achieved or the maximum number of interconnected collision-free qubits is found within computational time constraints. Static optimizers using Monte Carlo tuning or simulated annealing can also be used.

[0098] The success or completion of junction tuning can be determined by how close the junction resistance is to its target value. For example, a junction can be considered "complete" when the measured current junction resistance is within an acceptable threshold (e.g., 0.3%) of the target resistance. That is, if the target resistance is, for example, 10K ohms, the acceptable success band can be defined as + / - 30 ohms, or equivalently, a range from 9970 ohms to 10030 ohms. It should be noted that the term "current junction resistance" as used herein refers to the junction resistance measured in the sense that it occurs or exists at the current moment, or the most recently measured junction resistance.

[0099] A particular quantum computing-based device (e.g., a monolithic die designed as a separate quantum processor chip) can be considered complete when all junctions are satisfactorily tuned (e.g., within 0.3% of the target resistance) and the statistical yield model indicates that the expected probability of collisions or the probability of zero-collision yield is below an acceptable threshold. For example, the overall quality of tuning can be evaluated by observing a smooth and monotonous progression from the initial resistance towards the target resistance. It should be noted that it is also possible, for example, that for a given scheme, the yield will never be acceptable after a certain number of annealing rounds of LASIQ tuning. Typically, a maximum of 10 annealing rounds are therefore allowed for a given scheme (e.g., because it is generally and empirically confirmed that a larger number of iterations will indicate that the tuning cannot converge to the desired target frequency scheme. If the qubits do not reach the target within that number of annealing rounds, the scheme is considered unachievable, and a new tuning scheme is generated. In this case, the process can also proceed to block 329, and a new scheme is generated. The acceptable number of annealing cycles can also be heuristically determined based on the rate of progress toward the target, which can be determined from historical tuning progress and / or calibration tuning rate on the test junction. See decision box 1033 for general information.

[0100] Yield can be understood as comprising at least two main elements. The first is tuning yield, which is a measure of the precision and / or accuracy of laser tuning of the Josephson junction. The second is functional yield, which is a measure of the number of collisions, zero-collision probability, gate error yield (i.e., average gate error and gate fidelity), etc., of the tuned multi-qubit lattice. Generally, the screening process (involving generating a tuning schedule and evaluating its quality) relies on the assumption of perfect tuning yield. That is, all qubits successfully reach their target frequency after laser annealing. However, imperfect tuning yield will affect functional yield in such a sense that the qubits are no longer able to reach their target frequency in all cases, which can affect the evaluation of collisions, zero-collision probability, gate errors, etc.

[0101] Therefore, it should be understood that one or more embodiments advantageously improve tuning accuracy in the adaptive tuning process, but such tuning deficiencies can be compensated for by determining alternative frequency constraints, so that new or modified tuning plans can be generated based on these alternative frequency constraints, thereby improving overall tuning accuracy and success rate.

[0102] In one or more embodiments, all structures are made of superconducting material on a dielectric substrate, and all structures include Josephson junctions whose tunneling barriers are tunable by laser annealing. Structures may include various types of qubits, or SQUIDs (superconducting quantum interference devices), or single Josephson junctions, or other combinations of Josephson junctions, capacitors, and inductors. They may be linked on-chip to adjacent structures with current-ground, inductive-ground, or capacitive-ground connections. The qubit chip may also include functional structures that are not qubits but contain Josephson junctions, which may have different designs and fabrications compared to the qubits. Modular quantum processor designs may also include quantum-coupled structures whose Josephson junctions have different designs or fabrications compared to the Josephson junctions in qubits and other functional structures. Various types of Josephson junctions typically undergo calibration to determine their response to laser power and exposure time. These individual calibrations determine tuning ranges specific to each type of qubit or other structure.

[0103] Summarize

[0104] Based on the discussion to date, and referring to, for example Figure 10 It will be understood that, according to one aspect of the invention, an exemplary method includes the steps of defining a plurality of qubit collision types 1005 and a plurality of constraints (typically, 1001). A further step 1027 includes, for the qubit group, using a computerized mixed-integer programming solver to iteratively minimize collisions under constraints by minimizing the sum of the products of the number of frequency collisions multiplied by the weights for a given constraint of each collision type. Refer to the definition of “optimization iteration” above. A further step includes outputting a frequency tuning plan 1035 for the qubit group based on the iterative minimization. Even further steps include performing or otherwise facilitating the tuning of physical qubits according to the frequency tuning plan, such as… Figure 13 As shown.

[0105] In one or more embodiments, tuning includes LASIQ (laser annealing of randomly damaged qubits) tuning.

[0106] One or more embodiments also include performing statistical modeling to assess yield associated with the frequency tuning schedule; in this respect, LASIQ (laser annealing of randomly damaged qubits) tuning is performed in response to the statistical modeling indicating an acceptable yield. Reference Figure 11The "Yes" branches of boxes 1111 and 1113 lead to 1115.

[0107] refer to Figure 10 In box 1029, one or more embodiments further include, after iterative minimization of collisions, using a computerized mixed-integer programming solver to iteratively maximize the frequency margin under constraints for the qubit set.

[0108] Some such embodiments also include determining that the solution to be iteratively minimized includes at least one collision; in this case, in response to such determination, an iterative maximization of the frequency margin is performed.

[0109] As described above, one or more embodiments utilize sublattices. Therefore, one or more embodiments further include, according to block 1019, accessing the specification of the qubit lattice; according to block 1021, selecting at least one sublattice shape; and according to block 1017, generating a sublattice according to the at least one sublattice shape such that each individual qubit in the qubit lattice is covered by at least one of the sublattices. In this respect, the aforementioned qubit group corresponds to one of the sublattices.

[0110] Then one or more embodiments traverse all sublattices according to decision box 1031; therefore, one or more embodiments also include, for additional qubit groups corresponding to the remaining sublattices, repeating the step of iteratively minimizing collisions by minimizing the sum of the products of the number of frequency collisions multiplied by the weights for each collision type.

[0111] In one or more embodiments, selecting at least one sublattice shape includes selecting at least one of a nine-qubit H-shape, an eleven-qubit H-shape, a twelve-qubit ring shape, and a shape comprising each qubit and its adjacent qubits, such as Figure 2-5 As shown.

[0112] In one or more embodiments, iterative minimization includes applying a scaling factor to increase or decrease the collision boundary by type; for example, applying... As discussed elsewhere in this article.

[0113] On the other hand (see example) Figure 19 (as discussed herein), a computer program product includes a computer-readable storage medium having program instructions embodied thereon. The program instructions can be executed by a processor such as 110 to cause the processor to perform any, some, or all of the method steps herein.

[0114] Those skilled in the art will understand that LASIQ tuning is a physical process in which a computer-controlled machine is making physical alterations to a Josephson junction. When completed, the end result is a quantum computing device configured and tuned according to the techniques disclosed herein, which can be deployed and can perform quantum computing. Advantageously, the characterization of yield is associated with availability—a good yield metric is a direct measure of the quantum processor's availability for quantum computing. Therefore, the steps of facilitating the tuning of physical qubits according to a frequency tuning plan may include sending instructions to the LASIQ machine to tune the chip according to the tuning plan. Such a tuned chip can then be deployed and used for computation. As noted below, end-user equipment 103 may also include all or part (e.g., the controller) of the LASIQ tuning machine (controller, laser, mounting table to hold the chip, etc.), and such a machine may be coupled to computer 101 via WAN 102 or other networks (e.g., local area network (WAN), wireless connection, direct cable connection, etc.). Those skilled in the art will be familiar with the LASIQ tuning machine itself, and, in light of the teachings herein, the LASIQ tuning machine can be used to implement tuning plans according to various aspects of the invention.

[0115] Now for reference Figure 19 It should be understood that the techniques disclosed herein include, for example, computer-aided design for quantum computers, wherein aspects of the design process can be implemented on any kind of computer, whether quantum or conventional.

[0116] Various aspects of this disclosure are described by narrative text, flowcharts, block diagrams of computer systems, and / or block diagrams of machine logic included in embodiments of a computer program product (CPP). Regarding any flowchart, depending on the technology involved, operations may be performed in a different order than that shown in a given flowchart. For example, again according to the technology involved, two operations shown in consecutive flowchart blocks may be performed in reverse order, as a single integrated step, simultaneously, or in a manner that at least partially overlaps in time.

[0117] Computer Program Product Embodiment (“CPP Embodiment” or “CPP”) is a term used in this disclosure to describe any collection of one or more storage media (also referred to as “media”) collectively included in a collection of one or more storage devices, the collection of one or more storage devices collectively including machine-readable code corresponding to instructions and / or data for performing computer operations specified in a given CPP claim. A “storage device” is any tangible device capable of holding and storing instructions used by a computer processor. Without limitation, a computer-readable storage medium can be an electronic storage medium, a magnetic storage medium, an optical storage medium, an electromagnetic storage medium, a semiconductor storage medium, a mechanical storage medium, or any suitable combination of the foregoing. Some known types of storage devices that include these media include: magnetic disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), compact disc read-only memory (CD-ROM), digital versatile disc (DVD), memory sticks, floppy disks, mechanical encoding devices (such as punch cards or pits / platforms formed in the main surface of the disk), or any suitable combination of the foregoing. Computer-readable storage media, as used in this disclosure, should not be construed as storing transient signals themselves, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides, optical pulses through fiber optic cables, electrical signals transmitted through wires, and / or other transmission media. As those skilled in the art will understand, data is typically moved at certain incidental points in time during the normal operation of the storage device, such as during access, defragmentation, or garbage collection; however, this does not render the storage device transient, as the data is not transient when it is stored.

[0118] Now for reference Figure 19 It should be noted that the end-user equipment 103 discussed below may also include all or part of a LASIQ tuning machine (controller, laser, mounting table to fix the chip, etc.) (e.g., the controller), and such a machine may be coupled to computer 101 via WAN 102 or other networks (e.g., local area network (WAN), wireless connection, direct cable connection, etc.).

[0119] Computing environment 100 includes examples of environments for executing at least some of the computer code involved in executing the inventive methods, as seen at 200 (e.g., code for optimizing to mitigate frequency congestion in multi-qubit processors). In addition to block 200, computing environment 100 includes, for example, a computer 101, a wide area network (WAN) 102, an end-user equipment (EUD) 103, a remote server 104, a public cloud 105, and a private cloud 106. In this embodiment, computer 101 includes a processor set 110 (including processing circuitry 120 and cache 121), communication infrastructure 111, volatile memory 112, persistent storage 113 (including an operating system 122 and block 200, as described above), a peripheral device set 114 (including a user interface (UI) device set 123, storage 124, and an Internet of Things (IoT) sensor set 125), and a network module 115. Remote server 104 includes a remote database 130. Public cloud 105 includes gateway 140, cloud orchestration module 141, host physical machine set 142, virtual machine set 143, and container set 144.

[0120] Computer 101 can take the form of a desktop computer, laptop computer, tablet computer, smartphone, smartwatch or other wearable computer, mainframe computer, quantum computer, or any other form of computer or mobile device now known or to be developed in the future capable of running programs, accessing networks, or querying databases such as remote database 130. As is well known in the field of computer technology, and depending on that technology, the execution of computer-implemented methods can be distributed among multiple computers and / or multiple locations. On the other hand, in this presentation of computing environment 100, the detailed discussion focuses on a single computer, specifically computer 101, to keep the presentation as simple as possible. Computer 101 can reside in the cloud, even... Figure 19 It is not shown that it is in the cloud. On the other hand, unless explicitly instructed otherwise, computer 101 is not required to be in the cloud.

[0121] Processor set 110 includes one or more computer processors of any type now known or to be developed in the future. Processing circuitry 120 may be distributed across multiple packages, such as multiple cooperating integrated circuit chips. Processing circuitry 120 may implement multiple processor threads and / or multiple processor cores. Cache 121 is memory located within the processor chip package and is typically used for data or code that should be available for fast access by the threads or cores running on processor set 110. Cache memory is typically organized into multiple levels based on its relative proximity to the processing circuitry. Alternatively, some or all of the cache in the processor set may be located “off-chip.” In some computing environments, processor set 110 may be designed to work with qubits and perform quantum computing.

[0122] Computer-readable program instructions are typically loaded onto computer 101 to cause the processor set 110 of computer 101 to perform a series of operational steps to implement a computer-implemented method, such that the instructions thus executed instantiate the method specified in the flowcharts and / or narrative descriptions of the computer-implemented method included in this document (collectively, the “inventive method”). These computer-readable program instructions are stored in various types of computer-readable storage media, such as cache 121 and other storage media discussed below. The program instructions and associated data are accessed by the processor set 110 to control and direct the execution of the inventive method. In computing environment 100, at least some of the instructions for performing the inventive method may be stored in block 200 of persistent storage 113.

[0123] Computer-readable program instructions are typically loaded onto computer 101 to cause the processor set 110 of computer 101 to perform a series of operational steps to implement a computer-implemented method, such that the instructions thus executed instantiate the method specified in the flowcharts and / or narrative descriptions of the computer-implemented method included in this document (collectively, the “inventive method”). These computer-readable program instructions are stored in various types of computer-readable storage media, such as cache 121 and other storage media discussed below. The program instructions and associated data are accessed by the processor set 110 to control and direct the execution of the inventive method. In computing environment 100, at least some of the instructions for performing the inventive method may be stored in block 200 of persistent storage 113.

[0124] Communication structure 111 is a signal transmission path that allows various components of computer 101 to communicate with each other. Typically, this structure consists of switches and conductive paths, such as switches and conductive paths forming buses, bridges, physical input / output ports, etc. Other types of signal communication paths can be used, such as fiber optic communication paths and / or wireless communication paths.

[0125] Volatile memory 112 is any type of volatile memory now known or to be developed in the future. Examples include dynamically typed random access memory (RAM) or statically typed RAM. Typically, volatile memory 112 is characterized by random access, but this is not required unless explicitly indicated. In computer 101, volatile memory 112 is located in a single package and is internal to computer 101; however, alternatively or additionally, volatile memory may be distributed across multiple packages and / or located externally relative to computer 101.

[0126] Persistent storage 113 is any form of non-volatile storage for a computer, now known or to be developed in the future. The non-volatility of this storage means that the stored data is retained regardless of whether power is supplied to the computer 101 and / or directly to the persistent storage 113. Persistent storage 113 may be read-only memory (ROM), but typically at least a portion of persistent storage allows for data writing, data deletion, and data rewriting. Some common forms of persistent storage include disks and solid-state storage devices. Operating system 122 may take several forms, such as various known proprietary operating systems or operating systems employing an open-source portable operating system interface type with a kernel. The code included in block 200 generally includes at least some of the computer code involved in performing the inventive methods described herein.

[0127] Peripheral device set 114 includes a collection of peripheral devices for computer 101. Data communication connections between peripheral devices and other components of computer 101 can be implemented in various ways, such as Bluetooth connectivity, near field communication (NFC) connectivity, connections made by cables (such as Universal Serial Bus (USB) type cables), plug-in connections (e.g., secure digital (SD) cards), connections made via local area communication networks, and even connections made via wide area networks such as the Internet. In various embodiments, UI device set 123 may include components such as displays, speakers, microphones, wearable devices (such as glasses and smartwatches), keyboards, mice, printers, touchpads, game controllers, and haptic devices. Storage 124 is an external storage device, such as an external hard drive, or a pluggable storage device, such as an SD card. Storage 124 can be persistent and / or volatile. In some embodiments, storage 124 may take the form of a quantum computing storage device for storing data in the form of qubits. In embodiments where computer 101 requires a large amount of storage (e.g., where computer 101 locally stores and manages a large database), this storage can be provided by peripheral storage devices designed to store very large amounts of data, such as a storage area network (SAN) shared by multiple geographically distributed computers. The IoT sensor set 125 consists of sensors that can be used in IoT applications. For example, one sensor could be a thermometer, while another could be a motion detector.

[0128] Network module 115 is a collection of computer software, hardware, and firmware that allows computer 101 to communicate with other computers via WAN 102. Network module 115 may include hardware such as a modem or Wi-Fi transceiver, software for packetizing and / or depacketizing data for transmission over the communication network, and / or web browser software for transmitting data over the Internet. In some embodiments, the network control and network forwarding functions of network module 115 are performed on the same physical hardware device. In other embodiments (e.g., embodiments utilizing software-defined networking (SDN), the control and forwarding functions of network module 115 are performed on physically separate devices, such that the control function manages several different network hardware devices. Computer-readable program instructions for performing the methods of the invention can typically be downloaded to computer 101 from an external computer or external storage device via a network adapter card or network interface included in network module 115.

[0129] WAN 102 is any wide area network (e.g., the Internet) capable of transmitting computer data over non-local distances using any technology known now or developed in the future for transmitting computer data. In some embodiments, WAN 102 may be replaced by and / or supplemented by a local area network (LAN) designed to transmit data between devices located in a local area, such as a Wi-Fi network. WANs and / or LANs typically include computer hardware such as copper transmission cables, optical fiber transmissions, wireless transmissions, routers, firewalls, switches, gateway computers, and edge servers.

[0130] End User Equipment (EUD) 103 is any computer system used and controlled by an end user (e.g., a customer of the enterprise operating computer 101) and can take any of the forms discussed above in conjunction with computer 101. EUD 103 typically receives helpful and useful data from the operation of computer 101. For example, assuming computer 101 is designed to provide recommendations to the end user, these recommendations are typically transmitted from network module 115 of computer 101 to EUD 103 via WAN 102. In this way, EUD 103 can display or otherwise present recommendations to the end user. In some embodiments, EUD 103 can be a client device, such as a thin client, a thick client, a mainframe computer, a desktop computer, etc.

[0131] Remote server 104 is any computer system that provides at least some data and / or functionality to computer 101. Remote server 104 can be controlled and used by the same entity operating computer 101. Remote server 104 represents a machine that collects and stores helpful and useful data used by other computers, such as computer 101. For example, if computer 101 is designed and programmed to provide recommendations based on historical data, that historical data can be provided to computer 101 from a remote database 130 of remote server 104.

[0132] Public cloud 105 is any computer system that can be used by multiple entities, providing on-demand availability of computer system resources and / or other computing capabilities (especially data storage (cloud storage) and computing power) without direct active management by users. Cloud computing typically leverages resource sharing to achieve scalability consistency and economy. Direct and active management of the computing resources of public cloud 105 is performed by the computer hardware and / or software of cloud orchestration module 141. The computing resources provided by public cloud 105 are typically implemented by virtual computing environments running on various computers constituting host physical set 142, which is the entirety of physical computers in and / or available to the public cloud 105. Virtual computing environments (VCEs) typically take the form of virtual machines from virtual machine set 143 and / or containers from container set 144. It should be understood that these VCEs can be stored as images and can be transferred between various physical machine hosts as images or after the VCEs are instantiated. Cloud orchestration module 141 manages the transfer and storage of images, deploys new instantiations of VCEs, and manages active instantiations of VCE deployments. Gateway 140 is a collection of computer software, hardware, and firmware that allow public cloud 105 to communicate via WAN 102.

[0133] Now, we will provide some further explanation of Virtualized Computing Environments (VCEs). A VCE can be stored as an "image." A new active instance of a VCE can be instantiated from this image. Two common types of VCEs are virtual machines and containers. A container is a VCE that uses operating system-level virtualization. This refers to an operating system feature where the kernel allows multiple isolated user-space instances, called containers, to exist. From the perspective of the programs running within them, these isolated user-space instances typically appear as actual computers. Computer programs running on a regular operating system can utilize all the resources of that computer, such as connected devices, files and folders, network shares, CPU power, and quantifiable hardware capabilities. However, programs running within a container can only use the contents of the container and the devices allocated to the container; this is a characteristic known as containerization.

[0134] Private cloud 106 is similar to public cloud 105, except that computing resources are available only to a single enterprise. While private cloud 106 is depicted as communicating with WAN 102, in other embodiments, private cloud may be completely disconnected from the Internet and accessible only via a local / private network. A hybrid cloud is a combination of multiple clouds of different types (e.g., private, community, or public cloud types) typically implemented by different vendors. Each of the multiple clouds remains a separate and discrete entity, but the larger hybrid cloud architecture is bound together by standardization or proprietary technology that enables orchestration, management, and / or data / application portability across the multiple component clouds. In this embodiment, public cloud 105 and private cloud 106 are both part of a larger hybrid cloud.

[0135] Therefore, one or more embodiments of the present invention or elements thereof may be implemented in the form of an apparatus including a memory and at least one processor coupled to the memory and operable to perform exemplary method steps. Figure 19 A computer system that can be used to implement one or more aspects and / or elements of the present invention is described.

[0136] It should be noted that any method described herein may include additional steps to provide a system comprising different software modules embodied on a computer-readable storage medium; modules may include, for example, any or all suitable elements shown in the block diagrams and / or described herein; any, some, or all of the modules / blocks and / or submodules / subblocks described by way of example and not limitation. The method steps may then be performed using the different software modules and / or submodules executed on one or more hardware processors of the system as described above. Furthermore, a computer program product may include a computer-readable storage medium having code adapted to be implemented to perform one or more method steps described herein (including providing the different software modules for the system).

[0137] In some cases, an example of a user interface that can be used is Hypertext Markup Language (HTML) code provided to the user's computing device's browser by a server or similar entity. The HTML is then parsed by the browser on the user's computing device to create a graphical user interface (GUI).

[0138] Various embodiments of this disclosure have been described for illustrative purposes, but are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein has been chosen to best explain the principles of the embodiments, their practical application, or technical improvements to existing technologies on the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A method comprising: Define multiple qubit collision types and multiple constraints; For a qubit set, a computerized mixed-integer programming solver is used to iteratively minimize collisions under the constraints by minimizing the sum of the products of the frequency of collisions multiplied by the weights of the given constraints for each of the collision types. Based on the iterative minimization, the frequency tuning plan for the qubit group is output; as well as The frequency tuning scheme facilitates the tuning of physical qubits.

2. The method according to claim 1, wherein, The tuning includes LASIQ (laser annealing of randomly damaged qubits) tuning.

3. The method of claim 2, further comprising performing statistical modeling to assess the yield associated with the frequency tuning program, wherein, The LASIQ (Laser Annealing of Randomly Damaged Quantum Bits) is performed in response to the statistical modeling indicating an acceptable yield.

4. The method according to any one of the preceding claims further comprises, after iteratively minimizing collisions, using the computerized mixed-integer programming solver to iteratively maximize the frequency margin under the constraints for the qubit set.

5. The method of claim 4, further comprising determining that the iteratively minimized solution includes at least one collision, wherein, In response to the determination, the iterative process of maximizing the frequency margin is performed.

6. The method according to any one of the preceding claims, further comprising: Specifications for accessing the quantum bit lattice; Choose at least one sublattice shape; A sublattice is generated according to the at least one sublattice shape, such that each individual qubit in the qubit lattice is covered by at least one of the sublattices; The qubit group includes one of the sublattices.

7. The method of claim 6, further comprising the step of iteratively minimizing collisions by minimizing the sum of the products of the number of collisions multiplied by the weights of the frequency of a given constraint in each of the collision types for additional qubit groups corresponding to the remaining sublattices in the sublattice.

8. The method according to any one of claims 6 to 7, wherein, Selecting the at least one sublattice shape includes selecting at least one of a nine-qubit H-shape, an eleven-qubit H-shape, a twelve-qubit ring shape, and a shape that includes each qubit and its adjacent qubits.

9. The method according to any one of the preceding claims, wherein, The iterative minimization includes applying scaling factors to increase or decrease collision boundaries by type.

10. A computer program product comprising a computer-readable storage medium embodying program instructions therein, the program instructions being executable by a processor to cause the processor to perform a method, the method comprising: Define multiple qubit collision types and multiple constraints; For a qubit set, a computerized mixed-integer programming solver is used to iteratively minimize collisions under the constraints by minimizing the sum of the products of the frequency of collisions multiplied by the weights of the given constraints for each of the collision types. Based on the iterative minimization, the frequency tuning plan for the qubit group is output; as well as The frequency tuning scheme facilitates the tuning of physical qubits.

11. The computer program product according to claim 10, wherein, The method executed by the processor further includes, after iteratively minimizing collisions, using the computerized mixed-integer programming solver to iteratively maximize the frequency margin under the constraints for the qubit set.

12. A system comprising: Memory; as well as At least one processor is coupled to the memory and is operated to: Define multiple qubit collision types and multiple constraints; For a qubit set, a computerized mixed-integer programming solver is used to iteratively minimize collisions under the constraints by minimizing the sum of the products of the frequency of collisions multiplied by the weights of the given constraints for each of the collision types. Based on the iterative minimization, the frequency tuning plan for the qubit group is output; as well as The frequency tuning scheme facilitates the tuning of physical qubits.

13. The system according to claim 12, wherein, The tuning includes LASIQ (laser annealing of randomly damaged qubits) tuning.

14. The system according to claim 13, wherein, The at least one processor is also configured to perform statistical modeling to evaluate the yield associated with the frequency tuning scheme, wherein the LASIQ (laser annealing of randomly damaged qubits) is performed in response to the statistical modeling indicating an acceptable yield.

15. The system according to any one of claims 12 to 14, wherein, The at least one processor is also configured to, after the iterative minimization of collisions, use the computerized mixed-integer programming solver to iteratively maximize the frequency margin under the constraints for the qubit set.

16. The system according to claim 15, wherein, The at least one processor is further configured to determine that the iteratively minimized solution includes at least one collision, wherein the iterative maximization of frequency margin is performed in response to the determination.

17. The system according to any one of claims 12 to 16, wherein, The at least one processor is further operated to: Specifications for accessing the quantum bit lattice; Choose at least one sublattice shape; A sublattice is generated according to the at least one sublattice shape, such that each individual qubit in the qubit lattice is covered by at least one of the sublattices; The qubit group includes one of the sublattices.

18. The system according to claim 17, wherein, The at least one processor is also operated to repeat the step of iteratively minimizing collisions by minimizing the sum of the products of the number of collisions multiplied by the weights of the frequency of a given constraint in each of the collision types for an additional set of qubits corresponding to the remaining sublattices in the sublattice.

19. The system according to any one of claims 17 to 18, wherein, Selecting the at least one sublattice shape includes selecting at least one of a nine-qubit H-shape, an eleven-qubit H-shape, a twelve-qubit ring shape, and a shape that includes each qubit and its adjacent qubits.

20. The system according to any one of claims 12 to 19, wherein, The iterative minimization includes applying scaling factors to increase or decrease collision boundaries by type.

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