A control system

Abstract

A control system includes multiple analog output devices and multiple redundant communication bus watchdog modules corresponding one-to-one with each analog output device. A redundant communication bus is provided between the analog output devices, and a redundant communication bus watchdog module is installed on each of the redundant communication buses. The redundant communication bus watchdog module is used to power off the corresponding analog output device when its state is abnormal. This solution, by setting redundant communication bus watchdog modules on the redundant communication bus between the analog output devices, achieves state monitoring of the analog output devices and can power off the devices when their state is abnormal, thereby improving the stability and reliability of the control system.

Description

Technical Field

[0001] The embodiments of this application relate to, but are not limited to, the field of industrial automation control, and in particular to a control system. Background Technology

[0002] In industrial control environments such as power plants, electronic equipment faces complex electromagnetic conditions, making the stability of the control system particularly important. Analog output devices, as a crucial component of the control system, directly impact the performance and reliability of the entire system. Currently, many designs only configure a watchdog circuit at the reset control pin of the microcontroller unit. This approach limits reliability in complex electromagnetic environments.

[0003] Therefore, in order to improve the accuracy and reliability of analog output devices in complex electromagnetic environments, it is urgent to develop new design solutions. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0005] This application provides a control system that, by setting up a redundant communication bus watchdog module between analog output devices, enables status monitoring of the analog output devices. When the status of the analog output devices is abnormal, it can power them off, thereby improving the stability and reliability of the control system.

[0006] One embodiment of this application provides a control system, which includes multiple analog output devices and multiple redundant communication bus watchdog modules corresponding one-to-one with each analog output device; a redundant communication bus is provided between the analog output devices, and a redundant communication bus watchdog module is provided on the redundant communication bus; the redundant communication bus watchdog module is used to cut off the power to the analog output device when the state of its corresponding analog output device is abnormal.

[0007] Compared with related technologies, the present application provides a control system comprising multiple analog output devices and multiple redundant communication bus watchdog modules corresponding one-to-one with each analog output device. Specifically, a redundant communication bus is provided between the analog output devices, and a redundant communication bus watchdog module is installed on the redundant communication bus. The redundant communication bus watchdog module is used to power off the corresponding analog output device when its state is abnormal. This scheme achieves state monitoring of the analog output devices, and enables power-off processing when an analog output device's state is abnormal, thereby improving the stability and reliability of the control system.

[0008] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the application. Other advantages of this application can be realized and obtained by means of the embodiments described in the description and the accompanying drawings. Attached Figure Description

[0009] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0010] Figure 1 A schematic diagram of the watchdog setup in an embodiment of this application;

[0011] Figure 2 This is a schematic diagram illustrating the output principle of the analog output device in an embodiment of this application.

[0012] Figure 3 This is a schematic diagram of a disconnection detection circuit according to an embodiment of this application;

[0013] Figure 4 This is a schematic diagram of the data bus watchdog module under the bus timeout state in an embodiment of this application;

[0014] Figure 5 This is a schematic diagram of the data bus watchdog module under the bus timeout state in an embodiment of this application;

[0015] Figure 6 This is a schematic diagram of the redundant communication bus watchdog module under normal communication conditions in an embodiment of this application;

[0016] Figure 7 This is a schematic diagram of a redundant communication bus watchdog module under abnormal communication conditions in an embodiment of this application;

[0017] Figure 8 This is a schematic diagram illustrating the redundant communication principle in an embodiment of this application;

[0018] Figure 9 This is a schematic diagram of current output under abnormal redundant communication conditions in an embodiment of this application;

[0019] Figure 10 This is a schematic diagram of current output under abnormal redundant communication conditions in an embodiment of this application;

[0020] Figure 11 This is a schematic diagram of the power watchdog module in an embodiment of this application. Detailed Implementation

[0021] This application describes several embodiments, but these descriptions are exemplary and not limiting, and it will be apparent to those skilled in the art that many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with, or may replace, any feature or element of any other embodiment.

[0022] This application includes and contemplates combinations of features and elements known to those skilled in the art. The embodiments, features, and elements disclosed in this application can also be combined with any conventional features or elements to form unique inventive solutions. Any feature or element of any embodiment can also be combined with features or elements from other inventive solutions to form another unique inventive solution. Therefore, it should be understood that any feature shown and / or discussed in this application can be implemented individually or in any suitable combination. Therefore, the embodiments are not limited except by the limitations imposed by the appended claims and their equivalents. Furthermore, various modifications and changes can be made within the scope of the appended claims.

[0023] Furthermore, in describing representative embodiments, the specification may have presented methods and / or processes as a specific sequence of steps. However, the method or process should not be limited to the specific order of steps described herein, to the extent that it does not depend on such a specific order. As will be understood by those skilled in the art, other sequences of steps are also possible. Therefore, the specific order of steps set forth in the specification should not be construed as a limitation of the claims. Moreover, the claims concerning the method and / or process should not be limited to the steps performed in the written order, and those skilled in the art will readily understand that these orders can be varied and still remain within the spirit and scope of the embodiments of this application.

[0024] One embodiment of this disclosure provides a control system, such as Figure 1 As shown, the control system includes multiple analog output devices and multiple redundant communication bus watchdog modules corresponding one-to-one with the analog output devices.

[0025] A redundant communication bus is provided between the analog output devices, and a redundant communication bus watchdog module is provided on the redundant communication bus; the redundant communication bus watchdog module is used to cut off the power to the analog output device when the corresponding analog output device is in an abnormal state.

[0026] The control system in this embodiment sets up a redundant communication bus watchdog module on the redundant communication bus between analog output devices. The redundant communication bus watchdog module corresponds one-to-one with the analog output devices, realizing the status monitoring of the analog output devices. When the status of the analog output devices is abnormal, it can cut off the power to them, thereby improving the stability and reliability of the control system.

[0027] It should be noted that, Figure 1 This example only illustrates a scenario with two analog output devices, but the control system of this embodiment is not limited to containing only two analog output devices; it may contain multiple analog output devices. For instance, any pair of analog output devices in the control system of this embodiment can be used redundantly, and the pair of analog output devices can exchange and synchronize data through redundant communication.

[0028] In one exemplary embodiment, such as Figure 2 As shown, the control system may further include a controller, and the analog output device may include a preset number of current output circuits;

[0029] The current output circuits are isolated from each other; each current output circuit includes a DAC (Digital-to-Analog Converter) chip, a first voltage follower V1, a first transistor Q1, a first diode D1, a second diode D2, a first resistor R1, and a first fuse F1;

[0030] The DAC chip is connected to the controller and is used to receive the digital signal output by the controller and convert the digital signal into a first current signal.

[0031] The non-inverting input of the first voltage follower V1 is connected to the output of the DAC chip to receive a first current signal output by the DAC chip; the inverting input of the voltage follower V1 is used to receive a second current signal returned by an external device; and the output of the voltage follower V1 is used to output a third current signal generated based on the first and second current signals.

[0032] The base of the first transistor Q1 is connected to the output terminal of the first voltage follower V1, the emitter is connected to the power supply, and the collector is connected to the input terminal of the first diode D2.

[0033] The input terminal of the first resistor R1 is grounded, and the output terminal is connected to the second diode D2;

[0034] The input terminal of the first fuse F1 is connected to the output terminals of the first diode D1 and the second diode D2.

[0035] For example, the preset number can be 8, and the current of each current output circuit can be controlled between 4 and 20mA. In this example, the analog output device can interact with the controller via a data bus and simultaneously output 8 channels of 4-20mA signals according to the controller's instructions.

[0036] For example, the first resistor R1 can be a 100Ω high-precision resistor.

[0037] In the above embodiments, the first diode can be used to prevent reverse connection and to prevent external high voltage from affecting the internal circuit; the second diode can prevent high voltage from affecting the system; and the first fuse can be used to prevent current overload and protect the internal circuit.

[0038] In this embodiment, the analog output device obtains the required output Iout value by interacting with the host computer. After the logic control part converts and controls the DAC chip to output the corresponding Vout, the output adopts a combination of DAC chip and voltage-to-current conversion circuit. After the DAC chip outputs Vout, the voltage across the high-precision resistor R1 is clamped at Vout through a voltage follower, thereby generating a constant current Iout = Vout / R1 flowing through the high-precision resistor. After amplification by the transistor, the loop current is stabilized at Iout, thereby achieving a stable current output.

[0039] In one exemplary embodiment, such as Figure 2 As shown, a disconnection detection circuit can also be set between the first transistor Q1 and the first diode D1 (i.e., the OP_IN point in the figure). The disconnection detection circuit shown is as follows: Figure 3 As shown, this can be implemented using a comparator. The non-inverting input of the comparator is connected to a bias voltage formed by a resistor divider network, and the inverting input is connected to... Figure 2 At OP_IN, the output is connected to the logic control section.

[0040] In this embodiment of the control system, when no load is connected, the OP_IN voltage is higher than the voltage at the non-inverting input of the comparator, the comparator outputs 0V, and OP_OUT is detected as low. When a load is connected, the OP_IN voltage is lower than the voltage at the non-inverting input of the comparator, the comparator outputs 24V, and OP_OUT is detected as high. Therefore, the logic control section can determine whether the output is disconnected by identifying the level of OP_OUT.

[0041] In one exemplary embodiment, such as Figure 1 As shown, the control system may further include a controller and multiple data bus watchdog modules corresponding one-to-one with the analog output devices;

[0042] Each of the analog output devices is connected to the controller via a data bus, and the data bus circuit is equipped with a data bus watchdog module corresponding to the connected analog output device; the data bus watchdog module is used to control the duration of continuous communication between the corresponding analog output device and the controller.

[0043] For example, the analog output device can interact with the controller via a data bus, which can be a 485 data bus.

[0044] For example, when the data bus watchdog module detects that the continuous communication time between a certain analog output device and the controller exceeds a preset time, it can prevent the driver of the analog output device from continuing to output enable.

[0045] In the prior art, when an analog output device interacts with the controller via a data bus, the driver output is enabled when data needs to be sent. However, if a controller has multiple analog output devices of this type or other types connected to it, and one of the analog output devices occupies the bus for a long time, it will cause other devices to be unable to interact with the controller, resulting in data loss or conflict and making the bus communication unstable.

[0046] This embodiment uses a data bus watchdog module on the data bus circuit to control the duration of continuous communication between the analog output device and the controller. After a certain period of time, the watchdog will forcibly disable the output enable, preventing the problem of prolonged bus occupation and solving the above-mentioned technical problem.

[0047] In one example of this embodiment, the data bus watchdog module may include a timing gating circuit;

[0048] The timing gating circuit is used to output a high-level enable signal after receiving the transmit enable signal generated by the corresponding analog output device at the input terminal, and output a low-level enable signal after a predetermined time.

[0049] The analog output device is used to output data to the controller when it receives the high-level enable signal, and to stop outputting data to the controller when it receives the low-level enable signal.

[0050] In one example of this embodiment, such as Figure 4 and Figure 5 As shown, the timing gating circuit may include a third monostable trigger circuit and a second AND gate; the analog output device may include a control chip (not shown in the figure) and a driver;

[0051] The control chip is used to generate the transmit enable signal, which is a high-level signal;

[0052] The driver is configured to output data to the controller when it receives a high-level enable signal, and to stop outputting data to the controller when it receives a low-level enable signal.

[0053] The second input terminal B of the third monostable trigger circuit is connected to the control chip in the analog output device, and is used to receive the transmit enable signal; and output a high-level third-level signal in the metastable state and a low-level third-level signal in the steady state;

[0054] The first input terminal of the second AND gate is connected to the second output terminal Q of the third monostable trigger circuit to receive the third level signal; the second input terminal is connected to the control chip in the analog output device to receive the transmit enable signal; the output terminal is connected to the input terminal of the driver to output the enable signal (the enable signal refers to the enable signal that outputs a high level or a low level in the previous example).

[0055] For example, the third monostable trigger circuit may further include a first output terminal A, a third output terminal C, and a fourth output terminal R, the specific connections of which can be referred to Figure 4 and Figure 5 .

[0056] The control system in this embodiment monitors the output enable by configuring a data bus watchdog module. When the output enable of a certain analog output device driver exceeds a certain time, the data bus watchdog module will forcibly prevent it from continuing to output enable, thus preventing the problem of a certain analog output device occupying the bus for a long time.

[0057] For example, the monostable trigger circuit can be a monostable trigger, and the driver can be a 485 driver.

[0058] like Figure 4 As shown, the data bus watchdog timer uses a monostable multivibrator for timing. When the enable signal is input at terminal B of the monostable multivibrator, the Q terminal outputs a high level for the timing duration of terminal C. The B and Q terminals are ANDed by a third AND gate circuit, and the third AND gate circuit outputs a high level to enable the 485 driver to send.

[0059] like Figure 5 As shown, when the transmit enable signal input at terminal B of the monostable multivibrator exceeds the timing duration at terminal C, terminal Q outputs a low-level signal. The third AND gate circuit performs an AND operation on terminals B and Q, and the low-level output of the third AND gate circuit disables the 485 driver from transmitting, preventing the bus from being occupied for a long time, thus realizing the watchdog function of the data bus.

[0060] In one exemplary embodiment, such as Figure 6 and Figure 7As shown, the redundant communication bus watchdog module includes a first monostable trigger circuit, a second monostable trigger circuit, and a first switching circuit;

[0061] The first monostable trigger circuit is used to monitor the first data signal emitted by the corresponding analog output device and output a first level signal according to the first data signal;

[0062] The second monostable trigger circuit is used to monitor the second data signal received by the corresponding analog output device and output a second level signal according to the second data signal;

[0063] The first switching circuit is used to power on or power off the corresponding analog output device according to the first level signal and the second level signal.

[0064] For example, when the analog output device is in an abnormal state, both the first level signal and the second level signal are high level signals, and the first switching circuit disconnects the connection between the power supply and the power supply terminal of the analog output device; when the analog output device is in a normal state, the first level signal is a low level signal, the second level signal is a high level signal, and the first switching circuit connects the connection between the power supply and the power supply terminal of the analog output device.

[0065] In one example of this embodiment, such as Figure 6 and Figure 7 As shown, the first monostable trigger circuit includes a first input terminal A and a first output terminal. The first input terminal A of the first monostable trigger circuit is connected to the TX pin of the analog output device;

[0066] The second monostable trigger circuit includes a first input terminal A and a second output terminal Q. The first input terminal A of the second monostable trigger circuit is connected to the RX pin of the analog output device.

[0067] The first switching circuit may include a first AND gate and a P-type field-effect transistor, wherein the first input terminal and the second input terminal of the first AND gate are respectively connected to the first output terminal of the first monostable multivibrator. The second output terminal Q of the second monostable trigger circuit is connected to the gate of the first AND gate, the source of the P-type field-effect transistor is connected to the power supply, and the drain is connected to the power supply terminal of the corresponding analog output device. Thus, when the first switching circuit is turned off, the main power supply to the corresponding analog output device can be stopped.

[0068] Alternatively, the first switching circuit may also include a first NAND gate and an N-type field-effect transistor, with the first input terminal and the second input terminal of the first NAND gate respectively connected to the first output terminal of the first monostable multivibrator. The second output terminal Q of the second monostable trigger circuit; the gate of the N-type field-effect transistor is connected to the output terminal of the first NAND gate, the source is connected to the power supply, and the drain is the power supply terminal; or other forms can be used, as long as POWER can be output when the analog output device is communicating normally, and POWER is not output when the analog output device is communicating abnormally.

[0069] For example, the field-effect transistor can be a MOS (Metal-Oxide-Semiconductor Field-Effect Transistor); the first monostable trigger circuit and the second monostable trigger circuit can be monostable triggers.

[0070] In one exemplary embodiment, a schematic diagram of the redundant communication principle can be referred to... Figure 8 .like Figure 8 As shown, when using a pair of analog output devices for redundancy, the TTL signal (Transistor-Transistor Logic) is converted into a differential signal by the driver inside the analog output device. A communication watchdog can be set in the TTL signal section to monitor redundant communication.

[0071] like Figure 6 As shown, when the analog output device's transmitting and receiving functions are normal, TX and RX receive the falling edge of the data, and in Q and The system outputs high-level and low-level pulses for the timing duration at terminal C, respectively. When the AND gate output is 0, the MOS transistor is turned on, and the POWER outputs power. At this point, communication is normal, the POWER output is normal, and the current output diagram can be found in [reference needed]. Figure 9 Both analog output device 1 and analog output device 2 can output current normally, and Iout output is normal.

[0072] like Figure 7 As shown, when the TX signal of analog output device 1 or analog output device 2 malfunctions, terminal A remains at a high level, while RX normally has a falling edge input. A continuous high-level output is maintained. When Q receives a falling edge at terminal A, it outputs a high-level signal for the duration of the timing at terminal C. The AND gate output is 1, the MOS transistor is turned off, and the POWER output is cut off. For example, when the TX signal of analog output device 1 malfunctions, the current output diagram can be found in [reference needed]. Figure 10When the Powr of analog output device 1 is cut off, the circuit of analog output device 1 does not participate in Iout output, and analog output device 2 can still ensure normal Iout output through diode; since the circuit of analog output device 1 does not participate in Iout output, the redundant Iout output will not be affected by the problem of TX.

[0073] The control system in this embodiment, through a redundant communication bus watchdog module composed of two monostable trigger circuits, AND gates, and switching circuits, can ensure that when communication problems occur with the analog output device, the power supply to the faulty card is promptly disconnected, cutting off its output and ensuring the accuracy of the analog output device's output (for...). Figure 2 In other words, it means ensuring the correctness of the final output current value.

[0074] In one exemplary embodiment, the control system may further include a main power supply for supplying power to the control system;

[0075] A power watchdog module may be installed at the main power supply; the power watchdog module is used to disconnect the main power supply from the control system when the control system malfunctions.

[0076] In one example of this embodiment, the power watchdog module includes a monitoring chip and an external switching circuit;

[0077] The monitoring chip is used to monitor the transition edge signal output by the control system; and when the transition edge signal is detected within a preset monitoring time, it outputs a high-level signal; when the transition edge signal is not detected within the preset monitoring time, it outputs a low-level signal; and when the transition edge signal is still not detected after a preset maximum reset time, it resumes outputting a high-level signal.

[0078] The peripheral switching circuit is connected to the monitoring chip and is used to turn on the main power supply and the control system when a high-level signal is received from the monitoring chip; and to turn off the main power supply and the control system when a low-level signal is received from the monitoring chip.

[0079] In one example of this embodiment, the monitoring chip is a 706 chip, such as IMP706, SP706, MAX706, etc.; the preset maximum reset time can be 200ms.

[0080] like Figure 11As shown, the monitoring chip includes a WDI (Watchdog Input) terminal, a WDO (Watchdog Output) terminal, an MR (Manual Reset) terminal, and an nRESET (Not Reset) terminal. The WDI terminal is connected to the I / O port of the control system, the WDO terminal is connected to the MR terminal, and the nRESET terminal is connected to the base of the fourth transistor. The emitter of the fourth transistor is grounded, and the collector is connected to the gate of the fourth MOSFET. The source of the fourth MOSFET is connected to the power supply voltage, and the drain is the output terminal.

[0081] In this example, when the control section is working normally, the control I / O outputs a timing edge. After receiving a continuous timing edge, the monitoring chip's WDI pin outputs a continuous high level, the MR pin remains high, the nRESET pin remains high, the fourth transistor is on, the fourth MOSFET is on, and the output is normal. When the control section malfunctions, the I / O fails to output timing edges. After the monitoring chip's WDI pin no longer outputs a continuous timing edge, the WDO pin outputs a continuous low-level pulse, the MR pin remains on, the nRESET pin outputs a 200ms low level, the fourth transistor is off, the fourth MOSFET is off, the output is cut off, and the control section's power supply is cut off. After the nRESET pin outputs a 200ms low level, it resumes a high-level output, the fourth transistor and fourth MOSFET turn on, the output resumes, and the control section is reset.

[0082] The control system in this embodiment is equipped with a power watchdog circuit at the main power supply. When an abnormality occurs in the operation of the control part program, the power to the entire control system can be cut off in time, and the control system can be reset in time after a certain period of time so that it can return to normal operation as soon as possible.

[0083] In summary, the control system of this application can greatly improve the stability and reliability of the system by configuring watchdogs (data bus watchdog, redundant communication bus watchdog, and power supply watchdog) at various critical locations.

[0084] It will be understood by those skilled in the art that all or some of the steps, systems, or apparatuses disclosed above, and their functional modules / units, can be implemented as software, firmware, hardware, or suitable combinations thereof. In hardware implementations, the division between functional modules / units mentioned above does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed collaboratively by several physical components. Some or all components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software may be distributed on a computer-readable medium, which may include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term "computer storage medium" includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

[0085] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0086] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.

Claims

1. A control system, characterized in that, The control system includes multiple analog output devices and multiple redundant communication bus watchdog modules corresponding one-to-one with the analog output devices. A redundant communication bus is provided between the analog output devices, and a redundant communication bus watchdog module is provided on the redundant communication bus; the redundant communication bus watchdog module is used to cut off the power to the analog output device when the corresponding analog output device is in an abnormal state.

2. The control system according to claim 1, characterized in that, The redundant communication bus watchdog module includes a first monostable trigger circuit, a second monostable trigger circuit, and a first switching circuit; The first monostable trigger circuit is used to monitor the first data signal emitted by the corresponding analog output device and output a first level signal according to the first data signal; The second monostable trigger circuit is used to monitor the second data signal received by the corresponding analog output device and output a second level signal according to the second data signal; The first switching circuit is used to power on or power off the corresponding analog output device according to the first level signal and the second level signal.

3. The control system according to claim 2, characterized in that: The first monostable trigger circuit includes a first input terminal A and a first output terminal. The first input terminal A of the first monostable trigger circuit is connected to the TX pin of the analog output device; The second monostable trigger circuit includes a first input terminal A and a second output terminal Q. The first input terminal A of the second monostable trigger circuit is connected to the RX pin of the analog output device. The first switching circuit includes a first AND gate and a P-type field-effect transistor. The first input terminal and the second input terminal of the first AND gate are respectively connected to the first output terminal of the first monostable multivibrator. The second output terminal Q of the second monostable trigger circuit; the gate of the P-type field-effect transistor is connected to the output terminal of the first AND gate, the source is connected to the power supply, and the drain is connected to the power supply terminal of the corresponding analog output device.

4. The control system according to claim 3, characterized in that: When the analog output device is in an abnormal state, both the first level signal and the second level signal are high level signals, and the first switching circuit disconnects the connection between the power supply and the power supply terminal of the analog output device; when the analog output device is in a normal state, the first level signal is a low level signal, the second level signal is a high level signal, and the first switching circuit connects the connection between the power supply and the power supply terminal of the analog output device.

5. The control system according to claim 1, characterized in that, The control system also includes a controller and multiple data bus watchdog modules that correspond one-to-one with the analog output devices. Each of the analog output devices is connected to the controller via a data bus, and the data bus circuit is equipped with a data bus watchdog module corresponding to the connected analog output device; the data bus watchdog module is used to control the duration of continuous communication between the corresponding analog output device and the controller.

6. The control system according to claim 5, characterized in that, The data bus watchdog module includes a timing gating circuit; The timing gating circuit is used to output a high-level enable signal after receiving the transmit enable signal generated by the corresponding analog output device at the input terminal, and output a low-level enable signal after a predetermined time. The analog output device is used to output data to the controller when it receives the high-level enable signal, and to stop outputting data to the controller when it receives the low-level enable signal.

7. The control system according to claim 6, characterized in that, The timing gating circuit includes a third monostable trigger circuit and a second AND gate; the analog output device includes a control chip and a driver. The control chip is used to generate the transmit enable signal, which is a high-level signal; The driver is configured to output data to the controller when it receives a high-level enable signal, and to stop outputting data to the controller when it receives a low-level enable signal. The second input terminal B of the third monostable trigger circuit is connected to the control chip in the analog output device, and is used to receive the transmit enable signal; and output a high-level third-level signal in the metastable state and a low-level third-level signal in the steady state; The first input terminal of the second AND gate is connected to the second output terminal Q of the third monostable trigger circuit, and is used to receive the third level signal; The second input terminal is connected to the control chip in the analog output device and is used to receive the transmit enable signal. The output terminal is connected to the input terminal of the driver and is used to output the enable signal.

8. The control system according to claim 1, characterized in that, The control system also includes a main power supply, which is used to power the control system. A power watchdog module is provided at the main power supply; the power watchdog module is used to disconnect the main power supply from the control system when the control system malfunctions.

9. The control system according to claim 8, characterized in that, The power watchdog module includes a monitoring chip and peripheral switching circuitry; The monitoring chip is used to monitor the transition edge signal output by the control system; and to output a high-level signal when the transition edge signal is detected within a preset monitoring time. If the transition edge signal is not detected within the preset monitoring time, a low-level signal is output, and if the transition edge signal is still not detected after the preset maximum reset time, a high-level signal is output. The peripheral switching circuit is connected to the monitoring chip and is used to turn on the main power supply and the control system when a high-level signal is received from the monitoring chip; and to turn off the main power supply and the control system when a low-level signal is received from the monitoring chip.

10. The control system according to claim 1, characterized in that, The control system further includes a controller, and the analog output device includes a preset number of current output circuits; each of the current output circuits includes a DAC chip, a first voltage follower, a first transistor, a first diode, a second diode, a first resistor, and a first fuse; The DAC chip is connected to the controller and is used to receive the digital signal output by the controller and convert the digital signal into a first current signal. The non-inverting input terminal of the first voltage follower is connected to the output terminal of the DAC chip to receive the first current signal output by the DAC chip. Reverse The input terminal is used to receive the second current signal returned by external devices; The output terminal is used to output a third current signal generated based on the first current signal and the second current signal; The base of the first transistor is connected to the output terminal of the first voltage follower, the emitter is connected to the power supply, and the collector is connected to the input terminal of the first diode. The input terminal of the first resistor is grounded, and the output terminal is connected to the second diode; The input terminal of the first fuse is connected to the output terminals of the first diode and the second diode.

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