Temperature control method and 3D stacked dram chip

By incorporating a temperature sensor into the 3D stacked DRAM chip, the downlink traffic and access load can be monitored and actively adjusted in real time, thus solving the heat dissipation problem of the 3D stacked DRAM chip and improving the heat dissipation effect.

CN122131887APending Publication Date: 2026-06-02BEIJING MINGXIN QIRUI TECHNOLOGY CO LTD
View PDF 0 Cites 0 Cited by

Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
BEIJING MINGXIN QIRUI TECHNOLOGY CO LTD
Filing Date
2026-02-06
Publication Date
2026-06-02

AI Technical Summary

Technical Problem

3D stacked DRAM chips face significant heat dissipation challenges in the field of high-performance computing, and existing technologies struggle to effectively improve internal thermal conductivity to address the heat generation issues associated with high power density.

Method used

By setting temperature sensors in 3D stacked DRAM chips, the chip temperature is monitored in real time, and requests to reduce downlink traffic are actively sent to the external host based on temperature thresholds. Combined with external host regulation and internal strategies, access load and response time are adjusted to optimize the heat dissipation process.

Benefits of technology

It effectively reduces the heat generation rate of DRAM chips, improves the heat dissipation effect of existing heat dissipation processes such as air cooling, liquid cooling and vertical heat conduction channels, and achieves efficient heat dissipation of chips.

✦ Generated by Eureka AI based on patent content.

Smart Images

  • Figure CN122131887A_ABST
    Figure CN122131887A_ABST
Patent Text Reader

Abstract

This invention provides a temperature control method and a 3D stacked DRAM chip, belonging to the interdisciplinary field of computer storage and heat dissipation control. The method includes: acquiring the real-time temperature output by a temperature sensor; if the real-time temperature is greater than a first preset value, executing a first cooling scheme, the first cooling scheme including: sending a request to an external host to reduce downlink traffic, so as to reduce the access load on the DRAM chip according to the downlink traffic adjusted by the external host. This invention can reduce the access load on the DRAM chip based on the downlink traffic adjusted by the external host, reducing the rate of heat generation of the stacked DRAM chips, thereby improving the heat dissipation effect of the original heat dissipation processes of the 3D stacked DRAM chip, such as system-level solutions like air cooling and liquid cooling, and package-level structural solutions like vertical heat conduction channels.
Need to check novelty before this filing date? Find Prior Art