A data processing system, method, apparatus, electronic device, and storage medium

Abstract

This application discloses a data processing system, method, apparatus, electronic device, and storage medium, relating to the field of integrated circuit technology. Since the data receiving end receives monitoring data and first caches the target data locally instead of directly writing it to an external destination memory, when a preset transfer trigger condition is met, the data receiving end monitors the length of the target data represented by the monitoring data, moves the locally cached target data to the external destination memory, and generates a target interrupt signal based on the interrupt signal represented by the monitoring data. This allows the delay in generating the target interrupt signal to flexibly adapt to the actual delay. Finally, the target interrupt signal is sent to the local core controller, enabling the core controller to read the target data from the external destination memory at an appropriate time. This ensures that the core controller can read the target data normally, improving the reliability of the entire data processing system.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a data processing system, method, apparatus, electronic device and storage medium. Background Technology

[0002] Field-Programmable Gate Arrays (FPGAs) are a special type of integrated circuit chip that can be reprogrammed during manufacturing to meet specific application requirements, such as prototyping, complex digital signal processing, and communication interface design. However, with the continuous improvement of application requirements, there are often situations where a single FPGA cannot meet the application needs. If two or more FPGAs are combined into a single unit, how to achieve cross-FPGA data processing has become a key research topic.

[0003] In related technologies, considering that data transmission between two FPGAs is typically achieved using a chip-to-chip interface and interrupt signals are transmitted via GPIO, the transmission delay of the interrupt signal is much smaller than the data transmission delay. To prevent the receiving FPGA from missing data when responding to the interrupt signal, a fixed maximum delay is usually designed for the receiving FPGA, and a shift register is used to handle the interrupt signal with this fixed delay. However, since both the transmission delay of the interrupt signal and the data transmission delay are affected by various factors, the related technologies using a fixed maximum delay have low flexibility and are not conducive to ensuring the reliability of the entire FPGA data processing system. Summary of the Invention

[0004] This application provides a data processing system, method, apparatus, electronic device, and storage medium to at least solve the problem of low flexibility in related technologies, which is not conducive to ensuring the reliability of the entire FPGA data processing system.

[0005] This application provides a data processing system, including: a data sending end and a data receiving end; the data receiving end includes a monitoring cache module, a data receiving module, a local data cache module, a data transfer module, an interrupt generation module, and a core controller; The data transmitter is used to acquire monitoring data during the process of sending target data to the data receiver and generating an interrupt signal, and then send the monitoring data to the monitoring cache module; the monitoring data includes the interrupt signal generation delay of the data transmitter and the data length of the target data; The monitoring cache module is used to cache monitoring data; The data receiving module is used to receive the target data sent by the data receiving end and write the target data into the local data cache module; The local data caching module is used to cache target data locally; The data transfer module is used to read monitoring data from the monitoring cache module when the preset transfer trigger conditions are met, and to obtain the corresponding target data from the local data cache module according to the data length of the target data represented by the monitoring data, and then transfer the target data to the external destination storage. The interrupt generation module is used to read monitoring data from the monitoring cache module after the target data is moved to the external destination memory, generate the target interrupt signal by generating a delay according to the interrupt signal represented by the monitoring data, and send the target interrupt signal to the core controller. The core controller is used to respond to target interrupt signals in order to read target data from external target memory.

[0006] This application also provides a data processing method, applied to the data sending end of any of the above-mentioned data processing systems, the method comprising: Send the target data to the data receiving end; An interrupt signal is generated after the target data has been sent. During the process of sending target data to the data receiving end and generating an interrupt signal, monitoring data is acquired; Send the monitoring data to the data receiving end; Specifically, the data receiving end caches monitoring data in the monitoring cache module and writes target data to the local data cache module. When the preset relocation trigger condition is met, the data receiving end reads monitoring data from the monitoring cache module, retrieves the corresponding target data from the local data cache module according to the data length of the target data represented by the monitoring data, and relocates the target data to the external destination memory. After the target data is relocated to the external destination memory, the receiving end reads monitoring data from the monitoring cache module, generates a target interrupt signal based on the delay of the interrupt signal represented by the monitoring data, and sends the target interrupt signal to the core controller so that the core controller responds to the target interrupt signal and reads the target data from the external destination memory.

[0007] This application also provides a data processing method, applied to the data receiving end of any of the above-mentioned data processing systems, the method comprising: Acquire target data and monitoring data sent by the data sender; wherein, during the process of sending target data to the data receiver and generating an interrupt signal, the data sender acquires monitoring data and sends the monitoring data to the data receiver. Cache the monitoring data to the monitoring cache module; Cache the target data to the local data cache module; When the preset relocation trigger condition is met, the monitoring data is read from the monitoring cache module; According to the data length of the target data represented by the monitoring data, the corresponding target data is obtained from the local data cache module and moved to the external destination storage; After the target data is moved to the external destination memory, a target interrupt signal is generated based on the interrupt signal generated by the monitoring data and a delay is generated. The target interrupt signal is then sent to the core controller so that the core controller responds to the target interrupt signal and reads the target data from the external destination memory.

[0008] This application also provides a data processing apparatus, applied to the data transmission end of any of the above-described data processing systems, the apparatus comprising: The first sending module is used to send target data to the data receiving end; The generation module is used to generate an interrupt signal after the target data has been sent. The first acquisition module is used to acquire monitoring data during the process of sending target data to the data receiving end and generating an interrupt signal; The second sending module is used to send monitoring data to the data receiving end; Specifically, the data receiving end caches monitoring data in the monitoring cache module and writes target data to the local data cache module. When the preset relocation trigger condition is met, the data receiving end reads monitoring data from the monitoring cache module, retrieves the corresponding target data from the local data cache module according to the data length of the target data represented by the monitoring data, and relocates the target data to the external destination memory. After the target data is relocated to the external destination memory, the receiving end reads monitoring data from the monitoring cache module, generates a target interrupt signal based on the delay of the interrupt signal represented by the monitoring data, and sends the target interrupt signal to the core controller so that the core controller responds to the target interrupt signal and reads the target data from the external destination memory.

[0009] This application also provides a data processing apparatus, applied to the data receiving end of any of the above-described data processing systems, the apparatus comprising: The second acquisition module is used to acquire the target data and monitoring data sent by the data sender; wherein, during the process of sending the target data to the data receiver and generating an interrupt signal, the data sender acquires the monitoring data and sends the monitoring data to the data receiver. The first caching module is used to cache monitoring data to the monitoring caching module; The second caching module is used to cache the target data to the local data caching module; The reading module is used to read monitoring data from the monitoring cache module when the preset relocation trigger conditions are met; The transfer module is used to retrieve the corresponding target data from the local data cache module according to the data length of the target data represented by the monitoring data, and transfer the target data to the external destination storage. The interrupt module is used to generate a target interrupt signal after the target data is moved to the external destination memory, based on the interrupt signal represented by the monitoring data, and send the target interrupt signal to the core controller so that the core controller can respond to the target interrupt signal and read the target data from the external destination memory.

[0010] This application also provides an electronic device, including: a memory for storing a computer program; and a processor for executing the computer program to implement the steps of any of the above data processing methods.

[0011] This application also provides a computer-readable storage medium storing a computer program, wherein the computer program, when executed by a processor, implements the steps of any of the above-described data processing methods.

[0012] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of any of the above-described data processing methods.

[0013] Through this application, since the data receiving end receives the monitoring data and first caches the target data locally instead of directly writing it to the external destination memory, when the preset transfer trigger condition is met, the data receiving end monitors the data length of the target data represented by the monitoring data, moves the locally cached target data to the external destination memory, and generates a target interrupt signal based on the interrupt signal represented by the monitoring data. This allows the delay in generating the target interrupt signal to flexibly adapt to the actual delay. Finally, the target interrupt signal is sent to the local core controller, so that the core controller can read the target data from the external destination memory at the appropriate time. This ensures that the core controller can read the target data normally and improves the reliability of the entire data processing system. Attached Figure Description

[0014] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0015] Figure 1 This is a schematic diagram of the interaction flow of the data processing system provided in the embodiments of this application; Figure 2 This is a schematic diagram of the structure of the data sending end provided in an embodiment of this application; Figure 3This application provides a schematic diagram of the structure of an exemplary data processing system. Figure 4 A flowchart illustrating a data processing method provided in an embodiment of this application; Figure 5 A flowchart illustrating another data processing method provided in an embodiment of this application; Figure 6 This is a schematic diagram of the structure of a data processing device provided in an embodiment of this application; Figure 7 This is a schematic diagram of another data processing apparatus provided in an embodiment of this application; Figure 8 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0016] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0017] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0018] The main advantages of FPGAs lie in their flexibility and reconfigurability, making them suitable for prototyping, complex digital signal processing, and communication interface design. Compared to fully custom ASICs, FPGAs offer shorter development cycles, lower costs, and less risk, making them ideal for small to medium-sized projects and large-scale system integration.

[0019] FPGA prototyping is a mature technology used to verify the functionality and performance of application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), and systems-on-chips (SoCs) by porting the register-transfer level (RTL) to a field-programmable gate array (FPGA). FPGA prototyping is a verification method for SoCs based on FPGAs, generally following front-end RTL design and RTL simulation. Both FPGA and ASIC front-end code are developed based on Verilog HDL, so ASIC code can theoretically run on the FPGA platform. It's a verification method to confirm the correctness of chip functionality as much as possible before tape-out. FPGA prototyping is crucial in digital chip design because, compared to using simulators or accelerators for simulation, FPGA operation speed is closer to that of a real chip, allowing software developers to collaborate on low-level software development. This collaborative hardware and software development before tape-out is its most irreplaceable aspect.

[0020] Taking the BMC chip as an example, this chip includes an ARM (core controller) and a USB module (verification module). The USB module is responsible for handling communication via the USB interface within the BMC chip. It efficiently writes data from the USB device to DDR memory through an internal DMA (Direct Memory Access) mechanism. When the USB module communicates with the ARM, it writes data to DDR via internal DMA and then sends an interrupt signal to notify the ARM. After receiving the interrupt, the ARM retrieves data from DDR, checks what event the USB device has sent, and then proceeds with the next step of processing.

[0021] During large-scale chip prototyping, insufficient logic resources on the FPGA chip may occur, causing the entire design to be unable to fit on a single FPGA chip, necessitating the splitting of the design across two FPGAs. The USB module is then placed on a separate FPGA chip. When the USB module writes data to DDR, it does so through a chip-to-chip module, and the IRQ signal (interrupt signal) is transmitted through a general-purpose input / output (GPIO) channel.

[0022] However, the latency of C2C data transmission is greater than that of IRQ transmission via GPIO. This can lead to a situation where the IRQ signal is transmitted to the ARM processor before the data arrives, resulting in the ARM processor being unable to read the data and malfunctioning. Taking the USB module as a separate FPGA0 and the ARM and other modules as FPGA1 as an example, related technologies propose a solution to address this latency by timing the IRQ signal on FPGA0. Specifically, the time interval between data generation and interrupt IRQ generation is calculated on FPGA1 and denoted as the cnt signal. This clock cycle is then transmitted to FPGA0, where a shift register shifts the IRQ signal. Based on the cnt signal, the delayed IRQ is selected, ensuring that the latency between the delayed IRQ and the data is consistent with the latency between the IRQ and the data on FPGA1.

[0023] This method can indeed solve the problem of interrupts occurring before data is generated, but it also has certain drawbacks: when using a shift register to delay the IRQ on FPGA0, since the delay between the IRQ and the data on FPGA1 cannot be known in advance, a relatively large shift register with a fixed maximum delay length can be used to delay the IRQ signal by pacing. Once the delay on FPGA1 exceeds the maximum delay on FPGA0, the processing of the IRQ on FPGA0 will have problems.

[0024] To address the aforementioned technical problems, this application provides a data processing system, method, apparatus, electronic device, and storage medium. The system includes a data transmitter and a data receiver. The data receiver includes a monitoring cache module, a data receiving module, a local data cache module, a data transfer module, an interrupt generation module, and a core controller. The data transmitter acquires monitoring data and sends it to the monitoring cache module during the process of sending target data to the data receiver and generating an interrupt signal. The monitoring data includes the interrupt signal generation delay at the data transmitter and the data length of the target data. The monitoring cache module caches the monitoring data. The data receiving module receives the target data sent by the data receiver and transfers the target data to the monitoring cache module. The data is written to the local data cache module; the local data cache module is used to cache the target data locally; the data transfer module is used to read monitoring data from the monitoring cache module when the preset transfer trigger condition is met, and obtain the corresponding target data from the local data cache module according to the data length of the target data represented by the monitoring data, and transfer the target data to the external destination memory; the interrupt generation module is used to read monitoring data from the monitoring cache module after the target data is transferred to the external destination memory, and generate a target interrupt signal according to the interrupt signal represented by the monitoring data, and send the target interrupt signal to the core controller; the core controller is used to respond to the target interrupt signal to read the target data from the external destination memory. The system provided by the above solution, because the data receiving end receives the monitoring data and first caches the target data locally instead of directly writing it to the external destination memory, when the preset transfer trigger condition is met, the data receiving end monitors the length of the target data represented by the monitoring data, moves the locally cached target data to the external destination memory, and generates a target interrupt signal based on the interrupt signal represented by the monitoring data. This allows the delay in generating the target interrupt signal to flexibly adapt to the actual delay. Finally, the target interrupt signal is sent to the local core controller, so that the core controller can read the target data from the external destination memory at the appropriate time. This ensures that the core controller can read the target data normally and improves the reliability of the entire data processing system.

[0025] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0026] This application provides a data processing system for processing data transmitted between two or more FPGAs involved in the prototype verification of an integrated circuit.

[0027] like Figure 1The diagram shown is an interactive flow diagram of the data processing system provided in this application embodiment. The system includes: a data sending end and a data receiving end; the data receiving end includes a monitoring cache module, a data receiving module, a local data cache module, a data transfer module, an interrupt generation module, and a core controller.

[0028] The data transmitter is used to acquire monitoring data and send the monitoring data to the monitoring cache module during the process of sending target data to the data receiver and generating interrupt signals.

[0029] The monitoring data includes the delay in the interrupt signal generation at the data sending end and the data length of the target data.

[0030] The monitoring cache module is used to cache monitoring data.

[0031] The data receiving module is used to receive the target data sent by the data receiving end and write the target data into the local data cache module.

[0032] The local data caching module is used to cache target data locally.

[0033] The data transfer module is used to read monitoring data from the monitoring cache module when the preset transfer trigger conditions are met, and to obtain the corresponding target data from the local data cache module according to the data length of the target data represented by the monitoring data, and then transfer the target data to the external destination storage.

[0034] The interrupt generation module is used to read monitoring data from the monitoring cache module after the target data is moved to the external destination memory, generate the target interrupt signal by generating a delay according to the interrupt signal represented by the monitoring data, and send the target interrupt signal to the core controller.

[0035] The core controller is used to respond to target interrupt signals in order to read target data from external target memory.

[0036] It should be noted that the data sending end refers to the FPGA with a USB device deployed. The data sending end generates the target data to be verified and transmits the target data to the data receiving end. The data receiving end writes the target data into the external destination memory (DDR). After determining that the target data has been written, the data sending end generates an interrupt signal to notify the core controller that the data is ready. When the core controller receives the interrupt signal, it accesses the DDR to obtain the target data. However, when the core controller receives the interrupt signal, the DDR may not have written or finished writing the target data. Therefore, this embodiment ensures that the core controller receives the interrupt signal only after the DDR data is ready.

[0037] Specifically, during the process of sending target data to the data receiver and generating an interrupt signal, the data transmitter also acquires monitoring data. The interrupt signal generation delay refers to the time interval elapsed from the completion of the USB module's transmission of one frame of target data to the generation of an interrupt signal, if the prototype verification is implemented based on a single FPGA. This time interval is typically measured by a counter in clock cycles, and the interrupt signal generation delay is denoted as cnt1. The target data length refers to the size or quantity of the target data transmitted, and the target data length is denoted as cnt2.

[0038] Specifically, the local data cache module is implemented by RAM (Random Access Memory) to temporarily store the target data locally at the receiving end, instead of writing it directly to the final destination memory (DDR). This decouples the uncertain latency of cross-FPGA data transmission from the interrupt signal transmission to the core controller, providing flexibility for subsequent synchronization operations.

[0039] Specifically, the data transfer module monitors preset transfer trigger conditions. When the conditions are met, it reads the data length information from the monitoring cache module and extracts the complete data frame of the corresponding length from the local data cache module accordingly, and then transfers it to the external destination storage.

[0040] Specifically, after the target data has been successfully moved to the external destination memory, the interrupt generation module reads the interrupt signal from the monitoring cache module to generate a delay and waits for the corresponding number of clock cycles to restore the original timing relationship of the data in the USB module. Finally, it generates the target interrupt signal and sends it to the core controller. This ensures that the data in the external destination memory is fully readable when the core controller receives the interrupt signal, thereby guaranteeing the reliability of the system.

[0041] Based on the above embodiments, such as Figure 2 This is a schematic diagram of the structure of a data transmitter provided in an embodiment of this application. As one possible implementation, in one embodiment, the data transmitter includes: The verification module is used to send target data to the data receiving end through the data transmission link and generate an interrupt signal after the target data transmission operation is completed.

[0042] The monitoring module is used to acquire monitoring data and send the monitoring data to the monitoring cache module during the process of the verification module sending target data to the data receiving end and generating interrupt signals.

[0043] The interrupt signal generated by the verification module is sent to the data receiving end through the signal transmission link.

[0044] It should be noted that the verification module specifically refers to the USB module. The verification module generates the target data to be transmitted. The target data can be a data packet received from the USB device and sent to the data receiving end through the data transmission link (C2C). After the verification module completes the transmission of one frame of target data, due to the uncertain transmission delay of the target data, the verification module generates an interrupt signal according to the interrupt signal generation delay based on the start time of the target data transmission operation. The interrupt signal is a level signal used to inform the core controller of the receiving end that the data has been written to DDR.

[0045] Specifically, in one embodiment, the monitoring module includes a first counter for determining the interrupt signal generation delay; wherein the interrupt signal generation delay characterizes the time interval between the verification module completing the target data transmission operation and the interrupt signal generation operation; and a second counter for determining the data length of the target data.

[0046] Specifically, the first counter counts in clock cycles, incrementing by 1 with each clock cycle. Counting begins when the verification module starts sending target data, and stops when the verification module generates an interrupt signal. The second counter also starts counting when the verification module starts sending target data, and stops counting when the verification module generates a data completion signal, indicating that the transmission of target data has been completed. This second counter is used to count based on the validity signal or byte enable signal of the data bus, and can count by the number of bytes or data packets.

[0047] Based on the above embodiments, such as Figure 3 This application provides an exemplary structural diagram of a data processing system. As one implementable approach, in one embodiment, the monitoring cache module includes: The receiving unit is used to receive monitoring data through a signal transmission link and perform data merging processing on the monitoring data to obtain merged monitoring data.

[0048] The caching unit is used to cache the monitoring data after the merging process.

[0049] The receiving unit is essentially the front-end interface of the monitoring cache module. It receives monitoring data from the signal transmission link (GPIO) and performs data merging processing, combining cnt1 and cnt2 into a single data set to save cache unit capacity. The cache unit can employ a first-in, first-out queue, with the user temporarily caching the merged monitoring data processed by the receiving unit. To cache cnt1 and cnt2 into the cache unit, the data sending end requires a write-valid signal. Therefore, when cnt1 counts to completion, the data sending end generates a write-valid signal lasting one clock cycle. This signal is also transmitted to the receiving unit via GPIO, enabling the receiving unit to perform monitoring data merging and caching based on the write-valid signal.

[0050] Specifically, in one embodiment, the signal receiving module is used to receive target data sent by the data receiving end through the data transmission link; and to write the received target data into the local data cache module through the internal link.

[0051] The data transmission link includes at least a C2C link, and the internal link refers to the on-chip communication bus of the FPGA at the data receiving end, such as the AXI bus.

[0052] Specifically, in one embodiment, the data transfer module includes a bus interconnect module for connecting the local data cache module and the external destination memory controller; the external destination memory controller is used to access the local data cache module through the bus interconnect module, read monitoring data from the monitoring cache module, obtain the corresponding target data from the local data cache module according to the data length of the target data represented by the monitoring data, and transfer the target data to the external destination memory.

[0053] The bus interconnect module serves as the internal communication infrastructure of the data receiver, responsible for establishing data transmission paths between multiple master devices (external destination memory controller and core controller) and slave devices (data local cache module). This module implements the on-chip bus protocol (AXI). When a transfer operation is initiated, the bus interconnect module responds to the request from the external destination memory controller and establishes a data channel between it and the data local cache module to transmit the target data.

[0054] Specifically, the external destination memory controller is the DDR controller. When the preset relocation trigger condition is met, the external destination memory controller first reads the monitoring data from the monitoring cache module. Based on the obtained data length information, it initiates a read request to the data local cache module (RAM) through the bus interconnect module to continuously read data of length cnt2 from the starting address of RAM, that is, to read the target data. Then, it initiates a write request to the external destination memory to move the target data to the external destination memory.

[0055] By reading and relying on the length information in the monitoring data, the integrity and accuracy of the transferred data are ensured, data transfer errors are avoided, and the core controller is prevented from reading incorrect data from the DDR in the future.

[0056] Based on the above embodiments, as an implementable approach, in one embodiment, the interrupt generation module is further configured to receive an interrupt signal sent by the data sending end; monitor the target data writing progress of the data local cache module; determine whether the preset migration trigger condition is met based on the timing of the interrupt signal reception and the target data writing progress of the data local cache module; and, if it is determined that the preset migration trigger condition is met, send a trigger signal to the data migration module to inform the data migration module that the preset migration trigger condition is currently met.

[0057] It should be noted that the data sending end generates and sends an interrupt signal to the data receiving end according to the original logic. The interrupt signal is transmitted through a low-latency GPIO signal transmission link and generally arrives at the data receiving end earlier than the target data.

[0058] Specifically, in one embodiment, the interrupt generation module is specifically used to determine, when an interrupt signal is received, that the preset relocation triggering condition is met if no interrupt signal is received before the target data has been completely written to the data local cache module.

[0059] Furthermore, in one embodiment, the interrupt generation module is used to generate a target interrupt signal based on the interrupt signal generation delay represented by the monitoring data and the target data transfer delay.

[0060] Specifically, if the target data has been completely written to the local data cache module but no interrupt signal has been received, this indicates that the time difference between the interrupt signal and the completion of data transmission at the data sending end is greater than the delay of the target data transmission via C2C. Therefore, the timing for reading the local data cache module should be when the data receiving end receives the interrupt signal from the data sending end, simultaneously reading the values ​​of cnt1 and cnt2 in the cache. Based on cnt2, the corresponding length of data is read from the local data cache module and then sent to the external destination memory controller. After the data transmission is complete, a new target interrupt signal is generated and sent to the core controller after waiting for cnt1 clock cycles. This restores the time difference between data transmission and interrupt generation at the data sending end.

[0061] Accordingly, in one embodiment, the interrupt generation module is specifically used to determine that the preset relocation triggering condition is met when the target data has been completely written into the data local cache module, even if the target data has not yet been written into the data local cache module but an interrupt signal is received.

[0062] Specifically, if an interrupt signal is received from the data sender before a data frame (target data) has even begun to be written to the data local buffer module at the data receiver, it indicates that the data transmission delay via C2C is relatively large. The time difference between the interrupt signal and the completion of data transmission at the data receiver, plus the transmission delay corresponding to the data length, is less than the C2C transmission delay. In this case, it's not possible to read the data local buffer module and buffer unit based on the arrival time of the interrupt signal, because there is no data in the data local buffer module at this point. Instead, the data local buffer module and buffer unit should be read only after a data frame has been written to the data local buffer module, indicated by a marker on the AXI bus indicating that the data local buffer module has been written.

[0063] Accordingly, in one embodiment, the interrupt generation module is specifically used to determine, when the target data is being written to the local data cache module but an interrupt signal is received, that the preset transfer triggering conditions are met.

[0064] Specifically, during the process of writing the target data to the local data cache module, the data receiver received an interrupt signal from the data sender. This indicates that the C2C transmission delay is relatively large, and the time difference between the interrupt signal and the completion of data transmission on FPGA1 is less than the C2C transmission delay. Similarly, the local data cache module can be read at this point based on the interrupt signal, as the values ​​of the two counters are now available. Furthermore, since the local data cache module can read and write simultaneously, it ensures that a complete frame of data is obtained. Likewise, the target data read from the local data cache module is sent to the external destination memory.

[0065] Specifically, in one embodiment, the data transfer module is further configured to determine the transfer delay of the target data based on the data length of the target data.

[0066] Specifically, since the movement of target data also incurs a delay, the timing of the target interrupt signal generation can be the cumulative value of the data movement start time, the movement delay, and the interrupt signal generation delay. This ensures that regardless of the amount of target data, the interrupt signal is always issued only after the target data has been completely stored in DDR, eliminating the risks that may arise from ignoring internal operation delays and further improving system reliability.

[0067] Specifically, in one embodiment, the core controller is specifically used to respond to a target interrupt signal by initiating an access request to an external target memory controller through a bus interconnect module, so as to read target data from an external target memory through the external target memory controller; and to determine the prototype verification result corresponding to the verification module based on the result of reading the target data.

[0068] Specifically, when the target interrupt signal generated by the interrupt generation module reaches the core controller, the core controller suspends its current operation, preserves its context, and jumps to the preset interrupt service routine to begin execution. In the interrupt service routine, the core controller, acting as a bus master, initiates a read request to the external destination memory controller via the bus interconnect module. The bus interconnect module, acting as a switching center, establishes a communication path from the core controller to the external destination memory controller for this access. Upon receiving the request, the external destination memory controller performs necessary addressing and timing control, reads the target data requested by the core controller from the external destination memory, and returns the data to the core controller via the bus interconnect module.

[0069] After receiving the target data, the core controller parses, calculates, or compares it with expected values. For example, if the verification module is a USB module, the core controller checks whether the received data packet is completely consistent with the data sent by the data sender, and whether the checksum is correct. Based on the data processing results, it determines whether the verification module's functionality is correct. If the data is correct, it proves that the verification module's RTL design functions normally on the current FPGA prototype platform, and the prototype verification passes. If the data is incorrect, it indicates that there may be a problem with the design or integration of the verification module, the prototype verification fails, and debugging and modification are required.

[0070] This application provides a data processing system where, upon receiving monitoring data, the data receiver first caches the target data locally instead of directly writing it to an external destination memory. When a preset transfer trigger condition is met, the data receiver monitors the length of the target data and moves the locally cached target data to the external destination memory. Based on the interrupt signal represented by the monitoring data, a delay is generated to produce a target interrupt signal, allowing the delay to flexibly adapt to actual latency. Finally, the target interrupt signal is sent to the local core controller, enabling the core controller to read the target data from the external destination memory at the appropriate time. This ensures the core controller can read the target data correctly, improving the reliability of the entire data processing system. Furthermore, it solves the problem of system malfunctions caused by asynchronous data transmission and interrupts across FPGAs during FPGA prototype verification, improving the accuracy of dual-FPGA prototype verification and reducing the occurrence of anomalies.

[0071] Through the above description of the embodiments, those skilled in the art can clearly understand that the system according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method.

[0072] This application provides a data processing method applied to the data sending end of the data processing system provided in the above embodiments.

[0073] like Figure 4 The diagram shown is a flowchart illustrating a data processing method provided in an embodiment of this application. The method includes: Step 401: Send the target data to the data receiving end; Step 402: After the target data is sent, an interrupt signal is generated; Step 403: During the process of sending target data to the data receiving end and generating an interrupt signal, acquire monitoring data; Step 404: Send the monitoring data to the data receiving end.

[0074] Specifically, the data receiving end caches monitoring data in the monitoring cache module and writes target data to the local data cache module. When the preset relocation trigger condition is met, the data receiving end reads monitoring data from the monitoring cache module, retrieves the corresponding target data from the local data cache module according to the data length of the target data represented by the monitoring data, and relocates the target data to the external destination memory. After the target data is relocated to the external destination memory, the receiving end reads monitoring data from the monitoring cache module, generates a target interrupt signal based on the delay of the interrupt signal represented by the monitoring data, and sends the target interrupt signal to the core controller so that the core controller responds to the target interrupt signal and reads the target data from the external destination memory.

[0075] For a description of the features in the embodiments corresponding to the data processing method, please refer to the relevant descriptions in the embodiments corresponding to the data processing system, which will not be repeated here.

[0076] This application provides another data processing method, applied to the data receiving end of the data processing system provided in the above embodiments.

[0077] like Figure 5 The diagram shown is a flowchart illustrating another data processing method provided in an embodiment of this application. The method includes: Step 501: Obtain the target data and monitoring data sent by the data sender; wherein, during the process of sending the target data to the data receiver and generating an interrupt signal, the data sender obtains the monitoring data and sends the monitoring data to the data receiver. Step 502: Cache the monitoring data to the monitoring cache module; Step 503: Cache the target data in the local data cache module; Step 504: When the preset relocation trigger condition is met, read the monitoring data from the monitoring cache module; Step 505: According to the data length of the target data represented by the monitoring data, obtain the corresponding target data from the local data cache module and move the target data to the external destination storage; Step 506: After the target data is moved to the external destination memory, a target interrupt signal is generated according to the interrupt signal generated by the monitoring data, and the target interrupt signal is sent to the core controller so that the core controller responds to the target interrupt signal and reads the target data from the external destination memory.

[0078] For a description of the features in the embodiments corresponding to the data processing method, please refer to the relevant descriptions in the embodiments corresponding to the data processing system, which will not be repeated here.

[0079] Embodiments of this application also provide a data processing apparatus for executing the data processing method applied to a data receiving end provided in the above embodiments.

[0080] like Figure 6 The diagram shown is a structural schematic of a data processing device provided in an embodiment of this application. The data processing device 60 includes: a first sending module 601, a generating module 602, a first acquiring module 603, and a second sending module 604.

[0081] The system includes a first sending module for sending target data to the data receiving end; a generating module for generating an interrupt signal after the target data is sent; a first acquiring module for acquiring monitoring data during the process of sending target data to the data receiving end and generating an interrupt signal; and a second sending module for sending the monitoring data to the data receiving end.

[0082] Specifically, the data receiving end caches monitoring data in the monitoring cache module and writes target data to the local data cache module. When the preset relocation trigger condition is met, the data receiving end reads monitoring data from the monitoring cache module, retrieves the corresponding target data from the local data cache module according to the data length of the target data represented by the monitoring data, and relocates the target data to the external destination memory. After the target data is relocated to the external destination memory, the receiving end reads monitoring data from the monitoring cache module, generates a target interrupt signal based on the delay of the interrupt signal represented by the monitoring data, and sends the target interrupt signal to the core controller so that the core controller responds to the target interrupt signal and reads the target data from the external destination memory.

[0083] For a description of the features in the embodiment corresponding to the data processing device, please refer to the relevant description in the embodiment corresponding to the data processing method, which will not be repeated here.

[0084] The embodiments of this application also provide another data processing apparatus for executing the data processing method applied to a data receiving end provided in the above embodiments.

[0085] like Figure 7The diagram shown is a structural schematic of another data processing device provided in an embodiment of this application. The data processing device 70 includes: a second acquisition module 701, a first cache module 702, a second cache module 703, a reading module 704, a transfer module 705, and an interrupt module 706.

[0086] The system includes the following components: a second acquisition module for acquiring target data and monitoring data sent by the data sender; wherein the data sender acquires monitoring data and sends it to the data receiver during the process of sending target data to the data receiver and generating an interrupt signal; a first cache module for caching monitoring data in a monitoring cache module; a second cache module for caching target data in a local data cache module; a read module for reading monitoring data from the monitoring cache module when a preset transfer trigger condition is met; a transfer module for acquiring the corresponding target data from the local data cache module according to the data length of the target data represented by the monitoring data and transferring the target data to an external destination memory; and an interrupt module for generating a target interrupt signal after the target data has been transferred to the external destination memory, generating a delay according to the interrupt signal represented by the monitoring data, and sending the target interrupt signal to the core controller so that the core controller responds to the target interrupt signal and reads the target data from the external destination memory.

[0087] For a description of the features in the embodiment corresponding to the data processing device, please refer to the relevant description in the embodiment corresponding to the data processing method, which will not be repeated here.

[0088] Embodiments of this application also provide an electronic device, such as... Figure 8 The diagram shown is a schematic diagram of the structure of an electronic device provided in an embodiment of this application, including a processor 10 and a memory 20. The memory 20 stores a computer program, and the processor 10 is configured to run the computer program to perform the steps in any of the above-described data processing method embodiments.

[0089] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above data processing method embodiments when it is run.

[0090] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0091] Embodiments of this application also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in any of the above data processing method embodiments.

[0092] Embodiments of this application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps in any of the above data processing method embodiments.

[0093] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0094] The data processing system, method, apparatus, electronic device, and storage medium provided in this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only intended to help understand the method and core ideas of this application. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A data processing system, characterized in that, include: The system includes a data sending end and a data receiving end; the data receiving end includes a monitoring cache module, a data receiving module, a local data cache module, a data transfer module, an interrupt generation module, and a core controller. The data sending end is used to acquire monitoring data and send the monitoring data to the monitoring cache module during the process of sending target data to the data receiving end and generating an interrupt signal; wherein, the monitoring data includes the interrupt signal generation delay of the data sending end and the data length of the target data; The monitoring cache module is used to cache the monitoring data; The data receiving module is used to receive target data sent by the data receiving end and write the target data into the local data cache module; The local data caching module is used to cache the target data locally; The data migration module is used to read the monitoring data from the monitoring cache module when the preset migration trigger condition is met, and to obtain the corresponding target data from the local data cache module according to the data length of the target data represented by the monitoring data, and to migrate the target data to the external destination memory. The interrupt generation module is used to read the monitoring data from the monitoring cache module after the target data is moved to the external destination memory, generate a target interrupt signal according to the interrupt signal represented by the monitoring data, generate a delay, and send the target interrupt signal to the core controller. The core controller is used to respond to the target interrupt signal in order to read the target data from the external destination memory.

2. The data processing system according to claim 1, characterized in that, The data sending end includes: The verification module is used to send target data to the data receiving end through the data transmission link, and generate an interrupt signal after completing the sending operation of the target data; The monitoring module is used to acquire monitoring data and send the monitoring data to the monitoring cache module during the process of the verification module sending target data to the data receiving end and generating an interrupt signal. The interrupt signal generated by the verification module is sent to the data receiving end through the signal transmission link.

3. The data processing system according to claim 2, characterized in that, The monitoring module includes: A first counter is used to determine the interrupt signal generation delay; wherein, the interrupt signal generation delay characterizes the time interval between the verification module completing the target data transmission operation and the interrupt signal generation operation; The second counter is used to determine the data length of the target data.

4. The data processing system according to claim 1, characterized in that, The monitoring cache module includes: The receiving unit is used to receive the monitoring data through a signal transmission link and perform data merging processing on the monitoring data to obtain merged monitoring data. A caching unit is used to cache the monitoring data after the merging process.

5. The data processing system according to claim 1, characterized in that, The signal receiving module is specifically used for: Receive the target data sent by the data receiving end through the data transmission link; The received target data is written to the local data cache module via an internal link.

6. The data processing system according to claim 1, characterized in that, The data migration module includes: A bus interconnect module is used to connect the local data cache module and the external destination memory controller; An external destination memory controller is used to access the local data cache module through the bus interconnect module, read the monitoring data from the monitoring cache module, obtain the corresponding target data from the local data cache module according to the data length of the target data represented by the monitoring data, and move the target data to the external destination memory.

7. The data processing system according to claim 1, characterized in that, The interrupt generation module is also used for: Receive the interrupt signal sent by the data sending end; Monitor the target data writing progress of the local data cache module; Based on the timing of the interrupt signal reception and the target data writing progress of the local data cache module, determine whether the preset relocation trigger condition is met. If the preset transfer triggering conditions are met, a trigger signal is sent to the data transfer module to inform the data transfer module that the preset transfer triggering conditions are met.

8. The data processing system according to claim 7, characterized in that, The interrupt generation module is specifically used for: If no interrupt signal is received before the target data has been completely written to the local data cache module, when the interrupt signal is received, it is determined that the preset relocation trigger condition is met.

9. The data processing system according to claim 7, characterized in that, The interrupt generation module is specifically used for: If the target data has not yet been written to the local data cache module, but the interrupt signal is received, the preset relocation trigger condition is determined to be met when the target data is fully written to the local data cache module.

10. The data processing system according to claim 7, characterized in that, The interrupt generation module is specifically used for: When the target data is being written to the local data cache module, but an interrupt signal is received, it is determined that the preset relocation trigger condition is currently met.

11. The data processing system according to claim 1, characterized in that, The data transfer module is also used for: The relocation delay of the target data is determined based on the data length of the target data.

12. The data processing system according to claim 11, characterized in that, The interrupt generation module is used for: A target interrupt signal is generated based on the interrupt signal generation delay represented by the monitoring data and the target data transfer delay.

13. The data processing system according to claim 1, characterized in that, The core controller is specifically used for: In response to the target interrupt signal, an access request is initiated to the external destination memory controller via the bus interconnect module, so as to read the target data from the external destination memory through the external destination memory controller; Based on the reading results of the target data, the prototype verification result corresponding to the verification module is determined.

14. A data processing method, applied to the data sending end of the data processing system as described in any one of claims 1 to 13, characterized in that, The method includes: Send the target data to the data receiving end; An interrupt signal is generated after the target data has been sent. During the process of sending target data to the data receiving end and generating an interrupt signal, monitoring data is acquired; The monitoring data is sent to the data receiving end; Specifically, the data receiving end caches the monitoring data in the monitoring cache module and writes the target data to the local data cache module. When a preset relocation trigger condition is met, the data receiving end reads the monitoring data from the monitoring cache module, obtains the corresponding target data from the local data cache module according to the data length of the target data represented by the monitoring data, and relocates the target data to an external destination memory. After the target data is relocated to the external destination memory, the data receiving end reads the monitoring data from the monitoring cache module, generates a target interrupt signal according to the interrupt signal generation delay represented by the monitoring data, and sends the target interrupt signal to the core controller, so that the core controller responds to the target interrupt signal and reads the target data from the external destination memory.

15. A data processing method, applied to the data receiving end of the data processing system as described in any one of claims 1 to 13, characterized in that, The method includes: The system acquires target data and monitoring data sent by the data sender; wherein, during the process of sending target data to the data receiver and generating an interrupt signal, the data sender acquires monitoring data and sends the monitoring data to the data receiver. The monitoring data is cached in the monitoring cache module; The target data is cached in the local data cache module; When the preset relocation trigger condition is met, the monitoring data is read from the monitoring cache module; According to the data length of the target data represented by the monitoring data, the corresponding target data is obtained from the local data cache module, and the target data is moved to an external destination storage; After the target data is moved to the external destination memory, a target interrupt signal is generated according to the interrupt signal generated by the monitoring data, and the target interrupt signal is sent to the core controller so that the core controller can read the target data from the external destination memory in response to the target interrupt signal.

16. A data processing apparatus, applied to the data transmission end of a data processing system as described in any one of claims 1 to 13, characterized in that, The device includes: The first sending module is used to send target data to the data receiving end; The generation module is used to generate an interrupt signal after the target data has been sent. The first acquisition module is used to acquire monitoring data during the process of sending target data to the data receiving end and generating an interrupt signal; The second sending module is used to send the monitoring data to the data receiving end; Specifically, the data receiving end caches the monitoring data in the monitoring cache module and writes the target data to the local data cache module. When a preset relocation trigger condition is met, the data receiving end reads the monitoring data from the monitoring cache module, obtains the corresponding target data from the local data cache module according to the data length of the target data represented by the monitoring data, and relocates the target data to an external destination memory. After the target data is relocated to the external destination memory, the data receiving end reads the monitoring data from the monitoring cache module, generates a target interrupt signal according to the interrupt signal generation delay represented by the monitoring data, and sends the target interrupt signal to the core controller, so that the core controller responds to the target interrupt signal and reads the target data from the external destination memory.

17. A data processing apparatus, applied to the data receiving end of a data processing system as described in any one of claims 1 to 13, characterized in that, The device includes: The second acquisition module is used to acquire target data and monitoring data sent by the data sending end; wherein, during the process of sending target data to the data receiving end and generating an interrupt signal, the data sending end acquires monitoring data and sends the monitoring data to the data receiving end; The first caching module is used to cache the monitoring data to the monitoring caching module; The second caching module is used to cache the target data to the local data caching module; The reading module is used to read the monitoring data from the monitoring cache module when the preset relocation trigger condition is met; The transfer module is used to obtain the corresponding target data from the local data cache module according to the data length of the target data represented by the monitoring data, and transfer the target data to an external destination storage; An interrupt module is used to generate a target interrupt signal after the target data is moved to an external destination memory, based on the interrupt signal represented by the monitoring data, generate a delay, and send the target interrupt signal to the core controller, so that the core controller responds to the target interrupt signal and reads the target data from the external destination memory.

18. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor for executing the computer program to implement the steps of the data processing method as described in claim 14 or 15.

19. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the steps of the data processing method as described in claim 14 or 15.

20. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the data processing method as described in claim 14 or 15.

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