A flash memory management method and apparatus based on a state machine

Abstract

This application discloses a flash memory management method and apparatus based on a state machine. The method first divides the atomic operations of the flash memory into multiple flash memory states, and configures a state machine and a variable set for each flash memory corresponding to a chip select (CE) signal. This variable set includes first, second, third, and fourth variables. After receiving a flash memory operation task and obtaining the corresponding CE, physical plane group, and valid block distribution information, the state transition type is determined based on the first and second variables. The task operation type is then determined based on the transition type, plane group, block distribution information, the third variable, and the flash memory operation requirements. The operation type is assigned to the fourth variable, and the flash memory controller is configured and controlled to send atomic operation commands to the flash memory based on the fourth variable. This application ensures that all operations performed by the controller on the flash memory comply with the flash memory operation requirements, while simultaneously achieving complete independence of the operations corresponding to each chip select signal in a multi-CE flash memory system, fully guaranteeing the stability of flash memory operation and the performance of the multi-channel system.

Description

Technical Field

[0001] This application relates to, but is not limited to, the field of flash memory management, and particularly to a flash memory management method and apparatus based on a state machine. Background Technology

[0002] The firmware of storage products must adhere to the specifications in the flash memory datasheet when sending flash memory timings and commands via the controller. Otherwise, flash memory malfunctions and unpredictable errors may occur. Therefore, the firmware needs a mechanism to uniformly manage all atomic operations sent by the controller to the flash memory, ensuring that all operations comply with the flash memory datasheet requirements. Operations between the channels corresponding to chip enable must remain completely independent, without any mutual interference, thereby maximizing the optimal performance of multi-channel flash memory (i.e., multi-chip select flash memory). Existing technologies typically encapsulate various flash memory atomic operations independently, forming corresponding interfaces for the flash memory conversion layer to call. The physical layer then combines the input parameters and multiple judgment conditions to ultimately determine the timing of the atomic operation commands sent by the controller to the flash memory.

[0003] However, this method has the following drawbacks: when the flash memory malfunctions, the existing technology only records the relevant information of the current operation, making subsequent analysis of the problem difficult; the existing technology cannot make the operations between multi-channel flash memory completely independent, and if different channels call the same interface, coupling may occur, thus failing to fully utilize the optimal performance of multi-channel flash memory. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0005] This application provides a state machine-based flash memory management method and apparatus, which can ensure that all operations of the controller on the flash memory meet the flash memory operation requirements, and at the same time realize the complete independence of the operations corresponding to each chip select signal in a multi-chip select signal flash memory system, thus fully guaranteeing the stability of flash memory operation and the performance of multi-channel systems.

[0006] In a first aspect, embodiments of this application provide a flash memory management method based on a state machine, comprising: dividing different atomic operations of flash memory into multiple flash memory states; configuring an independent state machine and variable set for each flash memory corresponding to a chip select signal (CE), the variable set including a first variable for recording the current flash memory state, a second variable for recording the previous flash memory state, a third variable for recording the previous task information, and a fourth variable for recording the current operation type; receiving a current flash memory operation task and obtaining the CE, target physical plane group, and valid block distribution information corresponding to the current flash memory operation task; determining a state transition type through the state machine based on the first and second variables, and determining an operation type matching the task based on the state transition type, target physical plane group, valid block distribution information, the third variable of the CE corresponding to the current flash memory operation task, and flash memory-related operation requirements; assigning the operation type matching the task to the fourth variable, and configuring a flash memory controller according to the operation type recorded in the fourth variable, and controlling the flash memory controller to send atomic operation commands that meet timing requirements to the flash memory corresponding to the CE.

[0007] In conjunction with the first aspect, in one embodiment of this application, the previous task information recorded by the third variable includes at least one of the following: physical address, block type, first identifier, and second identifier; wherein the block type is an SLC block or a TLC block, the first identifier is used to record the flash target physical plane group occupied by the flash operation task, and the second identifier is used to record the physical plane subset in the target physical plane group where there are valid blocks.

[0008] In conjunction with the first aspect, in one embodiment of this application, the atomic operation includes at least one of single read, single program, read flash memory ID, obtain characteristic parameters, set characteristic parameters, single erase, batch erase, idle state, multi-plane read, multi-plane cache read, SLC multi-plane program, SLC multi-plane cache program, TLC multi-plane program, and TLC multi-plane cache program.

[0009] In conjunction with the first aspect, in one embodiment of this application, the method further includes: when the current flash memory operation task is a single read, single program, or single erase operation, determining the operation type matching the task based on the state switching type and flash memory-related operation requirements.

[0010] In conjunction with the first aspect, in one embodiment of this application, after sending the atomic operation command, the method further includes: detecting the condition of the flash memory medium through a state machine based on the return result of the flash memory controller, and obtaining a detection result; when the detection result indicates that there is an error in the flash memory medium, processing the error through the state machine, and obtaining a processing result; and sending the processing result to the flash memory conversion layer.

[0011] In conjunction with the first aspect, in one embodiment of this application, after the error is processed, the method further includes: updating the first variable to the current flash memory state and updating the second variable to the flash memory state before the current operation.

[0012] Secondly, embodiments of this application provide a state machine-based flash memory management device, applied to the aforementioned state machine-based flash memory management method. The flash memory management device includes: a state division module, used to divide different atomic operations of flash memory into multiple flash memory states; a configuration module, used to configure an independent state machine and variable set for each flash memory corresponding to a chip select signal (CE), the variable set including a first variable for recording the current flash memory state, a second variable for recording the previous flash memory state, a third variable for recording the previous task information, and a fourth variable for recording the current operation type; a task receiving module, used to receive the current flash memory operation task and obtain the CE, target physical plane group, and valid block distribution information corresponding to the current flash memory operation task; an operation type determination module, used to determine the state switching type through the state machine based on the first and second variables, and determine the operation type matching the task based on the state switching type, target physical plane group, valid block distribution information, the third variable of the CE corresponding to the current flash memory operation task, and flash memory-related operation requirements; and a control module, used to assign the operation type matching the task to the fourth variable, configure the flash memory controller according to the operation type recorded in the fourth variable, and control the flash memory controller to send atomic operation commands that meet timing requirements to the flash memory corresponding to the CE.

[0013] In conjunction with the second aspect, in one embodiment of this application, the previous task information recorded by the third variable includes physical address, block type, first identifier and second identifier, wherein the block type is an SLC block or a TLC block.

[0014] In conjunction with the second aspect, in one embodiment of this application, the control module is further configured to determine the variables that need to be called for the current operation type according to timing requirements, wherein single read, single program, and single erase operations do not require calling the first identifier and the second identifier.

[0015] In conjunction with the second aspect, in one embodiment of this application, the flash memory management device further includes an error handling module for detecting flash memory media errors via a state machine; when an error is detected, the state machine processes the error according to the error type and sends the processing result to the flash memory conversion layer.

[0016] This application provides a flash memory management method and device based on a state machine. In this method, different atomic operations of the flash memory are first divided into multiple flash memory states. An independent state machine and variable set are configured for each flash memory corresponding to a chip select signal (CE). The variable set includes a first variable for recording the current flash memory state, a second variable for recording the previous flash memory state, a third variable for recording the previous task information, and a fourth variable for recording the current operation type. After receiving the current flash memory operation task and obtaining the CE, target physical plane group, and valid block distribution information corresponding to the current flash memory operation task, the state machine determines the state transition type based on the first and second variables. Based on the state transition type, target physical plane group, valid block distribution information, the third variable of the CE corresponding to the current flash memory operation task, and flash memory-related operation requirements, the operation type matching the task is determined. Subsequently, the operation type matching the task is assigned to the fourth variable, and the flash memory controller is configured according to the operation type recorded in the fourth variable. The flash memory controller then sends atomic operation commands that meet timing requirements to the flash memory corresponding to the CE. This method divides flash memory into states based on atomic operations, configures the flash memory controller by combining state transition types and related variable information, and sends atomic operation commands that meet timing requirements. This ensures that the command timing during the transition between different atomic operations meets the relevant flash memory operation requirements, effectively preventing unexpected flash memory errors. By refining different atomic operations into multiple flash memory states and using a variable set configured for each chip select signal to record relevant information about the current and previous operations, the error timing can be roughly deduced when a flash memory anomaly occurs, facilitating problem localization and resolution. Configuring an independent state machine and variable set for each flash memory corresponding to a chip select signal allows for completely independent operations between flash memory instances with multiple chip select signals, ensuring that operations corresponding to each chip select signal do not affect each other and fully leveraging the optimal performance of multi-chip select flash memory. Attached Figure Description

[0017] Figure 1 This is a flowchart of a state machine-based flash memory management method provided in an embodiment of this application; Figure 2 This is a flowchart of the flash memory management method provided in the embodiments of this application; Figure 3 This is a module diagram of a state machine-based flash memory management method device provided in an embodiment of this application. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0019] It should be noted that although the flowchart shows a logical order, in some cases, the steps shown or described may be performed in a different order than that shown in the flowchart. The terms "first," "second," etc., used in the specification, claims, and the aforementioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the structures, proportions, sizes, etc., depicted in the drawings are only used to complement the content disclosed in the specification for those skilled in the art to understand and read, and are not intended to limit the implementation conditions of this application. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to size, without affecting the effects and purposes achieved by this application, should still fall within the scope of the technical content disclosed in this application. Similarly, the terms such as "upper," "lower," "left," "right," "middle," and "one" used in this specification are only for clarity of description and are not used to limit the scope of implementation of this application. Changes or adjustments in their relative relationships, without substantially altering the technical content, should also be considered within the scope of implementation of this application.

[0020] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0021] The firmware of storage products must adhere to the flash memory timing and commands sent by the controller, as specified in the flash memory datasheet. Failure to do so can cause flash memory malfunctions and unpredictable errors. Therefore, the firmware needs a mechanism to manage all atomic operations sent by the controller to the flash memory, ensuring that all operations comply with the flash memory datasheet requirements. The operations of each channel corresponding to the Chip Enable (CE) signal (also known as the chip select signal) remain completely independent, without any mutual interference, thus maximizing the performance of multi-channel flash memory. The backend module of the firmware is typically divided into an upper Flash Translation Layer (FTL) and a lower Physical Layer. The FTL is primarily responsible for executing strategies and managing mapping tables, while the Physical Layer is responsible for operating the flash memory according to the tasks issued by the FTL. Existing technologies typically encapsulate various flash memory atomic operations independently, forming corresponding interfaces for the FTL to call. The Physical Layer then combines the input parameters and multiple judgment conditions to ultimately determine the timing of the atomic operation commands sent by the controller to the flash memory.

[0022] However, this method has the following drawbacks: (1) When a flash memory malfunctions, existing technology only records the relevant information of the current operation, making subsequent analysis of the problem difficult; (2) Existing technology cannot achieve complete independence of operation between multi-channel flash memory. If different channels call the same interface, coupling may occur, thus failing to fully utilize the best performance of multi-channel flash memory.

[0023] In view of this, embodiments of this application provide a flash memory management method and flash memory management device based on a state machine. In this method, different atomic operations of the flash memory are first divided into multiple flash memory states, and an independent state machine and variable set are configured for each flash memory corresponding to a chip select signal (CE). The variable set includes a first variable for recording the current flash memory state, a second variable for recording the previous flash memory state, a third variable for recording the previous task information, and a fourth variable for recording the current operation type. After receiving the current flash memory operation task and obtaining the CE, target physical plane group, and valid block distribution information corresponding to the current flash memory operation task, the state machine can determine the state transition type based on the first and second variables. Based on the state transition type, target physical plane group, valid block distribution information, the third variable of the CE corresponding to the current flash memory operation task, and flash memory-related operation requirements, the operation type matching the task is determined. Subsequently, the operation type matching the task is assigned to the fourth variable, and the flash memory controller is configured according to the operation type recorded in the fourth variable. Then, the flash memory controller is controlled to send atomic operation commands that meet timing requirements to the flash memory corresponding to the CE. This method divides flash memory into states based on atomic operations, configures the flash memory controller by combining state transition types and related variable information, and sends atomic operation commands that meet timing requirements. This ensures that the command timing during the transition between different atomic operations meets the relevant flash memory operation requirements, effectively preventing unexpected flash memory errors. By refining different atomic operations into multiple flash memory states and using a variable set configured for each chip select signal to record relevant information about the current and previous operations, the error timing can be roughly deduced when a flash memory anomaly occurs, facilitating problem localization and resolution. Configuring an independent state machine and variable set for each flash memory corresponding to a chip select signal allows for completely independent operations between flash memory instances with multiple chip select signals, ensuring that operations corresponding to each chip select signal do not affect each other and fully leveraging the optimal performance of multi-chip select flash memory.

[0024] The embodiments of this application will be further described below with reference to the accompanying drawings.

[0025] Reference Figure 1 , Figure 1 This is a flowchart of a state machine-based flash memory management method provided in an embodiment of this application. The process may specifically include, but is not limited to, steps 110 to 150.

[0026] Step 110: Divide the different atomic operations of the flash memory into multiple flash memory states; Step 120: Configure an independent state machine and variable set for each flash memory corresponding to the chip select signal CE. The variable set includes a first variable for recording the current flash memory state, a second variable for recording the previous flash memory state, a third variable for recording the previous task information, and a fourth variable for recording the current operation type. Step 130: Receive the current flash memory operation task and obtain the CE, target physical plane group and valid block distribution information corresponding to the current flash memory operation task; Step 140: Determine the state transition type using the state machine based on the first and second variables, and determine the operation type that matches the task based on the state transition type, the target physical plane group, the effective block distribution information, the third variable of the CE corresponding to the current flash memory operation task, and the flash memory-related operation requirements. Step 150: Assign the operation type that matches the task to the fourth variable, and configure the flash controller according to the operation type recorded in the fourth variable, and control the flash controller to send atomic operation commands that meet the timing requirements to the flash memory of the corresponding CE.

[0027] Steps 110 to 150 will be described in detail below.

[0028] In a feasible embodiment, in step 110, the atomic operation of flash memory refers to the smallest indivisible flash memory operation unit, mainly including single read, single program, read flash ID, obtain characteristic parameters, set characteristic parameters, single erase, batch erase, idle state, multi-plane read, multi-plane cache read, SLC multi-plane programming, SLC multi-plane cache programming, TLC multi-plane programming, and TLC multi-plane cache programming. In the process of dividing different atomic operations of flash memory into multiple flash memory states, operations such as single read, single program, read flash ID, obtain characteristic parameters, set characteristic parameters, single erase, batch erase, and idle state, which do not need to be combined with the next operation to form a complete command sequence, can all be classified as the first type of flash memory state; multi-plane read and multi-plane cache read can be classified as the second type of flash memory state; SLC multi-plane programming and SLC multi-plane cache programming can be classified as the third type of flash memory state; and TLC multi-plane programming and TLC multi-plane cache programming can be classified as the fourth type of flash memory state. In addition, read operations that encounter error check and correction errors (eccerror), write operations that fail, and erase operations that fail are classified as the fifth type of flash memory state.

[0029] In one feasible embodiment, a chip select signal is a control signal used to select a target flash memory chip in a storage system composed of multiple flash memory chips. Changes in the signal level can activate or deactivate a specific flash memory chip, thereby distinguishing different flash memory chips and allowing for independent operation. Configuring an independent state machine and variable set for each flash memory chip corresponding to a chip select signal means configuring a dedicated state machine and a variable set containing operational status, task information, etc., for each flash memory chip associated with a chip select signal in the storage system. The state machines and variable sets corresponding to different chip select signals are independent of each other and operate independently, ensuring the independence of the operation of each flash memory chip.

[0030] In a feasible embodiment, the first variable is mainly used to record the current state of the flash memory corresponding to each chip select signal, the second variable is mainly used to record the previous state of the flash memory corresponding to each chip select signal, the third variable is mainly used to record the detailed information of the previous task of the flash memory corresponding to each chip select signal, and the fourth variable is mainly used to record the current operation of the flash memory corresponding to each chip select signal.

[0031] In a feasible embodiment, the initial values ​​of both the first variable and the second variable can be set to the first flash memory state among a variety of flash memory states.

[0032] In a feasible embodiment, the previous task information recorded by the third variable includes at least one of the following: physical address, block type, first identifier, and second identifier. The block type is either an SLC block or a TLC block, the first identifier can be used to record the flash target physical plane group occupied by the current flash operation task, and the second identifier can be used to record a subset of physical planes in the target physical plane group that contain valid blocks.

[0033] In one feasible embodiment, the target physical plane group refers to the physical plane locations used by the current task. Assuming the flash memory has four planes, and the current task uses plane0 and plane2, then the value of the first identifier can be set to 0x5. If all four planes are used, then the value of the first identifier is 0xF, and so on.

[0034] In one feasible embodiment, the valid block distribution information refers to the location of good blocks in the multi-plane used by the current task. Assuming the flash memory has 4 planes, and plane2 in the current multi-plane is an unusable bad block, while plane0, plane1, and plane3 are all good blocks, then the value of the second identifier can be set to 0xB. If all 4 planes are good blocks, then the value of the second identifier can be set to 0xF.

[0035] In a feasible embodiment, in step 130, after receiving the current flash memory operation task, the core execution parameters corresponding to the task can be extracted synchronously. This involves obtaining the CE pointed to by the task, determining the target physical plane group required by the task, and collecting the effective block distribution information involved in the current task. After obtaining these parameters, the system can enter the state machine dedicated to the CE corresponding to the task and proceed with subsequent operation processes.

[0036] In a feasible embodiment, different state transition types can be obtained by combining the first, second, third, fourth, and fifth flash memory states in pairs. These state transition types are categorized based on the combination of the current state and the previous state, resulting in 20 valid state transition types. In step 140, the state machine can combine the current flash memory state recorded by the first variable with the previous flash memory state recorded by the second variable to determine the state transition type corresponding to the current flash memory operation task.

[0037] It is understandable that the requirements for flash memory operations can be defined by the flash memory specification. The specification usually indicates the timing requirements or command requirements when switching between different operations. If the requirements are not followed, the flash memory may produce unexpected errors, including but not limited to: (1) the flash memory hangs and does not respond to any commands sent by the controller. (2) when querying the flash memory status, the obtained status value is invalid, affecting the firmware's judgment. (3) the flash memory RB line is abnormal, the RB line does not move, the busy time is too long or too short. At this time, there may be problems with the data transmission inside the flash memory, which will eventually manifest as incomplete data or data errors.

[0038] Furthermore, the flash memory specification defines fixed timing rules for all atomic operations on the flash memory, and the controller must operate the flash memory according to these specified timing rules. For example: (1) The “multiplane cache read” specifies that the first group of atomic operations sent is “00H-ADDR1-32H, 00H-ADDR2-30H”, which is used to pre-read ADDR1 and ADDR2 of the flash memory. The second group of atomic operations sent is “00H-ADDR3-32H, 00H-ADDR4-31H”, which is used to pre-read ADDR3 and ADDR4 of the flash memory. The third group of atomic operations sent is “06H-ADDR1-E0H-DATA, 06H-ADDR2-E0H-DATA”, which is used to fetch data from ADDR1 and ADDR2 of the flash memory. Subsequent atomic operations are sent in the same manner. If you want to end the “multiplane cache read” and fetch the data from the last group of addresses, the atomic operations that need to be sent are: “3FH, 06H-ADDRn-E0H-DATA, 06H-ADDR(n+1)-E0H-DATA”.

[0039] (2) The “multi-plane cache program” specifies that the first group of atomic operations sent is “80H-ADDR1-DATA-11H, 80H-ADDR2-DATA-15H”. The second group of atomic operations sent is “80H-ADDR2-DATA-11H, 80H-ADDR3-DATA-15H”, and then “70H” is sent to query the write results of ADDR1 and ADDR2. Subsequent atomic operations follow the same pattern.

[0040] In a feasible embodiment, after determining the state transition type, the firmware can further determine the operation type matching the task based on the state transition type, the target physical plane group, the effective block distribution information, and the third variable of the CE corresponding to the current flash memory operation task, combined with the requirements of the relevant operations in the flash memory specification. The operation type corresponds to the sub-timing of the command timing in the flash memory specification.

[0041] It should be noted that the operation type recorded by the fourth variable can determine the timing of the flash commands that the flash controller will send subsequently. The firmware can determine the configuration scheme of the flash controller based on the operation type obtained from the state machine.

[0042] In a feasible embodiment, in step 150, after determining the operation type matching the task, the operation type can be further assigned to a fourth variable, and the flash controller can be configured according to the operation type recorded in the fourth variable. This allows the flash controller to send atomic operation commands that meet the specification timing requirements to the corresponding CE flash memory. For example, in a multi-plane read operation, the flash memory specification requires that the plane addresses must increment sequentially, i.e., the operation instructions for plane0 are sent first, then plane1, and so on. The specification also stipulates that the page addresses of all plane operations in the same multi-plane read must be the same. Based on these requirements, the state machine can determine whether the current multi-plane read task meets all the above requirements based on the state transition type, the first identifier, and the second identifier, and then determine the value of the fourth variable, thereby controlling the controller to send a sub-timing segment of the multi-plane read command timing sequence.

[0043] In a feasible embodiment, the operation type values ​​and their corresponding flash memory commands are as follows: NEW_MULTI_READ corresponds to multi-plane read prefetching, MULTI_CACHE_READ corresponds to multi-plane cache read prefetching, MULTI_READ_DATA_OUT corresponds to multi-plane read data retrieval, NONE corresponds to no operation, SLC_MULTI_NORMAL_WRITE corresponds to single-level cell multi-plane programming, and so on. All operation types are decomposed according to the command timing sequence in the flash memory datasheet. One operation type corresponds to a sub-timing sequence of a command timing sequence. This is because a complete command timing sequence often needs to be decomposed into multiple independent sub-timing sequences, and the overall operation process is completed by combining these sub-timing sequences.

[0044] It is worth noting that not all flash memory operations use all variables. Which variables need to be called in the decision-making process is determined by the timing requirements specified in the flash memory datasheet.

[0045] In a feasible embodiment, when the current flash memory operation task is any one of a single read, single program, and single erase operation, it is not necessary to determine the specific values ​​of the first and second identifiers. The operation type matching the current task can be determined simply by combining the state switching type and the flash memory-related operation requirements.

[0046] In a feasible embodiment, the physical address, block type, first identifier, second identifier, and other relevant information of the current task can be fully recorded in the third variable of the corresponding chip select signal, providing data support for judging the state switching type and determining the operation type of the next flash memory operation task.

[0047] It should be noted that each CE is equipped with a dedicated and independent state machine mechanism. Various variables used to record operation status and task information are also stored and maintained separately by their corresponding chip select signals, with no coupling between different chip select signals. Assuming there are two chip select signals, CE0 and CE1, in the current storage system, where CE0 has an incomplete task, the firmware will not incorporate any information related to CE0 into its judgment when performing operations on CE1. This ensures that the operation process corresponding to each CE is completely independent.

[0048] Understandably, in existing technologies, all atomic operations on flash memory are determined by the upper-layer flash translation layer. Even if errors occur, such as read operation error verification and correction errors, write operation failures, or erase operation failures, the physical layer must feed back the error information to the flash translation layer, which then decides when to handle these errors. This error handling efficiency is clearly insufficient. In this embodiment, after sending an atomic operation command to the corresponding CE's flash memory, a state machine can detect the flash memory medium's condition based on the flash memory controller's return result, obtaining the detection result. When the detection result indicates an error in the flash memory medium, the state machine processes the error to obtain the processing result, which is then sent to the flash translation layer. Specifically, an independent state machine configured for each CE by the physical layer can be used to complete the entire process control and error handling of flash memory atomic operations. All errors caused by the flash memory medium itself can be handled autonomously by the physical layer's state machine, without the flash translation layer's intervention. After the physical layer completes the error handling, it feeds back the final execution result of the operation to the flash translation layer. The specific steps include: obtaining and analyzing the return results of the flash memory controller through the state machine of the physical layer to detect the operation of the flash memory medium and obtain the corresponding detection results; when the detection results show that there is an error in the flash memory medium, the preset error handling process is started through the state machine to handle various media errors in a targeted manner and obtain the corresponding processing results; finally, the processing results are synchronously sent to the flash memory conversion layer to complete the entire error handling closed loop.

[0049] In one feasible embodiment, when an error check and correction occurs during a read operation corresponding to CE0, the state machine first switches the flash memory state corresponding to CE0 to an error state to indicate that the chip select signal is in the error handling stage. Then, a reread mechanism is initiated to carry out targeted processing. After processing is completed, the final processing result is fed back to the flash memory translation layer. It should be noted that during this process, the normal operation of all other CEs besides CE0 is unaffected, and they can still independently execute their respective flash memory operation tasks.

[0050] In a feasible embodiment, after error handling is completed, the first and second variables can be updated. The specific update logic is as follows: the first variable is updated to the current flash memory state, and the second variable is updated to the flash memory state before the current operation, thus completing the iteration of variable states. This ensures that when the next flash memory operation task is executed, the state machine can determine the state transition type based on the latest variable data, ensuring the temporal continuity and logical accuracy of the entire operation process.

[0051] The following describes this method using a specific processing flow.

[0052] like Figure 2 As shown, upon receiving a new flash memory operation task, the current flash memory state of the CE corresponding to the task can be obtained first, and then the CE-specific state machine corresponding to the task can be entered. The state machine can determine the corresponding state transition type by combining the current flash memory state recorded in the first variable and the previous flash memory state recorded in the second variable. Based on this, the state machine can further determine the matching operation type and assign it to the fourth variable based on the state transition type, the first identifier, the second identifier, and the third variable of the chip select signal corresponding to the current task, combined with the requirements of the flash memory specification for related operations. The firmware can determine the atomic operation instruction that the flash memory controller will send to the corresponding flash memory based on the operation type recorded in the fourth variable. After the instruction is sent, the relevant information of the current task can be recorded in the third variable of the corresponding chip select signal to provide data support for the judgment of the next task.

[0053] See Figure 3 , Figure 3 This is a block diagram of a state machine-based flash memory management device provided in an embodiment of this application. The device 300 is applicable to the aforementioned state machine-based flash memory management method. The device 300 includes: The state division module 310 is used to divide different atomic operations of flash memory into multiple flash memory states; The configuration module 320 is used to configure an independent state machine and variable set for each flash memory corresponding to the chip select signal CE. The variable set includes a first variable for recording the current flash memory state, a second variable for recording the previous flash memory state, a third variable for recording the previous task information, and a fourth variable for recording the current operation type. The task receiving module 330 is used to receive the current flash memory operation task and obtain the CE, target physical plane group and effective block distribution information corresponding to the current flash memory operation task; The operation type determination module 340 is used to determine the state transition type through the state machine based on the first and second variables, and to determine the operation type that matches the task based on the state transition type, the target physical plane group, the effective block distribution information, the third variable of the CE corresponding to the current flash memory operation task, and the flash memory related operation requirements. The control module 350 is used to assign the operation type matching the task to the fourth variable, configure the flash controller according to the operation type recorded in the fourth variable, and control the flash controller to send atomic operation commands that meet the timing requirements to the flash memory of the corresponding CE.

[0054] In one feasible embodiment, the previous task information recorded by the third variable includes physical address, block type, first identifier and second identifier, and the block type is SLC block or TLC block.

[0055] In one feasible embodiment, the control module is also used to determine the variables that need to be called for the current operation type according to timing requirements, wherein single read, single program, and single erase operations do not require calling the first and second identifiers.

[0056] In one feasible embodiment, the flash memory management device further includes an error handling module for detecting flash memory media errors via a state machine; when an error is detected, the state machine processes the error according to the error type and sends the processing result to the flash memory conversion layer.

[0057] It should be noted that device 300 is applicable to the state machine-based flash memory management method described above. In other words, the functions implemented by each module in the device are similar to the execution logic and technical effects of steps 110 to 150 and the corresponding stages in related embodiments. For details regarding the specific operational logic and implementation principles of each module, please refer to the detailed description above; further elaboration is not provided here.

[0058] This application also discloses an electronic device, which includes a processor, a memory, and a computer program stored in the memory and executable by the processor. When the computer program is executed by the processor, it implements the state machine-based flash memory management method described above.

[0059] This application also discloses a computer-readable storage medium storing a processor-executable program, which, when executed by a processor, is used to perform the state machine-based flash memory management method described above.

[0060] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A flash memory management method based on a state machine, characterized in that, include: Divide different atomic operations of flash memory into multiple flash memory states; Each flash memory corresponding to the chip select signal CE is configured with an independent state machine and a set of variables. The set of variables includes a first variable for recording the current flash memory state, a second variable for recording the previous flash memory state, a third variable for recording the previous task information, and a fourth variable for recording the current operation type. Receive the current flash memory operation task and obtain the CE, target physical plane group and effective block distribution information corresponding to the current flash memory operation task; The state machine determines the state transition type based on the first and second variables, and determines the operation type that matches the task based on the state transition type, the target physical plane group, the effective block distribution information, the third variable of the CE corresponding to the current flash memory operation task, and the flash memory related operation requirements. The operation type matching the task is assigned to the fourth variable, and the flash controller is configured according to the operation type recorded in the fourth variable. The flash controller is then controlled to send atomic operation commands that meet the timing requirements to the flash memory of the corresponding CE.

2. The flash memory management method based on a state machine according to claim 1, characterized in that, The information about the previous task recorded by the third variable includes at least one of the following: Physical address, block type, first identifier, second identifier; The block type is either an SLC block or a TLC block. The first identifier is used to record the flash target physical plane group occupied by the flash operation task, and the second identifier is used to record the physical plane subset in the target physical plane group that contains valid blocks.

3. The flash memory management method based on a state machine according to claim 1, characterized in that, The atomic operations include at least one of the following: single read, single program, read flash ID, get characteristic parameters, set characteristic parameters, single erase, batch erase, idle state, multi-plane read, multi-plane cache read, SLC multi-plane program, SLC multi-plane cache program, TLC multi-plane program, and TLC multi-plane cache program.

4. The flash memory management method based on a state machine according to claim 1, characterized in that, The method further includes: When the current flash memory operation task is a single read, single program, or single erase operation, the operation type that matches the task is determined based on the state switching type and the flash memory-related operation requirements.

5. The flash memory management method based on a state machine according to claim 1, characterized in that, After sending the atomic operation command, the method further includes: The state machine detects the condition of the flash memory medium based on the return result from the flash memory controller, and obtains the detection result. When the detection result indicates that there is an error in the flash memory medium, the error is processed by the state machine to obtain the processing result; The processing result is sent to the flash memory conversion layer.

6. The flash memory management method based on a state machine according to claim 5, characterized in that, After error handling is complete, the method further includes: Update the first variable to the current flash memory state, and update the second variable to the flash memory state before this operation.

7. A state machine-based flash memory management device, characterized in that, The flash memory management device, applied to the state machine-based flash memory management method as described in any one of claims 1-6, comprises: The state partitioning module is used to divide different atomic operations of flash memory into multiple flash memory states; The configuration module is used to configure an independent state machine and variable set for each flash memory corresponding to the chip select signal CE. The variable set includes a first variable for recording the current flash memory state, a second variable for recording the previous flash memory state, a third variable for recording the previous task information, and a fourth variable for recording the current operation type. The task receiving module is used to receive the current flash memory operation task and obtain the CE, target physical plane group and effective block distribution information corresponding to the current flash memory operation task; The operation type determination module is used to determine the state transition type through a state machine based on the first variable and the second variable, and to determine the operation type that matches the task based on the state transition type, the target physical plane group, the effective block distribution information, the third variable of the CE corresponding to the current flash memory operation task, and the flash memory related operation requirements. The control module is used to assign the operation type matching the task to a fourth variable, configure the flash controller according to the operation type recorded in the fourth variable, and control the flash controller to send atomic operation commands that meet the timing requirements to the flash memory of the corresponding CE.

8. The state machine-based flash memory management device according to claim 7, characterized in that, The third variable records the previous task information, including physical address, block type, first identifier and second identifier, wherein the block type is SLC block or TLC block.

9. The state machine-based flash memory management device according to claim 7, characterized in that, The control module is also used to determine the variables that need to be called for the current operation type according to the timing requirements, wherein single read, single program, and single erase operations do not need to call the first and second identifiers.

10. The state machine-based flash memory management device according to claim 7, characterized in that, The flash memory management device also includes an error handling module for detecting flash memory media errors via a state machine; When an error is detected, the state machine processes it according to the error type and sends the processing result to the flash memory conversion layer.

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