A method for migrating data of a NAND flash memory

Abstract

This application relates to the fields of 3D flash memory, vertical NAND, data migration, and particle swarm optimization (PSO) algorithms. Specifically, it relates to a NAND flash memory data migration method applicable to both 3D flash memory and vertical NAND flash memory storage. The method includes the following steps: Step 1: An external calculator obtains the physical address of the smallest physical page and the physical address of the smallest physical block in the NAND memory, and establishes a simulation address table; Step 2: The control instructions of the controller in the NAND memory are monitored. These control instructions include read instructions for physical pages, write instructions for physical pages, and erase instructions for physical blocks. This application, through the powerful processing capabilities of an external calculator, completely solves the bottleneck of severely limited computing power of the built-in controller in NAND flash memory, enabling real-time execution of complex particle swarm optimization algorithms. It performs global, dynamic, and multi-objective collaborative optimization on the simulated NAND physical state, generating high-precision optimal balance instructions.

Description

Technical Field

[0001] This application relates to the fields of three-dimensional flash memory, vertical NAND, storage, data migration, and particle swarm optimization, and more specifically, to a NAND flash memory data migration method. Background Technology

[0002] The content in this section provides only background information related to this application and may not constitute prior art.

[0003] NAND flash memory has become a core medium in modern storage systems due to its advantages such as non-volatility, high density, and relatively low cost. The physical characteristics of NAND flash memory necessitate periodic data migration operations. To efficiently complete these migration tasks, modern NAND flash memory systems typically employ a hybrid migration strategy, combining internal and external migration. Internal migration is performed by a finite state machine or simple controller integrated within the NAND flash memory chip. Data moves between packets within the chip without passing through an external controller or channel bus. External migration, on the other hand, is initiated and executed by an external controller. Data is read from the controller's cache (DRAM) via the channel bus, processed (e.g., error correction, reassembly), and then written back to the NAND (which may be at different locations on the same chip or on other chips). Hybrid migration aims to leverage the low latency and low bus consumption advantages of internal migration while relying on external migration to handle more complex tasks or those requiring controller resources, thus balancing performance, lifespan, and system overhead.

[0004] When implementing a hybrid migration strategy, it is necessary to find the optimal ratio of internal to external migration to maximize overall system benefits (such as performance, lifetime, and power consumption). In existing technologies, this allocation typically relies on preset thresholds. These include, for example, the number of erase / write operations per block / page, the number of read operations, the raw bit error rate (RBER) or the number of bits requiring error correction, the proportion of invalid data, and the number of available free blocks. The system monitors these parameters and triggers corresponding migration operations (internal or external) when they reach preset thresholds, or dynamically adjusts the triggering frequency or ratio of internal and external migrations based on different threshold ranges.

[0005] The threshold-based hybrid migration allocation method described above has significant limitations, stemming from the extremely limited computing and storage resources (computing power) available within NAND flash memory chips. The primary design goal of NAND chips is high-density data storage; their built-in controllers (typically simple state machines or microcontrollers) have limited computing power, and their on-chip cache (SRAM) capacity is extremely small (usually only a few KB to tens of KB). This strict computing power constraint forces the hybrid migration allocation algorithm to be designed to be extremely simple, typically only able to implement fixed thresholds or very limited linear / piecewise linear rules. This simplicity leads to low accuracy in allocation decisions.

[0006] Therefore, there is an urgent need for a more intelligent, accurate, and adaptive method for allocating the ratio of internal migration to external migration under the limited computing power constraints of NAND flash memory chips, in order to overcome the shortcomings of existing methods based on simple thresholds. Summary of the Invention

[0007] The summary section of this application is intended to provide a brief overview of the concepts, which will be described in detail in the detailed description section below. This summary section is not intended to identify key or essential features of the claimed technical solutions, nor is it intended to limit the scope of the claimed technical solutions.

[0008] Some embodiments of this application propose a NAND flash memory data migration method to solve the technical problems mentioned in the background section above.

[0009] As a first aspect of this application, some embodiments of this application provide a NAND flash memory data migration method, including the following steps: Step 1: Use an external calculator to obtain the physical address of the smallest physical page and the physical address of the smallest physical block in the NAND memory, and build a simulation address table; Step 2: Monitor the control commands of the controller in the NAND memory. The control commands include read commands for physical pages, write commands for physical pages, and erase commands for physical blocks. Monitor the address mapping table in the controller and obtain the mapping address update instruction for the source data in the address mapping table; Step 3: The external calculator simulates the physical state of the NAND memory in the simulation address table according to the control instructions and the mapped address update instructions; The physical status includes the proportion of valid information in each physical page, the number of times each physical block is erased, and the number of times each physical page is accessed; Step 4: Solve the physical state of the NAND memory using the particle swarm optimization algorithm to obtain the optimal balance instruction for the NAND memory; Among them, the particle swarm optimization algorithm aims to optimize the synchronous wear rate of each physical block, the remaining storage capacity of the NAND memory, the controller communication bandwidth utilization rate, and the bit error rate of information migration inside the NAND memory, and generates the best balanced instructions. Step 5: Periodically send optimal balancing instructions to the NAND memory. The NAND memory adjusts the internal data migration conditions, external data migration conditions, and physical block erasure order based on the optimal balancing instructions.

[0010] This application leverages the powerful processing capabilities of an external calculator to completely overcome the bottleneck of severely limited computing power in the built-in controller of NAND flash memory. It enables the real-time execution of complex particle swarm optimization algorithms to perform global, dynamic, and multi-objective collaborative optimization (synchronously optimizing physical block wear rate, remaining capacity, external bandwidth usage, and internal migration error rate) on the simulated NAND physical state (effective information ratio, erase count, access count). This generates high-precision optimal balancing instructions. These instructions dynamically guide the NAND to adjust internal migration conditions, erase order, hot data threshold, and external migration order, thereby significantly improving wear leveling to extend lifespan, optimizing bandwidth utilization to improve performance (reducing latency and increasing IOPS), reducing error risk to enhance reliability, and effectively improving overall storage efficiency. This overcomes the shortcomings of traditional built-in simple threshold methods, such as inaccurate allocation, poor adaptability, and low resource utilization efficiency due to insufficient computing power.

[0011] Furthermore, step 1 includes the following steps: Step 11: Obtain all physical pages in the NAND memory, and generate the physical address of each physical page based on its physical location; the physical address includes the wafer number, group number, block number, and page number; Step 12: For each physical page, generate a type label for the physical page, add the type label to the physical address, and generate a physical identifier for each physical page; Step 13: Obtain all physical blocks in the NAND memory, obtain the physical address of each physical block, and record the physical identifiers of all physical pages under each physical block; Step 14: Construct a simulation address table based on the physical identifiers of all physical pages under each physical block and the physical address of each physical block.

[0012] Furthermore, step 2 includes the following steps: Step 21: Monitor the controller's response to the host's control commands in real time to obtain the controller's read commands for physical pages, write commands for physical pages, and erase commands for physical blocks; Step 22: Monitor the address mapping table in the controller and obtain the mapping address update instruction of the source data in the address mapping table.

[0013] Furthermore, step 3 includes the following steps: Step 31: Construct a physical state table, which includes the physical state of each physical page; Physical states include blank state, valid state, and number of erases; Step 32: Construct a data status table, which includes the storage status of each piece of data; Storage status includes the data identifier, the current storage address of the data, and the number of times the data has been accessed; Step 33: Construct a data mapping table, which is used to map the mapping relationship between each element in the physical state table and each element in the data state table; Step 34: Extract the physical state of the NAND memory from the physical state table, data state table, and data mapping table.

[0014] The technical solution provided in this application constructs a physical state table (recording page-level blank / valid states and erase counts), a data state table (recording data identifiers, storage locations, and access frequency), and a data mapping table (precisely associating physical states with data states), which together constitute a high-fidelity NAND memory internal information migration model. This model not only provides a structured foundation for extracting physical states but also supports dynamic simulation of the data migration process directly on the model, thereby enabling pre-verification and optimization of the effects of different migration strategies.

[0015] Furthermore, step 4 includes the following steps: Step 41: Construct the basic model for data migration of NAND memory; Step 42: Solve the physical state of the NAND memory using the particle swarm optimization algorithm to generate balancing instructions; Step 43: Send a balancing command to the NAND memory and adjust the built-in parameters in the base model based on the balancing command; Step 44: NAND memory performs data migration based on the adjusted base model; The basic model includes: Data migration methods and conditions; Data migration methods include internal data migration and external data migration. Data migration conditions include a first migration condition for whether to perform data migration, a second migration condition for triggering internal data migration, and a third migration condition for triggering external data migration; Internal data migration methods include the order of source and target pages when performing internal data migration; External data migration methods include the order of source and target pages when performing external data migration; The balancing command specifies the numerical values ​​of various information items in the basic model.

[0016] The technical solution provided in this application establishes a clear and configurable data migration execution framework for NAND memory by constructing a basic model (clearly defining the data migration method, migration conditions, and source / target page order). This model entrusts the core decisions of the migration strategy (condition threshold setting and page migration order optimization) to a powerful external processor that dynamically calculates and generates balancing instructions through a particle swarm optimization algorithm to adjust the model parameters. The NAND internally only needs to efficiently monitor and respond to preset migration conditions. This decoupling of strategy decision-making and execution significantly improves wear leveling accuracy to extend lifespan, optimizes internal / external bandwidth utilization to improve overall performance, and greatly reduces the computational burden of real-time decision-making within the NAND.

[0017] Furthermore, the first migration conditions include: storage load limit threshold a1, storage minimum remaining value a2, and total valid pages to total invalid pages ratio threshold a3; The first migration condition is triggered when the memory meets the following conditions: current load is less than a1, remaining memory capacity is less than a2, and the ratio of total valid pages to total invalid pages is less than a3.

[0018] Furthermore, the second migration conditions include: the remaining threshold of controller transmission resources b1, the ratio of valid pages to invalid pages in the physical block where the source page is located b2, and the number of erases in the physical block where the source page is located b3; The second migration condition is triggered when the source page meets the following conditions: the controller transfer resources are higher than b1, the ratio of valid pages to invalid pages in the physical block where the source page is located is less than b2, and the number of erases in the physical block where the source page is located is less than b3. The third migration conditions include: the remaining threshold of controller transmission resources b1, the ratio of valid pages to invalid pages in the physical block where the source page is located b2, and the number of erases in the physical block where the source page is located b3; The third migration condition is triggered when the source page meets the following conditions: the controller transfer resources are less than b1, the ratio of valid pages to invalid pages in the physical block where the source page is located is less than b2, and the number of erases in the physical block where the source page is located is less than b3.

[0019] This application constructs a hierarchical and logically rigorous migration triggering mechanism by setting system-level thresholds (load limit, remaining capacity limit, effective / invalid page ratio threshold) for the first migration condition (whether to perform migration), and shared but differentiated thresholds (transmission resources, effective / invalid page ratio within the block, number of block erases) based on the source page physical block state and transmission resources for the second migration condition (triggering internal migration) and the third migration condition (triggering external migration). This mechanism accurately matches the core driving factors of different migration types (global decision, internal migration, external migration), ensuring that migration operations are efficiently triggered only when system resources allow and the target block state meets optimization requirements. This effectively avoids invalid or inefficient migrations, thereby significantly improving the execution efficiency of garbage collection and wear leveling, and optimizing the dynamic allocation of internal / external communication resources.

[0020] Furthermore, in step 41, the migration conditions are transformed into a logical chain, and the logical chain of the migration conditions is as follows: Condition 1: Data migration is triggered when the first migration condition is met; data migration is stopped when the first migration condition is not met. Condition 2: When condition 1 is met, traverse all physical pages that have already stored information and divide the physical pages into two categories: Category 1: Meets the second migration condition but does not meet the third migration condition; Category 2: Does not meet the second migration condition, but meets the third migration condition; For the first type of physical page, mark it as a source page and perform internal data migration; for the second type of physical page, mark it as a source page and perform external data migration. Data migration will stop if condition 1 is not met. In step 41, the data migration method is changed to source page sorting and target page sorting; Use all blank physical pages as target pages, and assign the target pages to the idle weight parameter. Arrange them in order as the target pages during data migration; Idle weight parameters Related to the number of erases on the physical block it belongs to; The first type of physical pages are assigned according to the first weight parameter. Arranged to serve as the source page order when performing internal data migration; The second type of physical pages are assigned according to the second weighting parameter. Arranged to serve as the source page order when performing external data migration; The first weighting parameter is related to the ratio of valid to invalid pages in the physical block where the source page is located, the number of times the physical block where the source page is located is erased, and the access density of the information stored in the source page; The second weighting parameter is related to the ratio of valid to invalid pages in the physical block where the source page is located, the number of erases in the physical block where the source page is located, and the access density of the information stored in the source page; ; ; ; ; Let represent the i-th impact factor, where i represents the index of the impact factor, i∈{1,2,3,4,5,6,7}, and n represents the physical page index. This indicates the number of erases performed on the physical block containing physical page n. This represents the ratio of valid pages to invalid pages within the physical block containing physical page n. This represents the access density of information stored in physical page n.

[0021] By transforming migration conditions into a rigorous two-level logical chain (first determining whether to migrate based on system-level thresholds, then intelligently classifying internal / external migrations based on source page block status and resource thresholds), and introducing a dynamic sorting algorithm based on multi-dimensional weight parameters (erasure count, ratio of valid / invalid pages within a block, and data access density) (defining sorting rules for blank target pages, internal migration source pages, and external migration source pages respectively), this solution constructs a highly structured and optimizable migration decision and execution pipeline. This design significantly improves the accuracy and efficiency of source page selection and target page matching, ensuring that migration operations prioritize data that has the greatest impact on system health (high fragmentation, high wear) and performance (high access density), and dynamically optimizes resource consumption and latency according to migration type (internal / external), thereby maximizing the overall benefits of migration operations, significantly reducing migration latency, and improving storage resource utilization.

[0022] Furthermore, step 42 includes the following steps: Step 421: Extract all variable parameters from the basic module, generate a variable parameter set, and set the domain and minimum step range for each variable parameter; The set of variable parameters includes a1, a2, a3, b1, b2, b3, c1, c2, c3, c4, c5, c6, c7; Step 422: Set a random value for each variable parameter in the variable parameter set according to its domain and minimum step range, generate a particle, and randomly generate N particles; Step 423: Set the fitness function F(x) and the termination condition, iterate through N particles until the termination condition is reached, and use the globally optimal particle when the termination condition is reached as the balance instruction. ; , , Let represent the first weighting factor, the second weighting factor, and the third weighting factor, respectively, and let U represent the synchronous wear rate of the physical block under this particle allocation scheme. This represents the controller communication bandwidth utilization rate under this particle allocation scheme, and E represents the bit error rate of information migration within the NAND memory under this particle allocation scheme.

[0023] This application extracts key threshold parameters and weight factors from the basic model into a set of variable parameters that can be optimized within the domain, and applies a particle swarm optimization algorithm (randomly initializing the particle swarm and defining a multi-objective fitness function). This scheme achieves global, dynamic, and multi-objective collaborative optimization of NAND memory data migration strategies by simultaneously optimizing physical block wear rate U, communication bandwidth utilization B, internal migration bit error rate E, and setting termination conditions for iterative optimization. The process automatically explores and locks the optimal combination of variable parameter sets, generating high-precision balancing instructions. It significantly overcomes the shortcomings of traditional fixed thresholds or manual parameter tuning, which result in suboptimal strategies, poor adaptability, and inability to balance conflicting objectives (such as wear leveling vs. bandwidth utilization vs. reliability). Thus, it achieves the optimal balance of extended lifespan, improved performance, and enhanced reliability at the system level.

[0024] Furthermore, step 5 includes the following steps: Step 51: The external calculator sends a balancing command to the controller; Step 52: The controller loads the basic parameters of the base model based on the balance command; Step 53: The controller monitors the status information of each storage device in real time and determines whether the threshold of each migration condition in the basic model has been reached based on the status information; when the set migration condition threshold is reached, the corresponding data migration method and data migration order are selected.

[0025] Furthermore, the internal data migration process includes the following steps: S1: Obtain the source page from which the data to be migrated, and the target page corresponding to the source page; S2: Import the data from the source page into the register of the corresponding group, and perform bit calibration on the data in the register; S3: The register sends the calibration-passed data to the target page and marks the source page data as invalid. External data migration methods include the following steps: Z1: Obtain the source page from which the data to be migrated, and the target page corresponding to the source page; Z2: Import the data from the source page into the register of the corresponding group, and then import it to the controller via the data bus. The controller performs full code calibration on the data from the source page. Z3: The controller sends the calibrated data to the target page, and marks the source page data as invalid.

[0026] This application has the following beneficial effects: (1) A precise internal digital twin model of NAND is constructed through physical identifiers (including type labels) and a three-layer state table (physical / data / mapping table). The migration conditions, methods, and page order rules are clearly defined in conjunction with the basic model to form a structured migration pipeline. This design provides a comprehensive data foundation and configurable strategy interface for external optimization.

[0027] (2) The core parameters of the migration strategy are extracted into a set of variable parameters, which are dynamically optimized by an external processor using a multi-objective particle swarm optimization algorithm to generate high-precision balancing instructions. This externalized decision-making and lightweight execution architecture breaks through the limitations of NAND computing power and achieves global collaborative optimization of conflicting objectives such as wear leveling, bandwidth utilization, and reliability.

[0028] (3) The scheme significantly reduces invalid migration operations and shortens migration delay through physical block-level migration scheduling (intelligent sorting of source / target pages) and dynamic optimization triggering mechanism (hierarchical conditional logic chain); at the same time, multi-target balancing instructions drive wear leveling accuracy improvement, achieving a synergistic leap in performance, durability and reliability. Attached Figure Description

[0029] Figure 1 This is a flowchart of a NAND flash memory data migration method.

[0030] Figure 2 This is a schematic diagram of the NAND flash memory structure. Detailed Implementation

[0031] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below in conjunction with specific embodiments. The same reference numerals in the accompanying drawings represent the same components. It should be noted that the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the described embodiments of this application without creative effort are within the scope of protection of this application.

[0032] Compared to the embodiments shown in the accompanying drawings, feasible embodiments within the scope of this application may have fewer components, other components not shown in the drawings, different components, differently arranged components, or components with different connections, etc. Furthermore, two or more components in the drawings may be implemented in a single component, or a single component shown in the drawings may be implemented as multiple separate components.

[0033] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this application pertains. The terms “first,” “second,” and similar terms used in this specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an” or “a” and similar terms do not necessarily indicate a quantity limitation. Terms such as “upper” and “lower” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described object changes.

[0034] NAND memory consists of a controller and NAND flash memory chips. The controller is located outside the NAND flash memory chips and is responsible for performing complex management tasks.

[0035] like Figure 2 As shown, NAND flash memory chips are the core medium for data storage, and each NAND flash memory chip consists of one or more wafers. Each wafer integrates multiple independent dies (groups). Each die typically contains multiple physical blocks, which are the smallest units for performing erase operations. Each physical block consists of multiple physical pages, which are the smallest units for performing read and write operations.

[0036] Write operations on NAND flash memory chips must be performed on erased physical pages, and the smallest unit of an erase operation is a physical block (containing multiple physical pages). When the data on some physical pages in a physical block becomes invalid, in order to reclaim the physical block for erasure and obtain usable blank physical pages again, the remaining valid physical page data in that physical block must be migrated (copied) to other blank physical pages. Therefore, NAND flash memory chips require continuous data migration during use.

[0037] Data migration generally includes external migration and internal migration. During internal data migration, NAND flash memory chips typically integrate a simple finite state machine or microcontroller to perform the internal data migration operation. In internal migration, data moves directly between packets within the chip, without needing to pass through an external controller or channel bus.

[0038] In this embodiment, the internal data migration method includes the following steps: S1: Obtain the source page from which the data to be migrated, and the target page corresponding to the source page; S2: Import the data from the source page into the register of the corresponding group, and perform bit calibration on the data in the register; S3: The register sends the calibration-passed data to the target page and marks the source page data as invalid. During external migration, data is read from the NAND flash memory chip via the channel bus to the cache (such as DRAM) connected to the controller, processed (such as error correction and reassembly), and then written back to the NAND flash memory (which may be located in different positions on the same chip or on other chips).

[0039] Whether internal data migration can be performed across groups depends primarily on the internal architecture and communication protocols of the NAND flash memory chip. This solution does not impose any limitations on this and is applicable to all types of NAND flash memory.

[0040] External data migration methods include the following steps: Z1: Obtain the source page from which the data to be migrated, and the target page corresponding to the source page; Z2: Import the data from the source page into the register of the corresponding group, and then import it to the controller via the data bus. The controller performs full code calibration on the data from the source page. Z3: The controller sends the calibrated data to the target page, and marks the source page data as invalid.

[0041] External migration is initiated and executed by a controller located outside the NAND flash memory chip. Data is read out to the controller's buffer via the channel bus. The controller can perform complex processing on the data (such as error correction and reassembly) and then write it back to the NAND flash memory chip, but this consumes channel bus bandwidth and controller resources.

[0042] Internal migration is performed by a finite state machine or simple controller integrated within the NAND flash memory chip. Data moves directly between groups within the chip without passing through an external channel bus and controller. This process has low latency and does not consume external communication resources, but due to the limited processing power within the chip, error correction and other safeguards that can be implemented during data transmission are relatively weak.

[0043] Therefore, a hybrid data migration approach is generally adopted, which involves using a combination of external data migration and external data migration in a certain proportion. However, many factors need to be considered when determining the proportion of external data migration and external data migration. These include, for example, the communication bandwidth of the external bus, the accuracy of information migration, and the consistency of physical block wear.

[0044] If the mixing ratio and specific migration targets are entirely controlled by the NAND memory controller, only a greedy algorithm can be used, which is prone to getting trapped in local optima. To address this issue, this application employs an external powerful computing chip to guide the data migration process within the NAND memory. In practice, one external powerful computing chip can simultaneously handle the data migration processes within multiple NAND memories because data between two different NAND memories does not need to interact. Therefore, this solution only describes the scenario where the external powerful computing chip processes only one NAND memory. Of course, in other embodiments, one powerful computing chip can be connected to multiple NAND memories. This solution is applicable to 3D NAND flash memory and vertical NAND flash memory storage.

[0045] refer to Figure 1 Example 1: The NAND flash memory data migration method includes the following steps: Step 1: Use an external calculator to obtain the physical address of the smallest physical page and the physical address of the smallest physical block in the NAND memory, and build a simulation address table.

[0046] Step 1 includes the following steps: Step 11: Obtain all physical pages in the NAND memory, and generate the physical address of each physical page based on its physical location; the physical address includes the wafer number, group number, block number, and page number; Step 12: For each physical page, generate a type label for the physical page, add the type label to the physical address, and generate a physical identifier for each physical page; Step 13: Obtain all physical blocks in the NAND memory, obtain the physical address of each physical block, and record the physical identifiers of all physical pages under each physical block; Step 14: Construct a simulation address table based on the physical identifiers of all physical pages under each physical block and the physical address of each physical block.

[0047] The simulation address table is essentially a table that maps the internal architecture of the NAND flash memory chip in the NAND storage device to an external computer.

[0048] As shown in the table below: Table 1 Simulation Address Table: Step 2: Monitor the control commands of the controller in the NAND memory. The control commands include read commands for physical pages, write commands for physical pages, and erase commands for physical blocks. Monitor the address mapping table in the controller and obtain the mapping address update instruction for the source data in the address mapping table; Step 2 includes the following steps: Step 21: Monitor the controller's response to the host's control commands in real time to obtain the controller's read commands for physical pages, write commands for physical pages, and erase commands for physical blocks; Step 22: Monitor the address mapping table in the controller and obtain the mapping address update instruction of the source data in the address mapping table.

[0049] An address mapping table is a data structure stored in the controller's memory that maintains a dynamic mapping between the logical addresses used by the host and the physical addresses in the NAND flash memory chip. When the host reads or updates data, the controller uses this table to find the current physical location where the data is actually stored.

[0050] Thus, by using the instructions in steps 21 and 22, it is possible to determine which data in the NAND flash memory chip is hot data, which is cold data, which is invalid data, and which is valid data.

[0051] For example, in step 21, information A is written to physical page 1, and in step 22, it is detected that the actual physical address of information A has been updated to physical page 1. Thus, it can be determined that the information stored in physical page 2, which originally corresponded to the physical address of information A, was invalid.

[0052] The physical page read command can determine whether the data is hot or cold. For example, if a certain piece of data is read 1000 times in a unit of time, and a certain piece of data is read only once, then the former is hot data and the latter is cold data.

[0053] The erase command for a physical block determines the number of erases required for each physical block. If a physical block is erased too many times, it will become invalid. Therefore, the number of erases required for each physical block needs to be approximately the same to balance the performance of the NAND flash memory chip.

[0054] Step 3: The external calculator simulates the physical state of the NAND memory in the simulation address table according to the control instructions and the mapped address update instructions; The physical state includes the percentage of valid information in each physical page, the number of times each physical block has been erased, and the number of times each physical page has been accessed.

[0055] Step 3 includes the following steps: Step 31: Construct a physical state table, which includes the physical state of each physical page; Physical states include blank state, valid state, and number of erases; Step 32: Construct a data status table, which includes the storage status of each piece of data; Storage status includes the data identifier, the current storage address of the data, and the number of times the data has been accessed; Step 33: Construct a data mapping table, which is used to map the mapping relationship between each element in the physical state table and each element in the data state table; Step 34: Extract the physical state of the NAND memory from the physical state table, data state table, and data mapping table.

[0056] In this way, the external calculator uses the control instructions (read / write / erase) and mapped address update instructions obtained from step 2 to construct and simulate the accurate physical state information inside the NAND memory in real time based on the simulated address table.

[0057] The physical status table tracks the real-time status (blank / valid / invalid) of each physical page and the number of erases on its corresponding physical block; the data status table records the current storage location of each data unit (identified by a unique identifier) ​​and its access frequency (number of accesses); the data mapping table precisely associates physical pages with the data units stored on them. By comprehensively analyzing these three tables (step 34), the external calculator can extract physical status indicators crucial for optimizing migration decisions. These include, for example, the number of erases on each physical block, the number of reads for each data item, and the ratio of valid to invalid information in a physical page.

[0058] Step 4: Solve the physical state of the NAND memory using the particle swarm optimization algorithm to obtain the optimal balance instruction for the NAND memory; Among them, the particle swarm optimization algorithm aims to generate the best balanced instructions by synchronizing the wear rate of each physical block, the remaining storage capacity of the NAND flash memory, the controller communication bandwidth utilization, and the bit error rate of information migration within the NAND flash memory.

[0059] Step 4 includes the following steps: Step 41: Construct the basic model for data migration of NAND memory; Step 42: Solve the physical state of the NAND memory using the particle swarm optimization algorithm to generate balancing instructions; Step 43: Send a balancing command to the NAND memory and adjust the built-in parameters in the base model based on the balancing command; Step 44: NAND memory performs data migration based on the adjusted base model; Step 5: Periodically send optimal balancing instructions to the NAND memory. The NAND memory adjusts the internal data migration conditions, external data migration conditions, and physical block erasure order based on the optimal balancing instructions.

[0060] Step 5 includes the following steps: Step 51: The external calculator sends a balancing command to the controller; Step 52: The controller loads the basic parameters of the base model based on the balance command; Step 53: The controller monitors the status information of each storage device in real time and determines whether the threshold of each migration condition in the basic model has been reached based on the status information; when the set migration condition threshold is reached, the corresponding data migration method and data migration order are selected.

[0061] The key to this solution lies in building a fundamental model for data migration in NAND memory by setting up an external calculator independent of the NAND controller and flash memory chips. The external calculator utilizes its powerful computing and storage resources to continuously monitor and analyze the controller's fundamental model, thereby accurately simulating key physical state information (such as the effective page ratio of each physical block, erase count, and data access frequency) that is difficult for the built-in controller to obtain or calculate in real time.

[0062] Therefore, the key to this solution lies in how to set up the basic model and how to control the data migration method and sequence based on the balancing instructions obtained from solving the basic model. Based on this, this application provides Embodiment 2 to detail this process: Example 2: Provides the basic model that needs to be built in step 41.

[0063] The basic model includes: data migration methods and migration conditions.

[0064] Data migration methods include internal data migration and external data migration. Data migration conditions include a first migration condition for whether to perform data migration, a second migration condition for triggering internal data migration, and a third migration condition for triggering external data migration; Internal data migration methods include the order of source and target pages when performing internal data migration; External data migration methods include the order of source and target pages when performing external data migration; The balancing command specifies the numerical values ​​of various information items in the basic model.

[0065] In this solution, the basic model is transformed into a model consisting of conditions and the order of source and target pages. That is, after loading the basic model into the controller, the controller only needs to monitor the current state of the NAND flash memory chip in real time. If the data migration conditions are met, the controller will match the source and target pages sequentially according to their order, and then complete the data migration.

[0066] Throughout the entire data migration process, no additional algorithmic calculations are performed. It is only necessary to determine the timing of migration conditions and match the source and target pages sequentially to complete the data migration.

[0067] When migrating data internally between source and target pages, there are many constraints, such as matching within the same group and having the same data type. Therefore, the source page only needs to find the most suitable target page to match, following the order of the target pages.

[0068] The first migration conditions include: storage load upper limit threshold a1, storage minimum remaining value a2, and total valid pages to total invalid pages ratio threshold a3; load refers to the power of the storage. If the storage power is too high, data migration should be avoided as much as possible to prevent the storage from overheating.

[0069] The first migration condition is triggered when the memory meets the following conditions: current load is less than a1, remaining memory capacity is less than a2, and the ratio of total valid pages to total invalid pages is less than a3.

[0070] Furthermore, the second migration conditions include: the remaining threshold of controller transmission resources b1, the ratio of valid pages to invalid pages in the physical block where the source page is located b2, and the number of erases in the physical block where the source page is located b3; The second migration condition is triggered when the source page meets the following conditions: the controller transfer resources are higher than b1, the ratio of valid pages to invalid pages in the physical block where the source page is located is less than b2, and the number of erases in the physical block where the source page is located is less than b3. The third migration conditions include: the remaining threshold of controller transmission resources b1, the ratio of valid pages to invalid pages in the physical block where the source page is located b2, and the number of erases in the physical block where the source page is located b3; The third migration condition is triggered when the source page meets the following conditions: the controller transfer resources are less than b1, the ratio of valid pages to invalid pages in the physical block where the source page is located is less than b2, and the number of erases in the physical block where the source page is located is less than b3.

[0071] In reality, only one of the second and third migration conditions will be met. That is, when the first migration condition is met (the migration opportunity is available), the choice can be made based on the remaining threshold of the controller's transmission resources. If the remaining threshold of transmission resources is high, then external migration will be used; otherwise, internal migration will be used.

[0072] The above outlines the technical principles of the basic model. However, in practical computer processing, this basic model cannot be translated into a feasible implementation plan. Therefore, it needs to be transformed into a logical chain. After being transformed into a logical chain, the entire basic model can be programmed based on corresponding conditions. Specifically: In step 41, the migration conditions are transformed into a logical chain. The logical chain of the migration conditions is as follows: Condition 1: Data migration is triggered when the first migration condition is met; data migration is stopped when the first migration condition is not met. Condition 2: When condition 1 is met, traverse all physical pages that have already stored information and divide the physical pages into two categories: Category 1: Meets the second migration condition but does not meet the third migration condition; Category 2: Does not meet the second migration condition, but meets the third migration condition; For the first type of physical page, mark it as a source page and perform internal data migration; for the second type of physical page, mark it as a source page and perform external data migration. Data migration will stop if condition 1 is not met. In step 41, the data migration method is changed to source page sorting and target page sorting; Use all blank physical pages as target pages, and assign the target pages to the idle weight parameter. Arrange them in order as the target pages during data migration; Idle weight parameters Related to the number of erases on the physical block it belongs to; The first type of physical pages are assigned according to the first weight parameter. Arranged to serve as the source page order when performing internal data migration; The second type of physical pages are assigned according to the second weighting parameter. Arranged to serve as the source page order when performing external data migration; The first weighting parameter is related to the ratio of valid to invalid pages in the physical block where the source page is located, the number of times the physical block where the source page is located is erased, and the access density of the information stored in the source page; The second weighting parameter is related to the ratio of valid to invalid pages in the physical block where the source page is located, the number of erases in the physical block where the source page is located, and the access density of the information stored in the source page; ; ; ; ; Let represent the i-th impact factor, where i represents the index of the impact factor, i∈{1,2,3,4,5,6,7}, and n represents the physical page index. This indicates the number of erases performed on the physical block containing physical page n. This represents the ratio of valid pages to invalid pages within the physical block containing physical page n. This represents the access density of information stored in physical page n.

[0073] Both source page and target page refer to physical pages. A blank physical page can be used as a target page, while a physical page containing information can be used as a source page. Source page and target page are simply labels for physical pages during data migration.

[0074] The idea behind this approach, which transforms the basic model into a logical chain, is to convert it into a model built from conditions, each of which can be directly translated into a programming language. In other words, it discretizes and structures pre-defined, quantifiable transition conditions and weight calculation formulas into a series of clear, sequential "condition-action" decision nodes. This transformation encodes complex state dependencies and optimization objectives (wear leveling, GC efficiency, performance) into clear, executable operation sequences, thereby translating the simulation results of the basic model into a flow of transition instructions that the controller can execute.

[0075] Step 42 includes the following steps: Step 421: Extract all variable parameters from the basic module, generate a variable parameter set, and set the domain and minimum step range for each variable parameter; The set of variable parameters includes a1, a2, a3, b1, b2, b3, c1, c2, c3, c4, c5, c6, and c7.

[0076] For each variable parameter, a transformation range and a corresponding step range need to be set. The step range refers to the smallest integer multiple of each change. For example, if the range of a1 is 0 to 0.5 and the step range is 0.1, then a1 can only be a tenths decimal such as 0.1 or 0.2, and not a hundredths decimal such as 0.11.

[0077] After defining the domain and minimum step size for each variable parameter, randomly selecting an executable value for each variable parameter will form a feasible solution (particle). If this feasible solution has good fitness (high advantage), it can be used as the optimal solution.

[0078] Step 422: Set a random value for each variable parameter in the variable parameter set according to its domain and minimum step range, generate a particle, and randomly generate N particles; Step 423: Set the fitness function F(x) and the termination condition, iterate through N particles until the termination condition is reached, and use the globally optimal particle when the termination condition is reached as the balance instruction. ; , , Let represent the first weighting factor, the second weighting factor, and the third weighting factor, respectively, and let U represent the synchronous wear rate of the physical block under this particle allocation scheme. This represents the controller communication bandwidth utilization rate under this particle allocation scheme, and E represents the bit error rate of information migration within the NAND memory under this particle allocation scheme.

[0079] In the Particle Swarm Optimization (PSO) algorithm, each "particle" represents a potential solution to the problem (in this application, a specific combination of variable parameter values). During iteration, each particle adjusts its "speed" and "direction" (i.e., the trend of parameter value changes) based on three key factors: the particle's historical best solution; the global best solution; and the particle's current inertia. The particle dynamically updates its position (i.e., generates new parameter combinations) by comprehensively considering these three factors (moving closer to its own best point, moving closer to the global best point, and maintaining a certain inertia). After multiple iterations, the particle swarm gradually converges, eventually tending to locate the optimal or near-optimal solution in the problem space.

[0080] The particle swarm optimization (PSO) algorithm's update and iteration methods are existing technologies and will not be elaborated upon here. Given a fitness function, anyone skilled in the art can perform iterations using the PSO algorithm.

[0081] The above are merely preferred embodiments of this application and are not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A method for migrating NAND flash memory data, characterized in that, Includes the following steps: Step 1: Use an external calculator to obtain the physical address of the smallest physical page and the physical address of the smallest physical block in the NAND memory, and build a simulation address table; Step 2: Monitor the control commands of the controller in the NAND memory. The control commands include read commands for physical pages, write commands for physical pages, and erase commands for physical blocks. Monitor the address mapping table in the controller and obtain the mapping address update instruction for the source data in the address mapping table; Step 3: The external calculator simulates the physical state of the NAND memory in the simulation address table according to the control instructions and the mapped address update instructions; The physical status includes the proportion of valid information in each physical page, the number of times each physical block is erased, and the number of times each physical page is accessed; Step 4: Solve the physical state of the NAND memory using the particle swarm optimization algorithm to obtain the optimal balance instruction for the NAND memory; Among them, the particle swarm optimization algorithm aims to optimize the synchronous wear rate of each physical block, the remaining storage capacity of the NAND memory, the controller communication bandwidth utilization rate, and the bit error rate of information migration inside the NAND memory, and generates the best balanced instructions. Step 5: Periodically send optimal balancing instructions to the NAND memory. The NAND memory adjusts the internal data migration conditions, external data migration conditions, and physical block erasure order based on the optimal balancing instructions.

2. The NAND flash memory data migration method according to claim 1, characterized in that, Step 1 includes the following steps: Step 11: Obtain all physical pages in the NAND memory, and generate the physical address of each physical page based on its physical location; the physical address includes the wafer number, group number, block number, and page number; Step 12: For each physical page, generate a type label for the physical page, add the type label to the physical address, and generate a physical identifier for each physical page; Step 13: Obtain all physical blocks in the NAND memory, obtain the physical address of each physical block, and record the physical identifiers of all physical pages under each physical block; Step 14: Construct a simulation address table based on the physical identifiers of all physical pages under each physical block and the physical address of each physical block.

3. The NAND flash memory data migration method according to claim 1, characterized in that, Step 2 includes the following steps: Step 21: Monitor the controller's response to the host's control commands in real time to obtain the controller's read commands for physical pages, write commands for physical pages, and erase commands for physical blocks; Step 22: Monitor the address mapping table in the controller and obtain the mapping address update instruction of the source data in the address mapping table.

4. The NAND flash memory data migration method according to claim 1, characterized in that, Step 3 includes the following steps: Step 31: Construct a physical state table, which includes the physical state of each physical page; Physical states include blank state, valid state, and number of erases; Step 32: Construct a data status table, which includes the storage status of each piece of data; Storage status includes the data identifier, the current storage address of the data, and the number of times the data has been accessed; Step 33: Construct a data mapping table, which is used to map the mapping relationship between each element in the physical state table and each element in the data state table; Step 34: Extract the physical state of the NAND memory from the physical state table, data state table, and data mapping table.

5. A NAND flash memory data migration method according to claim 1, characterized in that, Step 4 includes the following steps: Step 41: Construct the basic model for data migration of NAND memory; Step 42: Solve the physical state of the NAND memory using the particle swarm optimization algorithm to generate balancing instructions; Step 43: Send a balancing command to the NAND memory and adjust the built-in parameters in the base model based on the balancing command; Step 44: NAND memory performs data migration based on the adjusted base model; The basic model includes: Data migration methods and conditions; Data migration methods include internal data migration and external data migration. Data migration conditions include a first migration condition for whether to perform data migration, a second migration condition for triggering internal data migration, and a third migration condition for triggering external data migration; Internal data migration methods include the order of source and target pages when performing internal data migration; External data migration methods include the order of source and target pages when performing external data migration; The balancing command specifies the numerical values ​​of various information items in the basic model.

6. A NAND flash memory data migration method according to claim 5, characterized in that, The first migration conditions include: storage load limit threshold a1, minimum remaining storage value a2, and total valid pages to total invalid pages ratio threshold a3; The first migration condition is triggered when the memory meets the following conditions: current load is less than a1, remaining memory capacity is less than a2, and the ratio of total valid pages to total invalid pages is less than a3.

7. A NAND flash memory data migration method according to claim 5, characterized in that, The second migration conditions include: the remaining threshold of controller transmission resources b1, the ratio of valid pages to invalid pages in the physical block where the source page is located b2, and the number of erases in the physical block where the source page is located b3; The second migration condition is triggered when the source page meets the following conditions: the controller transfer resources are higher than b1, the ratio of valid pages to invalid pages in the physical block where the source page is located is less than b2, and the number of erases in the physical block where the source page is located is less than b3. The third migration conditions include: the remaining threshold of controller transmission resources b1, the ratio of valid pages to invalid pages in the physical block where the source page is located b2, and the number of erases in the physical block where the source page is located b3; The third migration condition is triggered when the source page meets the following conditions: the controller transfer resources are less than b1, the ratio of valid pages to invalid pages in the physical block where the source page is located is less than b2, and the number of erases in the physical block where the source page is located is less than b3.

8. A NAND flash memory data migration method according to claim 7, characterized in that, In step 41, the migration conditions are transformed into a logical chain. The logical chain of the migration conditions is as follows: Condition 1: Data migration is triggered when the first migration condition is met; data migration is stopped when the first migration condition is not met. Condition 2: When condition 1 is met, traverse all physical pages that have already stored information and divide the physical pages into two categories: Category 1: Meets the second migration condition but does not meet the third migration condition; Category 2: Does not meet the second migration condition, but meets the third migration condition; For the first type of physical page, mark it as a source page and perform internal data migration; for the second type of physical page, mark it as a source page and perform external data migration. Data migration will stop if condition 1 is not met. In step 41, the data migration method is changed to source page sorting and target page sorting; Use all blank physical pages as target pages, and assign the target pages according to the idle weight parameter. Arrange them in order as the target pages during data migration; Idle weight parameters Related to the number of erases on the physical block it belongs to; The first type of physical pages are assigned according to the first weight parameter. Arranged to serve as the source page order when performing internal data migration; The second type of physical pages are assigned according to the second weighting parameter. Arranged to serve as the source page order when performing external data migration; The first weighting parameter is related to the ratio of valid to invalid pages in the physical block where the source page is located, the number of erases in the physical block where the source page is located, and the access density of the information stored in the source page; The second weighting parameter is related to the ratio of valid to invalid pages in the physical block where the source page is located, the number of erases in the physical block where the source page is located, and the access density of the information stored in the source page; ; ; ; ； Let represent the i-th impact factor, where i represents the index of the impact factor, i∈{1,2,3,4,5,6,7}, and n represents the physical page index. This indicates the number of erases performed on the physical block containing physical page n. This represents the ratio of valid pages to invalid pages within the physical block containing physical page n. This represents the access density of information stored in physical page n.

9. A NAND flash memory data migration method according to claim 8, characterized in that, Step 42 includes the following steps: Step 421: Extract all variable parameters from the basic module, generate a variable parameter set, and set the domain and minimum step range for each variable parameter; The set of variable parameters includes a1, a2, a3, b1, b2, b3, c1, c2, c3, c4, c5, c6, c7; Step 422: Set a random value for each variable parameter in the variable parameter set according to its domain and minimum step range, generate a particle, and randomly generate N particles; Step 423: Set the fitness function F(x) and the termination condition, iterate through N particles until the termination condition is reached, and use the globally optimal particle when the termination condition is reached as the balance instruction. ； , , Let represent the first weighting factor, the second weighting factor, and the third weighting factor, respectively, and let U represent the synchronous wear rate of the physical block under this particle allocation scheme. This represents the controller communication bandwidth utilization rate under this particle allocation scheme, and E represents the bit error rate of information migration within the NAND memory under this particle allocation scheme.

10. A NAND flash memory data migration method according to claim 1, characterized in that, Step 5 includes the following steps: Step 51: The external calculator sends a balancing command to the controller; Step 52: The controller loads the basic parameters of the base model based on the balance command; Step 53: The controller monitors the status information of each storage device in real time and determines whether the threshold of each migration condition in the basic model has been reached based on the status information; when the set migration condition threshold is reached, the corresponding data migration method and data migration order are selected.

Images