Chip adapter operator code generation method, device, medium and product

Abstract

This invention discloses a method, device, medium, and product for generating operator code for chip adaptation operators. The method includes: extracting adaptation requirement information for generating target operator code in response to an operator code generation request from a target operator; obtaining multiple update large model prompts corresponding to each preset exploration strategy based on the adaptation requirement information and multiple preset exploration strategies; inputting each update large model prompt into multiple working nodes equipped with the same target large model, and then triggering each working node to cyclically execute the operator code generation task in parallel; monitoring and assisting in the task execution in real time until the target operator code that has been verified and meets the performance requirements is successfully obtained in multiple working nodes, and then using the target operator code as the response result of the operator code generation request. This technical solution can improve the reliability and efficiency of generating operator code adapted to different hardware platforms and improve the utilization of computing resources.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and in particular to a method, apparatus, medium, and product for generating operator code for chip adapter operators. Background Technology

[0002] With the rapid development of deep learning technology, the independent controllability of domestically produced artificial intelligence chips has become a focus of the industry. Domestic chips face severe challenges such as a lack of operator libraries, incomplete development documentation, and extremely high low-level programming barriers. Migrating existing massive unified computing device architecture operators to domestically produced tensor processing units requires not only overcoming differences in programming languages ​​but also bridging the paradigm gap between "single-instruction multi-threading" and "domain-specific architecture." Utilizing large language models to automatically generate operator code has become an industry trend.

[0003] Existing technologies often employ the following approaches: First, a single-point serial generation approach, which uses a single prompt word and a single model to generate and verify code in parallel; second, a simple parallel generation approach, which simultaneously starts multiple identical large language model instances to generate code and selects the correct result; and third, a template-based generation approach, which predefines operator templates and allows the large language model to fill in only the relevant parameters to generate operator code.

[0004] Existing technical solutions have significant limitations: single-point serial generation schemes have low success rates, are prone to getting stuck in erroneous logic loops leading to task failure, and cannot explore multiple optimization possibilities, resulting in poor performance of generation operators; simple parallel generation schemes waste resources severely, with multiple worker nodes using the same strategy lacking diversity, prone to simultaneous failure, and lacking a unified scheduling and termination mechanism, leading to ineffective use of computing resources; template-based generation schemes have poor flexibility, making it difficult to adapt to the varied hardware architectures of domestic tensor processing units and unable to adapt to complex fusion operators; in general, existing technologies either get stuck in inefficient loops of repeated individual execution or inefficient parallelism that wastes resources, and both lack dynamic collaboration between worker nodes and intelligent control based on expectations, failing to meet the needs of practical applications. Summary of the Invention

[0005] This invention provides a method, device, medium, and product for generating operator code for chip adaptation operators, in order to solve the problems of randomness, low exploration efficiency, and inability to balance correctness and performance in the process of generating operator code for large models.

[0006] According to one aspect of the present invention, a method for generating operator code for a chip adaptation operator is provided, comprising: In response to the operator code generation request for the target operator, the adaptation requirement information for generating the target operator code is extracted from the operator code generation request. The adaptation requirement information includes the operator type of the target operator, the target hardware platform to be adapted, the input and output tensor dimensions, and the performance requirements. Based on the adaptation requirements and multiple preset exploration strategies, multiple updated large model prompt words corresponding to each exploration strategy are obtained; After inputting the update prompt words for each large model in multiple worker nodes carrying the same target large model, each worker node is triggered to start cyclically executing the operator code generation task in parallel; the operator code generation task includes a series of code generation subtasks, code compilation subtasks and code verification subtasks; During the execution of tasks at each worker node, the task execution status is monitored and assisted in correction in real time until the target operator code that has been verified and meets the performance requirements is successfully obtained in multiple worker nodes, and the target operator code is used as the response result of the operator code generation request.

[0007] According to another aspect of the present invention, an operator code generation apparatus for chip adaptation operators is provided, comprising: The request and response module is used to respond to the operator code generation request for the target operator. It extracts the adaptation requirement information for generating the target operator code from the operator code generation request. The adaptation requirement information includes the operator type of the target operator, the target hardware platform to be adapted, the input and output tensor dimensions, and the performance requirements. The prompt word generation module is used to generate multiple updated large model prompt words corresponding to each exploration strategy, based on the adaptation requirement information and multiple preset exploration strategies. The operator code generation module is used to trigger the operator code generation task to be executed in parallel on each working node after inputting the update prompt words of each large working node that carries the same target large model. The operator code generation task includes a series of code generation subtasks, code compilation subtasks and code verification subtasks. The task monitoring module is used to monitor and assist in correcting the task execution status in real time during the execution of tasks at each worker node, until the target operator code that has been verified and meets the performance requirements is successfully obtained in multiple worker nodes, and the target operator code is used as the response result of the operator code generation request.

[0008] According to another aspect of the present invention, an electronic device is provided, the electronic device comprising: At least one processor; and A memory communicatively connected to the at least one processor; wherein, The memory stores a computer program that can be executed by the at least one processor, which is then executed by the at least one processor to enable the at least one processor to execute the operator code generation method for chip adaptation operators according to any embodiment of the present invention.

[0009] According to another aspect of the present invention, a computer-readable storage medium is provided, the computer-readable storage medium storing computer instructions, the computer instructions being configured to cause a processor to execute and implement the operator code generation method of the chip adaptation operator according to any embodiment of the present invention.

[0010] According to another aspect of the present invention, a computer program product is also provided, including a computer program that, when executed by a processor, implements the steps of the method as described in any embodiment of the present invention.

[0011] This invention, through the aforementioned technical solution, can respond to operator code generation requests. It extracts the operator type and target hardware platform of the target operator from the adaptation requirement information used to generate the target operator code, along with the input / output tensor dimension and performance requirements. Based on multiple preset exploration strategies, it obtains multiple update large model hints corresponding to each strategy. These update large model hints are then input into multiple worker nodes equipped with the same target large model for parallel processing. Each worker node cyclically executes the operator code generation task, including a series of code generation sub-tasks, code compilation sub-tasks, and code verification sub-tasks. During the cyclical execution of the operator code generation task by each worker node, the task execution status of each worker node is monitored and assisted in correction in real time until any worker node successfully generates verified target operator code that meets the performance requirements. This is then used as the response result to the operator code generation request. This technical solution improves the reliability and efficiency of generating operator code adapted to different hardware platforms and enhances the utilization of computing resources by having multiple worker nodes execute the large model target operator code generation task in parallel.

[0012] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0013] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0014] Figure 1This is a flowchart of an operator code generation method for a chip adaptation operator according to Embodiment 1 of the present invention; Figure 2 This is a flowchart of an operator code generation method for a chip adaptation operator according to Embodiment 2 of the present invention; Figure 3 This is a schematic diagram of the structure of an operator code generation device for a chip adaptation operator according to Embodiment 3 of the present invention; Figure 4 This is a schematic diagram of the structure of an electronic device that implements the operator code generation method of the chip adaptation operator in the embodiments of the present invention. Detailed Implementation

[0015] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0016] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0017] Example 1 Figure 1 This is a flowchart of an operator code generation method for a chip-adaptive operator provided in Embodiment 1 of the present invention. This embodiment is applicable to situations where operator code is generated from a large model to adapt to operators on different hardware platforms. This method can be executed by an operator code generation device for the chip-adaptive operator. This device can be implemented in hardware and / or software and is generally configured in computer electronic devices. Figure 1 As shown, the method includes: S110. In response to the operator code generation request for the target operator, extract the adaptation requirement information for generating the target operator code from the operator code generation request. The adaptation requirement information includes the operator type of the target operator, the target hardware platform to be adapted, the input and output tensor dimensions, and the performance requirements.

[0018] In this context, a target operator can refer to the smallest program unit, specifically designed for the computational needs of a designated type of hardware chip platform, possessing unique numerical computation, logical processing, or data transformation functions. Operator code can refer to program code that can run on the hardware chip platform and perform corresponding numerical computation, logical processing, or data transformation functions. The target hardware platform can refer to a designated type of hardware chip platform that needs to run the operator code in the current application scenario; it has a specific hardware architecture and computational paradigm and serves as the physical carrier for operator code adaptation and execution. Tensor dimension can refer to structured data existing in the form of a multi-dimensional array used for deep learning computation; it is the input or output data form for the operator to perform computational functions on the target hardware platform. Target operator code can refer to executable operator program code that meets the adaptation requirements in the operator code generation request for the target operator, has passed functional verification, and meets performance indicators.

[0019] Understandably, in order to generate operator code that can adapt to the target operator on the target hardware platform, the adaptation requirement information for generating the target operator code needs to be extracted when responding to the operator code generation request. The adaptation requirement information can specify the operator type of the target operator. The specified operator type can include basic operation operators (such as addition, subtraction, multiplication, division, matrix multiplication, convolution, pooling, and activation functions), data transformation operators (such as dimension transformation, data concatenation / splitting, and format conversion), logic control operators (such as conditional judgment, loop execution, and branch selection), and fusion operators (composite computational units that integrate the logic of multiple basic operators). Different types of operators correspond to different computational logic and resource scheduling strategies on the target hardware platform. The adaptation requirement information can also specify the target hardware platform to be adapted, the input and output tensor dimensions, and performance requirements. For example, a method for generating the target operator code... The adaptation requirements for the operator code can be specified as follows: the operator type is Conv2D, a convolutional operator for feature extraction; the target hardware platform is set to the domestically developed tensor processor TPU-X; and the input and output tensor dimensions are specified as [Batch_Size, Num_Heads, Seq_Len, Head_Dim]. Here, Batch_Size is the batch size, representing the number of samples fed into the operator for computation in a single run, and is the element size of the first dimension of the tensor. Num_Heads is the number of attention heads, representing the number of attention heads used in parallel computation in the deep learning attention mechanism, corresponding to the second dimension of the tensor. Seq_Len is the sequence length, representing the length of sequence data such as text or time series, corresponding to the third dimension of the tensor. Head_Dim is the head dimension, representing the feature dimension size of a single attention head, corresponding to the fourth dimension of the tensor. The data precision is set to FP16, i.e., 16-bit floating-point data precision, and low latency is prioritized as the performance requirement.

[0020] S120. Based on the adaptation requirements information and multiple preset exploration strategies, obtain multiple update large model prompt words corresponding to each exploration strategy.

[0021] Among them, the exploration strategy can refer to the corresponding reasoning strategy adopted by the large model to generate target operator code through prompt words, depending on the different needs.

[0022] Understandably, in order to improve the efficiency of target operator code generation by inferring target operator code based on prompt words, while satisfying the requirements and features in the adaptation information, multiple exploration strategies for inferring target operator code based on the usage scenario requirements of target operator code can be preset, and corresponding updated prompt words for large models can be generated based on the inference features of multiple preset exploration strategies.

[0023] S130. After inputting the update prompt words for each large model in multiple working nodes carrying the same target large model, each working node is triggered to start executing the operator code generation task in parallel. The operator code generation task includes a series of code generation subtasks, code compilation subtasks and code verification subtasks.

[0024] Here, the target large model can refer to a deep learning inference model that executes a matching exploration strategy to infer and generate target operator code based on the demand emphasis of the adaptation requirement information for generating target operator code. A worker node can refer to an independent execution unit with independent computing resources, capable of loading and running the target large model to complete the code generation subtask, code compilation subtask, and code verification subtask within the operator code generation task.

[0025] Understandably, to improve the efficiency of target operator code inference and generation, multiple independent worker nodes executing operator code generation tasks can be used, each carrying the same target large model. The updated large model prompts corresponding to different exploration strategies are used as input information, and the operator code generation tasks, including code generation sub-tasks, code compilation sub-tasks, and code verification sub-tasks, are executed in a loop. This ensures that the operator code generated by the target large model compiles without syntax and semantic errors, passes code verification to match the target hardware platform and meet the operator's functional requirements, and optimizes the generated operator code to improve code execution performance during the loop execution of the operator code generation tasks.

[0026] S140. During the execution of tasks at each working node, the task execution status is monitored and assisted in correction in real time until the target operator code that has been verified and meets the performance requirements is successfully obtained in multiple working nodes, and the target operator code is used as the response result of the operator code generation request.

[0027] Understandably, during the cyclic execution of operator code generation tasks, each worker node can continuously optimize the generated operator code and monitor the task execution status of each worker node in real time. For abnormal issues that occur during the execution of code compilation and code verification subtasks, targeted auxiliary corrections can be made according to preset repair strategies. The operator code that has been corrected continues to execute code compilation and code verification subtasks. During the parallel cyclic execution of operator code generation tasks by each worker node, the performance parameters of the operator code generated by each worker node when executing code verification subtasks are monitored in real time. When the operator code generated by any worker node in the parallel execution is verified and meets the preset performance indicators, the operator code generated by that worker node is used as the target operator code and output as the response result of the operator code generation request.

[0028] This invention, through the aforementioned technical solution, can respond to operator code generation requests. It extracts the operator type and target hardware platform of the target operator from the adaptation requirement information used to generate the target operator code, along with the input / output tensor dimension and performance requirements. Based on multiple preset exploration strategies, it obtains multiple update large model hints corresponding to each strategy. These update large model hints are then input into multiple worker nodes equipped with the same target large model for parallel processing. Each worker node cyclically executes the operator code generation task, including a series of code generation sub-tasks, code compilation sub-tasks, and code verification sub-tasks. During the cyclical execution of the operator code generation task by each worker node, the task execution status of each worker node is monitored and assisted in correction in real time until any worker node successfully generates verified target operator code that meets the performance requirements. This is then used as the response result to the operator code generation request. This technical solution improves the reliability and efficiency of generating operator code adapted to different hardware platforms and enhances the utilization of computing resources by having multiple worker nodes execute the large model target operator code generation task in parallel.

[0029] Example 2 Figure 2 This is a flowchart of an operator code generation method for a chip adaptation operator provided in Embodiment 2 of the present invention. This embodiment is a specific embodiment based on the above embodiments, including: specific methods for generating different large model prompt words according to different types of exploration strategies, and specific methods for real-time monitoring and auxiliary correction of the task execution process of each parallel working node. Figure 2 As shown, the method includes: S210. In response to the operator code generation request for the target operator, extract the adaptation requirement information for generating the target operator code from the operator code generation request. The adaptation requirement information includes the operator type of the target operator, the target hardware platform to be adapted, the input and output tensor dimensions, and the performance requirements.

[0030] S220. Based on the adaptation requirements information and multiple preset exploration strategies, obtain multiple update large model prompt words corresponding to each exploration strategy.

[0031] Optionally, based on the adaptation requirements and multiple preset exploration strategies, multiple update prompts for the large model are obtained, each corresponding to a different exploration strategy, including: Generate standard large-model prompt words based on adaptation requirements; Depending on the strategy type of the exploration strategy, multiple updated large model hints can be obtained by either directly using standard large model hints or by adding differentiated instructions that match the strategy type to the standard large model hints.

[0032] Among them, standard large model prompt words can refer to natural language instruction texts that are clearly instructive, structured and reusable, constructed based on the core objectives, input and output specifications and logical constraints of the task in order to enable the large model to accurately execute the operator code generation task. Its characteristic is that it can standardize the model output to meet the preset requirements and can adapt to the execution needs of similar tasks in different scenarios.

[0033] Understandably, when worker nodes execute operator code generation tasks using a large model, they can extract adaptation requirement information from the operator code generation request. Based on the operator type of the target operator, the target hardware platform, input / output tensor dimensions, and performance requirements in the adaptation requirement information, standard large model hint words can be generated to adapt to the execution requirements of similar tasks in different scenarios. Depending on the strategy type of different exploration strategies executed by each worker node, the standard large model hint words can be used directly, or updated large model hint words can be obtained by adding differentiated instructions matching the strategy type to the standard large model hint words, thus meeting the requirements of generating target operator code for that type of exploration strategy.

[0034] Optionally, depending on the strategy type of the exploration strategy, you can choose to directly use the standard large model hints, or add differentiated instructions matching the strategy type to the standard large model hints to obtain multiple updated large model hints, including: If the exploration strategy is a deterministic execution strategy, then the standard large model cue words are used directly as the update large model cue words corresponding to the deterministic execution strategy; If the exploration strategy is a high-performance optimization strategy, then construct a high-performance optimization instruction that matches the required high-performance optimization dimension, and inject the high-performance optimization instruction into the standard large model hint words to obtain the updated large model hint words corresponding to the high-performance optimization strategy. If the exploration strategy is a specific rule coverage strategy, then construct the technology stack instructions that match the rules to be covered, and inject the technology stack instructions into the standard large model prompt words to obtain the updated large model prompt words corresponding to the specific rule coverage strategy; If the exploration strategy is a hardware-aware strategy, then a hardware defect avoidance instruction matching the sensitive hardware is constructed, and the hardware defect avoidance instruction is injected into the standard large model hint words to obtain the updated large model hint words corresponding to the hardware-aware strategy.

[0035] Among them, a deterministic execution strategy can refer to a large model execution strategy that satisfies the preset target requirements in the adaptation requirement information of the operator code generation request and directly uses the standard large model hint words generated from the requirement information to generate operator code. A high-performance optimization strategy can refer to a large model execution strategy that satisfies the preset target requirements in the adaptation requirement information of the operator code generation request and uses the large model hint words updated according to the performance optimization requirements to generate operator code. A technology stack instruction can refer to the set of instructions corresponding to the large model hint word constraint condition units that reflect the technical characteristics of the target operator executing the target operator code. A specific rule coverage strategy can refer to a large model execution strategy that satisfies the preset target requirements in the adaptation requirement information of the operator code generation request and uses the large model hint words updated according to the technology stack instructions to generate operator code. A hardware-aware strategy can refer to a large model execution strategy that satisfies the preset target requirements in the adaptation requirement information of the operator code generation request and uses the large model hint words updated according to the sensitive hardware defect avoidance instructions on the target operator to generate operator code.

[0036] Understandably, the corresponding large model hints can be determined based on the exploration strategy type. When the exploration strategy is a deterministic execution strategy, the generated standard large model hints can be directly used as the corresponding update large model hints to generate the target operator code. For example, the standard large model hints could be: "Role: Compiler engineer with TPU-X architecture expertise, this role covers the entire operator development and inference process; Core task: Implement the Softmax operator based on the input tensor, prioritizing correctness, employing aggressive pipeline optimization and loop unrolling strategies to generate syntactically correct and performance-optimized C language code; Input parameters: Tensor dimensions [32, 12, 128, 128], data type FP16, the core processing object throughout the entire process; Hardware constraints: TPU-X compatibility." The architecture adheres to memory size limitations, prioritizing the use of vector exponentiation and vector summation instructions, with constraints covering all stages of operator development. References are based on optimized code snippets of similar operators retrieved from vector libraries. Output specifications: only operator code compatible with the TPU-X architecture is output, with no redundant text. This can include differentiated prompts based on the standard large model prompts. The principle is to perform rigorous logical reasoning based on input information, prioritizing correctness, without introducing additional complex instructions or irrelevant constraints, and only outputting objective and accurate reasoning results. The process of generating standardized operator code based on standard large model prompts for work nodes employing a deterministic execution strategy can be as follows: first, calculate the maximum input value and perform subtraction to prevent numerical overflow; then, perform exponentiation and summation; finally, perform division to obtain the result. The generated operator code uses a conventional structure and can quickly generate a runnable benchmark implementation. Although this implementation does not utilize hardware features, it guarantees correct calculation results and serves as a safety net benchmark version during development.

[0037] If the exploration strategy is a high-performance optimization strategy, a high-performance optimization instruction with added high-performance optimization dimensions can be constructed to match the operator code generation request. After injecting the high-performance optimization instruction into the standard large model hint, the corresponding updated large model hint can be obtained. For example, the difference hint generated based on the standard large model hint could be "In the process of operator code development, an aggressive pipeline optimization strategy is adopted to reconstruct the computation execution process, and the loop body execution logic is optimized through loop unrolling technology to break through the conventional optimization boundary and improve the execution efficiency of the operator under the target hardware architecture." The processing of the corresponding work node executing the high-performance optimization strategy can be: by reconstructing and adjusting the instruction execution order of data loading, exponent calculation, summation and storage, the memory access latency can be masked. This processing method is expected to generate operator code with significantly improved execution performance, but there is a risk of syntax errors (such as data dependency conflicts). If errors occur, the generated code draft can be used as the basic material for repair and optimization.

[0038] If the exploration strategy is a rule-specific coverage strategy, a technology stack instruction containing specific rules can be constructed to match the operator code generation request. After injecting the technology stack instruction into the standard large model hint, the corresponding updated large model hint can be obtained. For example, the difference hint generated based on the standard large model hint could be "Perform strict logical reasoning based on input information, with correctness as the primary principle, without introducing additional complex instructions and irrelevant constraints, and forcibly using shared memory (or local memory under the tensor processor architecture) to complete data reuse operations during the reasoning process, outputting only objective and accurate reasoning results." The processing procedure of the corresponding work node executing the rule-specific coverage strategy could be: for the characteristic that the normalization exponent operator needs to scan data multiple times, load a single set of 128 data elements into the on-chip shared memory at once to avoid repeatedly reading data from global memory. For operators like the normalization exponent that are sensitive to memory access efficiency, this processing method is expected to generate a solution with optimal execution performance.

[0039] If the exploration strategy is a hardware-aware strategy, hardware defect avoidance instructions matching the sensitive hardware can be constructed. These instructions are then injected into the standard large model hints to obtain the corresponding updated large model hints. For example, the difference hint generated based on the standard large model hints could be: "Execute strict logical reasoning based on input information, prioritizing correctness, without introducing additional complex instructions or irrelevant constraints, incorporating the specific principle of static random access memory (SRAM) conflict avoidance under the Tensor Processor (TPU-X) architecture during the reasoning process, and only outputting objective and accurate reasoning results." The corresponding processing procedure for the working node executing the hardware-aware strategy could be: during the reasoning code generation process, based on the hint information "Static random access memory (SRAM) under the Tensor Processor (TPU-X) architecture will trigger a memory conflict when the access step size is an integer multiple of 64," this hardware architecture defect is avoided by adding padding operations in the memory layout or adjusting the loop access step size. This processing method is expected to generate operator code that avoids the specific defects of the target hardware architecture, possessing high stability and high execution efficiency.

[0040] Furthermore, during the large model's operator code generation inference task, the value of the temperature parameter (T) directly affects the determinism of the model output and the selection of inference strategies: when a low temperature parameter is used, the determinism of the model output is significantly improved, and the inference process tends to select the vocabulary unit with the optimal probability, adapting to generate operator code with robustness and standardization, which can be applied to deterministic execution strategies; when the temperature parameter is high, the randomness of the model output is enhanced, and the inference process can try low-frequency vocabulary units (i.e., unconventional code writing methods), adapting to explore innovative operator optimization schemes. This type of inference strategy has a high execution risk and can be applied to high-performance optimization strategies. Specific rule coverage strategies and hardware-aware strategies can choose a more moderate temperature parameter.

[0041] S230. After inputting the update prompt words for each large model in multiple working nodes carrying the same target large model, each working node is triggered to start executing the operator code generation task in parallel. The operator code generation task includes a series of code generation subtasks, code compilation subtasks and code verification subtasks.

[0042] S240. During the execution of tasks at each working node, if an execution exception is detected in the first node, the node shall first attempt to repair the execution exception by means of in-node repair. If it is determined that the execution exception cannot be repaired, the exception code in the first node shall be migrated to the second node for repair, and the repair code fed back by the second node shall be fed back to the first node to continue execution.

[0043] The first node can refer to any of the multiple parallel worker nodes whose exploration strategy employs a high-performance optimization strategy, a specific rule coverage strategy, or a hardware-aware strategy. The second node can refer to any of the multiple parallel worker nodes whose exploration strategy employs a deterministic execution strategy.

[0044] Understandably, when multiple worker nodes executing different exploration strategies perform operator code generation tasks in parallel, the task execution status of each worker node can be monitored and assisted in correction in real time. When an anomaly is detected in the code compilation subtask or code verification subtask executed by the first node using a high-performance optimization strategy, a specific rule coverage strategy, or a hardware-aware strategy, an anomaly repair strategy within the node can be implemented first. If it is determined that the first node cannot repair the execution anomaly, the abnormal operator code in the first node can be migrated to the second node for assisted repair. The second node repairs and generates new operator code according to the difference prompt words: "Perform strict logical reasoning based on input information, with correctness as the primary principle, without introducing additional complex instructions and irrelevant constraints, and only outputting objective and accurate reasoning results." After the second node completes the assisted repair, it feeds back the repaired operator code to the first node to continue executing the code compilation subtask and the code verification subtask, as well as cyclically executing subsequent operator code generation tasks.

[0045] Optionally, if an execution exception is detected in the first node, the exception should first be repaired using in-node repair methods, including: After detecting an execution exception in the first node, obtain the exception log information of the first node; Based on the exception type and description information recorded in the exception log of the first node, construct the exception repair model prompt words; Provide the large model prompt for anomaly repair to the first node so that the first node can continue to execute the built-in operator code generation task based on the large model prompt for anomaly repair; After confirming that the first node still exhibits execution anomalies after multiple attempts to send the large model prompt for anomaly repair to it, it was determined that the execution anomalies of the first node could not be repaired.

[0046] The first node exception log information can refer to the log information recorded when an execution exception occurs during the execution of the operator code generation task by a worker node employing a high-performance optimization strategy, a specific rule coverage strategy, or a hardware-aware strategy. The exception repair large model prompt word can refer to the current large model prompt word when an exception occurs during the execution of the operator code generation task in the worker node, and the large model prompt word generated after repair based on the exception situation.

[0047] Understandably, during the parallel execution of operator code generation tasks by multiple worker nodes employing different exploration strategies, when an execution anomaly is detected in the first node using a high-performance optimization strategy, a specific rule coverage strategy, or a hardware-aware strategy, the corresponding anomaly log information of the first node can be obtained. Based on the anomaly type and description information recorded therein, an appropriate anomaly handling strategy can be adopted. If an anomaly occurs during the execution of the code compilation subtask, the subtask is executed repeatedly. If an anomaly persists after a preset number of executions, a large-scale anomaly repair model prompt is constructed based on the anomaly description information. If an anomaly occurs during the execution of the code verification subtask, a large-scale anomaly repair model prompt is directly constructed based on the anomaly description information and provided to the first node. The code compilation and code verification subtasks within the built-in operator code generation task are then executed in sequence. If the in-node repair method is followed, and the first node continues to execute the operator code generation task after receiving the large-scale anomaly repair model prompt multiple times, and the number of anomalies reaches a preset number, it is determined that the execution anomaly of the first node cannot be repaired.

[0048] S250. During the execution of tasks by each working node, if it is detected that the operator code generated by the third node has been verified and meets the performance requirements, then a timer is started to count down within the target duration, and the target operator code with the best performance is selected from the operator codes that have been verified by each working node within the target duration.

[0049] The third node can refer to the first worker node among multiple parallel worker nodes that generate operator code that has been verified and meets performance requirements. The target duration can refer to the time threshold used to monitor the execution performance of the operator code generated by each parallel worker node.

[0050] Understandably, when any worker node in the parallel execution of the operator code generation task detects that the operator code generated by any worker node has been verified and meets the performance requirements, that worker node is designated as the third node and a timer is started synchronously to keep track for the target duration. Among the operator codes generated by each worker node within the target duration that have passed verification and meet the performance requirements, the operator code with the best performance is selected as the target operator code.

[0051] Optionally, a timer is started to run for the target duration, and the target operator code with the best performance is selected from all operator codes that have passed verification within the target duration at each working node, including: During the timer's timing within the target duration, the performance metrics of each operator code verified by each work node are monitored in real time, and the fluctuation error of the performance metrics of the operator code generated by each work node is checked to see if it does not exceed the performance metric fluctuation threshold within the preset monitoring duration. If so, the operator code with the highest performance index among all working nodes is selected as the target operator code; Otherwise, when the timer reaches the target duration, the operator code with the highest performance among the operator codes generated by each working node is selected as the target operator code.

[0052] Among them, the performance index fluctuation threshold can refer to the maximum allowable deviation of the actual value of the preset performance index from the benchmark performance index of the preset operator code. It can be used to determine whether the performance of the operator code meets the preset standard.

[0053] Understandably, when the operator code generated by the third node is verified and meets performance requirements, the timer starts and runs for the target duration. Simultaneously, it's necessary to monitor the performance metrics of the operator codes generated by each working node as they pass the code verification subtask, and to detect the fluctuation error of each verified operator code's performance metrics compared to a preset benchmark value. If the fluctuation error of each operator code's performance metrics does not exceed the performance metric fluctuation threshold within the preset monitoring duration, the operator code with the highest performance metric can be selected as the target operator code. If, when the timer reaches the target duration, the fluctuation error of each operator code's performance metrics still has not converged to the performance metric fluctuation threshold, the operator code with the highest performance metric among the verified and performance-compliant operators can be selected as the target operator code.

[0054] Based on the above embodiments, after extracting the adaptation requirement information for generating the target operator code in the operator code generation request, the method further includes: In a pre-built vector database, the adaptation requirement information is retrieved to obtain historical operator code information that meets the similarity requirements, and the historical operator code information is added to the adaptation requirement information. Among them, the historical operator code information includes the historical operator codes that have been verified and meet the performance requirements inferred from the target large model, as well as the operator code metadata that matches the historical operator codes; Correspondingly, after successfully obtaining the verified target operator code that meets the performance requirements in multiple working nodes, the process also includes: updating and saving the verified target operator code that meets the performance requirements obtained by each working node, as well as the operator code metadata that matches the target operator code, as historical operator code information to the vector database. Extract the process description information of each working node to generate the verified target operator code that meets the performance requirements, and input the process description information into the target large model for training.

[0055] In this context, a vector database can refer to a data management system used to store, retrieve, and manage high-dimensional vector data, and to achieve efficient querying based on vector similarity. Historical operator code refers to the target operator code generated by each working node in previous operator code generation tasks, which has passed verification and meets performance requirements. Operator code metadata refers to structured data describing the attributes, characteristics, and operational constraints of the target operator code, covering non-executable core information such as the hardware architecture to which the operator is adapted, input / output tensor specifications, performance benchmark values, and dependent hardware instruction sets. Process description information refers to structured procedural data recording the entire process of the target operator code, from inference generation based on preset constraints, to compilation and adaptation to the specified hardware architecture, and finally to verification of functional correctness and performance compliance, covering core content such as execution steps, parameter configurations, result feedback, and exception information at each stage.

[0056] Understandably, responding to an operator code generation request first requires extracting the adaptation requirement information for generating the target operator code. This adaptation requirement information can be retrieved from a pre-built vector database to obtain historical operator code information that meets the similarity requirements for generating the target operator code. This historical operator code information is then added to the adaptation requirement information for generating the target operator code. This ensures that the adaptation requirement information includes verified historical operator codes that have been inferred from the target large model and meet performance requirements, as well as operator code metadata that matches the historical operator codes. Based on the attributes, constraints, and input / output specifications contained within, standard large model prompt words are generated.

[0057] Accordingly, to ensure the updating of the vector library content, after each worker node generates verified target operator code that meets performance requirements, the target operator code and its matching metadata can be synchronously updated and saved to the vector database as historical operator code information. Additionally, the process description information for generating verified target operator code that meets performance requirements at each worker node can be extracted. The execution steps, parameter configurations, result feedback, and exception information at each stage of the target operator code generation process can be input into the target large model for training, making the target large model more adaptable to the target operator code generation tasks of various hardware platforms and scenario requirements.

[0058] This invention, through the aforementioned technical solution, can respond to operator code generation requests. It extracts adaptation requirement information for generating target operator code and retrieves historical operator code information that meets similarity requirements from a vector library. Based on multiple preset exploration strategies, it sets relevant temperature parameters and difference prompts to obtain multiple updated large model prompts corresponding to deterministic execution strategies, high-performance optimization strategies, specific rule coverage strategies, and hardware-aware strategies, respectively. Each updated large model prompt is input into multiple working nodes equipped with the same target large model for parallel processing. Each working node cyclically executes the operator code generation task. During this process, the task execution status of each working node is monitored and assisted in correction in real time. Abnormal operator code is processed through a combination of intra-node correction and node switching assistance until any working node successfully generates a verified target operator code with the optimal performance indicators in the preset performance detection strategy. This is then used as the response result to the operator code generation request. This technical solution optimizes the method of multiple working nodes generating different large model prompts according to different exploration strategies, improving the flexibility of abnormal operator code repair and the efficiency of selecting operator codes that meet performance indicators.

[0059] Example 3 Figure 3 This is a schematic diagram of an operator code generation device for a chip adaptation operator provided in Embodiment 3 of the present invention. Figure 3 As shown, the device includes: a request response module 310, a prompt word generation module 320, an operator code generation module 330, and a task monitoring module 340.

[0060] The request response module 310 is used to respond to the operator code generation request for the target operator, and extract the adaptation requirement information for generating the target operator code from the operator code generation request. The adaptation requirement information includes the operator type of the target operator, the target hardware platform to be adapted, the input and output tensor dimensions, and the performance requirements. The prompt word generation module 320 is used to obtain multiple updated large model prompt words corresponding to each exploration strategy based on the adaptation requirement information and multiple preset exploration strategies. The operator code generation module 330 is used to trigger the operator code generation task to be executed in parallel on each working node after inputting each update prompt word of the large model in multiple working nodes equipped with the same target large model; wherein, the operator code generation task includes a series of code generation subtasks, code compilation subtasks and code verification subtasks; The task monitoring module 340 is used to monitor and assist in correcting the task execution status in real time during the execution of tasks at each working node, until the target operator code that has been verified and meets the performance requirements is successfully obtained in multiple working nodes, and the target operator code is used as the response result of the operator code generation request.

[0061] This invention, through the aforementioned technical solution, can respond to operator code generation requests. It extracts the operator type and target hardware platform of the target operator from the adaptation requirement information used to generate the target operator code, along with the input / output tensor dimension and performance requirements. Based on multiple preset exploration strategies, it obtains multiple update large model hints corresponding to each strategy. These update large model hints are then input into multiple worker nodes equipped with the same target large model for parallel processing. Each worker node cyclically executes the operator code generation task, including a series of code generation sub-tasks, code compilation sub-tasks, and code verification sub-tasks. During the cyclical execution of the operator code generation task by each worker node, the task execution status of each worker node is monitored and assisted in correction in real time until any worker node successfully generates verified target operator code that meets the performance requirements. This is then used as the response result to the operator code generation request. This technical solution improves the reliability and efficiency of generating operator code adapted to different hardware platforms and enhances the utilization of computing resources by having multiple worker nodes execute the large model target operator code generation task in parallel.

[0062] Optionally, the prompt word generation module 320 can be specifically used to: generate standard large model prompt words based on adaptation requirement information; and select to directly use the standard large model prompt words or add differentiated instructions matching the strategy type to the standard large model prompt words to obtain multiple updated large model prompt words based on the strategy type of the exploration strategy.

[0063] Optionally, the prompt word generation module 320 can also be specifically used for: If the exploration strategy is a deterministic execution strategy, then the standard large model prompt words are directly used as the updated large model prompt words corresponding to the deterministic execution strategy. If the exploration strategy is a high-performance optimization strategy, then high-performance optimization instructions matching the required high-performance optimization dimension are constructed, and the high-performance optimization instructions are injected into the standard large model prompt words to obtain the updated large model prompt words corresponding to the high-performance optimization strategy. If the exploration strategy is a specific rule coverage strategy, then technology stack instructions matching the rules to be covered are constructed, and the technology stack instructions are injected into the standard large model prompt words to obtain the updated large model prompt words corresponding to the specific rule coverage strategy. If the exploration strategy is a hardware-aware strategy, then hardware defect avoidance instructions matching sensitive hardware are constructed, and the hardware defect avoidance instructions are injected into the standard large model prompt words to obtain the updated large model prompt words corresponding to the hardware-aware strategy.

[0064] Optionally, the task monitoring module 340 can be specifically used for the following: During the execution of tasks on each worker node, if an execution exception is detected on the first node, it first attempts to repair the exception using in-node repair methods. If it is determined that the exception cannot be repaired, the exception code in the first node is migrated to the second node for repair, and the repaired code from the second node is fed back to the first node for continued execution. During the execution of tasks on each worker node, if it is detected that the operator code generated by the third node has been verified and meets the performance requirements, a timer is started to run for the target duration, and the target operator code with the best performance is selected from the operator codes that have passed verification on each worker node within the target duration.

[0065] Optionally, the task monitoring module 340 can also be specifically used for: obtaining the first node's exception log information after detecting an execution exception in the first node; constructing a large-scale exception repair model prompt based on the exception type and description information recorded in the first node's exception log information; providing the large-scale exception repair model prompt to the first node so that the first node can continue to execute the built-in operator code generation task based on the large-scale exception repair model prompt; and determining that the first node's execution exception cannot be repaired after multiple attempts to send the large-scale exception repair model prompt to the first node have failed.

[0066] Optionally, the task monitoring module 340 can also be specifically used to: monitor in real time the performance indicators of each operator code that has passed verification at each working node during the timer's timing within the target duration, and detect whether the fluctuation error of the performance indicators of the operator codes generated by each working node does not exceed the performance indicator fluctuation threshold within the preset monitoring duration. If so, the operator code with the highest performance indicator among all working nodes is selected as the target operator code; otherwise, when the timer reaches the target duration, the operator code with the highest performance indicator among the operator codes generated by all working nodes is selected as the target operator code.

[0067] Optionally, it may also include a vector database retrieval module, which is used to retrieve adaptation requirement information in a pre-built vector database, obtain historical operator code information that meets similarity requirements, and add the historical operator code information to the adaptation requirement information. The historical operator code information includes verified historical operator codes that meet performance requirements and have been inferred historically by the target large model, as well as operator code metadata that matches the historical operator codes.

[0068] Optionally, a vector database update module may also be included, used to update and save the verified target operator code that meets performance requirements obtained by each working node, as well as the operator code metadata matching the target operator code, as historical operator code information to the vector database. The process description information of each working node generating the verified target operator code that meets performance requirements is extracted, and this process description information is input into the target large model for training.

[0069] The chip adaptation operator code generation device provided in this embodiment of the invention can execute the chip adaptation operator code generation method provided in any embodiment of the invention, and has the corresponding functional modules and beneficial effects of the execution method.

[0070] Example 4 Figure 4 A schematic diagram of an electronic device 10, which can be used to implement embodiments of the present invention, is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices (e.g., helmets, glasses, watches, etc.), and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the invention described and / or claimed herein.

[0071] like Figure 4 As shown, the electronic device 10 includes at least one processor 11 and a memory, such as a read-only memory (ROM) 12 or a random access memory (RAM) 13, communicatively connected to the at least one processor 11. The memory stores computer programs executable by the at least one processor. The processor 11 can perform various appropriate actions and processes based on the computer program stored in the ROM 12 or loaded from storage unit 18 into the RAM 13. The RAM 13 can also store various programs and data required for the operation of the electronic device 10. The processor 11, ROM 12, and RAM 13 are interconnected via a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0072] Multiple components in electronic device 10 are connected to I / O interface 15, including: input unit 16, such as keyboard, mouse, etc.; output unit 17, such as various types of displays, speakers, etc.; storage unit 18, such as disk, optical disk, etc.; and communication unit 19, such as network card, modem, wireless transceiver, etc. Communication unit 19 allows electronic device 10 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0073] Processor 11 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. Processor 11 performs the various methods and processes described above, such as operator code generation methods for chip-adaptive operators.

[0074] That is, in response to the operator code generation request for the target operator, the adaptation requirement information for generating the target operator code is extracted from the operator code generation request. The adaptation requirement information includes the operator type of the target operator, the target hardware platform to be adapted, the input and output tensor dimensions, and the performance requirements. Based on the adaptation requirements and multiple preset exploration strategies, multiple updated large model prompt words corresponding to each exploration strategy are obtained; After inputting the update prompt words for each large model in multiple worker nodes carrying the same target large model, each worker node is triggered to start cyclically executing the operator code generation task in parallel; the operator code generation task includes a series of code generation subtasks, code compilation subtasks and code verification subtasks; During the execution of tasks at each worker node, the task execution status is monitored and assisted in correction in real time until the target operator code that has been verified and meets the performance requirements is successfully obtained in multiple worker nodes, and the target operator code is used as the response result of the operator code generation request.

[0075] In some embodiments, the operator code generation method for the chip adapter operator can be implemented as a computer program tangibly contained in a computer-readable storage medium, such as storage unit 18. In some embodiments, part or all of the computer program can be loaded and / or installed on the electronic device 10 via ROM 12 and / or communication unit 19. When the computer program is loaded into RAM 13 and executed by processor 11, one or more steps of the operator code generation method for the chip adapter operator described above can be performed. Alternatively, in other embodiments, processor 11 can be configured to execute the operator code generation method for the chip adapter operator by any other suitable means (e.g., by means of firmware).

[0076] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0077] Computer programs used to implement the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when executed by the processor, the computer programs cause the functions / operations specified in the flowcharts and / or block diagrams to be performed. The computer programs may be executed entirely on a machine, partially on a machine, or as a standalone software package, partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0078] In the context of this invention, a computer-readable storage medium can be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, apparatus, or device. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination thereof. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0079] To provide interaction with a user, the systems and techniques described herein can be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the electronic device. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0080] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or middleware components (e.g., application servers), or frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., communication networks). Examples of communication networks include local area networks (LANs), wide area networks (WANs), blockchain networks, and the Internet.

[0081] A computing system can include clients and servers. Clients and servers are generally located far apart and typically interact through communication networks. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. The server can be a cloud server, also known as a cloud computing server or cloud host, which is a hosting product within the cloud computing service system to address the shortcomings of traditional physical hosts and VPS services, such as high management difficulty and weak business scalability.

[0082] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0083] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A method for generating operator code for a chip adaptation operator, characterized in that, include: In response to the operator code generation request for the target operator, the adaptation requirement information for generating the target operator code is extracted from the operator code generation request. The adaptation requirement information includes the operator type of the target operator, the target hardware platform to be adapted, the input and output tensor dimensions, and the performance requirements. Based on the adaptation requirements and multiple preset exploration strategies, multiple updated large model prompt words corresponding to each exploration strategy are obtained; After inputting the update prompt words for each large model in multiple worker nodes carrying the same target large model, each worker node is triggered to start cyclically executing the operator code generation task in parallel; the operator code generation task includes a series of code generation subtasks, code compilation subtasks and code verification subtasks; During the execution of tasks at each worker node, the task execution status is monitored and assisted in correction in real time until the target operator code that has been verified and meets the performance requirements is successfully obtained in multiple worker nodes, and the target operator code is used as the response result of the operator code generation request.

2. The method according to claim 1, characterized in that, Based on the adaptation requirements and multiple preset exploration strategies, several update prompts for the large model are obtained, each corresponding to a different exploration strategy, including: Generate standard large-model prompt words based on adaptation requirements; Depending on the strategy type of the exploration strategy, multiple updated large model hints can be obtained by either directly using standard large model hints or by adding differentiated instructions that match the strategy type to the standard large model hints.

3. The method according to claim 2, characterized in that, Depending on the strategy type of the exploration strategy, multiple updated large model hints are obtained by choosing between directly using standard large model hints or adding differentiated instructions matching the strategy type to the standard large model hints, including: If the exploration strategy is a deterministic execution strategy, then the standard large model cue words are used directly as the update large model cue words corresponding to the deterministic execution strategy; If the exploration strategy is a high-performance optimization strategy, then construct a high-performance optimization instruction that matches the required high-performance optimization dimension, and inject the high-performance optimization instruction into the standard large model hint words to obtain the updated large model hint words corresponding to the high-performance optimization strategy. If the exploration strategy is a specific rule coverage strategy, then construct the technology stack instructions that match the rules to be covered, and inject the technology stack instructions into the standard large model prompt words to obtain the updated large model prompt words corresponding to the specific rule coverage strategy; If the exploration strategy is a hardware-aware strategy, then a hardware defect avoidance instruction matching the sensitive hardware is constructed, and the hardware defect avoidance instruction is injected into the standard large model hint words to obtain the updated large model hint words corresponding to the hardware-aware strategy.

4. The method according to claim 1, characterized in that, During task execution at each worker node, the task execution status is monitored and assisted in correction in real time until the verified target operator code that meets performance requirements is successfully obtained from multiple worker nodes, including: During the execution of tasks at each work node, if an execution exception is detected in the first node, the node will first attempt to repair the execution exception using the in-node repair method. If it is determined that the execution exception cannot be repaired, the exception code in the first node will be migrated to the second node for repair, and the repair code fed back by the second node will be fed back to the first node to continue execution. During the execution of tasks at each worker node, if it is detected that the operator code generated by the third node has been verified and meets the performance requirements, a timer is started to count down within the target duration, and the target operator code with the best performance is selected from all the operator codes that have been verified by each worker node within the target duration.

5. The method according to claim 4, characterized in that, If an execution exception is detected in the first node, the system will first attempt to repair the exception using in-node repair methods, including: After detecting an execution exception in the first node, obtain the exception log information of the first node; Based on the exception type and description information recorded in the exception log of the first node, construct the exception repair model prompt words; Provide the large model prompt for anomaly repair to the first node so that the first node can continue to execute the built-in operator code generation task based on the large model prompt for anomaly repair; After confirming that the first node still exhibits execution anomalies after multiple attempts to send the large model prompt for anomaly repair to it, it was determined that the execution anomalies of the first node could not be repaired.

6. The method according to claim 4, characterized in that, Start a timer to run for the target duration, and select the target operator code with the best performance from all operator codes that have passed verification within the target duration for each worker node, including: During the timer's timing within the target duration, the performance metrics of each operator code verified by each work node are monitored in real time, and the fluctuation error of the performance metrics of the operator code generated by each work node is checked to see if it does not exceed the performance metric fluctuation threshold within the preset monitoring duration. If so, the operator code with the highest performance index among all working nodes is selected as the target operator code; Otherwise, when the timer reaches the target duration, the operator code with the highest performance among the operator codes generated by each working node is selected as the target operator code.

7. The method according to any one of claims 1-6, characterized in that, After extracting the adaptation requirement information for generating the target operator code from the operator code generation request, it also includes: In a pre-built vector database, the adaptation requirement information is retrieved to obtain historical operator code information that meets the similarity requirements, and the historical operator code information is added to the adaptation requirement information. Among them, the historical operator code information includes the historical operator codes that have been verified and meet the performance requirements inferred from the target large model, as well as the operator code metadata that matches the historical operator codes; Correspondingly, after successfully obtaining the verified target operator code that meets the performance requirements in multiple working nodes, the process also includes: updating and saving the verified target operator code that meets the performance requirements obtained by each working node, as well as the operator code metadata that matches the target operator code, as historical operator code information to the vector database. Extract the process description information of each working node to generate the verified target operator code that meets the performance requirements, and input the process description information into the target large model for training.

8. An electronic device, characterized in that, The electronic device includes: At least one processor; and A memory communicatively connected to the at least one processor; wherein, The memory stores a computer program that can be executed by the at least one processor, the computer program being executed by the at least one processor to enable the at least one processor to perform the automatic operator code generation method according to any one of claims 1-7.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions that cause a processor to execute the automatic operator code generation method according to any one of claims 1-7.

10. A computer program product, characterized in that, The computer program product includes a computer program that, when executed by a processor, implements the automatic operator code generation method according to any one of claims 1-7.

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