A wireless swd debugging and burning system and method for a collaborative arm

Abstract

This invention relates to the technical field of program burning, and discloses a wireless SWD debugging and burning system and method for a collaborative arm. The wireless SWD debugging and burning method, applied to an SWD debugging and burning device, specifically includes the following steps: S101: Receiving a debugging and burning command sent by a host computer, and setting the embedded pins on the wireless debugging adapter of the ESP32 module. This invention, through a wireless gateway and software protocol simulator built around the ESP32 module, successfully upgrades the debugging and burning link, which previously relied on physical cables and dedicated hardware debuggers, to a fully wireless method. This eliminates the need for technicians to disassemble the device casing for each operation, completely avoiding mechanical wear and sealing failure caused by repeated disassembly and reassembly.

Description

Technical Field

[0001] This invention relates to the technical field of program burning, and more specifically, to a wireless SWD debugging and burning system and method for a collaborative arm. Background Technology

[0002] Currently, for embedded devices such as collaborative arms, robots, and their servo drivers that use ARM Cortex series cores as the main control unit, wired connection technology based on serial line debugging protocols is commonly relied upon during the software development and hardware debugging phases. This technology system is centered around a dedicated hardware debugger. One end of the debugger is connected to a personal computer running an integrated development environment (IDE) via a USB interface, while the other end is connected to the SWD interface pre-exposed on the target device's circuit board via a set of physical cables. The SWD protocol, with its simplicity of requiring only the SWCLK clock line and the SWDIO bidirectional data line, has become the de facto standard for online debugging and program burning of ARM core chips. In the graphical interface of the IDE, developers can perform operations such as downloading firmware, single-stepping, setting breakpoints, and viewing register and memory contents. All debugging commands and data are transmitted between the debugger and the debug access port of the target chip through this physical link.

[0003] Although the aforementioned wired debugging mode performs stably in a controlled development environment, its inherent physical connection characteristics introduce significant limitations in actual system debugging, production programming, and field maintenance scenarios: (1) In order to connect to the test line, the operator must disassemble the equipment casing. This process is not only tedious and time-consuming, increasing the labor cost of production and maintenance, but also accelerates the wear of the interface, stripping of screws and aging of seals in repeated disassembly and assembly, causing cumulative damage to the integrity of the equipment structure. (2) The cable tightly binds the debugging equipment to the target equipment in physical space, forcing the programmer or debugging computer to be placed close to the target equipment. When debugging high-voltage drivers, moving robotic arms or modules in complex assemblies, this close-range operation exposes technicians to potential dangers such as electric shock and mechanical collision, raising concerns about safety. (3) The existing technical solution has a functional breakpoint: it cannot maintain a real-time debugging connection to the CPU core while using the wireless network to burn the program. This means that if the developer wants to use the device’s existing Wi-Fi module to upgrade the firmware wirelessly, they will lose the ability to set breakpoints and single-step tracing in the process. Conversely, if they want to perform in-depth debugging, they must return to a wired connection. This artificial separation between the “wireless burning” and “online debugging” functions limits the possibility of remote problem diagnosis and in-depth repair through the wireless network after the device is deployed, and cannot meet the growing demand of intelligent devices for remote, non-intrusive maintenance. Summary of the Invention

[0004] The purpose of this invention is to provide a wireless SWD debugging and programming system and method for a collaborative arm. By using a wireless gateway and software protocol simulator built with the ESP32 module as the core, the debugging and programming link that previously relied on physical cables and dedicated hardware debuggers has been successfully upgraded to a fully wireless method. This eliminates the need for technicians to disassemble the device casing for each operation, completely avoiding mechanical wear and sealing failure caused by repeated disassembly and assembly.

[0005] This invention is implemented as follows: a wireless SWD debugging and programming method for a collaborative arm, applied to an SWD debugging and programming device, specifically includes the following steps: S101: Receives the debugging and programming command sent by the host computer and directly connects the embedded pins set by the wireless debugging adapter of the ESP32 module to the SWD interface pins on the target circuit board inside the collaborative arm driver. Some GPIOs of the ESP32 module are pre-configured as SWDIO and SWCLK functions to establish a low-level signal channel with the target ARM CPU. S102: Establish a wireless communication link based on Wi-Fi TCP / IP protocol between the host computer and the ESP32 module. The host computer runs a standard IDE development environment, and the ESP32 module acts as a wireless gateway and protocol conversion node, opening the TCP / IP server listening port. S103: After receiving a data packet from the wireless communication link, the firmware running in the ESP32 module extracts features from the data packet and converts the extracted features into SWD protocol instructions that follow the ARM CoreSight timing. The software drives GPIO to accurately simulate the behavior of the hardware debugger. S104: The SWD protocol instruction generated after protocol conversion is directly applied to the SWD pin of the target ARM CPU through the embedded pin, establishing a complete debugging and programming communication link. The host computer IDE can transparently perform online debugging operations on the ARM CPU in the cooperating arm driver, just like operating a local wired debugger. S105: In mass production scenarios, the host computer can simultaneously establish independent connections with multiple wireless debugging adapters deployed on multiple collaborative arms or drivers. Through the host computer software, it can selectively send the same or different firmware data packets and burning instructions to multiple target devices. Each ESP32 module completes its own protocol conversion and signal driving tasks in parallel, realizing the simultaneous batch wireless burning and debugging of multiple devices.

[0006] Furthermore, in S101, the debugging and programming commands sent by the host computer are received, including: The system receives a connection request sent by the host computer through a preset network. The connection request is used to request the establishment of a connection with the SWD debugging and burning device. Detect whether the current account on the host computer is the target account; If the current account of the host computer is the target account, then a connection is established with the host computer according to the connection request. After the connection is established, the debugging and burning instructions sent by the host computer are received.

[0007] Furthermore, some GPIOs of the ESP32 module are pre-configured as SWDIO and SWCLK functions to establish low-level signal channels with the target ARM CPU, including: At the hardware connection level, two sets of general-purpose input / output pins with high-speed response and precise timing control capabilities were selected on the ESP32 module and connected to the SWDIO and SWCLK test points corresponding to the ARM CPU on the target device board through physical circuits. During the firmware initialization phase, these two sets of pins are configured to specific digital modes. The GPIO used for analog clock is set to high-precision push-pull output to ensure the generation of a stable and clear clock signal. The GPIO used for bidirectional data communication is set to quasi-bidirectional or open-drain mode that can switch directions in real time, and is equipped with pull-up resistors to accurately simulate the read and write timing requirements of the SWDIO line and establish a reliable underlying electrical connection channel. At the software driver level, nanosecond-level precise operations on these two connected GPIOs are achieved by writing low-level pin control functions. For the SWCLK line, the high-resolution timer of the ESP32 or hardware peripherals are used to generate a standard clock pulse sequence with adjustable frequency and constant duty cycle. For the SWDIO line, the data direction of the pin is switched on time at each specific phase of SWCLK, and the corresponding data bits are read or written, strictly following the serial communication waveform defined by the ARM CoreSight debugging architecture.

[0008] Furthermore, in S102, a wireless communication link based on the Wi-Fi TCP / IP protocol is established between the host computer and the ESP32 module, including: The host computer runs a dedicated driver or configuration tool, broadcasts a discovery request in the local wireless network or locates the TCP server port opened by the ESP32 module through a pre-configured target IP address, and then the host computer actively initiates a TCP connection request. After completing the standard three-way handshake to establish a reliable transport layer connection, it immediately performs an application layer handshake and authentication. After the application layer handshake and authentication are completed, the debugging operations of the host computer's debugger will be encapsulated by the underlying driver into raw data packets with a specific frame structure. Each data packet contains a frame header, command code, data payload, and CRC checksum. The encapsulated data packets are then continuously sent to the ESP32 module through the network socket connection.

[0009] Furthermore, in S103, feature extraction is performed on the data packets, and the extracted features are converted into SWD protocol instructions conforming to the ARMCoreSight timing, including: The built-in command and data parser unpacks, verifies, and reassembles TCP / IP data streams to extract standard debugger command sequences. Through the real-time processing capabilities of a precisely programmed software protocol simulator, a precise SWCLK clock signal is generated and output in real time on GPIO pins configured for SWD function, according to the SWD protocol communication timing defined by the ARM CoreSight architecture. By synchronously performing serial input and output of data on the SWDIO data line, the hardware SWD interface behavior of the traditional wired debugger is completely and reliably simulated at the software level, realizing the protocol conversion from wireless signal to wired SWD protocol.

[0010] Furthermore, in S104, the SWD protocol instructions generated after protocol conversion are directly applied to the SWD pin of the target ARM CPU via embedded pins, establishing a complete debugging and programming communication link, including: The ESP32 module receives and parses instructions from the host computer in real time. As a coprocessor, it accurately executes core debugging functions, including memory and register read and write, setting hardware / software breakpoints, controlling single-step execution of the program, and monitoring variable values. At the same time, it fully handles the chip erasure, programming, and verification processes required for firmware burning. After executing each instruction, the ESP32 synchronously collects the response data returned by the target CPU through the SWD interface, reassembles it according to the protocol specifications, adds the necessary sequence number and status information, encapsulates it into a data packet, and reliably transmits it back to the host computer through the established Wi-Fi TCP link to complete the complete data interaction.

[0011] Furthermore, in S105, during mass production, the host computer can simultaneously establish independent connections with wireless debugging adapters deployed on multiple collaborating arms or drivers, including: In the production line environment, the host computer runs central control software, which actively discovers all online ESP32 wireless debugging adapters in the network by scanning preset IP address ranges or receiving multicast heartbeat packets, assigns an independent logical session identifier to each adapter, and initiates and maintains multiple parallel TCP connections to build a stable star topology network structure. The host computer's software maintains a dynamic connection pool and device status table, monitors the communication quality and adapter working status of each link in real time, and ensures that command interaction and data transmission with each adapter are logically independent and do not block each other through multi-threaded or asynchronous I / O technology, providing a parallel communication channel guarantee for subsequent synchronous or differentiated batch burning and debugging tasks.

[0012] Furthermore, the host computer's software maintains the dynamic connection pool and device status table, and monitors the communication quality and adapter operating status of each link in real time, including: During the system initialization phase, the software on the host computer creates and maintains a TCP connection resource pool based on the number of wireless adapters detected by the scan and the preset concurrency threshold. The TCP connection resource pool keeps the link active by periodically sending heartbeat data packets. At the same time, the TCP connection resource pool can dynamically allocate or reclaim connection resources according to the current queue status of batch tasks. The host computer's software creates a device status table in memory for each established adapter, which records the device ID, IP address, connection handle, and other static information, as well as continuously updates real-time working indicators. By monitoring threads polling and analyzing real-time working indicators, the system proactively identifies network anomalies or unresponsive devices and triggers predefined reconnection or alarm processes.

[0013] Compared with the prior art, the wireless SWD debugging and programming system and method for collaborative arms provided by the present invention have the following beneficial effects: 1. By using a wireless gateway and software protocol simulator built around the ESP32 module, the debugging and programming link that previously relied on physical cables and dedicated hardware debuggers was successfully upgraded to a fully wireless method. This eliminates the need for technicians to disassemble the equipment casing for each operation, completely avoiding mechanical wear and sealing failure caused by repeated disassembly and assembly. At the same time, it achieves physical isolation between operators and the equipment body, eliminating the risk of electric shock and mechanical injury from close-range debugging near high voltage and moving parts. The software accurately simulates the SWD hardware timing that originally required a dedicated chip on a general-purpose microcontroller, fully reproducing all the functions of the wired debugger in a wireless environment. 2. The constructed star-topology wireless network and host computer batch management module enable parallel and centralized programming and debugging of multiple devices on the production line, greatly improving the efficiency of mass production. As an independent middleware, the system maintains high compatibility with standard host computer debuggers and target devices. Users can seamlessly integrate without changing their existing development habits and hardware designs, significantly reducing technology migration costs. In addition, the compact embedded adapter design frees up valuable internal space resources, providing the possibility for further optimization of the product structure. It also achieves functional substitution and comprehensively surpasses traditional technologies in multiple dimensions such as operational safety, production efficiency, and system flexibility.

[0014] A wireless SWD debugging and programming system for a collaborative arm, used to perform the above-described debugging and programming method, the system comprising: The wireless communication module is used to establish a wireless connection with the host computer based on the Wi-Fi TCP / IP protocol and transmit data. The protocol conversion module is used to receive and parse the debugging and programming instructions and data from the host computer, and convert them into SWD protocol command sequences that conform to the ARM CoreSight standard. The signal driving module is used to convert the SWD protocol command sequence into a SWCLK clock signal and a SWDIO data signal with precise timing through a precisely configured GPIO interface, so as to drive the target ARM CPU. The batch management module is used to establish and maintain multiple independent concurrent connections with wireless debugging adapters deployed on multiple target devices, enabling centralized control and parallel programming and debugging of multiple devices.

[0015] Specifically, the protocol conversion module includes: The command and data parsing unit is used to unpack, verify, and reassemble the received TCP / IP data stream to extract standard debugger commands; The software protocol simulation unit is used to convert the debugger commands into corresponding SWD protocol bit streams in real time according to the communication timing defined by the ARM CoreSight architecture. Attached Figure Description

[0016] Figure 1 This is a flowchart of a wireless SWD debugging and programming method for a collaborative arm proposed in this invention. Figure 2 This is a schematic diagram of the structure of a wireless SWD debugging and programming system for a collaborative arm proposed in this invention. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0018] The implementation of the present invention will be described in detail below with reference to specific embodiments.

[0019] In the accompanying drawings of this embodiment, the same or similar reference numerals correspond to the same or similar components. In the description of this invention, it should be understood that if terms such as "upper," "lower," "left," and "right" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, they are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, the terms used to describe positional relationships in the drawings are only for illustrative purposes and should not be construed as limiting this invention. For those skilled in the art, the specific meaning of the above terms can be understood according to the specific circumstances.

[0020] Reference Figure 1 As shown, a wireless SWD debugging and programming method for a collaborative arm, applied to an SWD debugging and programming device, specifically includes the following steps: S101: Receives debugging and programming commands sent by the host computer and directly connects the embedded pins of the wireless debugging adapter of the ESP32 module to the SWD interface pins on the target circuit board inside the collaborative arm driver. This compact connection method avoids the space requirements of external cables and large interfaces, allowing the adapter to be permanently embedded in the device, laying the hardware foundation for debugging without removing the cover; some GPIOs of the ESP32 module are pre-configured as SWDIO and SWCLK functions to establish a low-level signal channel with the target ARM CPU. Among them, receiving debugging and programming commands sent by the host computer includes: The system receives connection requests from the host computer via a preset network. These connection requests are used to request the establishment of a connection with the SWD debugging and programming device. Check if the current account on the host computer is the target account; If the current account on the host computer is the target account, a connection is established with the host computer according to the connection request. After the connection is established, the debugging and programming instructions sent by the host computer are received. This authentication mechanism effectively prevents unauthorized access and debugging of unauthorized devices, and improves the security and controllability of the entire programming and debugging process. S102: A wireless communication link based on the Wi-Fi TCP / IP protocol is established between the host computer and the ESP32 module. The host computer runs a standard IDE development environment, and the ESP32 module acts as a wireless gateway and protocol conversion node, opening the TCP / IP server listening port. This creates a reliable data channel that replaces physical cables, allowing debugging operations to be performed at a distance, fundamentally eliminating the safety risks caused by operators needing to be close to the equipment. The wireless communication link based on the Wi-Fi TCP / IP protocol is established between the host computer and the ESP32 module, including: The host computer runs a dedicated driver or configuration tool, broadcasts a discovery request in the local wireless network or locates the TCP server port opened by the ESP32 module through a pre-configured target IP address. Then, the host computer actively initiates a TCP connection request. After completing the standard three-way handshake to establish a reliable transport layer connection, it immediately performs an application layer handshake and authentication. This connection establishment process combines automatic discovery and security authentication, which simplifies the user configuration steps while ensuring the legitimacy and robustness of the connection establishment. After the application layer handshake and authentication are completed, the debugging operations of the host computer's debugger will be encapsulated into raw data packets with a specific frame structure by the underlying driver. Each data packet contains a frame header, command code, data payload, and CRC checksum. The encapsulated data packets are then continuously sent to the ESP32 module through the network socket. This data encapsulation and verification mechanism ensures the integrity and correctness of the debugging commands and firmware data transmitted in the unreliable wireless channel, providing reliable data transmission services for the upper-layer debugging logic. S103: After the firmware running in the ESP32 module receives a data packet from the wireless communication link, it extracts features from the data packet and converts the extracted features into SWD protocol instructions that follow the ARM CoreSight timing. The software drives GPIO to accurately simulate the behavior of the hardware debugger. This core conversion process uses the software capabilities of a general-purpose microcontroller to replace a dedicated debug chip, which greatly reduces system cost and complexity while achieving full-function debugging. S104: The SWD protocol instruction generated after protocol conversion is directly applied to the SWD pin of the target ARM CPU through the embedded pin, establishing a complete debugging and programming communication link. The host computer IDE can transparently perform online debugging operations on the ARM CPU in the collaborative arm driver, just like operating a local wired debugger. This realizes lossless access to core debugging resources such as memory, registers, and breakpoints under wireless connection, making remote debugging functionally completely equivalent to the traditional wired method. S105: In mass production scenarios, the host computer can simultaneously establish independent connections with multiple wireless debugging adapters deployed on multiple collaborating arms or drivers. Through the host computer software, it selectively sends the same or different firmware data packets and burning instructions to multiple target devices. Each ESP32 module completes its own protocol conversion and signal driving tasks in parallel, enabling simultaneous batch wireless burning and debugging of multiple devices. This parallel processing architecture improves the efficiency of traditional serial burning by several times, making it particularly suitable for mass production line operations and significantly shortening the production and testing cycle. The constructed star-topology wireless network and the host computer's batch management module make parallel and centralized burning and debugging of multiple devices on the production line possible, greatly improving the efficiency of mass production. Furthermore, as an independent middleware, the system maintains high compatibility with standard host computer debuggers and target devices, allowing users to seamlessly integrate without changing existing development habits and hardware designs, significantly reducing technology migration costs. In addition, the compact embedded adapter design frees up valuable internal space resources, providing possibilities for further product structure optimization and functional substitution. Moreover, it achieves a comprehensive leap forward over traditional technologies in multiple dimensions, including operational safety, production efficiency, and system flexibility.

[0021] In S101 of this embodiment, some GPIOs of the ESP32 module are pre-configured as SWDIO and SWCLK functions to establish a low-level signal channel with the target ARM CPU, including: At the hardware connection level, two sets of general-purpose input / output pins with high-speed response and precise timing control capabilities were selected on the ESP32 module and connected to the SWDIO and SWCLK test points corresponding to the ARM CPU on the target device board through physical circuits. During the firmware initialization phase, these two sets of pins are configured to specific digital modes. The GPIO used for analog clock is set to high-precision push-pull output to ensure the generation of a stable and clear clock signal. The GPIO used for bidirectional data communication is set to quasi-bidirectional or open-drain mode that can switch directions in real time, and is equipped with pull-up resistors to accurately simulate the read and write timing requirements of the SWDIO line and establish a reliable underlying electrical connection channel. This hardware and software co-configuration method ensures that the SWD signal converted in the wireless link has electrical characteristics and timing accuracy comparable to wired connections, thus guaranteeing the reliability of communication. At the software driver level, nanosecond-level precise operations on these two connected GPIOs are achieved by writing low-level pin control functions. For the SWCLK line, the high-resolution timer of the ESP32 or hardware peripherals are used to generate a standard clock pulse sequence with adjustable frequency and constant duty cycle. For the SWDIO line, the data direction of the pin is switched on time at each specific phase of SWCLK, and the corresponding data bits are read or written. The serial communication waveform defined by the ARM CoreSight debugging architecture is strictly followed. This low-level driver achieves the ultimate time accuracy of protocol simulation and is compatible with the subtle differences in SWD timing of different manufacturers and different series of ARM chips, ensuring the wide applicability of the system.

[0022] In S103 of this embodiment, feature extraction is performed on the data packet, and the extracted features are converted into SWD protocol instructions that conform to the ARMCoreSight timing sequence, including: The built-in command and data parser unpacks, verifies, and reassembles the TCP / IP data stream, extracting standard debugger command sequences. This parsing process ensures the accurate reproduction of the host computer's complex debugging intentions, providing correct input for subsequent precise protocol simulation. Through the real-time processing capability of the precisely programmed software protocol simulator, a precise SWCLK clock signal is generated and output in real time on the GPIO pins configured for SWD function, according to the SWD protocol communication timing defined by the ARM CoreSight architecture. This realizes the software synthesis of the clock signal, and its frequency and stability are the cornerstone for ensuring the normal operation of the entire SWD link. By synchronously performing serial input and output of data on the SWDIO data line, the hardware SWD interface behavior of the traditional wired debugger is completely and reliably simulated at the software level. This enables the protocol conversion from wireless signal to wired SWD protocol, and ultimately completes the final conversion from network data packets to physical layer debug signals. This is the core technological breakthrough of this solution in achieving full-function wireless debugging.

[0023] In S104 of this embodiment, the SWD protocol instruction generated after protocol conversion is directly applied to the SWD pin of the target ARM CPU through the embedded pin, establishing a complete debugging and programming communication link, including: The ESP32 module receives and parses instructions from the host computer in real time. As a coprocessor, it accurately executes core debugging functions, including memory and register read and write, setting hardware / software breakpoints, controlling single-step execution of the program, and monitoring variable values. At the same time, it completely handles the chip erasure, programming, and verification processes required for firmware burning. This proves that the wireless adapter has the ability to handle complex debugging tasks and complete the burning process, and its functionality has reached the level of a professional debugger. After executing each instruction, the ESP32 synchronously collects the response data returned by the target CPU through the SWD interface, reassembles it according to the protocol specifications, adds the necessary sequence number and status information, encapsulates it into a data packet, and reliably transmits it back to the host computer through the established Wi-Fi TCP link to complete the complete data interaction. This two-way interaction mechanism ensures the real-time performance and visibility of the debugging process, enabling engineers to obtain the chip status in real time and make accurate judgments.

[0024] In S105 of this embodiment, during mass production, the host computer can simultaneously establish independent connections with wireless debugging adapters deployed on multiple collaborating arms or drivers, including: In the production line environment, the host computer runs central control software. By scanning preset IP address ranges or receiving multicast heartbeat packets, it actively discovers all online ESP32 wireless debugging adapters in the network, assigns an independent logical session identifier to each adapter, and initiates and maintains multiple parallel TCP connections to build a stable star topology network structure. This automatic discovery and connection management function greatly simplifies the complexity of multi-device deployment and maintenance, and provides infrastructure for centralized control. The host computer's software maintains a dynamic connection pool and device status table, monitors the communication quality and adapter working status of each link in real time, and ensures that command interaction and data transmission with each adapter are logically independent and do not block each other through multi-threaded or asynchronous I / O technology. This provides a parallel communication channel guarantee for subsequent execution of synchronous or differentiated batch burning and debugging tasks. This resource management and status monitoring mechanism ensures the overall stability and efficiency of the system during batch operations and avoids the overall process from stopping due to the failure of a single device. The host computer's software maintains the dynamic connection pool and device status table, and monitors the communication quality and adapter working status of each link in real time, including: During the system initialization phase, the host computer's software creates and maintains a TCP connection resource pool based on the number of wireless adapters detected by the scan and the preset concurrency threshold. The TCP connection resource pool keeps the links active by periodically sending heartbeat data packets. At the same time, the TCP connection resource pool can dynamically allocate or reclaim connection resources according to the current queue status of batch tasks. This intelligent connection pool management optimizes network resource utilization, reduces the overhead of connection establishment and disconnection, and improves system response speed and throughput. The host computer's software creates a device status table in memory for each established adapter, which records the device ID, IP address, connection handle, and other static information, as well as continuously updates real-time operating metrics. By monitoring threads polling and analyzing real-time operating metrics, the system proactively identifies network anomalies or unresponsive devices and triggers predefined reconnection or alarm processes. This proactive health monitoring and fault handling mechanism significantly improves the robustness and automation of the mass production system and reduces the need for manual intervention.

[0025] This technical solution successfully upgrades the debugging and programming link, which previously relied on physical cables and dedicated hardware debuggers, to a fully wireless method by using a wireless gateway and software protocol simulator built around the ESP32 module. This eliminates the need for technicians to disassemble the device casing for each operation, completely avoiding mechanical wear and sealing failure caused by repeated disassembly and assembly. At the same time, it achieves physical isolation between operators and the device itself, eliminating the risk of electric shock and mechanical injury from close-range debugging near high voltage and moving parts. Through software, the SWD hardware timing, which originally required a dedicated chip, is accurately simulated on a general-purpose microcontroller, completely reproducing all the functions of the wired debugger in a wireless environment.

[0026] Reference Figure 2 As shown, a wireless SWD debugging and programming system for a collaborative arm is used to execute the above-mentioned debugging and programming method. The system includes: a wireless communication module for establishing a wireless connection with a host computer based on the Wi-Fi TCP / IP protocol and transmitting data; a protocol conversion module for receiving and parsing debugging and programming instructions and data from the host computer, and converting them into SWD protocol command sequences conforming to the ARM CoreSight standard; a signal driving module for converting the SWD protocol command sequences into SWCLK clock signals and SWDIO data signals with precise timing through a precisely configured GPIO interface to drive the target ARM CPU; and a batch management module for establishing and maintaining multiple independent concurrent connections with wireless debugging adapters deployed on multiple target devices, realizing centralized control and parallel programming and debugging of multiple devices, achieving physical isolation between operators and the equipment body, eliminating the risk of electric shock and mechanical injury from close-range debugging near high voltage and moving parts, and accurately simulating the SWD hardware timing that originally required a dedicated chip on a general-purpose microcontroller through software, thus completely replicating all the functions of a wired debugger in a wireless environment.

[0027] In this embodiment, the protocol conversion module includes: The command and data parsing unit unpacks, verifies, and reassembles received TCP / IP data streams to extract standard debugger commands. The software protocol simulation unit converts debugger commands into corresponding SWD protocol bitstreams in real time, according to the communication timing defined by the ARM CoreSight architecture. The constructed star-topology wireless network and the host computer batch management module enable parallel and centralized programming and debugging of multiple devices on the production line, greatly improving the efficiency of mass production. Furthermore, as an independent middleware, the system maintains high compatibility with standard host computer debuggers and target devices, allowing users to seamlessly integrate without changing existing development habits and hardware designs, significantly reducing technology migration costs. This technical solution's compact embedded adapter design frees up valuable internal space resources, enabling further optimization of the product structure. It also achieves functional substitution and surpasses traditional technologies in multiple dimensions, including operational safety, production efficiency, and system flexibility.

[0028] In this embodiment, the entire operation process can be controlled by a computer to provide signal feedback and implement the steps sequentially. These are all conventional knowledge in current automation control, and will not be elaborated on in this embodiment.

[0029] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A wireless SWD debugging and programming method for a collaborative arm, characterized in that, When applied to SWD debugging and programming devices, the specific steps include: S101: Receives debugging and programming instructions sent by the host computer and executes the command to connect the embedded pins set by the wireless debugging adapter of the ESP32 module to the SWD interface pins on the target circuit board inside the collaborative arm driver. Some GPIOs of the ESP32 module are pre-configured as SWDIO and SWCLK functions to establish a low-level signal channel with the target ARM CPU. S102: Establish a wireless communication link based on Wi-Fi TCP / IP protocol between the host computer and the ESP32 module. The host computer runs a standard IDE development environment, and the ESP32 module acts as a wireless gateway and protocol conversion node, opening the TCP / IP server listening port. S103: After receiving a data packet from the wireless communication link, the firmware running in the ESP32 module extracts features from the data packet and converts the extracted features into SWD protocol instructions that follow the ARM CoreSight timing. The software drives GPIO to accurately simulate the behavior of the hardware debugger. S104: The SWD protocol command generated after protocol conversion is directly applied to the SWD pin of the target ARM CPU through the embedded pin, establishing a complete debugging and programming communication link. At this time, the host computer can perform online debugging operations on the ARM CPU in the collaborative arm driver. S105: During mass production, the host computer can simultaneously establish independent connections with wireless debugging adapters deployed on multiple cooperating arms or drivers. The host computer can selectively control the sending of the same or different firmware data packets and burning instructions to multiple target devices, and each ESP32 module can complete its own protocol conversion and signal driving tasks in parallel.

2. The wireless SWD debugging and programming method for a collaborative arm as described in claim 1, characterized in that, In S101, debugging and programming commands sent by the host computer are received, including: The system receives a connection request sent by the host computer through a preset network. The connection request is used to request the establishment of a connection with the SWD debugging and burning device. Detect whether the current account on the host computer is the target account; If the current account of the host computer is the target account, then a connection is established with the host computer according to the connection request. After the connection is established, the debugging and burning instructions sent by the host computer are received.

3. The wireless SWD debugging and programming method for a collaborative arm as described in claim 2, characterized in that, Some of the GPIOs in the ESP32 module are pre-configured as SWDIO and SWCLK functions to establish a low-level signal channel with the target ARM CPU, including: At the hardware connection level, two sets of general-purpose input / output pins with high-speed response and precise timing control capabilities were selected on the ESP32 module and connected to the SWDIO and SWCLK test points corresponding to the ARM CPU on the target device board through physical circuits. During the firmware initialization phase, these two sets of pins are configured to specific digital modes. The GPIO used for analog clock is set to high-precision push-pull output to ensure the generation of a stable and clear clock signal. The GPIO used for bidirectional data communication is set to quasi-bidirectional or open-drain mode that can switch directions in real time, and is equipped with pull-up resistors to accurately simulate the read and write timing requirements of the SWDIO line and establish a reliable underlying electrical connection channel. At the software driver level, nanosecond-level precise operations on these two connected GPIOs are achieved by writing low-level pin control functions. For the SWCLK line, the high-resolution timer of the ESP32 or hardware peripherals are used to generate a standard clock pulse sequence with adjustable frequency and constant duty cycle. For the SWDIO line, the data direction of the pin is switched on time at each specific phase of SWCLK, and the corresponding data bits are read or written, strictly following the serial communication waveform defined by the ARM CoreSight debugging architecture.

4. The wireless SWD debugging and programming method for a collaborative arm as described in claim 3, characterized in that, In S102, a wireless communication link based on the Wi-Fi TCP / IP protocol is established between the host computer and the ESP32 module, including: The host computer runs a dedicated driver or configuration tool, broadcasts a discovery request in the local wireless network or locates the TCP server port opened by the ESP32 module through a pre-configured target IP address, and then the host computer actively initiates a TCP connection request. After completing the standard three-way handshake to establish a reliable transport layer connection, it immediately performs an application layer handshake and authentication. After the application layer handshake and authentication are completed, the debugging operations of the host computer's debugger will be encapsulated by the underlying driver into raw data packets with a specific frame structure. Each data packet contains a frame header, command code, data payload, and CRC checksum. The encapsulated data packets are then continuously sent to the ESP32 module through the network socket connection.

5. The wireless SWD debugging and programming method for a collaborative arm as described in claim 4, characterized in that, In S103, feature extraction is performed on the data packets, and the extracted features are converted into SWD protocol instructions that conform to the ARM CoreSight timing, including: The built-in command and data parser unpacks, verifies, and reassembles TCP / IP data streams to extract standard debugger command sequences. Through the real-time processing capabilities of a precisely programmed software protocol simulator, a precise SWCLK clock signal is generated and output in real time on GPIO pins configured for SWD function, according to the SWD protocol communication timing defined by the ARM CoreSight architecture. By synchronously performing serial input and output of data on the SWDIO data line, the hardware SWD interface behavior of the traditional wired debugger is completely and reliably simulated at the software level, realizing the protocol conversion from wireless signal to wired SWD protocol.

6. The wireless SWD debugging and programming method for a collaborative arm as described in claim 5, characterized in that, In S104, the SWD protocol instructions generated after protocol conversion are directly applied to the SWD pin of the target ARM CPU via embedded pins, establishing a complete debugging and programming communication link, including: The ESP32 module receives and parses instructions from the host computer in real time. As a coprocessor, it accurately executes core debugging functions, including memory and register read and write, setting hardware / software breakpoints, controlling single-step execution of the program, and monitoring variable values. At the same time, it fully handles the chip erasure, programming, and verification processes required for firmware burning. After executing each instruction, the ESP32 synchronously collects the response data returned by the target CPU through the SWD interface, reassembles it according to the protocol specifications, adds the necessary sequence number and status information, encapsulates it into a data packet, and reliably transmits it back to the host computer through the established Wi-Fi TCP link to complete the complete data interaction.

7. The wireless SWD debugging and programming method for a collaborative arm as described in claim 6, characterized in that, In S105, during mass production, the host computer can simultaneously establish independent connections with wireless debugging adapters deployed on multiple collaborating arms or drivers, including: In the production line environment, the host computer runs central control software, which actively discovers all online ESP32 wireless debugging adapters in the network by scanning preset IP address ranges or receiving multicast heartbeat packets, assigns an independent logical session identifier to each adapter, and initiates and maintains multiple parallel TCP connections to build a stable star topology network structure. The host computer's software maintains a dynamic connection pool and device status table, monitors the communication quality and adapter working status of each link in real time, and ensures that command interaction and data transmission with each adapter are logically independent and do not block each other through multi-threaded or asynchronous I / O technology, providing a parallel communication channel guarantee for subsequent synchronous or differentiated batch burning and debugging tasks.

8. The wireless SWD debugging and programming method for a collaborative arm as described in claim 7, characterized in that, The host computer's software maintains the dynamic connection pool and device status table, and monitors the communication quality and adapter working status of each link in real time, including: During the system initialization phase, the software on the host computer creates and maintains a TCP connection resource pool based on the number of wireless adapters detected by the scan and the preset concurrency threshold. The TCP connection resource pool keeps the link active by periodically sending heartbeat data packets. At the same time, the TCP connection resource pool can dynamically allocate or reclaim connection resources according to the current queue status of batch tasks. The host computer's software creates a device status table in memory for each established adapter, which records the device ID, IP address, connection handle, and other static information, as well as continuously updates real-time working indicators. By monitoring threads polling and analyzing real-time working indicators, the system proactively identifies network anomalies or unresponsive devices and triggers predefined reconnection or alarm processes.

9. A wireless SWD debugging and programming system for a collaborative arm, characterized in that, The system is used to perform the debugging and programming method according to any one of claims 1-8, the system comprising: The wireless communication module is used to establish a wireless connection with the host computer based on the Wi-Fi TCP / IP protocol and transmit data. The protocol conversion module is used to receive and parse the debugging and programming instructions and data from the host computer, and convert them into SWD protocol command sequences that conform to the ARM CoreSight standard. The signal driving module is used to convert the SWD protocol command sequence into a SWCLK clock signal and a SWDIO data signal with precise timing through a precisely configured GPIO interface, so as to drive the target ARM CPU. The batch management module is used to establish and maintain multiple independent concurrent connections with wireless debugging adapters deployed on multiple target devices, enabling centralized control and parallel programming and debugging of multiple devices.

10. The wireless SWD debugging and programming system for a collaborative arm as described in claim 9, characterized in that, The protocol conversion module includes: The command and data parsing unit is used to unpack, verify, and reassemble the received TCP / IP data stream to extract standard debugger commands; The software protocol simulation unit is used to convert the debugger commands into corresponding SWD protocol bit streams in real time according to the communication timing defined by the ARM CoreSight architecture.

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