Address storage method, processor, device, apparatus, and storage medium

Abstract

This application provides an address storage method, processor, apparatus, device, and storage medium, relating to the field of storage technology. The method is applied to a processor, which includes a first storage unit and a second storage unit. The first storage unit stores address information of a first type of instruction, and the second storage unit stores address information of a second type of instruction. The address storage method includes: determining the instruction type of a target instruction, where the target instruction is an instruction that has not yet entered the execution stage and is in a pending detection state; if the target instruction is a first type of instruction, then storing the address information of the target instruction in the first storage unit; if the target instruction is a second type of instruction, then storing the address information of the target instruction in the second storage unit. This method reduces the waste of storage space.

Description

Technical Field

[0001] This application relates to the field of storage technology, and in particular to an address storage method, processor, apparatus, device, and storage medium. Background Technology

[0002] With the development of storage technology, when a processor encounters a branch instruction and / or a jump instruction during instruction execution, the program will jump to the jump target address corresponding to the instruction.

[0003] In related technologies, in order to reduce the latency caused by calculating the jump target address, the processor has a unified storage unit for storing the instruction address and jump target address corresponding to branch instructions and / or jump instructions.

[0004] However, since the jump target address corresponding to the return instruction is not read from the above-mentioned storage unit, storage space is wasted. Summary of the Invention

[0005] This application provides an address storage method, apparatus, device, and storage medium. The technical solutions provided by this application are as follows.

[0006] According to one aspect of the embodiments of this application, an address storage method is provided, applied in a processor, the processor including a first storage unit and a second storage unit, the first storage unit being used to store address information of a first type of instruction, and the second storage unit being used to store address information of a second type of instruction; the method includes: The instruction type of the target instruction is determined, wherein the target instruction refers to an instruction that has not yet entered the execution stage and is in a state of waiting to be detected; If the instruction type of the target instruction is the first type of instruction, then the address information of the target instruction is stored in the first storage unit; If the target instruction is of the second type, then the address information of the target instruction is stored in the second storage unit.

[0007] According to one aspect of the embodiments of this application, a processor is provided, the processor including a first storage unit and a second storage unit; The first storage unit is used to store the address information of the first type of instruction; The second storage unit is used to store the address information of the second type of instructions.

[0008] According to one aspect of the embodiments of this application, an address storage device is provided, characterized in that it is applied in a processor, the processor including a first storage unit and a second storage unit, the first storage unit being used to store address information of a first type of instruction, and the second storage unit being used to store address information of a second type of instruction; the device includes: The determination module is used to determine the instruction type of the target instruction, which refers to an instruction that has not yet entered the execution stage and is in a state of waiting to be detected. A storage module is used to store the address information of the target instruction into the first storage unit if the instruction type of the target instruction is the first type of instruction; The storage module is further configured to store the address information of the target instruction into the second storage unit if the instruction type of the target instruction is the second type of instruction.

[0009] According to one aspect of the embodiments of this application, a computer device is provided, the computer device including a processor and a memory, the memory storing a computer program, the computer program being loaded and executed by the processor to implement the above-described address storage method.

[0010] According to one aspect of the embodiments of this application, a computer-readable storage medium is provided, wherein a computer program is stored in the computer-readable storage medium, the computer program being loaded and executed by a processor to implement the above-described address storage method.

[0011] According to one aspect of the embodiments of this application, a chip is provided, the chip including programmable logic circuits and / or program instructions, which, when the chip is running, are used to implement the above-described address storage method.

[0012] According to one aspect of the embodiments of this application, a computer program product is provided, the computer program product including a computer program, the computer program being loaded and executed by a processor to implement the above-described address storage method.

[0013] The technical solution provided in this application can bring the following beneficial effects: By determining the instruction type of the target instruction and storing the address information in the corresponding storage unit according to the instruction type, an on-demand storage allocation strategy is achieved. Specifically, since the first type of instruction and the second type of instruction require different types of address information to be stored, the above storage strategy ensures that the first storage unit only stores the address information necessary for the first type of instruction, and the second storage unit only stores the address information necessary for the second type of instruction. In summary, the technical solution provided by the embodiments of this application avoids allocating unnecessary storage space to instructions by storing the address information of different types of instructions separately, thereby reducing the waste of storage space. Attached Figure Description

[0014] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0015] Figure 1 This is a schematic diagram of a prediction method for different types of instructions provided in one possible implementation of related technologies; Figure 2 This is a block diagram of the processor provided in one possible implementation of this application; Figure 3 This is a schematic diagram of the first storage unit provided in one possible implementation of this application; Figure 4 This is a schematic diagram of a second storage unit provided in one possible implementation of this application; Figure 5 This is a flowchart of an address storage method provided in one possible implementation of this application; Figure 6 This is a schematic diagram of a prediction method for different types of instructions provided in one possible implementation of this application; Figure 7 This is a structural block diagram of an address storage device provided in one possible implementation of this application; Figure 8 This is a structural block diagram of a computer device provided in one possible implementation of this application. Detailed Implementation

[0016] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0017] Before introducing the technical solution proposed in this application, the relevant technical background and related technologies will be briefly described below.

[0018] This application relates to the design of a high-performance processor microarchitecture based on the RISC-V (Reduced Instruction Set Computer-V) instruction set architecture (ISA). The RISC-V architecture is an open-source, modular instruction set architecture based on the principles of Reduced Instruction Set Computer (RISC). Its design philosophy emphasizes simplicity, efficiency, and scalability, which has led to its widespread application in embedded systems, the Internet of Things (IoT), and the growing field of High Performance Computing (HPC). To achieve higher instruction throughput and performance on the RISC-V architecture, modern processors commonly employ key technologies such as deep pipelines and branch prediction.

[0019] For example, during instruction execution, the instruction stream contains many branch instructions and jump instructions. When a branch instruction and / or jump instruction is executed, execution jumps to another address and continues to execute the instructions corresponding to that address. For instance, when software code contains some if-else statements... When an Else Statement (conditional statement) or a function call (or other control flow statement) is executed, the compiler generates branch or jump instructions. Specifically, the main branch / jump instructions can be categorized into the following two types: 1. Branch instructions: The execution result of these instructions is uncertain. Depending on the result of the operation, the instruction may jump to the target address or execute the next instruction sequentially.

[0020] 2. Jump Instructions: The execution result of these instructions is deterministic; a jump will always occur. Jump instructions can be further divided into two types: 1) Direct Jump Instructions: The jump offset is directly encoded in the immediate numeric field of the instruction itself. During branch prediction, the processor can directly parse the jump target address from the instruction code; 2) Indirect Jump Instructions: The jump target address is stored in a general-purpose register, not the instruction itself. Since the register value may change before execution, the jump target address usually cannot be determined in advance during the branch prediction stage.

[0021] Among the jump instructions mentioned above, there are two instruction pairs with special semantics: call instructions and return instructions. The processor can distinguish them by parsing the opcode and operands of specific instructions. For example, these specific instructions include JAL (Jump and Link), JALR (Jump and Link Register), and C.JALR (Compressed Jump and Link Register). The logic for determining call and return instructions is as follows: when JALR / JAL / C.JALR is present, and the instruction's rd (destination register) is x1 or x5, the instruction is identified as a call instruction; when JALR / JAL / C.JALR is present, and the instruction's rs (source register) is x1 or x5, the instruction is identified as a return instruction. Here, x1 and x5 are general-purpose register numbers defined in the RISC-V instruction set, typically used as dedicated link registers for storing jump addresses. Call instructions and return instructions always appear in pairs in a program. In the context of function calls, when the main program calls a sub-function, the compiler inserts a call instruction into the generated instruction stream; when the sub-function finishes execution and returns to the main program, the compiler generates a corresponding return instruction. Therefore, accurately predicting the target address of the return instruction is crucial for maintaining the correct program execution flow.

[0022] For example, different prediction methods exist for different types of instructions. Specifically, these may include: 1. For branch instructions, the processor can use the BHT (Branch History Table) to predict the direction of the jump (i.e., determine whether a jump will occur).

[0023] 2. For branch instructions and direct jump instructions, the processor can use the BTB (Branch Target Buffer) to store and quickly provide the jump target address of branch instructions and direct jump instructions.

[0024] 3. Similarly, for branch instructions and direct jump instructions, the processor can also be configured with ADDRGEN (AddressGenerator) to calculate the accurate jump target address after the branch prediction is completed, and use the address to update the corresponding entry in BTB.

[0025] 4. For non-direct jump instructions (i.e., indirect jump instructions), since the jump target address is not fixed in the instruction, the processor can use IND_BTB (Indirect Branch Target Buffer) to predict the jump target address.

[0026] 5. For call and return instruction pairs, the processor can use the Return Address Stack (RAS) for prediction. The basic workflow of the processor is as follows: when a call instruction is detected, the address of the next instruction after the call instruction (i.e., the return address) is pushed onto the top of the return address stack; when a return instruction is detected, the address is popped from the top of the return address stack and used as the jump target address for the return instruction, and the jump is executed.

[0027] For example, please refer to Figure 1 , Figure 1 This is a schematic diagram illustrating a prediction method for different types of instructions, provided as one possible implementation of related technologies. (Detailed explanation follows.) Figure 1 Before describing the method, it is necessary to briefly explain the other core components involved besides BHT, BTB, ADDRGEN, and IND_BTB mentioned above. These components together constitute the basic pathway for instruction fetching and prediction, as follows: 1. PCGEN (Program Counter Generator): PCGEN is responsible for generating the instruction address of the target instruction. If the currently executing instruction does not change the control flow (i.e., there are no branching, jumping, or other operations), PCGEN increments the value of PC (Program Counter) by 1, pointing to the next instruction to be executed sequentially. If a branch or jumping instruction is encountered, PCGEN generates a new instruction address for the target instruction based on the prediction result.

[0028] 2. Instruction Cache: The instruction cache stores recently accessed instructions. When the processor needs to execute an instruction, it first checks the instruction cache. If the instruction is already in the cache (i.e., a cache hit), it is read directly from the cache, thus speeding up instruction fetching. If the instruction is not in the cache (i.e., a cache miss), it needs to be read from memory and loaded into the cache.

[0029] 3. Pre-decoder: The pre-decoder is responsible for decoding instructions retrieved from the instruction buffer. Its main tasks are to identify the type of instruction (such as branch instructions, jump instructions, call instructions, return instructions, etc.) and extract key information from the instruction, such as the jump offset. The pre-decoded instruction information is then passed to other subsequent components for more accurate jump prediction.

[0030] Reference Figure 1 The following section, using the components shown in the diagram, details the prediction methods for different types of instructions in related technologies. In the aforementioned prediction methods, instruction processing can be divided into three consecutive pipeline stages to ensure smooth instruction execution and manage execution pauses (i.e., bubbles) that may be caused by prediction delays. Specifically, these include: 1. The IF (Instruction Fetch) stage: primarily responsible for generating the instruction address of the target instruction through PCGEN and retrieving the instruction from the instruction cache using this address; 2. The IP (Instruction Pre-decode) stage: primarily responsible for performing preliminary decoding on the instruction retrieved from the instruction cache using the pre-decoder, identifying the instruction type, and extracting key information (such as jump offsets); 3. The IB (Instruction Buffer) stage: primarily responsible for temporarily storing instructions and eliminating pipeline pauses (i.e., bubbles) caused by various prediction operations, ultimately sending the processed instructions to the downstream execution unit.

[0031] Based on the above pipeline, the behavior and timing logic of each prediction component in each clock cycle are as follows: 1. BHT workflow (prediction results obtained after 2 clock cycles): First clock cycle: Receive the PCGEN-BHT index signal from PCGEN and look up its internal history table accordingly.

[0032] In the second clock cycle: based on the search results, a direction prediction regarding whether to jump is generated. This prediction result will be fed back to BTB as one of its decision-making criteria.

[0033] 2. BTB workflow (prediction results obtained after 2 clock cycles): In the first clock cycle: PCGEN generates the instruction address of the target instruction and initiates two parallel operations during this cycle: 1) Initiating a read operation from the instruction cache using the instruction address; 2) Generating and sending the PCGEN-BTB index to the BTB to locate the tag storage area (used to store the instruction address) and data storage area (used to store the jump target address) within the BTB. Simultaneously, PCGEN also generates and sends the PCGEN-BHT index to the BHT to locate its internal history table.

[0034] In the second clock cycle: the pre-decoding information obtained from the instruction cache is sent to the pre-decoder. For example, the pre-decoding information may contain a 128-bit entry corresponding to four consecutive instructions. The pre-decoder identifies all branch instructions from this entry, and the BTB uses the PCGEN-BTB index received in the first clock cycle to compare addresses among the four candidate branch instructions and determine which is the earliest appearing branch instruction in sequence, thus outputting a corresponding candidate jump target address. Subsequently, the system combines the direction prediction given by the BHT in the first clock cycle (i.e., determining whether the branch should jump) and initiates an address change signal at the end of the second clock cycle. The final effectiveness of this signal requires arbitration with the prediction results of higher priority instructions.

[0035] 3. IND_BTB workflow (prediction results are given after 3 clock cycles): First clock cycle: The target instruction passes through the IF segment and is sent from the instruction cache to the pre-decoder.

[0036] In the second clock cycle: In the IP segment, after the pre-decoder decodes the instruction, its output is connected to an indirect jump judgment logic unit. The function of this unit is to determine whether the current instruction is an indirect jump instruction that needs to be processed by IND_BTB. If the judgment result is true, the instruction and its related information will be sent to IND_BTB.

[0037] In the third clock cycle: In segment IB, IND_BTB checks the incoming target instruction for a hit. If a hit is found, an address change signal is initiated. Such instructions will always jump, without relying on the direction determination of BHT.

[0038] 4. Workflow of returning to the address stack (prediction result given after 3 clock cycles): First clock cycle: The target instruction passes through the IF segment and is sent from the instruction cache to the pre-decoder.

[0039] In the second clock cycle: In the IP segment, the output of the pre-decoder is connected to a call / return instruction judgment logic unit. This unit's function is to identify whether the current instruction is a call instruction or a return instruction. If it is identified as a call instruction, the return address stack will push the address of the next instruction onto the stack; if it is a return instruction, it will prepare for a pop operation.

[0040] The third clock cycle: In segment IB, when a call instruction or return instruction is detected, the return address stack formally initiates an address change signal. If a return instruction is detected in segment IP, the jump target address is the address popped from the top of the return address stack.

[0041] 5. ADDRGEN workflow (prediction results are given after 4 clock cycles): First clock cycle: The target instruction passes through the IF segment and is sent from the instruction cache to the pre-decoder.

[0042] The second clock cycle: In the IP segment, after the pre-decoder decodes the instruction, it sends the instruction address and offset signal of the target instruction to ADDRGEN to prepare for subsequent calculations.

[0043] In the third clock cycle: In segment IB, ADDRGEN receives the above signal and calculates the accurate jump target address based on the instruction type.

[0044] The fourth clock cycle: ADDRGEN initiates an address change signal. For direct jump instructions, this signal will directly trigger the jump; for branch instructions, this signal needs to be combined with the direction prediction of the BHT to jointly determine whether to initiate the final address change.

[0045] It is worth noting that in existing prediction methods for different instruction types, whether it's the combination of BTB+BHT (2 clock cycles), prediction of IND_BTB or the return address stack (3 clock cycles), or calculation of ADDRGEN (4 clock cycles), they may all cause pipeline stalls during the prediction process. To further reduce latency, especially for address jumps to call and / or return instructions, related technologies have introduced L0 BTB (Level 0 Branch Target Buffer). Figure 1 As shown, each entry in an L0 BTB can contain four key fields: 1. Valid Bit: This is a Boolean flag. For example, when its value is "1", it indicates that the address information stored in the entry is valid and can be used for prediction; when its value is "0", it indicates that the entry is idle or invalid.

[0046] 2. ras flag: This is a flag specifically used to identify the instruction type. When its value is "0", it indicates that the entry corresponds to a non-return instruction; when its value is "1", it indicates that the entry corresponds to a return instruction.

[0047] 3. Instruction address: The address of the instruction that needs to be predicted is used to store the instruction.

[0048] 4. Jump target address: Used to store the jump target address of the instruction that needs to be predicted.

[0049] The hardware can automatically filter and update the contents of the L0 BTB, allowing only instruction addresses that meet specific conditions to be accessed. For example, instructions meeting these conditions may include: branch instructions deemed to have a very high jump probability by the BHT, direct jump instructions, and return instructions. For simplicity, the term "non-return instructions" as used below specifically refers to the other two types of instructions besides return instructions (i.e., branch instructions and direct jump instructions with very high jump probabilities). Alternatively, the update process can also be driven by a prediction unit (e.g., the BTB), synchronizing the most frequently hit instruction information to the L0 BTB.

[0050] Depending on the ras flag, the prediction flow for non-return instructions and return instructions differs in L0 BTB. Specifically, the differences include: 1. For non-return instructions: When a non-return instruction is determined to be a high-frequency instruction, its instruction address and corresponding jump target address are updated in an entry in the L0 BTB. Simultaneously, the valid bit of this entry is set to "1", and the ras flag is set to "0". During subsequent instruction execution, if the instruction address of the target instruction generated by PCGEN matches the instruction address of an entry in the L0 BTB, and that entry's valid bit is "1" and the ras flag is "0", then a hit is determined. At this point, the L0 BTB directly outputs the corresponding jump target address and initiates an address jump; the entire process requires only one clock cycle.

[0051] 2. For return instructions: When the return address stack detects a call instruction, the processor pushes the address of the next instruction after the call instruction onto the stack as the jump target address of the return instruction. Simultaneously, when the return address stack detects a return instruction, the processor stores the instruction address of the return instruction itself into a free entry in the L0 BTB, and sets the validity bit and ras flag of that entry to "1". During the execution of subsequent instructions, if the instruction address of the pending instruction generated by PCGEN matches the instruction address stored in an entry in the L0 BTB, and that entry's validity bit is "1" and ras flag is "1", then a hit is determined. At this point, the processor directly retrieves the address stored at the top of the return address stack and uses that address as the jump target address to initiate a jump. The above process can also be completed within one clock cycle.

[0052] However, the relevant technology has the following problems. The jump target address of the return instruction is not provided by the L0 BTB, but comes from the address stored in the return address stack. This means that the storage space allocated by the L0 BTB for the return instruction, used to store the "jump target address", is actually a redundant and invalid storage space. Specifically, the L0 BTB includes storage spaces for four types of data: [valid bit], [ras flag], [instruction address], and [jump target address]. For non-return instructions, all of the above storage spaces are effectively utilized. However, the situation is quite different for return instructions: the data in the [instruction address] storage space is used to indicate the instruction address and can be effectively utilized; the data in the [valid bit] and [ras flag] storage spaces are used to identify the state and type of the instruction and can also be effectively utilized; the data in the [jump target address] storage space is intended to indicate the instruction jump, but since this address is actually provided by the return address stack, the data in this storage space has no practical meaning and remains idle for a long time. The above situation results in L0 BTB occupying unnecessary storage space, directly causing a waste of storage space, which in turn leads to an increase in hardware area overhead.

[0053] To address the aforementioned problems, this application provides a processor. For example, please refer to... Figure 2 , Figure 2 This is a block diagram of a processor provided in one possible implementation of this application. As shown, the processor 200 includes a first storage unit 210 and a second storage unit 220. The first storage unit 210 is used to store address information of a first type of instruction, and the second storage unit 220 is used to store address information of a second type of instruction.

[0054] In one aspect of this embodiment, a processor refers to a processing core with instruction flow control and prediction capabilities. Specifically, the core function of a processor may include: predicting address jump behavior during instruction execution based on stored address information, and guiding the instruction execution flow according to the prediction result to reduce pipeline stalls caused by branches and / or jumps. The implementation of a processor is not limited to a specific type of computing unit. For example, it can be the core of a CPU (Central Processing Unit), or a dedicated module responsible for control flow in a GPU (Graphics Processing Unit), DSP (Digital Signal Processor), or AI (Artificial Intelligence) accelerator. It is worth noting that the specific types of processors described above are merely illustrative examples, and any hardware processing unit capable of performing instruction address storage and prediction functions falls within the protection scope of this application.

[0055] In one aspect of this embodiment, the first type of instruction is characterized in that the jump target address required for its execution cannot be directly obtained or calculated from the encoding information of the instruction itself, but needs to rely on the state or data dynamically determined at runtime. For example, the first type of instruction may include, but is not limited to: 1. a return instruction, whose jump target address comes from the top data of the call stack; 2. an indirect jump instruction, whose jump target address comes from a register value or the memory read result of register indirect addressing; 3. an indirect call instruction, whose jump target address is determined by a function pointer in a register or memory; 4. a jump instruction dynamically generated in a secure or encrypted context, whose jump target address can only be determined after decryption or verification; 5. a multiplexed jump instruction, which is a composite instruction that selects different jump target addresses based on the combination of multiple registers or flag bits. It is worth noting that the common feature of the first type of instruction is that the jump target address cannot be completely determined at compile time and must be dynamically obtained during program execution. Any instruction that meets the above characteristics, regardless of its specific mnemonic, encoding format, or instruction set architecture, falls within the protection scope of this application.

[0056] In one aspect of this embodiment, the address information stored in the first storage unit mainly revolves around the identifier of the instruction itself and necessary metadata. Its purpose is to provide information for the identification and matching of first-type instructions, without including information indicating address jumps. Specifically, the address information stored in the first storage unit may include, but is not limited to: 1. Instruction address: This can be the PC value of the first-type instruction during program execution, used to identify the instruction's position in the instruction stream; 2. Type flag: Used to indicate that an instruction belongs to the first-type instruction, so as to distinguish it from other types of instructions during querying or matching; 3. Optional metadata: For example, limited historical information related to an instruction (such as the branch direction of the last execution, hit count statistics), index information, or other parameters that help predict the jump address but are unrelated to the complete jump target address. It is worth noting that all of the above-mentioned address information aims to support the rapid identification and matching of first-type instructions. The core feature is that it does not include the complete information required for instruction execution address jumps, thereby avoiding additional storage and maintenance overhead.

[0057] In one aspect of this embodiment, the first storage unit can be implemented using various storage structures to adapt to different processor architectures and application scenarios. For example, the implementation of the first storage unit may include, but is not limited to: 1. Instruction cache structure: located at the front end of the processor pipeline, it can be part of the instruction cache or BTB, indexed by instruction address to achieve fast hit and lookup of the address of the first type of instruction; 2. CAM (Content Addressable Memory): CAM supports parallel matching lookup based on instruction address or address portion fields, and can complete the matching operation within a single clock cycle; 3. SRAM (Static Random-Access Memory): can use address indexing methods such as direct mapping, set-associative, or fully associative, with a simple structure and easy on-chip integration; 4. Register file or register file subset: can store the address information of recently used first type of instructions in a dedicated register set, which can be directly indexed and accessed by control logic; 5. Hybrid storage structure: can combine two or more different types of storage circuits, such as the above-mentioned CAM and SRAM. The specific forms listed above are merely illustrative examples and are not intended to limit the scope of protection of this application. Any storage circuit or structure capable of storing the address information of the first type of instruction and meeting the requirements for fast query and matching falls within the protection scope of this application.

[0058] In one aspect of this embodiment, the second type of instruction is characterized in that the jump target address required for its execution jump can be directly obtained from the encoding information of the instruction itself or derived according to fixed calculation rules. For example, the jump target address of the second type of instruction can be directly encoded in the immediate number field of the instruction, or it can be calculated by adding the current instruction address to a fixed offset. Exemplarily, the second type of instruction may include, but is not limited to: 1. Direct jump instructions, whose jump target address can be determined by the immediate number or relative offset in the instruction; 2. Branch instructions, whose jump target address can also be determined by the relative offset in the instruction; 3. Relative addressing call instructions, whose target address can be obtained by adding a fixed offset to the current PC value; 4. Instructions that calculate the jump target address based on a fixed formula. It is worth noting that the common feature of the second type of instructions is that the jump target address can be determined at compile time or directly calculated at the decoding stage according to fixed rules, without relying on runtime dynamic state or external data. Any instruction that meets the above characteristics, regardless of its specific mnemonic, encoding format, or instruction set architecture, falls within the protection scope of this application.

[0059] In one aspect of this embodiment, the address information stored in the second storage unit is typically more complete than that stored in the first storage unit, aiming to achieve direct prediction of jump behavior for the second type of instruction. Specifically, the address information stored in the second storage unit may include, but is not limited to: 1. Instruction address: This can be the PC value of the second type of instruction during program execution, used to identify the instruction location; 2. Jump target address: The jump target address derived according to the fixed encoding or calculation rules of the instruction, which can be directly used for prefetching and execution flow guidance during querying; 3. Optional metadata: For example, historical bits used to predict the jump direction, validity flags (marking whether the corresponding entry is available or invalid), usage frequency counts, timestamps, or other parameters that help improve prediction accuracy. All of the above information aims to support the rapid identification of the second type of instruction, the direct acquisition of the jump target address, and the prediction of the jump address. The core feature is that it includes the complete address information required for the instruction to execute the jump, which differs from the case where the first storage unit does not need to store complete address information.

[0060] It is worth noting that the various address information corresponding to the first and second types of instructions involved in the above embodiments—including the instruction address of the instruction itself during program execution and the jump target address used to indicate jump behavior—can be represented in either the form of a physical address or a virtual address, and this application does not impose any limitation on this. Regardless of the address space representation method used, as long as it can meet the functional requirements of identifying, matching, and predicting jump behavior of the corresponding instructions, it falls within the protection scope of this application.

[0061] In one aspect of this embodiment, the second storage unit can also be implemented using various storage structures to adapt to different processor architectures and application scenarios. For example, the implementation of the second storage unit may include, but is not limited to: 1. BTB: The jump target address and related prediction information can be stored according to the instruction address index; 2. Storage array: It can be composed of SRAM, DRAM (Dynamic Random Access Memory), or on-chip flash memory, and the stored address information is organized according to a predetermined address mapping rule; 3. Register file or register file subset: The address information of the second type of instructions can be placed in a dedicated register group for direct access by the control logic; 4. Hybrid storage structure: Two or more different types of storage circuits can be combined, for example, combining BTB with a multiplexed set-associative cache to balance hit rate and access speed; 5. Multi-level storage structure: It can be a combination of a first-level small-capacity low-latency storage (such as L0 BTB) and a second-level large-capacity storage (such as a main memory mapping table) to store the address information of multiple second type of instructions. It is worth noting that the specific forms listed above are merely illustrative examples and are not intended to limit the scope of protection of this application. Any storage circuit or structure capable of storing address information of the second type of instruction and meeting the requirements for fast query and matching falls within the protection scope of this application.

[0062] In one aspect of this embodiment, the address information in the aforementioned storage unit can be organized using entries as the basic unit. For example, each entry corresponds to a set of address information for one (or a group) of instructions. For the same instruction, different types of address information (such as instruction address, jump target address, flag bits, etc.) can be stored in the entry according to predetermined field rules to facilitate parallel reading, comparison, and updating. Regarding the architectural relationship between the first and second storage units, it can include, but is not limited to: 1. The first and second storage units can be two completely independent physical hardware circuits, respectively arranged in different areas of the chip or manufactured using different process units; 2. The first and second storage units can be two different logical partitions or storage areas divided by address space partitioning and / or logical view within the same physical storage hardware, but maintaining separation in logical function and storage content. Both of the above methods can achieve the core objective of this application to separately store the address information of two types of instructions. It is worth noting that the above-mentioned discrete hardware or same hardware partition forms are merely illustrative examples; any physical or logical organization that can achieve separation of function and storage content between the first and second storage units falls within the protection scope of this application.

[0063] Based on the different instruction types, different types of address information are stored in the first and second storage units respectively, achieving on-demand allocation and efficient utilization of storage space. Specifically, for the first type of instructions where address prediction information cannot be directly obtained, the first storage unit does not need to allocate redundant storage space; it only needs to store directly obtainable address information such as the instruction address. For the second type of instructions where address prediction information is easily obtained, the second storage unit can store complete address information. This storage strategy reduces storage space waste, thereby improving the efficiency of hardware resource utilization.

[0064] In some embodiments, the first type of instructions includes a return instruction, and the second type of instructions includes other jump instructions besides the return instruction. The address information of the return instruction includes: the instruction address of the return instruction; the address information of the other jump instructions includes: the instruction address of the other jump instruction and the jump target address.

[0065] In one aspect of this embodiment, the first type of instruction includes a return instruction. A return instruction is a special type of control flow transfer instruction in the instruction set. Its execution logic is as follows: it jumps to the address previously saved by the corresponding calling instruction, thereby returning to the next instruction after the calling point to continue execution. From an instruction encoding perspective, return instructions typically do not include an explicitly encoded jump target address; the determination of its jump target address is highly dependent on the processor's runtime state. Closely working in conjunction with the return instruction are calling instructions. When a calling instruction is executed, it pushes the address of its immediately following instruction onto the top of the return address stack. When the processor subsequently executes the return instruction, it pops the address from the top of the stack as the jump target address. This "call-return" pairing logic determines that the jump target address of the return instruction cannot be directly obtained or calculated from the instruction's own code, but must rely on an external, dynamically maintained stack structure. For example, the return address can exist in the following forms, including but not limited to: 1. Standard function return instructions: their jump target address comes from the top of the return address stack saved at the time of the call; 2. Exception or interrupt return instructions: their jump target address comes from the program state or dedicated link register saved during exception / interrupt handling; 3. Coprocessor or hardware acceleration module return instructions: in some architectures, dedicated return instructions used by the coprocessor to return control to the main processor after completing the task, their jump target address is provided by the coprocessor's internal state or dedicated registers; 4. Virtual machine or interpreter return instructions: instructions used to return from a subroutine or function call in a virtual machine execution environment, their jump target address is dynamically maintained by the virtual machine runtime stack. It is worth noting that the common feature of the above types of return instructions is that the jump target address cannot be determined at compile time and must be obtained during program execution through the dynamic state saved at the time of the call (such as the return address stack, link registers, etc.). Any instruction that meets the above characteristics, regardless of its specific mnemonic, encoding format, or instruction set architecture, falls within the protection scope of this application.

[0066] In one aspect of this embodiment, the address information stored in the first storage unit includes the instruction address of the return instruction, which refers to the address of the return instruction itself in memory, i.e., the address pointed to by the PC during the instruction fetch stage. When performing branch prediction, the processor compares the currently fetched instruction address with the instruction address field recorded in each entry of the storage unit. Only when the two match can the entry be hit and the subsequent prediction jump action be triggered. Therefore, regardless of the specific implementation, storing the instruction address of the return instruction is one of the important features for realizing its fast matching and location function. In some embodiments, the address information of the return instruction may only include the instruction address of the return instruction. Specifically, the storage entry may be a single field containing only the instruction address. When a hit occurs, the processor uses other independent logic (e.g., a preset signal or protocol) to identify whether the hit is a return instruction entry, and then can query the return address stack to obtain the corresponding jump target address. In some embodiments, the address information of the return instruction may include the instruction address of the return instruction and other auxiliary metadata. Specifically, one or more status fields may be added to the address information. For example, a validity bit could be included to indicate whether the entry currently contains valid data (i.e., the instruction address of the return instruction mentioned above), which is a common and important function in cache management. It is worth noting that even in the extended mode described above, the main body and core of the address information is still the instruction address of the return instruction. The added metadata is for better management and use of the instruction address, rather than for replacing and / or carrying the jump target address.

[0067] For example, please refer to Figure 3 , Figure 3 This is a schematic diagram of the first storage unit provided in one possible implementation of this application. For example... Figure 3 As shown, each entry in the first storage unit 210 includes two key fields: a valid bit and an instruction address. It should be clarified that in this embodiment, the first storage unit is used to store return instructions; therefore, the aforementioned "instruction address" corresponds to the instruction address of the return instruction. This embodiment... Figure 3 The structure shown illustrates how the address information of the return instruction is stored. The "valid bit" field indicates whether the entry is currently valid, i.e., whether a valid return instruction address is stored; while the "instruction address" field directly stores the address of the return instruction in memory, i.e., the instruction address. It is worth noting that the first storage unit 210 does not include a field for storing the jump target address, which reflects the core idea of ​​this embodiment: on-demand storage, i.e., storing only the minimum dataset necessary to implement the return instruction prediction function. However, it should be emphasized that... Figure 3The first storage unit shown is merely a specific example of this embodiment. As long as the address information stored in the first storage unit includes the instruction address and does not include the jump target address, it falls within the protection scope of this application.

[0068] In one aspect of this embodiment, the second type of instructions includes jump instructions other than return instructions. Exemplarily, the possible forms of these jump instructions, excluding return instructions, include, but are not limited to: 1. Direct jump instructions: their jump target address is directly encoded in the immediate number field of the instruction, which the processor can directly decode during the decoding stage; 2. Unconditional indirect jump instructions: although their jump target address originates from a register, the register value is fixed before program execution (e.g., through initialization or constant loading), therefore the target address can be considered known or predictable during the decoding stage; 3. Jump instructions that calculate the jump target address based on a fixed formula: in some DSPs or dedicated instruction sets, the jump target address can be directly generated by concatenating the PC and instruction fields using fixed bits or an arithmetic formula, without requiring runtime table lookups or memory access. It is worth noting that the common feature of the above-mentioned types of jump instructions is that the jump target address can be determined at compile time, or can be directly calculated during the decoding stage using fixed rules, without relying on runtime dynamic states or external data sources. Any jump instruction that meets the above characteristics falls within the protection scope of this application.

[0069] Furthermore, the second type of instructions in this application embodiment may also include branch instructions with high jump probability. Specifically, these instructions may be conditional branch instructions that have been screened by a specific mechanism and have shown a high jump probability in historical execution. For example, ways to prove that they have a high jump probability may include, but are not limited to: 1. Automatic hardware screening: The prediction unit in the processor (such as the BHT mentioned above) can identify branch instructions that execute jumps stably by monitoring the historical trajectory of instruction execution in real time and mark them as branch instructions with high probability of jump; 2. Software selection: When compiling a program, the compiler can identify code structures such as loop control and branches with fixed iteration counts through static code analysis and insert marks when generating machine code. Alternatively, it can collect execution statistics through the PMU (Performance Monitoring Unit) during program execution and feed them back to the processor to indicate branch instructions with high probability of jump; 3. Branch instructions stored in the BTB: When storing branch instructions, the BTB usually stores information such as their historical jump direction and confidence level. Branch instructions that exhibit extremely high jump confidence in BTB (e.g., multiple consecutive jumps in the same direction without any reversal) can also be considered branch instructions with high jump probability; 4. Hybrid screening mechanism: The jump probability of branch instructions can be comprehensively evaluated and marked by combining real-time hardware statistics and static / dynamic software analysis results to ensure the accuracy and adaptability of identifying high-probability branch instructions. It is worth noting that the above descriptions of non-return jump instructions and branch instructions with high jump probability are only illustrative examples. Any instruction type that meets the definition and characteristics of the second type of instruction, regardless of its specific implementation, architecture, or application scenario, falls within the protection scope of this application.

[0070] In one aspect of this embodiment, the address information of other jump instructions includes the instruction address and the jump target address of the other jump instructions. The meaning of the instruction address of the other jump instructions is the same as above, referring to the address of the jump instruction itself in memory, i.e., the address pointed to by the PC during the instruction fetch phase. The jump target address is the address in memory of the target instruction to which the instruction needs to jump during instruction execution. When performing branch prediction, the processor compares the currently fetched instruction address with the instruction addresses recorded in each entry in the second storage unit. Once a match is found, the processor can directly obtain the corresponding jump target address from the "jump target address" field of the entry without further complex calculations or queries, and trigger the subsequent address jump. In some embodiments, the address information of other jump instructions may only include the instruction address and the jump target address of the other jump instructions. Specifically, the storage entry may consist of two core fields: "instruction address" and "jump target address." When a match occurs, the processor can directly use the complete address information in the entry to complete the prediction and jump without relying on additional external data. In some embodiments, the address information of other jump instructions may include the instruction address of the other jump instruction, the jump target address, and other auxiliary metadata. Specifically, one or more status or key fields may be added to the address information. For example, it may include a validity bit to indicate whether the entry currently contains valid data; it may also include a record bit to record the branch jump / non-jump history of the corresponding instruction. It is worth noting that even in the above extended mode, the main body and core of the address information is still the combination of "instruction address" and "jump target address." The added metadata is for better management of address information, rather than for replacing and / or carrying other irrelevant address information.

[0071] For example, please refer to Figure 4 , Figure 4 This is a schematic diagram of a second storage unit provided in one possible implementation of this application. For example... Figure 4 As shown, each entry in the second storage unit 220 includes three key fields: valid bit, instruction address, and jump target address. It should be clarified that in this embodiment, the second storage unit is used to store other jump instructions; therefore, the aforementioned "instruction address" corresponds to the instruction address of the other jump instructions, while the "jump target address" is the target address to which the other jump instructions will jump. This embodiment... Figure 4The structure shown illustrates how the address information of other jump instructions is stored. The "valid bit" field indicates whether the entry is currently valid, i.e., whether it stores the address of a valid other jump instruction and / or the jump target address; the "instruction address" field directly stores the address of the other jump instruction in memory; and the "jump target address" field stores the target address to which the other jump instruction will jump. It is worth noting that the second storage unit 220 includes a field for storing the jump target address, which differs from the first storage unit 210, reflecting the different storage strategies for different types of instructions (return instructions and other jump instructions) in this embodiment. The first storage unit 210 only stores the instruction address of the return instruction, while the second storage unit 220 stores both the instruction address and the jump target address of other jump instructions to meet different prediction needs. It is worth noting that... Figure 4 The second storage unit shown is merely a specific example of this embodiment. As long as the address information stored in the second storage unit includes the instruction address and the jump target address, and the structure is reasonable, it falls within the protection scope of this application. This means that specific implementation methods can be... Figure 4 Based on this, various improvements and optimizations can be made, such as adding more control bits, adopting different data structures or storage formats, as long as the above core conditions are met.

[0072] By defining the first type of instructions as return instructions and the second type of instructions as other jump instructions that are not return instructions, the specific applicable instruction range is clearly defined. Furthermore, since the jump target address of a return instruction cannot be directly obtained from itself, the first storage unit only stores the instruction address of the return instruction, without storing redundant information such as its jump target address; while the jump target addresses of other jump instructions can be directly obtained, so the second storage unit can store complete address information, namely the instruction address and jump target address of the other jump instructions. In summary, this embodiment ensures that the storage strategy for the above two types of instructions can achieve on-demand storage, avoiding the storage of unnecessary address information for jump instructions, and further reducing space overhead.

[0073] In some embodiments, the processor further includes a return address stack for storing the jump target address of a return instruction.

[0074] In one aspect of this embodiment, the return address stack is a hardware stack that follows the LIFO (Last-In, First-Out) principle. Its core function is to dynamically save and restore the return address of function calls to ensure that the return instruction can correctly jump back to the corresponding call point. Specifically, the return address stack is usually a high-speed memory array located inside the processor core. It is characterized by extremely low access latency, atomic operations, and can be managed independently of general-purpose registers and main memory to meet pipeline timing and concurrency safety requirements. For example, the implementation of the return address stack can include, but is not limited to: 1. Flip-flop stack: a register stack consisting of a set of flip-flops, suitable for small capacity and low latency requirements (such as the return address stack in embedded processors or microcontrollers); 2. Low-latency SRAM: with a capacity larger than the above flip-flop stack, used in general-purpose CPUs or high-performance processor cores, allowing push / pop operations based on stack pointer indices; 3. Dedicated register file subset: a fixed area can be partitioned within the register file for use as the return address stack, with dedicated control logic managing the stack pointer and access; 4. On-chip cache block: can be used as part of the L0 cache or dedicated control flow cache, achieving tight coupling access with the pipeline front end; 5. Hybrid structure: combining two or more different types of storage circuits, such as a combination of flip-flop stack and SRAM, to balance low latency and large capacity requirements. It is worth noting that the above specific implementations are merely illustrative examples, and any hardware stack or equivalent structure capable of storing the jump target address of the return instruction and following LIFO logic falls within the protection scope of this application.

[0075] In one aspect of this embodiment, the reason why the return address stack can store the jump target address of the return instruction is due to the natural logical fit between the return address stack and the call-return instruction pair. Specifically, when a call instruction is executed, before jumping to the entry point of the called function, the processor can push the address of the next instruction after the call instruction (i.e., the expected return address) onto the top of the return address stack. Subsequently, when the called function is executed and the return instruction is read, the processor can directly pop the most recently stored address from the top of the return address stack, i.e., the address stored at the top of the stack, and use this address as the jump target address of the return instruction. The stack logic of LIFO described above is perfectly matched with the execution flow of nested function calls: in a multi-level nested function scenario, the innermost function returns first, and its corresponding return address is also pushed onto the stack first, thus being located at the top of the stack, and being popped first in subsequent return operations. The above mechanism ensures accurate matching between the return address and the call point, and will not be confused due to the nesting level. For example, in addition to the return address of a standard function call, the return address stack can also be used to store the jump target address of other similar mechanisms. Specifically, this may include, but is not limited to: 1. Exception or interrupt return address: When handling an exception or interrupt, the program address before the interruption can be pushed onto the return address stack, and popped and the execution flow restored upon return; 2. State return address of a secure or trusted execution environment: The address when returning from a secure domain to a normal domain; 3. Return class address in a custom ISA: The return address dynamically provided by a specific hardware state machine or register.

[0076] It is worth noting that the above description of the return address stack is merely illustrative. Any hardware stack or equivalent structure capable of storing the jump target address of the return instruction and following LIFO logic falls within the protection scope of this application.

[0077] By incorporating a return address stack in the processor, the jump target address of return instructions can be separated from general-purpose and / or shared memory resources and centrally managed. On one hand, storing the jump target address of return instructions through the return address stack ensures reduced access latency and minimizes pipeline stalls. On the other hand, it allows the first memory unit to focus on storing the instruction address of the return instruction without incurring the additional burden of storing the jump target address. Introducing the return address stack creates a highly efficient collaborative system, enabling the processor to achieve efficient processing of return instructions with an optimized structural combination.

[0078] The processor provided in this application embodiment stores different types of address information in a first storage unit and a second storage unit, respectively, based on the different instruction types, thereby achieving on-demand allocation and efficient utilization of storage space. Specifically, for the first type of instructions whose address prediction information cannot be directly obtained, the first storage unit does not need to allocate redundant storage space for them, but only needs to store directly obtainable address information such as the instruction address; while for the second type of instructions whose address prediction information can be directly obtained, the second storage unit can store complete address information. In summary, the processor provided in this application embodiment can reduce the waste of storage space, thereby improving the efficiency of hardware resource utilization.

[0079] The following are embodiments of the method of this application, which can be applied to the processor embodiments of this application. For details not disclosed in the method embodiments of this application, please refer to the processor embodiments of this application.

[0080] This application provides an address storage method. For example, please refer to... Figure 5 , Figure 5 This is a flowchart of an address storage method provided in one possible implementation of this application. It is worth noting that... Figure 5 The address storage method shown can be applied to the processor proposed in the processor embodiments of this application. Specifically, the processor includes a first storage unit and a second storage unit. The first storage unit stores address information of a first type of instruction, and the second storage unit stores address information of a second type of instruction. The method may include steps 510 to 530 as follows.

[0081] Step 510: Determine the instruction type of the target instruction. The target instruction refers to an instruction that has not yet entered the execution stage and is in a state of waiting to be detected.

[0082] In one aspect of this embodiment, the processor first needs to identify the type of the obtained target instruction and determine whether it belongs to the first type or the second type of instruction by analyzing the type of the target instruction, thereby providing a basis for decision-making for subsequent differentiated storage paths. On the other hand, a target instruction refers to an instruction in the processor pipeline that has not yet entered the execution stage and is in a state of pending detection. By identifying the type of the target instruction at this stage, the processor can identify the first and second type of instructions in advance and store the corresponding address information in the first or second storage unit, respectively. When the processor encounters the target instruction again in the pipeline (i.e., the target instruction has reached the execution stage) and needs to perform branch prediction, it does not need to wait until the execution time to calculate or parse its jump target address. In the storage stage, when the processor obtains the machine code of a target instruction, it triggers the execution of step 510. At this time, the instruction classification unit can analyze the target instruction and determine its instruction type. For example, the instruction classification unit may include, but is not limited to: 1. A pre-decoder: The pre-decoder is a front-end module of the processor pipeline that can quickly perform preliminary decoding of the target instruction. One of its main tasks is to determine the instruction type of the target instruction and pass the determination result to the downstream module in the form of attribute bits and / or control signals; 2. Instruction classifier: It can be set as independent hardware logic, whose responsibility is to receive the raw instruction stream and complete the instruction type discrimination and marking with high throughput; 3. Microcode controller: In some CISC (Complex Instruction Set Computing) processors, the type identification and decoding of some instructions may also be completed by the microcode controller. In the embodiments of this application, the execution entity can be a pre-decoder. As mentioned above, the pre-decoder is responsible for decoding the target instruction retrieved from the instruction cache. One of its main tasks is to identify the type of the target instruction (such as branch instruction, jump instruction, call instruction, return instruction, etc.). Specifically, the pre-decoder can quickly determine whether the instruction belongs to a return instruction or other jump instruction by parsing the opcode field of the target instruction, and use the above judgment result as the key input signal for subsequent branch prediction and address storage logic.

[0083] In one aspect of this embodiment, step 510 begins by acquiring the complete machine code of the target instruction and, according to the ISA specification followed by the processor, extracting the opcode field representing the instruction category from a predetermined location in the machine code. Since opcodes for different instruction types are designed to be distinct—for example, the opcode for a return instruction differs from that for a call instruction or a direct jump instruction—the type of the target instruction can be uniquely determined by matching the extracted opcode with the instruction template defined by the ISA. This comparison operation can be implemented using a lookup table or a logical chain of judgments; the core principle is to identify the type based on the uniqueness of the encoding. After identification, the target instruction can be determined to belong to a first-class instruction, a second-class instruction, or other instructions based on the comparison result. Furthermore, a corresponding type identifier or control signal can be generated in the attribute information of the target instruction. For example, in the above process, the opcode extraction can be performed by extracting the corresponding field from a fixed bit range according to the ISA encoding format. This process only involves data field parsing and does not change the instruction execution state. Type comparison can be achieved by looking up a table based on the uniqueness of the encoding. The generation of the type identifier can be achieved by setting a flag bit or assigning a type code to the attribute field of the target instruction, so that subsequent modules can know the instruction category without repeated decoding. The discrimination result can be transmitted in the pipeline in the form of control signals to participate in the judgment of logic such as address storage and / or subsequent control flow guidance.

[0084] It is worth noting that the above description of step 510 is merely illustrative. Any scheme that can achieve "determining the instruction type of the target instruction" in the method flow, regardless of the specific processor architecture or the combination of logic modules used, falls within the protection scope of this application.

[0085] Step 520: If the instruction type of the target instruction is a first type instruction, then the address information of the target instruction is stored in the first memory unit.

[0086] In one aspect of this embodiment, after determining the instruction type of the target instruction, if the determination result indicates that the target instruction belongs to the first type of instruction, the processor can write its address information into the first storage unit. It is worth noting that the characteristics, type flags, and data composition of the first type of instruction and its address information have been detailed in the above embodiments and will not be repeated here. During the storage phase, the processor can store the address information of the target instruction into the first storage unit based on the determination result that the target instruction is a first type of instruction. The specific method for the above storage action may include: organizing the instruction address (e.g., PC value) and necessary type flags and other metadata of the target instruction into a storage record according to a predetermined entry format of the first storage unit; during the writing process, the storage location can be determined according to the indexing rules of the first storage unit, and the corresponding status or retrieval information can be updated to ensure rapid subsequent querying and matching. Since the first storage unit only stores address information for identification and matching, and does not contain complete address information, the above storage action only involves writing the instruction's own identifier and metadata, without needing to access or calculate other related address information in an external data source.

[0087] It is worth noting that the above description of step 520 is merely illustrative. Any scheme that can achieve "when the target instruction is identified as a first type instruction, the corresponding address information is written into the first memory unit" in the method flow, regardless of the specific processor architecture or the combination of logic modules used, falls within the protection scope of this application.

[0088] Step 530: If the instruction type of the target instruction is a second type instruction, then the address information of the target instruction is stored in the second storage unit.

[0089] In one aspect of this embodiment, if the determination result indicates that the target instruction belongs to the second type of instruction, the processor can write its address information into the second storage unit. It is worth noting that the characteristics, type flags, and data composition of the second type of instruction and its address information have been detailed in the above embodiments and will not be repeated here. During the storage phase, the processor can store the address information of the target instruction into the second storage unit based on the determination result that the target instruction is a second type of instruction. For example, the specific method of the above storage operation may include: 1. Organizing the instruction address of the target instruction, necessary type flag bits, and address information that can be directly used for address jumps into a storage record according to a predetermined entry format of the second storage unit. The address information directly used for address jumps can be obtained during the storage phase by parsing the encoding of the target instruction, for example, directly from the numeric segment of the target instruction, or calculated based on the current instruction address and a fixed offset, or directly provided by the absolute address field in the target instruction, or generated according to the fixed bit concatenation rules of multiple fields in the target instruction, or obtained from the constant loading result known and fixed during compilation; the processor can complete the reading and extraction of the above address information after instruction fetching and before entering the storage decision stage. During the writing process, the storage location can be determined according to the indexing rules of the second storage unit, and the corresponding status or retrieval information can be updated to ensure that subsequent queries and matching can be performed quickly.

[0090] It is worth noting that the above description of step 530 is merely illustrative. Any scheme that can achieve "when the target instruction is identified as a second type of instruction, the corresponding address information is written into the second memory unit" in the method flow, regardless of the specific processor architecture or the combination of logic modules used, falls within the protection scope of this application.

[0091] By determining the instruction type of the target instruction and storing the address information in the corresponding memory unit according to the instruction type, an on-demand storage allocation strategy is achieved. Specifically, since the first type of instruction and the second type of instruction require different types of address information to be stored, the above storage strategy ensures that the first memory unit stores only the address information necessary for the first type of instruction, and the second memory unit stores only the address information necessary for the second type of instruction. In summary, by storing the address information of different types of instructions in an isolated manner, memory units are prevented from allocating unnecessary storage space for instructions, reducing storage space waste and thus improving the efficiency of hardware resource utilization.

[0092] In some embodiments, the first type of instructions includes a return instruction, and the second type of instructions includes other jump instructions besides the return instruction. The address information of the return instruction includes: the instruction address of the return instruction; and / or, the address information of the other jump instructions includes: the instruction address of the other jump instruction and the jump target address.

[0093] It is worth noting that the detailed analysis of the above terms and concepts, including return instructions, other jump instructions, the instruction address of the return instruction, the instruction address of other jump instructions, and the jump target address, has been provided in detail in the above embodiments. To avoid repetition, it will not be repeated here. In other embodiments below, whenever the above-defined concepts are involved, the content and scope explained above can be directly applied.

[0094] In some embodiments, the processor further includes a return address stack for storing the jump target address of a return instruction, and the method further includes: Once the target instruction enters the execution phase, obtain the instruction address of the target instruction.

[0095] If the target instruction is of type 1 and the first memory unit contains address information that matches the instruction address of the target instruction, the jump target address of the target instruction is obtained from the return address stack.

[0096] If the target instruction is of type 2 and the second memory unit contains address information that matches the instruction address of the target instruction, the jump target address of the target instruction is obtained from the second memory unit.

[0097] The instruction jump is executed based on the target address of the target instruction.

[0098] In one aspect of this embodiment, when the processor enters the execution stage of the target instruction, it can obtain the instruction address of the target instruction, i.e., the address currently pointed to by the PC. Subsequently, the processor determines the instruction type of the target instruction. As described above, during the storage stage of the target instruction, the processor has already performed preliminary decoding of the target instruction through a pre-decoder and generated type identification information. Therefore, the type identification information can be read directly without repeated decoding, thus ensuring execution efficiency. If the type identification indicates that the target instruction belongs to the first type of instruction (e.g., a return instruction), then the address matching stage begins.

[0099] In one aspect of this embodiment, the processor can query the first memory unit based on the instruction address of the target instruction and determine whether the first memory unit stores address information that matches the instruction address of the target instruction. Specifically, if the content of an entry stored in the first memory unit can be matched with the target instruction, it can be confirmed that the target instruction has been recorded in the previous storage stage. The matching relationship can be based on the instruction address itself or combined with other auxiliary information for comprehensive determination, as long as the identity of the instruction can be uniquely determined. When it is determined that the first memory unit stores address information that matches the instruction address of the target instruction, it means that the instruction has been successfully recorded in the storage stage, and its corresponding jump target address can be provided by the return address stack. At this time, the processor can obtain the jump target address of the target instruction from the return address stack. Finally, the processor performs an instruction jump operation based on the jump target address obtained from the return address stack, that is, writes the jump target address into the program counter, updates the processor's execution flow, and jumps to the location indicated by the address to continue executing subsequent instructions.

[0100] By obtaining the instruction address of the target instruction during the execution phase, and upon determining that the target instruction is a first-type instruction and that there is matching address information in the first memory unit, the jump target address of the target instruction can be obtained from the return address stack and the jump can be executed. This mechanism avoids allocating unnecessary storage space to the first memory unit, thus saving storage resources. Simultaneously, during the execution phase, the jump target address of the target instruction can be directly obtained by accessing the return address stack, eliminating the need for repeated instruction encoding parsing and improving the efficiency of address jumps.

[0101] In one aspect of this embodiment, after obtaining the instruction address of the target instruction, if the target instruction belongs to the second type of instruction and can be matched with corresponding address information in the second storage unit, the jump target address corresponding to the target instruction can be directly obtained from the second storage unit, thereby completing the instruction jump. Specifically, the execution steps of the above process may include, but are not limited to: 1. Obtain the instruction address of the target instruction. The instruction address of the target instruction can be directly obtained from the current PC value, which is used to identify the position of the target instruction in the instruction stream.

[0102] 2. Based on the type identification information generated for the target instruction during the storage phase, determine whether the target instruction belongs to the second type of instruction. This type identification information can be directly read during the execution phase without re-parsing the instruction encoding.

[0103] 3. If the target instruction is confirmed to be a type II instruction, the matching and querying phase begins. The processor uses the instruction address of the target instruction as the key to perform a query operation in the second memory unit. Specifically, it compares whether the instruction address field in the entry matches the instruction address of the target instruction, and further verifies that the valid bit in the entry is in a valid state, thereby ensuring the accuracy of the match.

[0104] 4. If a match is successful, the corresponding jump target address is read from the second storage unit. The jump target address and the instruction address used during the match can be located in the same storage entry, or the address information can be directly pointed to through the associated index in the entry. Therefore, the jump target address of the target instruction can be obtained directly without secondary retrieval or additional calculation, thereby achieving efficient address acquisition.

[0105] 5. The processor can update the PC value according to the jump target address of the target instruction obtained from the second memory unit, so that the execution flow jumps to the position indicated by the jump target address.

[0106] It is worth noting that the above steps are merely illustrative. Any scheme that can achieve the principle of "when the target instruction is a second type of instruction and matching information exists in the second memory unit, obtain the jump target address of the target instruction from the second memory unit and execute the jump" in terms of method flow, regardless of the specific processor architecture and / or the combination of logic modules used, falls within the protection scope of this application.

[0107] By obtaining the instruction address of the target instruction during the execution phase, and when it is determined that the instruction is a second type instruction and the second storage unit contains matching address information, the jump target address of the target instruction can be directly read from the second storage unit without accessing external data sources or performing additional calculations. This avoids the delay and uncertainty caused by accessing external data sources, shortens the time for obtaining the jump target address, and further improves the execution efficiency of instruction jump.

[0108] In some embodiments, after obtaining the instruction address of the target instruction, the method further includes: if the instruction type of the target instruction is a return instruction, performing a query operation on the first storage unit to obtain a query result, the query result being used to indicate whether the instruction address of the target instruction is stored in the first storage unit.

[0109] One aspect of this embodiment provides a method for querying the instruction address of a return instruction, applicable to situations where the processor obtains the instruction address of a target instruction during the execution phase and determines that the instruction is a return instruction. Specifically: First, the processor obtains the instruction address of the target instruction during the execution phase and determines the type of the instruction as a return instruction (i.e., belonging to the first type of instruction) based on the instruction decoding or pre-decoding result. After determining that the target instruction is a return instruction, the processor performs a query operation on a first storage unit using the instruction address of the target instruction as an index. For example, the first storage unit pre-stores multiple instruction address entries for return instructions. Each entry may include an instruction address field and a valid bit used to identify the validity of the entry. The processor can compare the instruction address of the target instruction with the instruction address fields stored in each entry in the first storage unit one by one. Optionally, it can further verify whether the valid bit of the matching entry is in a valid state to confirm that the address information of the entry is currently available.

[0110] In one aspect of this embodiment, the query result refers to the output information of the aforementioned query operation, used to explicitly indicate whether there is an entry in the first storage unit that matches the instruction address of the target instruction. For example, the query result can be a Boolean type (e.g., "Hit / Miss") or a status code (e.g., "Stored" or "Not Stored"), and may include a validity verification result (e.g., the valid bit status of the matching entry). The core function of the query result is to serve as the basis for judgment in subsequent processes, determining whether to proceed to the step of reading the jump target address from the return address stack. For example, if the query result indicates that the instruction address of the target instruction is stored in the first storage unit and the corresponding entry is valid, it means that the jump target address of the return instruction can be obtained from the return address stack; if the query fails (not stored or invalid), other address acquisition strategies must be adopted.

[0111] It is worth noting that the above steps are merely illustrative. Any technical solution that, after confirming that the target instruction is a return instruction during the execution phase, queries the first memory unit to obtain the query result to confirm whether a matching instruction address exists in the first memory unit, falls within the protection scope of this application.

[0112] In some embodiments, obtaining the jump target address of the target instruction from the return address stack includes: if the query result is that the instruction address of the target instruction is stored in the first storage unit, then reading the address stored at the top of the return address stack and using the address stored at the top of the stack as the jump target address of the target instruction.

[0113] In one aspect of this embodiment, if the query result shows that the address of the target instruction is stored in the first storage unit, i.e., the query is successful, then the address stored at the top of the return address stack is read. The return address stack is a hardware stack that follows the LIFO principle and is used to store the jump target address corresponding to the return instruction. According to the nesting rules of function calls, the return address pushed onto the most recently executed call instruction must be located at the top of the stack. Therefore, reading the top stack address can obtain the correct jump target address. Subsequently, the processor uses the read top stack address as the jump target address of the target instruction, writes this address into the program counter, executes the instruction jump operation, and causes the processor's execution flow to jump to this address to continue execution.

[0114] It is worth noting that the above steps are merely illustrative. Any technique that retrieves the jump target address from the top of the return address stack when the query result indicates that the target instruction is stored in the first storage unit falls within the protection scope of this application.

[0115] Through the above process, this application refines the process of obtaining the jump target address of the return instruction into two sequential steps: "querying the first memory unit" and "reading the return address stack," forming a clear and traceable operation flow. On the one hand, by explicitly querying the first memory unit using the instruction address as an index, the accuracy and reliability of instruction identification are ensured, avoiding prediction errors caused by incorrect matching. On the other hand, by following the LIFO characteristic of the return address stack and reading the address from the top of the stack, the correctness of the jump target address is guaranteed in multi-level nested function call scenarios, ensuring that the jump behavior of the return instruction matches the program's execution logic. Furthermore, the above steps are clearly divided and logically explicit, facilitating the pipelined design and modular implementation of hardware circuits and reducing the design complexity of the processor.

[0116] For example, please refer to Figure 6 , Figure 6 This is a schematic diagram illustrating a prediction method for different types of instructions provided in one possible implementation of this application. First, it needs to be clarified that... Figure 6This illustration presents only one specific embodiment, its core purpose being to clearly demonstrate how, during instruction processing, specific storage units (first storage unit 210 and second storage unit 220) are utilized to optimize instruction prediction and address jumps based on the instruction type, thereby improving instruction execution efficiency and reducing storage space waste. Specifically, this application embodiment focuses on demonstrating different processing flows for return instructions (first type of instructions) and jump and branch instructions (second type of instructions) other than return instructions, during the storage address information and instruction execution stages. The components involved in the figure, such as first storage unit 210, second storage unit 220, PCGEN, pre-decoder, instruction cache, BHT, BTB, etc., have been described in detail above and will not be repeated here.

[0117] In one aspect of this embodiment, during the address information storage stage, after the processor fetches the instruction and obtains the target instruction through the instruction cache, the pre-decoder performs preliminary decoding on the target instruction, extracting the opcode and key field information (such as jump offset, call / return flags, etc.) of the target instruction. The output of the pre-decoder is connected to the instruction type discrimination logic, which determines, based on the instruction's opcode and the pre-decoded information, whether the current target instruction is a return instruction, a call instruction, or a jump instruction or branch instruction that is not a return instruction. The above discrimination results drive different storage and update behaviors, as follows: 1. Return Instruction: When the predecoder identifies the target instruction as a return instruction, the processor writes the instruction address of the return instruction into the first memory unit 210 and sets the valid bit to "1" in the stored entry to mark the instruction address stored in that entry as valid. Thus, when the processor encounters the aforementioned return instruction in subsequent execution phases, it can directly match a valid entry in the first memory unit 210 and obtain the top address from the return address stack to complete the jump.

[0118] 2. Call Instruction: When the pre-decoder identifies the target instruction as a call instruction, the processor generates the address of the next instruction following the call instruction and pushes this address onto the return address stack for storage, serving as the jump target address for the return instruction. It's important to note that the address information related to the call instruction is not written to the first or second memory location; it is only used to update the return address stack contents, preparing for the address jump to the return instruction during the instruction execution phase.

[0119] 3. Non-returning jump instructions and branch instructions (i.e., second-type instructions): When the pre-decoder identifies a target instruction as a non-returning jump instruction such as a direct jump, unconditional jump, or conditional branch, it reads the instruction address and the jump target address, and writes these address, along with the valid bit (set to "1"), into the second storage unit 220. The entry structure of the second storage unit 220 ensures that in subsequent instruction execution stages, second-type instructions can be quickly matched using the instruction address and directly read the saved jump target address without needing to parse again or access an external data source.

[0120] As can be seen from the above process, during the storage stage, the pre-decoder can be responsible for extracting address and type information. The second storage unit 220 is used to store the complete address information (instruction address + jump target address) and valid bits of the second type of instruction. The first storage unit 210 is used to store the instruction address and valid bits of the return instruction (the actual jump target address is still provided by the return address stack). The return address stack manages and provides the jump target address of the return instruction in the call / return instruction scenario.

[0121] In one aspect of this embodiment, during the execution phase, PCGEN first generates the instruction address of the current target instruction and retrieves the instruction from the instruction cache, sending it to the pre-decoder. The pre-decoder performs preliminary decoding of the target instruction, extracts the opcode and key fields, and sends the decoding result to the instruction type determination logic. This logic, based on the opcode and pre-decoding information, determines in real time whether the current target instruction is a return instruction, a jump instruction, or a branch instruction, and selects different address jump paths based on the determination results. Specifically, this may include: 1. Return Instruction: When the discrimination logic confirms that the target instruction is a return instruction, the processor uses the instruction address of the target instruction as an index to search for a matching entry in the first storage unit 210. During the search, the processor compares whether the instruction address field in the entry matches the instruction address of the target instruction and verifies whether the valid bit is "1". If a match is successful, the processor can retrieve the address stored at the top of the return address stack, which is the jump target address of the return instruction. Subsequently, the processor can write the jump target address of the return instruction into the program counter, causing the execution flow to jump to the return location of the calling function, completing the address jump.

[0122] 2. Non-return jump and branch instructions: When the discrimination logic confirms that the target instruction is a non-return jump instruction such as a direct jump, unconditional jump, or conditional branch, the processor also uses the instruction address of the target instruction as an index to search for a matching entry in the second storage unit 220. The search process compares the instruction address field in the entry with the instruction address of the target instruction and verifies whether the valid bit is "1". If a match is successful, since the second storage unit 220 has already stored the jump target address corresponding to the instruction during the storage phase, the processor can directly read the jump target address without re-parsening the instruction code or accessing an external data source. The processor can then write the jump target address into the program counter, causing the execution flow to jump directly to the target location to continue execution.

[0123] It is worth noting that the above-mentioned Figure 6 The illustrated embodiments are merely illustrative examples, intended to clearly demonstrate how this application stores address information into the first and second storage units according to instruction type during the storage phase, and how, during the execution phase, it can retrieve the jump target address from the corresponding storage unit or trigger a return address stack pop based on the instruction type. Any technical solution that can implement "storing address information for different types of instructions separately and retrieving the jump target address from the corresponding storage space according to the type to complete the address jump" in the method flow or device structure, regardless of the specific processor architecture, storage unit organization method, or logic module combination it adopts, falls within the protection scope of this application.

[0124] In summary, in this embodiment, the address information of different types of instructions is stored in the first storage unit 210 and the second storage unit 220 respectively before the instruction execution stage. Therefore, in the storage structure design, it is not necessary to use the same storage format and space allocation for all instructions. Instead, the most necessary storage content can be configured for different instruction types as needed. For example, for return instructions (first type of instructions), only the instruction address and validity flag need to be stored in its dedicated storage unit (first storage unit 210). The jump target address can be provided by the return address stack, thereby avoiding the allocation of fixed storage space for the jump target address in the first storage unit and reducing the waste of storage resources. For jump instructions and branch instructions (second type of instructions) that are not return instructions, the instruction address and jump target address are directly stored in the second storage unit 220 for quick reading during the instruction execution stage. The above storage mechanism makes the storage structure more compact and efficient, while still allowing different types of instructions to follow their own optimal data paths during the instruction execution stage, ensuring the efficiency of jumps and reducing the waste of storage space.

[0125] The address storage method provided in this application embodiment determines the instruction type of the target instruction and stores the address information to the corresponding storage unit according to the instruction type, thereby realizing an on-demand storage allocation strategy. Specifically, since the first type of instruction and the second type of instruction require different types of address information to be stored, the above storage strategy ensures that the first storage unit only stores the address information necessary for the first type of instruction, and the second storage unit only stores the address information necessary for the second type of instruction. In summary, the address storage method provided in this application embodiment, by storing the address information of different types of instructions in isolation, avoids allocating unnecessary storage space for instructions, thereby reducing the waste of storage space.

[0126] The following are embodiments of the apparatus described in this application, which can be used to execute the embodiments of the method described in this application. For details not disclosed in the apparatus embodiments of this application, please refer to the embodiments of the method and the processor described in this application.

[0127] For example, please refer to Figure 7 , Figure 7 This is a structural block diagram of an address storage device provided in one possible implementation of this application. Figure 7 The address storage device 700 shown is used in a processor (not shown in the figure). The processor includes a first storage unit and a second storage unit. The first storage unit is used to store address information of a first type of instruction, and the second storage unit is used to store address information of a second type of instruction. The device 700 may include a determination module 710 and a storage module 720.

[0128] The determination module 710 is used to determine the instruction type of the target instruction, which refers to an instruction that has not yet entered the execution stage and is in a state of waiting to be detected.

[0129] The storage module 720 is used to store the address information of the target instruction into the first storage unit if the instruction type of the target instruction is a first type instruction.

[0130] The storage module 720 is also used to store the address information of the target instruction into the second storage unit if the instruction type of the target instruction is a second type instruction.

[0131] In some embodiments, the first type of instructions includes a return instruction, and the second type of instructions includes other jump instructions besides the return instruction. The address information of the return instruction includes: the instruction address of the return instruction; the address information of the other jump instructions includes: the instruction address of the other jump instruction and the jump target address.

[0132] In some embodiments, the processor further includes a return address stack for storing the jump target address of a return instruction. The apparatus 700 also includes an acquisition module and a jump module. It is worth noting that the acquisition module and jump module described above... Figure 7 Not shown in the image.

[0133] The acquisition module is used to obtain the instruction address of the target instruction when the target instruction enters the execution phase.

[0134] The acquisition module is also used to acquire the jump target address of the target instruction from the return address stack if the instruction type of the target instruction is a first type instruction and the first storage unit stores address information that matches the instruction address of the target instruction.

[0135] The acquisition module is also used to acquire the jump target address of the target instruction from the second storage unit if the instruction type of the target instruction is a second type instruction and the second storage unit stores address information that matches the instruction address of the target instruction.

[0136] The jump module is used to execute the instruction jump of the target instruction based on the jump target address of the target instruction.

[0137] In some embodiments, the acquisition module is further configured to: after acquiring the instruction address of the target instruction, if the instruction type of the target instruction is a return instruction, perform a query operation on the first storage unit to obtain a query result, the query result being used to indicate whether the instruction address of the target instruction is stored in the first storage unit.

[0138] In some embodiments, the acquisition module is further configured to: if the query result is that the address of the target instruction is stored in the first storage unit, then read the address stored at the top of the return address stack and use the address stored at the top of the stack as the jump target address of the target instruction.

[0139] The address storage device provided in this application embodiment determines the instruction type of the target instruction and stores address information to the corresponding storage unit according to the instruction type, thereby realizing an on-demand storage allocation strategy. Specifically, since the first type of instruction and the second type of instruction require different types of address information to be stored, the above storage strategy ensures that the first storage unit only stores the address information necessary for the first type of instruction, and the second storage unit only stores the address information necessary for the second type of instruction. In summary, the address storage device provided in this application embodiment, by storing address information of different types of instructions in isolation, avoids allocating unnecessary storage space for instructions, thereby reducing the waste of storage space.

[0140] It should be noted that the apparatus provided in the above embodiments is only illustrated by the division of the above functional modules when implementing its functions. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above. In addition, the apparatus and method embodiments provided in the above embodiments belong to the same concept, and the specific implementation process can be found in the method embodiments, which will not be repeated here.

[0141] For example, please refer to Figure 8 , Figure 8 This is a structural block diagram of a computer device provided in one possible implementation of this application. The computer device 800 can be any electronic device with data calculation, processing, and storage functions. The computer device 800 can be used to implement the address storage method provided in the above embodiments.

[0142] Typically, a computer device 800 may include a processor 200 and a memory 820.

[0143] Processor 200 may include one or more processing cores, such as a quad-core processor or an octa-core processor. Processor 200 may be implemented using at least one hardware form selected from DSP, FPGA (Field Programmable Gate Array), and PLA (Programmable Logic Array). Processor 200 may also include a main processor and a coprocessor. The main processor, also known as the CPU, is used to process data in the wake-up state; the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, processor 200 may integrate a GPU, which is responsible for rendering and drawing the content to be displayed on the screen. In some embodiments, processor 200 may also include an AI processor, which is used to handle computational operations related to machine learning.

[0144] The memory 820 may include one or more computer-readable storage media, which may be non-transitory. The memory 820 may also include high-speed random access memory and NVM (Non-Virtual Machine). Volatile memory, such as one or more disk storage devices or flash memory devices. In some embodiments, the non-transitory computer-readable storage medium in memory 820 is used to store a computer program configured to be executed by one or more processors to implement the address storage method described above.

[0145] Those skilled in the art will understand that Figure 8 The structure shown does not constitute a limitation on the computer device 800, and may include more or fewer components than shown, or combine certain components, or use different component arrangements.

[0146] In an illustrative embodiment, a computer-readable storage medium is also provided, which stores a computer program that, when executed by a processor of a computer device, implements the address storage method described above. Optionally, the computer-readable storage medium may be a ROM (Read-Only Memory), RAM (Random Access Memory), CD-ROM (Compact Disc Read-Only Memory), magnetic tape, floppy disk, or optical data storage device, etc.

[0147] In an exemplary embodiment, a chip is also provided, the chip including programmable logic circuitry and / or program instructions stored in a computer-readable storage medium. A processor of a computer device reads the programmable logic circuitry and / or program instructions from the computer-readable storage medium, and executes the programmable logic circuitry and / or program instructions, causing the computer device to perform the address storage method described above.

[0148] In an exemplary embodiment, a computer program product is also provided, which includes a computer program that is loaded and executed by a processor to implement the address storage method described above.

[0149] It should be understood that "multiple" as used herein refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. Furthermore, the step numbers described herein are merely illustrative of one possible execution order. In some other embodiments, the steps may not be executed in numerical order, such as two steps with different numbers being executed simultaneously, or two steps with different numbers being executed in the reverse order of the illustration. This application does not limit this.

[0150] The above description is merely an exemplary embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. An address storage method, characterized in that, Applied in a processor, the processor includes a first storage unit and a second storage unit, the first storage unit being used to store address information of a first type of instruction, and the second storage unit being used to store address information of a second type of instruction; the method includes: The instruction type of the target instruction is determined, wherein the target instruction refers to an instruction that has not yet entered the execution stage and is in a state of waiting to be detected; If the instruction type of the target instruction is the first type of instruction, then the address information of the target instruction is stored in the first storage unit; If the target instruction is of the second type, then the address information of the target instruction is stored in the second storage unit.

2. The method according to claim 1, characterized in that, The first type of instruction includes a return instruction, and the second type of instruction includes other jump instructions besides the return instruction; The address information of the return instruction includes: the instruction address of the return instruction; The address information of the other jump instructions includes: the instruction address and the jump target address of the other jump instructions.

3. The method according to claim 2, characterized in that, The processor further includes a return address stack, which is used to store the jump target address of a return instruction. The method further includes: If the target instruction enters the execution phase, obtain the instruction address of the target instruction; If the instruction type of the target instruction is the first type of instruction, and the first storage unit stores address information that matches the instruction address of the target instruction, the jump target address of the target instruction is obtained from the return address stack; If the instruction type of the target instruction is the second type of instruction, and the second storage unit stores address information that matches the instruction address of the target instruction, the jump target address of the target instruction is obtained from the second storage unit; The instruction jump of the target instruction is executed according to the jump target address of the target instruction.

4. The method according to claim 3, characterized in that, After obtaining the instruction address of the target instruction, the method further includes: If the instruction type of the target instruction is the return instruction, a query operation is performed on the first storage unit to obtain a query result. The query result is used to indicate whether the instruction address of the target instruction is stored in the first storage unit.

5. The method according to claim 4, characterized in that, The step of obtaining the jump target address of the target instruction from the return address stack includes: If the query result indicates that the address of the target instruction is stored in the first storage unit, then the address stored at the top of the return address stack is read, and the address stored at the top of the stack is used as the jump target address of the target instruction.

6. A processor, characterized in that, The processor includes a first storage unit and a second storage unit; The first storage unit is used to store the address information of the first type of instruction; The second storage unit is used to store the address information of the second type of instructions.

7. The processor according to claim 6, characterized in that, The first type of instruction includes a return instruction, and the second type of instruction includes other jump instructions besides the return instruction; The address information of the return instruction includes: the instruction address of the return instruction; The address information of the other jump instructions includes: the instruction address and the jump target address of the other jump instructions.

8. The processor according to claim 7, characterized in that, The processor also includes a return address stack, which is used to store the jump target address of the return instruction.

9. A computer device, characterized in that, The computer device includes the processor as described in any one of claims 6 to 8.

10. An address storage device, characterized in that, Applied in a processor, the processor includes a first storage unit and a second storage unit, the first storage unit being used to store address information of a first type of instruction, and the second storage unit being used to store address information of a second type of instruction; the device includes: The determination module is used to determine the instruction type of the target instruction, which refers to an instruction that has not yet entered the execution stage and is in a state of waiting to be detected. A storage module is used to store the address information of the target instruction into the first storage unit if the instruction type of the target instruction is the first type of instruction; The storage module is further configured to store the address information of the target instruction into the second storage unit if the instruction type of the target instruction is the second type of instruction.

11. A computer device, characterized in that, The computer device includes a processor and a memory, the memory storing a computer program that is loaded and executed by the processor to implement the method as described in any one of claims 1 to 5.

12. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, which is loaded and executed by a processor to implement the method as described in any one of claims 1 to 5.

13. A computer program product, characterized in that, The computer program product includes a computer program that is loaded and executed by a processor to implement the method as described in any one of claims 1 to 5.

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