A data loopback error analysis method, device, equipment and readable storage medium

Abstract

This invention discloses a data loopback error analysis method, apparatus, device, and readable storage medium, applied in the field of data communication technology. The method includes: acquiring a count value in a setting register determined based on a preset number of target identifiers; wherein the setting register records the number of consecutive loopbacks of the preset number of target identifiers; the target identifiers are predetermined values ​​that are not scrambled during transmission at a set rate; and analyzing errors in the data loopback process based on the count value. Compared to current methods where valid information cannot be directly obtained from the device side when an error occurs in the data loopback function, this invention records the number of consecutive loopbacks of the preset number of target identifiers in a register. Therefore, based on the count value in the register, problems when errors occur in the loopback state can be quickly analyzed, errors can be quickly located, and error analysis and location efficiency can be improved.

Description

Technical Field

[0001] This invention relates to the field of data communication technology, and in particular to a data loopback error analysis method, apparatus, device, and readable storage medium. Background Technology

[0002] Loopback is a sub-state within the PCIe (External Component Interconnect Standard) link training mechanism. In this sub-state, the host transmitter sends valid data to the slave receiver, and then the slave transmitter transmits the received data back to the host receiver without modification (except for adding or deleting SKPs). Because the current mechanism typically loops the received data back directly at the PCIe PHY (Physical Layer Chip) layer, when the Loopback function encounters an error, valid information cannot be directly obtained from the device side.

[0003] It is evident that how to perform data loopback error analysis is a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0004] In view of this, the purpose of the present invention is to provide a data loopback error analysis method, apparatus, device and readable storage medium, which solves the technical problem that the prior art cannot directly perform data loopback error analysis.

[0005] To address the aforementioned technical problems, this invention provides a data loopback error analysis method, comprising: Obtain the count value determined by a preset number of target identifiers from the setting register; wherein, the setting register is used to record the number of times the preset number of target identifiers are continuously looped back; the target identifier is a predetermined value that will not be scrambled when transmitted at a set rate; Errors in the data loopback process are analyzed based on the count values.

[0006] On the one hand, before obtaining the count value determined by the target identifier based on a preset number in the setting register, the process also includes: When it is determined that both the host and slave have entered the data loopback state, the data loopback recording module is used to record the number of target identifiers that have looped back to the preset number; wherein, the data loopback recording module is used to record the data looped back from the physical coding sub-layer after the device enters the loopback activation sub-state, and to parse whether there is a case of continuous loopback of the preset number of target identifiers based on the loopback data; The count value in the register is determined based on the quantity.

[0007] On the one hand, determining the count value in the register based on the quantity includes: When the target identifier is first identified, a first identification control signal corresponding to the target identifier is generated; From the moment the target identifier is first identified, monitor the data transmission of a preset length; After the data transmission of the preset length is completed, the target identifier is re-identified. If the target identifier is identified, a second identifier control signal corresponding to the target identifier is generated. Perform an XOR operation on the first identification control signal and the second identification control signal to obtain the XOR operation result; The counter value in the register is updated based on the result of the XOR operation; wherein, the data stored in the register includes the loopback activation enable flag and the counter value of the target identifiers for a preset number of loopbacks; Once the XOR operation is complete, the first identifier control signal identified for the first time and the second identifier control signal identified for the second time are released, thus initiating the next round of target identifier identification.

[0008] On one hand, determining the count value in the register based on the quantity includes: When the duration of the loopback activation sub-state reaches a preset time threshold, or when the slave device switches from the loopback activation sub-state to the loopback exit sub-state, the determined count value is written into the register.

[0009] On the one hand, errors in the data loopback process are analyzed based on the count values, including: If the count value is zero, the error is located to the physical layer loopback function of the slave device; If the count value grows normally to the expected range, the error will be located to a physical channel or host malfunction.

[0010] On the one hand, obtaining the count value determined by the target identifier based on a preset number in the setting register includes: If the link test fails, determine the step of retrieving the count value determined by the target identifier based on a preset number in the setting register.

[0011] On the one hand, the target identifier is TS1; the preset number of target identifiers is two TS1s.

[0012] The present invention also provides a data loopback error analysis device, comprising: The count value acquisition module is used to acquire a count value determined by a preset number of target identifiers in a setting register; wherein, the setting register records the number of times the preset number of target identifiers are continuously looped back; the target identifier is a predetermined value that will not be scrambled when transmitted at a set rate; The error analysis module is used to analyze errors in the data loopback process based on the count values.

[0013] The present invention also provides a data loopback error analysis device, comprising: Memory, used to store computer programs; A processor is used to execute the computer program to implement the steps of the above-described data loopback error analysis method.

[0014] The present invention also provides a readable storage medium (i.e., a computer-readable storage medium) on which a computer program is stored, wherein when the computer program is executed by a processor, it implements the steps of the above-described data loopback error analysis method.

[0015] The present invention also provides a computer program product, including a computer program / instruction, which, when executed by a processor, implements the steps of the above-described data loopback error analysis method.

[0016] This invention provides a data loopback error analysis method, comprising: acquiring a count value determined based on a preset number of target identifiers in a setting register; wherein the setting register records the number of consecutive loopbacks of a preset number of target identifiers; the target identifiers are predetermined values ​​that are not scrambled when transmitted at a set rate; and analyzing errors in the data loopback process based on the count value.

[0017] As can be seen from the above technical solution, the beneficial effects of the present invention are as follows: Compared with the current situation where effective information cannot be directly obtained from the device side when the data loopback function encounters an error, the present invention records the number of times a target identifier with a preset number of consecutive loopbacks occurs through a register. Based on the count value in the register, the problem when an error occurs in the loopback state can be quickly located, which can quickly locate the error and improve the error location efficiency.

[0018] This invention also provides a data loopback error analysis device, equipment, and readable storage medium, which also have the above-mentioned beneficial effects. Attached Figure Description

[0019] To more clearly illustrate the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 A flowchart of a data loopback error analysis method provided in an embodiment of the present invention; Figure 2 A schematic diagram of a setting register provided for an embodiment of the present invention; Figure 3 A schematic diagram of a PCIe EP IP module provided for an embodiment of the present invention; Figure 4 This is a schematic diagram illustrating the interaction between a PCIe RC IP module and a PCIe EP IP module, provided as an embodiment of the present invention. Figure 5 A schematic diagram of a data loopback recording module provided in an embodiment of the present invention; Figure 6 A flowchart illustrating a data loopback method provided in an embodiment of the present invention; Figure 7 This is a schematic diagram of the structure of a data loopback error analysis device provided in an embodiment of the present invention; Figure 8 This is a schematic diagram of a data loopback error analysis device provided in an embodiment of the present invention. Detailed Implementation

[0021] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present invention.

[0022] The terms "comprising" and "having," and any variations thereof, in the specification and accompanying drawings of this invention are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the steps or units listed, but may include steps or units not listed.

[0023] Some terms that appear in the description of the embodiments of the present invention are subject to the following interpretation: PCIe (Peripheral Component Interconnect Express) is a standard for interconnecting external components. I / O: (Input / Output) PHY: (Physical Layer), the physical layer chip; SKP: SKP ordered set; PCS: (Physical Coding Sublayer) EIOS: (Electrical Idle Ordered Set)

[0024] To enable those skilled in the art to better understand the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0025] PCIe is an external interface protocol used for information transmission between the host and I / O devices. During the link equalization test on the PCIe device's transmitting side, it enters a Loopback state. In this state, the host compares the data sent by the transmitter and the data received by the receiver to obtain the bit error rate (BER) on the transmission side. Based on the relationship between this BER and e-12, the host determines whether the device passes the test: a BER less than e-12 indicates a pass; a BER greater than e-12 indicates a fail. The Loopback state is a sub-state within the PCIe link training machine. In this sub-state, the host transmitter sends valid data to the slave receiver, and then the slave transmitter transmits the received data back to the host receiver without modification (except for adding or deleting SKP ordered sets). Because the current mechanism typically receives data at the PCIe PHY layer, the controller and PHY layer registers cannot determine whether data has been sent or which registers represent the valid data type. Therefore, when the Loopback function encounters an error, it's impossible to obtain valid information directly from the device side. The only solution is to rely on a protocol analyzer to capture data packets and locate the error. However, using a protocol analyzer for packet capture testing still faces two problems: First, due to the complex structure of the testing instruments and the long testing time, locating the error is time-consuming. Second, when locating problems, the protocol analyzer can only determine whether data packets were received in the channel and their content; it cannot distinguish whether the specific cause is a PHY layer error or poor channel quality if no data packets were received. Therefore, the process still requires lengthy debugging and verification to pinpoint the problem.

[0026] Next, we will describe in detail a data loopback error analysis method provided by an embodiment of the present invention. Figure 1 A flowchart of a data loopback error analysis method provided in an embodiment of the present invention, the method may include: S101, obtain the count value determined by the target identifier based on the preset number in the setting register; wherein, the setting register records the number of times the target identifier is continuously looped back to the preset number; the target identifier is a predetermined value that will not be scrambled when transmitted at the set rate.

[0027] Each step in this embodiment can be executed by a designated electronic device, which can specifically be a server, portable terminal, host, slave, or other form. The setting register in this embodiment is a register designed by this invention. If named based on a preset number of target identifiers, this register can be a Loopback 2TS1 register. In this embodiment, the preset number of target identifiers can be two "0x1e", i.e., the target identifier is TS1; the preset number of target identifiers is two TS1s. It is understood that for an ordered set of TS1s, when its Symbol0 is "0x1e" at Gen3.0 (Generation 3) speed and above, this identifier will not be scrambled throughout the entire process from transmission from the Tx (transmitter) end to reception at the Rx (receiver) end, and therefore can always be identified.

[0028] It should be further explained that, based on any of the above embodiments, the step of retrieving the count value determined by a preset number of target identifiers in the setting register can include: when the link test fails, determining to execute the step of retrieving the count value determined by a preset number of target identifiers in the setting register. In this embodiment, the link test failure refers to the transmit-side link balancing test of the PCIe device. This embodiment provides the timing for retrieval, enabling timely problem identification and improved testing efficiency when the test fails.

[0029] It should be further noted that, based on any of the above embodiments, before obtaining the count value determined by the target identifier based on a preset number in the setting register, the following may also be included: S01, when it is determined that both the host and slave have entered the data loopback state, the data loopback recording module is used to record the number of target identifiers of the preset number of loopbacks; wherein, the data loopback recording module is used to record the data looped back from the physical coding sub-layer after the device enters the loopback activation sub-state, and to parse whether there is a case of continuous loopback of the preset number of target identifiers based on the loopback data.

[0030] This embodiment uses a data loopback state recording mechanism to record the data looped back from the PCS layer after the device enters the Loopback. Active sub-state (loopback activation sub-state), and parses out whether there is a continuous loopback 2TS1 and the number of continuous loopback 2TS1.

[0031] S02 determines the count value in the register based on the quantity.

[0032] This embodiment allows the counter value to be written to the corresponding register based on the quantity. This register is located in the PCIe device's PHY register list, and one register is provided for each channel. The register is accessible via the APB (Advanced Peripheral Bus) interface. Based on this register, problems can be quickly located when errors occur in the Loopback state machine, shortening testing time.

[0033] It should be further noted that, based on any of the above embodiments, in order to improve the accuracy of the count value determination, the count value in the quantity determination register may include: S021, when the target identifier is first identified, generate the first identification control signal corresponding to the target identifier.

[0034] In this embodiment, upon first detection of "0x1e", the corresponding control signal is pulled high to set to "1", meaning the first identifier control signal is 1. TS1 identification in this embodiment involves recognizing the "1e" identifier in the data received through the data input interface. It is understandable that during the data loopback testing phase, when the Loopback_en (loopback enable signal) is enabled, the data sent from the RC (master) side Tx terminal loops back through the EP (slave) side PCS layer. The data sent from the RC side Tx (transmitter) terminal has already been scrambled; therefore, TS1 cannot be identified using the combination of symbol0 "0x1e" + symbol10 "0x4a". Instead, TS1 is identified by recognizing "0x1e".

[0035] S022, starting from the moment the target identifier is first identified, monitor the data transmission of a preset length.

[0036] In this embodiment, the preset length can be 16 bytes (bits). After 16 bytes of data transmission (including the first "0x1e"), the "1e" identifier is identified again.

[0037] S023, after the data transmission of the preset length is completed, the target identifier is re-identified. If the target identifier is identified, the second identifier control signal corresponding to the target identifier is generated.

[0038] In this embodiment, if the identifier "0x1e" is detected for the second time, the corresponding control signal is pulled high and set to "1".

[0039] S024, perform an XOR operation on the first identifier control signal and the second identifier control signal to obtain the XOR operation result.

[0040] In this embodiment, the two control signals are XORed (1 ⊙ 1 = 1), and the result of the XOR operation is transmitted to the TS1 counter module for incrementing the count by 1. At this time, the counter records the value of 2 TS1 signals transmitted each time.

[0041] S025, update the count value in the register based on the result of the XOR operation; wherein, the data stored in the register includes the loopback activation enable flag and the count value of the target identifier for the preset number of loopbacks.

[0042] In this embodiment, the register is the Loopback 2TS1 register, configured as follows: Figure 2 As shown, Figure 2 This is a schematic diagram of a setting register provided in an embodiment of the present invention. The Loopback 2TS1 register represents the Loopback 2TS1 register; Reserved indicates a reserved bit; LAE (Loopback. Active Enable0): bit width is 1, this bit is used to indicate that the slave device enters the Loopback. Active sub-state, set to 1 after the Loopback_en signal goes high, initial value is 1'b0, attribute: R / W; L2TS1C 0 (Loopback 2TS1 Counter): bit width is 3, used to indicate the number of consecutive 2TS1 ordered sets received after Loopback_en goes high, initial value is 3'b000, attribute: R / W; the above registers will be located in the PCIe device PHY register list, and each channel contains a corresponding register. The registers can be accessed through the APB (Advanced Peripheral Bus) interface. Therefore, there are a total of 16 Loopback 2TS1 registers.

[0043] S026, after the XOR operation is completed, the first identifier control signal identified in the first identification and the second identifier control signal identified in the second identification are released, and the identification of the target identifier in the next round is started.

[0044] In this embodiment, the control signal that first recognizes "0x1e" after the XOR operation is completed, and the control signal that second recognizes "0x1e" are both released as "0". This embodiment provides a specific method for determining the count value, improving the accuracy of the count value determination.

[0045] It should be further explained that, based on any of the above embodiments, the count value determined in the register based on the quantity can include: determining to write the count value to the register when the duration of the loopback active sub-state reaches a preset time threshold, or when the slave device switches from the loopback active sub-state to the loopback exit sub-state. In this embodiment, the "0x1e" identifier is identified again after transmitting 16 bytes of data, thereby initiating the next round of 2TS1 identification and counting. The counter value is written to the corresponding Loopback 2TS1 register after the slave device transitions from the Loopback.Active sub-state to the Loopback.Exit (loopback exit sub-state) or 100ms after the device enters the Loopback.Active sub-state. This embodiment provides a specific method for updating the count value, improving the accuracy of the update.

[0046] S102, Analyze errors in the data loopback process based on count values.

[0047] In this embodiment, the error analysis of the data loopback process mainly refers to the analysis based on the size of the count value to determine the specific reasons for the error in the data loopback.

[0048] It should be further noted that, based on any of the above embodiments, errors in the above-described data loopback process based on count values ​​may include: S1021, If ​​the count value is zero, the error is located to the physical layer loopback function of the slave device; S1022, if the count value increases normally to the expected range, the error will be located to a physical channel or host malfunction.

[0049] This embodiment performs error localization only when the test fails. In this embodiment, if the count value is zero, the error is determined to originate from a physical layer loopback function failure on the device side: "Device side" refers to the slave device (EP). "Physical layer loopback function" specifically refers to the loopback path and control logic (Loopback_en signal path) of the slave device's internal PHY (especially the PCS layer). A count value of zero directly proves that the internal loopback path is not working effectively. "If the count value increases normally to the expected range, the error is determined to originate from a physical channel or host malfunction": The implicit premise of this statement is that a normal count value indicates that the loopback function on the "device side" (i.e., the slave device) itself is intact. Therefore, the root cause of the problem should be shifted to the external physical link (channel) between the slave and the host, or the transmitting / receiving components on the host (RC) side. This embodiment provides a specific method for error localization based on count values, improving the accuracy of error localization.

[0050] It should be further explained that this embodiment can add a timestamped count log register group on both the master and slave sides. Instead of simply recording the final total value, it stores the current instantaneous count value along with a relative timestamp into a circular buffer at fixed time intervals (e.g., every N 2TS1 pairs). This records the count change curve over time. Error localization is based on this curve. A plateau, stagnation, or sudden drop in count growth indicates an intermittent problem, possibly caused by voltage instability, temperature changes, or internal state machine errors. By comparing the time points when the count stagnates on the master and slave sides, the source of the intermittent fault can be precisely located.

[0051] An embodiment of the present invention provides a data loopback error analysis method, which may include: S101, obtaining a count value determined based on a preset number of target identifiers in a setting register; wherein, the setting register records the number of consecutive loopbacks of the preset number of target identifiers; the target identifier is a predetermined value that is not scrambled during transmission at a set rate; S102, analyzing errors in the data loopback process based on the count value. Compared with the current method where effective information cannot be directly obtained from the device side when an error occurs in the data loopback function, the present invention records the number of consecutive loopbacks of the preset number of target identifiers in a register, thereby quickly locating the problem when an error occurs in the loopback state based on the count value in the register, which can quickly locate the error and improve the error location efficiency.

[0052] In existing solutions, when the host enters Loopback Active mode, data is received in the PMA (Physical Modeling Area) of the PHY and transmitted to the PCS layer. Then, the data is looped back to the peer at the PCS layer. The loopback occurs when the slave receives two TS1 values ​​with the Loopback bit high. Therefore, the data returned from the slave to the host does not originate from the PCIe control layer, making it impossible to locate the problem from the Tx-data in the query link training machine. This existing solution cannot obtain information about whether data loopback has occurred or the loopback data from the Loopback slave (device side). Therefore, when the Loopback function encounters an error, valid information cannot be directly obtained from the device side. Clearly, how to quickly locate errors is a critical technical problem that needs to be solved in the Loopback mechanism.

[0053] This invention proposes a data loopback state recording mechanism and hardware module. The hardware module mainly includes a controller and a PHY physical layer chip. The controller implements the transaction layer, link layer, and some physical layer logic of the PCIe protocol. The PHY includes PCS and PMA modules. The PCS module, the digital part of the PHY, implements the PIPE protocol and data processing, and includes a data loopback recording module and a Loopback 2TS1 register. The data loopback recording module records the data looped back from the PCS layer after the device enters the Loopback.Active sub-state and parses out whether there are consecutive 2TS1 loopbacks. The Loopback 2TS1 register records the number of consecutive 2TS1 loopbacks. Based on this register, problems can be quickly located when errors occur in the Loopback state machine, shortening testing time. This solves the problem of not being able to determine whether data loopback has occurred in the Loopback slave. It also solves the problem of not being able to quickly locate the source of errors when data is not received.

[0054] For a clearer understanding of this invention, please refer to the following details. Figure 3 , Figure 3 This diagram illustrates a PCIeEP IP module according to an embodiment of the present invention. The module mainly includes a controller and a PHY. The controller implements the transaction layer, link layer, and part of the physical layer logic of the PCIe protocol. The PHY implements the remaining physical layer logic of the PCIe protocol. The PHY can be further divided into a PCS module and a PMA module. The PCS module, the digital part of the PHY, is used to implement the PIPE protocol and data processing, and includes a data loopback recording module and a Loopback 2TS1 register. The data loopback recording module identifies consecutive 2TS1 loopbacks, and the Loopback 2TS1 register records the number of consecutive 2TS1 loopbacks. The PMA module is used for serial-to-parallel conversion and data transmission and reception.

[0055] The data loopback status recording mechanism uses a data loopback recording module to record the data looped back from the PCS layer after the device (slave) enters the Loopback.Active (loopback activation sub-state) sub-state, and parses out whether there are consecutive 2TS1 loopbacks and the number of consecutive 2TS1 loopbacks (Type 1 loopback mode of TS link 2). For example... Figure 4 As shown, Figure 4 This is a schematic diagram illustrating the interaction between a PCIe RC IP module (host) and a PCIe EP IP module (slave) according to an embodiment of the present invention. Wherein... Figure 4The example illustrates the data transmission and loopback path of the controller Tx (receiver) under the control of the Loopback_en (loopback enable signal). A data loopback recording module exists in the PCIe EP IP, which is also enabled by the Loopback_en signal. The internal structure diagram of this module is shown below. Figure 5 As shown, Figure 5 This is a schematic diagram of a data loopback recording module provided in an embodiment of the present invention. When the Loopback_en signal is enabled, the TS1 identification module identifies the "1e" identifier of the data received through the data input interface, and the counter records the value of 2 TS1s transmitted each time.

[0056] Based on the above mechanism, the PCIe Loopback process is as follows: Figure 6 As shown, Figure 6 This is a flowchart illustrating a data loopback method provided in an embodiment of the present invention. The count value obtained based on this data loopback method can be used for error location. The process is as follows: Step 1: Guided by the software layer, the host initiates the Loopback_Req (loopback request signal) and enters the Loopback.Entry sub-state. In this sub-state, the host sends two TS1 signals, in which the Loopback bit in the TS1 signal is pulled high.

[0057] Step 2: The slave device receives two TS1s and enters the Loopback Entry.

[0058] Step 3: The slave device continues to receive 2 more TS1s and enters Loopback. Active mode.

[0059] Step 4: The slave device pulls the Loopback_en signal high to start looping back the ordered set (at least 2 TS1s) sent from the RC side TX. The Loopback bit in TS1 is pulled high, and the master device enters Loopback Active mode. The data loopback recording module is enabled to record the number of Loopback 2TS1s and write the number value to the Loopback 2TS1 register of the corresponding channel.

[0060] Step 5: The master sends valid data in the Loopback.Active state. The slave sends back the valid data received in the loopback state to the master. This data does not need to be modified in any way, only the SKP Symbol needs to be added.

[0061] Step 6: Under guidance, the master switches to the Loopback.Exit sub-state, in which it sends 8 consecutive ordered sets of EIOS to the slave. After receiving the ordered sets of EIOS, the receiver enters the Loopback.Exit state after a certain period of time. Before this, the slave continues to loop back the received data to the master.

[0062] This invention proposes a data loopback state recording mechanism and hardware module. The hardware module mainly includes a controller and a PHY. The controller implements the transaction layer, link layer, and part of the physical layer logic of the PCIe protocol; the PHY implements the remaining physical layer logic of the PCIe protocol. The PHY can be further divided into a PCS (Physical Coding Sublayer) and a PMA module. The PCS module, the digital part of the PHY, implements the PIPE protocol and data processing, and includes a data loopback recording module and a Loopback 2TS1 register. The data loopback recording module identifies consecutive 2TS1 loopbacks, and the Loopback 2TS1 register records the number of consecutive 2TS1 loopbacks. The PMA module is used for serial-to-parallel conversion and data transmission and reception. The data loopback state recording mechanism uses the data loopback recording module to record the data looped back from the PCS layer after the device enters the Loopback.Active sub-state and parses it to determine whether consecutive 2TS1 loopbacks exist and the number of consecutive 2TS1 loopbacks. After transitioning from the Loopback.Active substate to Loopback.Exit, or 100ms after the device enters the Loopback.Active substate, the counter value is written to the corresponding Loopback 2TS1 register. This register is located in the PCIe device PHY register list, and each channel contains one. The register can be accessed via the APB interface. Based on this register, problems when errors occur in the Loopback state machine can be quickly located, shortening testing time.

[0063] The data loopback error analysis device provided in the embodiments of the present invention will be described below. The data loopback error analysis device described below can be referred to in correspondence with the data loopback error analysis method described above.

[0064] Figure 7 A schematic diagram of a data loopback error analysis device provided in an embodiment of the present invention may include: The counting value acquisition module 100 is used to acquire a counting value determined based on a preset number of target identifiers in a setting register; wherein, the setting register records the number of times the preset number of target identifiers are continuously looped back; the target identifier is a predetermined value that will not be scrambled when transmitted at a set rate; Error analysis module 200 is used to analyze errors in the data loopback process based on the count value.

[0065] Furthermore, the data loopback error analysis apparatus based on any of the above embodiments may further include: The quantity determination module is used to determine the number of target identifiers that loop back to the preset number when both the host and slave enter the data loopback state. The data loopback recording module is used to record the data looped back from the physical coding sub-layer after the device enters the loopback activation sub-state, and to parse whether there is a case of continuous loopback of the preset number of target identifiers based on the loopback data. A count value determination module is used to determine the count value in the register based on the quantity.

[0066] Furthermore, based on any of the above embodiments, the count value determination module may include: The first identifier control signal determination unit is used to generate a first identifier control signal corresponding to the target identifier when the target identifier is first identified. A preset length determination unit is used to monitor data transmission of a preset length from the moment the target identifier is first identified; The second identifier control signal determination unit is used to re-identify the target identifier after the data transmission of the preset length is completed. If the target identifier is identified, a second identifier control signal corresponding to the target identifier is generated. The arithmetic unit is used to perform an XOR logic operation on the first identifier control signal and the second identifier control signal to obtain the XOR operation result. The counter value update unit is used to update the counter value in the register based on the result of the XOR operation; wherein, the data stored in the register includes a loopback activation enable flag and a counter value of a preset number of target identifiers for loopback; The next round of identification unit is used to release the first identifier control signal identified in the first round and the second identifier control signal identified in the second round after the XOR operation is completed, thereby determining to start the identification of the target identifier in the next round.

[0067] Furthermore, based on any of the above embodiments, the count value determination module may include: The count value writing module is used to determine to write a predetermined number of count values ​​into the register when the duration of the loopback activation sub-state reaches a preset time threshold, or when the slave device switches from the loopback activation sub-state to the loopback exit sub-state.

[0068] Furthermore, based on any of the above embodiments, the error analysis module 200 may include: The first error location unit is used to locate the error to the physical layer loopback function of the slave device if the count value is zero. The second error location unit is used to locate the error to a physical channel or host malfunction if the count value grows normally to the expected range.

[0069] Furthermore, based on any of the above embodiments, the count value acquisition module 100 may include: The count value acquisition unit is used to determine the step of acquiring the count value determined by the target identifier based on a preset number in the setting register when the host test fails.

[0070] Furthermore, based on any of the above embodiments, the target identifier is TS1; the preset number of target identifiers is two TS1s.

[0071] It should be noted that the order of the modules and units in the aforementioned data loopback error analysis device can be changed without affecting the logic.

[0072] Figure 7 The description of the features in the corresponding embodiments can be found in [reference needed]. Figure 7 The relevant descriptions of the corresponding embodiments will not be repeated here.

[0073] This invention provides a data loopback error analysis device, which may include: a count value acquisition module 100, used to acquire a count value determined by a preset number of target identifiers in a setting register; wherein the setting register records the number of consecutive loopbacks of the preset number of target identifiers; the target identifier is a predetermined value that is not scrambled during transmission at a set rate; and an error analysis module 200, used to analyze errors in the data loopback process based on the count value. Compared with the current method where effective information cannot be directly obtained from the device side when an error occurs in the data loopback function, this invention records the number of consecutive loopbacks of the preset number of target identifiers in a register, thereby quickly locating the problem when an error occurs in the loopback state based on the count value in the register, thus improving error location efficiency.

[0074] The following describes a data loopback error analysis device provided by an embodiment of the present invention. The data loopback error analysis device described below and the data loopback error analysis method described above can be referred to in correspondence.

[0075] Figure 8 This is a schematic diagram of the structure of a data loopback error analysis device provided in an embodiment of the present invention, as shown below. Figure 8 As shown, the error location includes: a memory 60 for storing computer programs; The processor 61 is used to implement the steps of the data loopback error analysis method as described in the above embodiment when executing a computer program.

[0076] The data loopback error analysis device provided in this embodiment may include, but is not limited to, smartphones, tablets, laptops, or desktop computers.

[0077] The processor 61 may include one or more processing cores, such as a quad-core processor or an octa-core processor. The processor 61 may be implemented using at least one hardware form selected from Digital Signal Processing (DSP), Field-Programmable Gate Array (FPGA), and Programmable Logic Array (PLA). The processor 61 may also include a main processor and a coprocessor. The main processor, also known as the Central Processing Unit (CPU), is used to process data in the wake-up state; the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, the processor 61 may integrate a Graphics Processing Unit (GPU), which is responsible for rendering and drawing the content to be displayed on the screen. In some embodiments, the processor 61 may also include an Artificial Intelligence (AI) processor, which handles computational operations related to machine learning.

[0078] The memory 60 may include one or more computer-readable storage media, which may be non-transitory. The memory 60 may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices or flash memory devices. In this embodiment, the memory 60 is used to store at least the following computer program 601, which, after being loaded and executed by the processor 61, is capable of implementing the relevant steps of the data loopback error analysis method disclosed in any of the foregoing embodiments. In addition, the resources stored in the memory 60 may also include an operating system 602 and data 603, etc., and the storage method may be temporary storage or permanent storage. The operating system 602 may include Windows, Unix, Linux, etc. The data 603 may include, but is not limited to, the data required by the data loopback error analysis method.

[0079] In some embodiments, the data loopback error analysis device may further include a display screen 62, an input / output interface 63, a communication interface 64, a power supply 65, and a communication bus 66.

[0080] Those skilled in the art will understand that Figure 8 The structure shown does not constitute a limitation on the data loopback error analysis device and may include more or fewer components than shown.

[0081] It is understood that if the data loopback error analysis method in the above embodiments is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the current technology, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and executes all or part of the steps of the methods in the various embodiments of the present invention. The aforementioned storage medium includes: USB flash drive, mobile hard drive, read-only memory (ROM), random access memory (RAM), electrically erasable programmable ROM, register, hard disk, removable disk, CD-ROM, magnetic disk, or optical disk, and other media capable of storing program code.

[0082] Based on this, embodiments of the present invention also provide a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps of the data loopback error analysis method described above.

[0083] The data loopback error analysis method provided by the embodiments of the present invention has been described in detail above. The various embodiments in the specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section.

[0084] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0085] The foregoing has provided a detailed description of a data loopback error analysis method, apparatus, device, and readable storage medium provided by the present invention. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The descriptions of the embodiments above are merely for the purpose of helping to understand the method and core ideas of the present invention. It should be noted that those skilled in the art can make various improvements and modifications to the present invention without departing from its principles, and these improvements and modifications also fall within the protection scope of the present invention.

Claims

1. A method for analyzing data loopback errors, characterized in that, include: Obtain the count value determined by a preset number of target identifiers from the setting register; wherein, the setting register is used to record the number of times the preset number of target identifiers are continuously looped back; the target identifier is a predetermined value that will not be scrambled when transmitted at a set rate; Errors in the data loopback process are analyzed based on the count values.

2. The data loopback error analysis method according to claim 1, characterized in that, Before retrieving the count value determined by the target identifier based on a preset number from the setting register, the process also includes: When it is determined that both the host and slave have entered the data loopback state, the data loopback recording module is used to record the number of target identifiers that have looped back to the preset number; wherein, the data loopback recording module is used to record the data looped back from the physical coding sub-layer after the device enters the loopback activation sub-state, and to parse whether there is a case of continuous loopback of the preset number of target identifiers based on the loopback data; The count value in the register is determined based on the quantity.

3. The data loopback error analysis method according to claim 2, characterized in that, Determining the count value in the register based on the quantity includes: When the target identifier is first identified, a first identification control signal corresponding to the target identifier is generated; From the moment the target identifier is first identified, monitor the data transmission of a preset length; After the data transmission of the preset length is completed, the target identifier is re-identified. If the target identifier is identified, a second identifier control signal corresponding to the target identifier is generated. Perform an XOR operation on the first identification control signal and the second identification control signal to obtain the XOR operation result; The counter value in the register is updated based on the result of the XOR operation; wherein, the data stored in the register includes the loopback activation enable flag and the counter value of the target identifiers for a preset number of loopbacks; Once the XOR operation is complete, the first identifier control signal identified for the first time and the second identifier control signal identified for the second time are released, thus initiating the next round of target identifier identification.

4. The data loopback error analysis method according to claim 2, characterized in that, Determining the count value in the register based on the quantity includes: When the duration of the loopback activation sub-state reaches a preset time threshold, or when the slave device switches from the loopback activation sub-state to the loopback exit sub-state, the determined count value is written into the register.

5. The data loopback error analysis method according to any one of claims 1 to 4, characterized in that, Errors in the data loopback process are analyzed based on the count values, including: If the count value is zero, the error is located to the physical layer loopback function of the slave device; If the count value grows normally to the expected range, the error will be located to a physical channel or host malfunction.

6. The data loopback error analysis method according to claim 1, characterized in that, Retrieve the count value determined by the target identifier based on a preset number from the setting register, including: If the link test fails, determine the step of retrieving the count value determined by the target identifier based on a preset number in the setting register.

7. The data loopback error analysis method according to claim 1, characterized in that, The target identifier is TS1; the preset number of target identifiers is two TS1s.

8. A data loopback error analysis device, characterized in that, include: The count value acquisition module is used to acquire a count value determined by a preset number of target identifiers in a setting register; wherein, the setting register records the number of times the preset number of target identifiers are continuously looped back; the target identifier is a predetermined value that will not be scrambled when transmitted at a set rate; The error analysis module is used to analyze errors in the data loopback process based on the count values.

9. A data loopback error analysis device, characterized in that, include: Memory, used to store computer programs; A processor for executing the computer program to implement the steps of the data loopback error analysis method as described in any one of claims 1 to 7.

10. A readable storage medium, characterized in that, The readable storage medium stores a computer program that, when executed by a processor, implements the steps of the data loopback error analysis method as described in any one of claims 1 to 7.

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