Data access methods, devices, cache units, and computer systems
By adopting a cache delay allocation strategy in the computer system, the resource waste caused by the predefined granularity of cache lines is solved, and the available cache capacity and utilization efficiency are improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- T-HEAD (SHANGHAI) SEMICON CO LTD
- Filing Date
- 2026-01-28
- Publication Date
- 2026-06-02
Smart Images
Figure CN122132336A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of computer technology, and more specifically, to a data access method, apparatus, cache unit, and computer system. Background Technology
[0002] In current computer systems, especially after the introduction of large models, a memory management mechanism with multiple page table granularities is needed. In order to reduce data access latency, storing page tables near prefetch requests in the same cache line is an effective way. However, allocating cache lines according to predefined page table granularity will reduce the available cache capacity and thus waste cache resources. Summary of the Invention
[0003] In view of this, embodiments of the present invention provide a data access method, apparatus, cache unit, and computer system. The method employs a cache delay allocation strategy and, upon receiving a memory access response, determines whether the page table range of a previously requested memory access response covers the current memory access response by using the status information in the corresponding target entry. Simultaneously, it checks whether a cache line with a matching address exists. Only after determining that no local memory access response exists in the current cache is a new cache line allocated. Based on this, the present application can effectively avoid the problem of duplicate page table storage, improve the available cache capacity, and avoid resource waste.
[0004] In a first aspect, embodiments of the present invention provide a data access method, the method comprising: Obtain the memory access response for the target request, where the target request is a cache miss request; In response to the status information in the target entry corresponding to the target request indicating an unready state, and the absence of a cache line matching the address information of the target request, a corresponding target cache line is allocated based on a predetermined replacement algorithm; The memory access response is stored in the target cache line.
[0005] Furthermore, the method also includes: Query the missing status holding register for each request entry; The status information and cache index information in the matching entries are updated to the ready status and the target index corresponding to the target cache line, respectively. The matching entries are used to represent request entries whose memory access address information is covered by the page table range corresponding to the memory access response.
[0006] Furthermore, the method also includes: In response to the status information in the target entry corresponding to the target request, which indicates a ready state, the cache index information of the target entry is obtained; The target cache line corresponding to the memory access response is determined based on the cache index information.
[0007] Furthermore, the method also includes: Compare the address information of the target request with the address information of each cache line; In response to the existence of partially missed cache lines, the partially missed cache lines are identified as target cache lines.
[0008] Furthermore, the page table attribute information in the partially missed cache lines is consistent with the memory access response.
[0009] Furthermore, the method also includes: Obtain the target request; In response to the target request not hitting the cache, a target entry corresponding to the target request is generated. The target entry includes request additional information, address information, status information, and cache index information.
[0010] In a second aspect, embodiments of the present invention provide a data access device, the device comprising: The acquisition unit is used to acquire the memory access response of the target request, wherein the target request is not a cached miss request; The allocation unit is used to allocate the corresponding target cache line based on a predetermined replacement algorithm in response to the status information in the target entry corresponding to the target request indicating an unprepared state and the absence of a cache line matching the address information of the target request. A storage unit is used to store the memory access response to the target cache line.
[0011] Thirdly, embodiments of the present invention provide a cache unit, the cache unit comprising: The missing status holding register is used to store cache access requests for data that have been missed in the cache. The data cache area includes multiple cache lines, which are used to cache memory access data; The controller is used to execute the methods described above.
[0012] Fourthly, embodiments of the present invention provide a computer system, the computer system comprising: The computing engine is used to generate data access requests and send the data access requests to the cache unit; The cache unit as described above; and Memory is used to respond to a received data memory access request and return a memory access response corresponding to the data memory access request.
[0013] Fifthly, embodiments of the present invention provide a computer program product, the computer program product including a computer program / instruction, which, when executed by a processor, implements the method described above.
[0014] In a sixth aspect, embodiments of the present invention provide a computer-readable storage medium storing a computer program that, when executed by a processor, implements the method described above.
[0015] This embodiment of the invention obtains the memory access response of a target request that has missed a cache hit. The response is based on the status information in the target entry corresponding to the target request, indicating an unprepared state, and the absence of a cache line matching the address information of the target request. A corresponding target cache line is allocated based on a predetermined replacement algorithm, and the memory access response is stored in the target cache line. Therefore, this embodiment employs a cache delay allocation strategy. Upon receiving the memory access response, it determines whether the page table range of a previously requested memory access response covers the current memory access response by checking the status information in the corresponding target entry. Simultaneously, it checks whether a cache line with a matching address exists. Only after determining that there is no local memory access response in the current cache is a new cache line allocated. Based on this, this embodiment effectively avoids the problem of duplicate page table storage, improves the available cache capacity, and avoids resource waste. Attached Figure Description
[0016] The above and other objects, features and advantages of the present invention will become clearer from the following description of embodiments of the invention with reference to the accompanying drawings, in which: Figure 1 This is a flowchart of a data access method according to an embodiment of the present invention; Figure 2 This is a schematic diagram of the data access process according to an embodiment of the present invention; Figure 3 This is a schematic diagram of a partial miss determination process according to an embodiment of the present invention; Figure 4 This is a schematic diagram of the entry update process according to an embodiment of the present invention; Figure 5 This is a schematic diagram of a data access device according to an embodiment of the present invention; Figure 6 This is a schematic diagram of a cache unit according to an embodiment of the present invention; Figure 7 This is a schematic diagram of a computer system according to an embodiment of the present invention. Detailed Implementation
[0017] The present application is described below based on embodiments, but it is not limited to these embodiments. In the detailed description of the present application below, certain specific details are described in detail. Those skilled in the art can fully understand the present application without these details. To avoid obscuring the substance of the present application, well-known methods, processes, flows, elements, and circuits are not described in detail.
[0018] Furthermore, those skilled in the art should understand that the accompanying drawings provided herein are for illustrative purposes only and are not necessarily drawn to scale.
[0019] Unless the context explicitly requires it, words such as "including" or "contains" throughout the application should be interpreted as including rather than exclusive or exhaustive; that is, meaning "including but not limited to".
[0020] In the description of this application, it should be understood that the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Furthermore, in the description of this application, unless otherwise stated, "a plurality of" means two or more.
[0021] The solutions described in this specification and embodiments, if involving the processing of personal information, will be processed only on the premise of having a legal basis (such as obtaining the consent of the personal information subject, or being necessary for the performance of a contract), and will only be processed within the scope stipulated or agreed upon. A user's refusal to process personal information beyond what is necessary for basic functions will not affect the user's use of basic functions.
[0022] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.
[0023] Before providing a further detailed description of the embodiments of this application, the nouns and terms involved in the embodiments of this application will be explained, and the nouns and terms involved in the embodiments of this application shall be interpreted as follows.
[0024] Cache: A high-speed cache used to temporarily store frequently accessed data and instructions by the processor, reducing the number of accesses to slower main memory and thus improving overall performance. When the processor needs to retrieve data, it first checks the cache; if the data exists, it is called a cache hit; if the data does not exist, a cache miss occurs.
[0025] Cache line: A data transmission area consisting of several consecutive bytes. It is the smallest unit for data storage and transmission in the cache and for data exchange between main memory and cache. According to the mapping method, it can be divided into three types: direct mapping, set-associative and fully associative.
[0026] Set-associative cache: A cache that uses a set-associative mapping method. In a set-associative cache, the cache is divided into multiple sets, and each set contains several cache lines (also known as the way or associativity). A memory address is mapped to any line within a specific set. This design balances the simplicity of direct-mapped caches with the flexibility of fully associative caches.
[0027] Late Allocation is a strategy used in system resource management. Its core idea is to postpone the actual allocation of resources as much as possible until the resource is actually needed. Before that, only logical / virtual mappings or reserved information are retained. If the resource is not ultimately used, there is no need to actually allocate it, thus saving resources.
[0028] Sector: A cache organization method that divides a cache line into multiple fixed-size sub-blocks, allowing for finer-grained data management and replacement, improving space locality utilization efficiency and reducing bandwidth overhead.
[0029] In this scenario, assuming each request accesses a sub-block sector of a cache line, the first cache miss is called a cacheline miss. The cache will allocate a cache line for this request and request the required sector data from memory. The second cache miss, which accesses the same cache line but a different sub-block, is called a sector miss. The cache will then request the required sector data from memory. Furthermore, in MSHR, requests following a sector miss must wait for the cacheline miss requests to be popped before they can be popped, ensuring the accuracy of data operations.
[0030] VA (virtual address): Virtual address.
[0031] PA (physical address): Physical address.
[0032] Page: The page table stores the mapping from virtual addresses to physical addresses and the corresponding permissions.
[0033] MSHR (Miss Status Holding Register): is a hardware structure used to record and manage the status of cache miss requests, supporting concurrent miss handling and data backfill coordination in non-blocking caches.
[0034] MSHR entry: A specific entry or table item in MSHR. Each entry stores detailed information about a missed request, such as memory address and cache line status.
[0035] MSHR_Ready: The status flag of the entry in MSHR. A value of 1 indicates that the data has been stored in the corresponding cache, and a value of 0 indicates that the data has not yet been stored.
[0036] Cache miss: The request did not find a valid cache line.
[0037] Partial_miss: The request is compared with a valid cache line. If a valid cache line that matches the request address exists, that is, the cache is hit at the cacheline level, but one or more sectors accessed by the request are missing in the hit valid cache line, this situation is called Partial_miss.
[0038] Hit rate: The percentage of requests that successfully hit a valid cached line out of all requests.
[0039] TLB (Translation Lookaside Buffer): The translation lookaside buffer is a cache in the memory management unit (MMU) used to cache page table entries from virtual addresses to physical addresses.
[0040] Based on the above explanation of the nouns and terms involved in the embodiments of this application, the data access method provided in the embodiments of this application, as well as the cache unit, computer system, etc., that apply it, are explained.
[0041] Figure 1 This is a flowchart of a data access method according to an embodiment of the present invention. In this embodiment, a delayed allocation cache strategy is adopted, that is, cache resources are allocated after the memory access response is returned. Figure 1 As shown, the data access method of this embodiment includes the following steps: Step S110: Obtain the memory access response for the target request. The target request is a cache miss request.
[0042] Optionally, in this embodiment, a target request is obtained, and in response to a cache miss, a target entry corresponding to the target request is generated. Further, the cache unit includes a hit test unit to determine whether a received data memory access request hits the cache. For a cache miss request, a request entry is allocated in the MSHR to store the cache miss request information, and the cache miss request is sent downstream (e.g., the next level cache or content) to obtain the corresponding memory access response (i.e., the requested data). The request entry includes request sideinfo, address information (e.g., virtual address VA), status information (ready flag), and cache line index information (cacheline_index). The initial value of the status information in the request entry is ready flag = 0. Since this embodiment uses delayed allocation, the initial value of the cache line index information is cacheline_index = 0, indicating that the cache line corresponding to the request has not yet been allocated.
[0043] Step S120: In response to the status information in the target entry corresponding to the target request indicating an unprepared state and the absence of a cache line matching the address information of the target request, a corresponding target cache line is allocated based on a predetermined replacement algorithm.
[0044] Furthermore, the cache unit receives the memory access response from the downstream target request and determines whether the data range corresponding to the memory access response is covered by the access response of the previous request, so as to avoid the same data being cached repeatedly.
[0045] In one optional implementation, upon receiving a memory access response from the downstream system, this embodiment queries the MSHR for the target entry corresponding to the target request, retrieves the address information of the target request from the target entry, and executes three cache index determination steps in parallel: The first step involves initiating a predetermined replacement algorithm to obtain the newly allocated cache line. The second step compares the address information of the target request with the address information corresponding to each valid cache line to determine if a cache line matching the address information of the target request exists. The third step involves querying the status information and cache index information in the target entry to determine whether the status information in the target entry was prepared before the current memory access response was returned, in order to determine whether the cache index can be directly obtained from the cache index information in the target entry.
[0046] This embodiment executes the three cache index determination steps in parallel and obtains the cache index of the memory access response for the target request based on the three results. Furthermore, this embodiment sets a predetermined priority order for the results of the three steps. Since the allocation of a new cache line is performed on the premise that there is no duplicate caching, the result of the new cache line allocation is set to the lowest priority. The priority order of the address information matching result of the current valid cache line and the entry information in MSHR can be customized. For example, the judgment of the entry information in MSHR can be configured as the highest priority, followed by the judgment of the address information matching result of the valid cache line, and then the judgment of the result of the new cache line allocation. Alternatively, the judgment of the address information matching result of the valid cache line can be configured as the highest priority, followed by the judgment of the entry information in MSHR, and then the judgment of the result of the new cache line allocation. In other words, this embodiment improves memory access efficiency by executing the three cache index determination steps in parallel and sets the priority of the results of the cache index determination steps to ensure that duplicate caching is avoided.
[0047] In other alternative implementations, such as in this embodiment, the three cache index determination steps can be executed sequentially according to a predetermined priority order, so that when the memory access response satisfies the judgment result of a certain step, the corresponding cache index can be directly obtained.
[0048] In one optional implementation, initiating a predetermined replacement algorithm to obtain the newly allocated cache line can specifically involve: selecting a replaceable cache line from the cache using a predetermined replacement algorithm as the target cache line to store the current memory access response, thereby improving the cache hit rate, and recording the cache index (cacheline_index) of the target cache line. The replacement algorithm can be LRU (Least Recently Used), PLRU (Pseudo-LRU), NRU (Not Recently Used), LFU (Least Frequently Used), LRU-K, ARC (Adaptive Replacement Cache), TBR (Time-Based Replacement), etc. It should be understood that this embodiment can use existing or future replacement algorithms, which will not be listed here. It should be understood that during the cache indexing step, only the cache index of the newly allocated cache line is recorded. At this time, the cache allocation is not actually completed. Therefore, when the memory access response of the target request satisfies the other two steps, the cache index of the newly allocated cache line can be cleared directly. Thus, this step does not actually occupy the cache line.
[0049] Further, comparing the address information of the target request with the address information corresponding to each valid cache line to determine whether there is a cache line matching the address information of the target request can specifically be: comparing the address information of the target request with the address information of each cache line, and in response to the existence of a partially miss cache line, determining the partially miss cache line as the target cache line. Optionally, in this embodiment, the virtual address of the target request is compared with the virtual address corresponding to each valid cache line, and the valid cache line that matches the partially miss is determined as the target cache line, and the cache index (cacheline_index) of the target cache line is recorded.
[0050] Furthermore, to maintain the accuracy of cached data in cache lines, this embodiment requires ensuring that the page table attribute information in partially missed cache lines is consistent with the memory access response when performing Partial_miss checks. This page table attribute information includes the page table size, for example, a single page table is 4KB.
[0051] Furthermore, querying the status information in the target entry to determine the index information specifically involves: responding to the status information in the target entry corresponding to the target request, which indicates a ready state, and retrieving the cache index information in the target entry. Specifically, the ready state in the target entry indicates that the page table range corresponding to the memory access response of a previous request of the target request covers the memory access response of the target request. This causes the status information in the target entry to be updated, and the cache index information in the target entry is updated synchronously. Therefore, the cache index of the corresponding target cache line can be directly determined from the cache index information in the target entry.
[0052] Furthermore, taking the priority order of querying the target entry—partial_miss judgment—replacement algorithm to obtain the newly allocated cache line for cache index determination as an example, in this embodiment, in response to the status information in the target entry corresponding to the target request indicating a ready state, the cache index corresponding to the cache index information in the target entry is obtained, that is, the cache index of the target cache line. In response to the status information in the target entry corresponding to the target request indicating a not ready state, and there is a cache line that matches the address information of the target request (that is, a partial miss), the cache index of the cache line is obtained, that is, the cache index of the target cache line. In response to the status information in the target entry corresponding to the target request indicating a not ready state, and there is no cache line that matches the address information of the target request, the cache index of the corresponding target cache line is allocated based on the predetermined replacement algorithm.
[0053] Step S130: Store the memory access response to the target cache line.
[0054] Furthermore, in this embodiment, each request entry in the missing status holding register is queried, and the status information and cache index information in the matching entries are updated to the ready status and the target index corresponding to the target cache line, respectively. The matching entries represent request entries whose memory access address information is covered by the page table range corresponding to the current memory access response. That is, when the page table range of the current memory access response covers the memory access address information of other cache-missed requests, it can be considered that the data accessed by those other cache-missed requests has been returned, and therefore the status information and cache index information of the matching entries corresponding to those other cache-missed requests can be directly updated.
[0055] This embodiment of the invention obtains the memory access response of a target request that has missed a cache hit. The response is based on the status information in the target entry corresponding to the target request, indicating an unprepared state, and the absence of a cache line matching the address information of the target request. A corresponding target cache line is allocated based on a predetermined replacement algorithm, and the memory access response is stored in the target cache line. Therefore, this embodiment employs a cache delay allocation strategy. Upon receiving the memory access response, it determines whether the page table range of a previously requested memory access response covers the current memory access response by checking the status information in the corresponding target entry. Simultaneously, it checks whether a cache line with a matching address exists. Only after determining that there is no local memory access response in the current cache is a new cache line allocated. Based on this, this embodiment effectively avoids the problem of duplicate page table storage, improves the available cache capacity, and avoids resource waste.
[0056] Figure 2 This is a schematic diagram of the data access process according to an embodiment of the present invention. Figure 2As shown, in this embodiment, after receiving a data access request req1 from the upstream, a cache hit test is performed on the data access request req1. If a cache hit occurs, the data in the corresponding cache line is retrieved based on the address information of the data access request req1 and fed back to the upstream. Further, if the data access request req1 misses the cache, a request entry entry1 is allocated in MSHR to store the cache-missing data access request req1, and the cache-missing data access request req1 is forwarded to the downstream cache or downstream memory to request the corresponding data. Upon receiving the data access request req1, the downstream cache or memory retrieves the corresponding access response rsq1 and feeds back the access response rsq1 to the cache unit. When a cache unit receives a memory access response rsq1, it executes target entry status judgment, partial miss judgment, and replacement algorithm allocation in parallel. If the status information of the target entry rsq1 indicates that it is ready, the corresponding cache index is obtained from the cache index information of the target entry rsq1. If the status information of the target entry rsq1 indicates that it is not ready, and there is a cache line that matches the address information of the data memory access request req1 (i.e., partial miss), the cache index of that cache line is obtained, which is the cache index of the target cache line. If the status information of the target entry rsq1 indicates that it is not ready, and there is no cache line that matches the address information of the data memory access request req1, the corresponding cache index of the target cache line is allocated based on a predetermined replacement algorithm, and finally the target cache index Cacheline index A is obtained.
[0057] Furthermore, after obtaining the target cache line index A, a corresponding cache line is allocated based on the target cache line index A, and the memory access response rsq1 is stored in the corresponding cache line. Simultaneously, each request entry in the missing status holding register is queried, and the status information and cache index information in the matching entries are updated to the ready state and the target index corresponding to the target cache line, respectively. The matching entries are used to represent request entries whose memory access address information is covered by the page table range corresponding to the memory access response.
[0058] Figure 3 This is a schematic diagram illustrating part of the miss determination process according to an embodiment of the present invention. For example... Figure 3As shown, assume that cache line Cacheline0 is divided into four blocks: Sector0, Sector1, Sector2, and Sector3. Sector0 stores a 4KB page table. Further, when the address information of the data memory access request req0 corresponding to the returned memory access response rsp0 matches the address information of cache line Cacheline0, and the memory access response rsp0 includes four 4KB page tables, there are some cache misses for cache line Cacheline0. However, the page table attribute information in cache line Cacheline0 is consistent with the memory access response rsp0. Therefore, cache line Cacheline0 can be used as the target page table for the memory access response rsp0. Thus, this embodiment avoids cache duplication, increases available cache capacity, and prevents resource waste.
[0059] Figure 4 This is a schematic diagram of the entry update process according to an embodiment of the present invention. Figure 4 As shown, after receiving a cache miss data access request req2, the cache unit allocates a request entry 2 in MSHR to store the cache miss data access request req2, and then forwards the cache miss data access request req2 to the downstream cache or downstream memory to request the corresponding data. The request entry 2 includes valid bit information (valid=1), status information (ready=0), request additional information (sideinfo), address information (VA=xxxx1), and cache index information (cacheline_index=0). Further, after receiving a cache miss data access request req3, the cache unit allocates a request entry 3 in MSHR to store the cache miss data access request req3, and then forwards the cache miss data access request req3 to the downstream cache or downstream memory to request the corresponding data. The request entry 3 includes valid bit information (valid=1), status information (ready=0), request additional information (sideinfo), address information (VA=xxxx1), and cache index information (cacheline_index=0).
[0060] Furthermore, after receiving the memory access response rsq2 corresponding to the data memory access request req2, the cache unit executes as follows: Figure 2The cache line confirmation process shown determines that the cache index corresponding to the memory access response rsq2 is cacheline_index=A, and updates the status information ready=1 and cache index information cacheline_index=A in the request entry 2. Further, querying each request entry in MSHR reveals that the page table range corresponding to the memory access response rsq2 covers the address accessed by the data memory access request req3. This means that the data accessed by the data memory access request req3 has essentially been returned, and the status information ready=1 and cache index information cacheline_index=A of the request entry 3 can be synchronously updated.
[0061] Furthermore, after receiving the memory access response rsq3 corresponding to the data memory access request req3, the cache unit queries the corresponding request entry 3 and finds that the status information indicates the data is ready and has the corresponding cache index information cacheline_index=A. It can then directly obtain the cache index cacheline_index=A corresponding to the target cache line from the request entry 3. Therefore, this embodiment can avoid the problem of cache duplication, improve the available cache capacity, and avoid resource waste.
[0062] This embodiment of the invention obtains the memory access response of a target request that has missed a cache hit. The response is based on the status information in the target entry corresponding to the target request, indicating an unprepared state, and the absence of a cache line matching the address information of the target request. A corresponding target cache line is allocated based on a predetermined replacement algorithm, and the memory access response is stored in the target cache line. Therefore, this embodiment employs a cache delay allocation strategy. Upon receiving the memory access response, it determines whether the page table range of a previously requested memory access response covers the current memory access response by checking the status information in the corresponding target entry. Simultaneously, it checks whether a cache line with a matching address exists. Only after determining that there is no local memory access response in the current cache is a new cache line allocated. Based on this, this embodiment effectively avoids the problem of duplicate page table storage, improves the available cache capacity, and avoids resource waste.
[0063] Figure 5 This is a schematic diagram of a data access device according to an embodiment of the present invention. Figure 5 As shown, the data access device in this embodiment includes an acquisition unit 51, an allocation unit 52, and a storage unit 53.
[0064] The acquisition unit 51 is used to acquire the memory access response of the target request, wherein the target request is not a cached miss request. The allocation unit 52 is used to allocate a corresponding target cache line based on a predetermined replacement algorithm, in response to the status information in the target entry corresponding to the target request indicating an unready state and the absence of a cache line matching the address information of the target request. The storage unit 53 is used to store the memory access response into the target cache line.
[0065] Furthermore, the data access device also includes an entry update unit, which performs the following actions: querying each request entry in the missing status holding register; updating the status information and cache index information in the matching entry to the ready status and the target index corresponding to the target cache line, respectively, wherein the matching entry is used to characterize the request entry whose access address information is covered by the page table range corresponding to the access response.
[0066] Furthermore, the data access device also includes a first determining unit, configured to: respond to the status information in the target entry corresponding to the target request representing a ready state, obtain cache index information in the target entry; and determine the target cache line corresponding to the access response based on the cache index information.
[0067] Furthermore, the data access device also includes a second determining unit, configured to: compare the address information of the target request with the address information of each cache line; and, in response to the existence of partially missed cache lines, determine the partially missed cache lines as the target cache lines.
[0068] Furthermore, the page table attribute information in the partially missed cache lines is consistent with the memory access response.
[0069] Furthermore, the data access device also includes an entry generation unit, used to perform: obtaining a target request; in response to the target request not hitting the cache, generating a target entry corresponding to the target request, the target entry including request additional information, address information, status information and cache index information.
[0070] This embodiment of the invention obtains the memory access response of a target request that has missed a cache hit. The response is based on the status information in the target entry corresponding to the target request, indicating an unprepared state, and the absence of a cache line matching the address information of the target request. A corresponding target cache line is allocated based on a predetermined replacement algorithm, and the memory access response is stored in the target cache line. Therefore, this embodiment employs a cache delay allocation strategy. Upon receiving the memory access response, it determines whether the page table range of a previously requested memory access response covers the current memory access response by checking the status information in the corresponding target entry. Simultaneously, it checks whether a cache line with a matching address exists. Only after determining that there is no local memory access response in the current cache is a new cache line allocated. Based on this, this embodiment effectively avoids the problem of duplicate page table storage, improves the available cache capacity, and avoids resource waste.
[0071] Figure 6 This is a schematic diagram of a cache unit according to an embodiment of the present invention. Figure 6 As shown, the cache unit in this embodiment includes a miss status holding register 61, a data cache area 62, and a controller 63. The miss status holding register 61 stores data access requests that have resulted in cache misses; its request storage structure is consistent with the previous embodiment and will not be repeated here. The data cache area 62 includes multiple cache lines, which are used to cache accessed data. Optionally, the cache unit in this embodiment can use a set-associative cache or other types of caches; this embodiment does not limit its use. When using a set-associative cache, the data cache area 62 includes multiple cache groups, and each cache group includes multiple cache lines.
[0072] The controller 63 is used to obtain the memory access response of the target request that has a cache miss. In response to the status information in the target entry corresponding to the target request indicating an unready state and the absence of a cache line that matches the address information of the target request, the controller allocates the corresponding target cache line based on a predetermined replacement algorithm and stores the memory access response in the target cache line.
[0073] Furthermore, the controller 63 is also used to query each request entry in the missing status holding register, and update the status information and cache index information in the matching entry to the ready status and the target index corresponding to the target cache line, respectively. The matching entry is used to characterize the request entry whose memory access address information is covered by the page table range corresponding to the memory access response.
[0074] Furthermore, the controller 63 is also configured to respond to the status information in the target entry corresponding to the target request, which represents a ready state, obtain the cache index information in the target entry, and determine the target cache line corresponding to the memory access response based on the cache index information.
[0075] Furthermore, the controller 63 is also configured to compare the address information of the target request with the address information of each cache line; in response to the existence of partially missed cache lines, the partially missed cache lines are identified as target cache lines. Optionally, the page table attribute information in the partially missed cache lines is consistent with the memory access response.
[0076] Furthermore, the controller 63 is also configured to acquire a target request, and in response to the target request not hitting the cache, generate a target entry corresponding to the target request, the target entry including request additional information, address information, status information and cache index information.
[0077] This embodiment of the invention obtains the memory access response of a target request that has missed a cache hit. The response is based on the status information in the target entry corresponding to the target request, indicating an unprepared state, and the absence of a cache line matching the address information of the target request. A corresponding target cache line is allocated based on a predetermined replacement algorithm, and the memory access response is stored in the target cache line. Therefore, this embodiment employs a cache delay allocation strategy. Upon receiving the memory access response, it determines whether the page table range of a previously requested memory access response covers the current memory access response by checking the status information in the corresponding target entry. Simultaneously, it checks whether a cache line with a matching address exists. Only after determining that there is no local memory access response in the current cache is a new cache line allocated. Based on this, this embodiment effectively avoids the problem of duplicate page table storage, improves the available cache capacity, and avoids resource waste.
[0078] Figure 7 This is a schematic diagram of a computer system according to an embodiment of the present invention. Figure 7 As shown, the computer system in this embodiment includes a computing engine 71, a cache unit 72, and memory 73. The computing engine 71 generates data access requests and sends these requests to the cache unit. The structure and operation of the cache unit 72 can be found in [reference needed]. Figure 6The description of the above embodiments will not be repeated here. Memory 73 is used to respond to a received data memory access request and return a memory access response corresponding to the data memory access request. Thus, in this embodiment, the memory access response of a cache-missed target request is obtained. In response to the status information in the target entry corresponding to the target request indicating an unprepared state and the absence of a cache line matching the address information of the target request, a corresponding target cache line is allocated based on a predetermined replacement algorithm, and the memory access response is stored in the target cache line. Thus, this embodiment adopts a cache delayed allocation strategy. After receiving the memory access response, it determines whether the page table range of the previously requested memory access response covers the current memory access response through the status information in the corresponding target entry, and simultaneously determines whether there is a cache line matching the address. Only after determining that there is no local memory access response in the current cache is a new cache line allocated. Based on this, this embodiment can effectively avoid the problem of duplicate page table storage, improve the available cache capacity, and avoid resource waste.
[0079] Another embodiment of the present invention relates to a non-volatile storage medium for storing a computer-readable program for use by a computer to execute some or all of the above-described method embodiments.
[0080] That is, those skilled in the art will understand that all or part of the steps in the methods of the above embodiments can be implemented by a program instructing related hardware. This program is stored in a storage medium and includes several instructions to cause a device (which may be a microcontroller, chip, etc.) or processor to execute all or part of the steps of the methods described in the embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as a USB flash drive, a portable hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.
[0081] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.
Claims
1. A data access method, characterized in that, The method includes: Obtain the memory access response for the target request, where the target request is a cache miss request; In response to the status information in the target entry corresponding to the target request indicating an unready state, and the absence of a cache line matching the address information of the target request, a corresponding target cache line is allocated based on a predetermined replacement algorithm; The memory access response is stored in the target cache line.
2. The method according to claim 1, characterized in that, The method further includes: Query the missing status holding register for each request entry; The status information and cache index information in the matching entries are updated to the ready status and the target index corresponding to the target cache line, respectively. The matching entries are used to represent request entries whose memory access address information is covered by the page table range corresponding to the memory access response.
3. The method according to claim 1, characterized in that, The method further includes: In response to the status information in the target entry corresponding to the target request, which indicates a ready state, the cache index information of the target entry is obtained; The target cache line corresponding to the memory access response is determined based on the cache index information.
4. The method according to claim 1, characterized in that, The method further includes: Compare the address information of the target request with the address information of each cache line; In response to the existence of partially missed cache lines, the partially missed cache lines are identified as target cache lines.
5. The method according to claim 4, characterized in that, The page table attribute information in the partially missed cache lines is consistent with the memory access response.
6. The method according to claim 1, characterized in that, The method further includes: Obtain the target request; In response to the target request not hitting the cache, a target entry corresponding to the target request is generated. The target entry includes request additional information, address information, status information, and cache index information.
7. A data access device, characterized in that, The device includes: The acquisition unit is used to acquire the memory access response of the target request, wherein the target request is not a cached miss request; The allocation unit is used to allocate the corresponding target cache line based on a predetermined replacement algorithm in response to the status information in the target entry corresponding to the target request indicating an unprepared state and the absence of a cache line matching the address information of the target request. A storage unit is used to store the memory access response to the target cache line.
8. A cache unit, characterized in that, The cache unit includes: The missing status holding register is used to store cache access requests for data that have been missed in the cache. The data cache area includes multiple cache lines, which are used to cache memory access data; A controller for performing the method as described in any one of claims 1-6.
9. A computer system, characterized in that, The computer system includes: The cache unit as described in claim 8; A computing engine is used to generate data access requests and send the data access requests to the cache unit; and Memory is used to respond to a received data memory access request and return a memory access response corresponding to the data memory access request.
10. A computer program product, characterized in that, The computer program product includes a computer program / instruction that, when executed by a processor, implements the method as described in any one of claims 1-6.
11. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the method as described in any one of claims 1-6.