A three control line-based synchronous parallel bus communication method, system, device and storage medium

Abstract

This invention discloses a synchronous parallel bus communication method based on three control lines, comprising: S1, determining the default state of all signal lines and initializing the first, second, and third control signal lines, clock signal line, and data signal line; S2, the device is in a receiving state and continuously listens to the control signal lines on the bus; S3, if a valid data frame is detected, it is stored in the receiving queue; S4, if the device needs to send data, it controls the bus and enters the arbitration segment according to the level of the data to be sent; S5, the device sends its own node arbitration ID to participate in bus arbitration; S6, the arbitration result is judged; S7, the device controls the bus and sends data in sequence according to the information segment, data segment, check segment, and response segment; S8, the sending status is monitored and corresponding operations are performed according to the sending result; this invention adopts a preemptive bus, a hybrid priority and a dual-mode arbitration mechanism, and dynamic preemptive arbitration meets real-time control requirements, improving bus utilization and system response speed.

Description

[0001] This application is a divisional application of patent number "202510672637.3", filed on "20250523", entitled "A Synchronous Parallel Differential Bus Communication Method, System, Device and Storage Medium Based on Preemptive Arbitration". Technical Field

[0002] This invention relates to the field of communications, and specifically to a synchronous parallel bus communication method, system, device, and storage medium based on three control lines. Background Technology

[0003] In industrial control and the power industry, with the development of intelligence and related controlled devices, the amount of data generated by each node is increasing, and the requirements for communication latency are becoming more and more stringent.

[0004] With the widespread application of distributed electronic systems in industrial control, vehicle networks, aerospace, and the Internet of Things, bus communication has become a core technology for data interaction between devices. To meet the communication needs of multi-node, high real-time, and high-interference environments, traditional parallel buses (such as ISA and PCI) and serial buses (such as CAN, LIN, and UART) each have their limitations. While parallel buses offer high transmission rates, they have numerous signal lines, complex wiring, are susceptible to interference, and their arbitration mechanisms are inefficient in multi-master contention scenarios. Serial buses, while saving on cabling, can easily become a bottleneck in high-speed, high-capacity data transmission, and most protocols lack effective preemption mechanisms for responding to high-priority messages.

[0005] The applicant's research revealed shortcomings in existing parallel bus communication methods regarding real-time performance and priority handling. Traditional parallel buses often employ fixed timing or simple polling arbitration mechanisms, making it difficult to support the immediate interruption of low-priority transmissions by high-priority urgent messages. This results in system response delays and fails to meet the demands of real-time scenarios such as industrial control and automotive networks. Furthermore, the node state reset and bus release procedures after arbitration failure or transmission interruption are not clearly defined in most buses, easily leading to bus conflicts or state confusion, thus affecting communication reliability. Summary of the Invention

[0006] To overcome the above-mentioned technical defects, the present invention provides a synchronous parallel bus communication method, system, device and storage medium based on three control lines. It adopts a preemptive bus, a hybrid priority and a dual-mode arbitration mechanism. The dynamic preemptive arbitration meets the real-time control requirements and supports communication between multiple nodes, thereby improving bus utilization and system response speed.

[0007] To solve the above problems, the present invention is implemented according to the following technical solution:

[0008] This invention discloses a synchronous parallel bus communication method based on three control lines, comprising the following steps:

[0009] S1. Determine the default state of all signal lines and initialize the first control signal line, the second control signal line, the third control signal line, the clock signal line, and the data signal line;

[0010] S2. The device is in receiving mode and continuously listens to the control signal lines on the bus.

[0011] S3. If a valid data frame is detected, it is stored in the receive queue;

[0012] S4. If the device needs to send data, control the bus and enter the arbitration segment according to the level of data transmission.

[0013] S5. The device sends its own node arbitration ID to participate in bus arbitration;

[0014] S51. If the highest bit of ID is 0, then the first arbitration method shall be adopted;

[0015] S52. If the highest bit of ID is 1, then the second arbitration method shall be adopted;

[0016] S6. Determine the arbitration result:

[0017] S61. If the arbitration is successful, the bus control is obtained and the system enters the transmit state.

[0018] S62. If arbitration fails, return to the receiving state and continue listening;

[0019] S7, the device control bus, sends data in a frame structure, which includes an information segment, a data segment, a check segment, and a response segment.

[0020] S8. Monitor the sending status and perform corresponding operations based on the sending results.

[0021] Furthermore, the control signal line, clock signal line, and data signal line in step S1 are specifically as follows:

[0022] The control signal lines include: a first control signal line indicating the bus operating state, a second control signal line indicating the bus data state and the return status, and a third control signal line forcing a node to release the bus;

[0023] The clock signal line is used for the clock signal of the synchronization bus;

[0024] The data signal lines include: data0-data15, a sixteen-bit parallel data signal line.

[0025] Furthermore, in step S2, the device is in a receiving state and continuously listens to the control signal lines on the bus, specifically:

[0026] Based on the state of the second control signal line, the data received by the data signal line is stored in the FIFO. After verification, the data frame in the FIFO is sent to the receiving queue and the FIFO is cleared.

[0027] If the rising edge of the first control signal line is received, the receiving state needs to be reset;

[0028] If a falling edge of the second control signal line is received, bus data needs to be received twice consecutively on the falling edge of the clock signal line, and the received data should be stored in the FIFO.

[0029] If a rising edge of the third control signal line is received, the bus needs to be released and the receiving state reset.

[0030] Furthermore, in step S4, if the device needs to send data, it controls the bus and enters the arbitration segment according to the data transmission level, specifically as follows:

[0031] The data transmission levels include normal-level messages and privileged-level messages, and the control bus includes the following steps:

[0032] S41, determine the bus operating status based on the first control signal line and the third control signal line;

[0033] When the first control signal line and the third control signal line of S411 are both at a low level, it means that the bus is not occupied and can immediately send a normal-level message or a privileged-level message to enter the arbitration segment.

[0034] S412, when the first control signal line is high and the third control signal line is low, it indicates that the bus is occupied. Check the message level and the level of the message to be sent on the bus, specifically:

[0035] S4121, If ​​the level of the message on the bus is a normal level message, and the level of the message to be sent is a privileged level message, then the third control signal line is used to interrupt the current bus transmission, preempt the sending permission, and enter the arbitration segment;

[0036] S4122, If the level of the message on the bus is a privileged message, and the level of the message to be sent is also a privileged message, then after the message on the bus is sent, the arbitration segment is entered;

[0037] S4123, If the level of the message on the bus is a normal-level message, and the level of the message to be sent is also a normal-level message, then after the message on the bus is sent, the arbitration segment is entered.

[0038] Furthermore, when the device needs to send a normal-level message or a privileged-level message,

[0039] Sending a normal message only requires setting the first control signal line to the active state;

[0040] Privileged message sending requires both the first and third control signal lines to be enabled, and the third control signal line to be disabled after approximately one clock cycle.

[0041] Furthermore, in step S51, if the highest bit of ID is 0, the first arbitration method is adopted, specifically as follows:

[0042] Within one clock cycle, the node requiring arbitration sends its ID to the data signal line on the rising edge of the clock. On the falling edge of the clock, each node acquires data from the data signal line, XORs the acquired data with its own ID to obtain ID1, and then compares ID with ID1.

[0043] If ID > ID1, the bus is obtained directly, and the second control signal line is set to the active state.

[0044] If ID < ID1, the bus is lost.

[0045] Furthermore, in step S52, if the highest bit of ID is 1, then the second arbitration method is adopted, specifically as follows:

[0046] Within 2n-1 clock cycles, where n is the number of arbitrations; on the rising edge of the first clock cycle of each round of arbitration, the respective arbitration ID1 is sent to the data signal line, and the initial state of ID1 is equal to its own ID; on the falling edge, the bus data is read and XORed with ID1 to obtain ID2;

[0047] If ID2 equals 0, the bus is acquired, the second control signal line is set to the active state, and the arbitration segment ends.

[0048] If ID2 is greater than ID1, the bus is lost;

[0049] If the second control signal line is detected to be invalid before the start of the second clock cycle of each round, the second clock cycle needs to be entered. On the rising edge of the second clock cycle, the node that has not lost the bus needs to send ID2 to the data bus, obtain the bus data ID3 on the falling edge, set ID1 to the value of ID3-ID2, and then proceed with the next round of arbitration.

[0050] Further, in step S7, the device control bus sends data according to a frame structure, wherein the frame structure includes an information segment, a data segment, a check segment, and a response segment, specifically:

[0051] The information segment consists of four clock cycles and two data segments, including the source ID of one clock cycle, the target ID of one clock cycle, the index value of one clock cycle, and the data length of one clock cycle.

[0052] The data segment consists of several 32-bit data, and it takes two clock cycles to send one data segment.

[0053] The verification segment performs CRC32 verification on all data in the information segment and data segment, which requires two clock cycles, and the node response status is obtained in the second clock cycle.

[0054] The response segment consists of the IDs of each node that has correctly received the information and requires one clock cycle.

[0055] Furthermore, in step S8, monitoring the transmission status and performing corresponding operations based on the transmission result, the monitoring of the transmission status specifically includes:

[0056] At the end of the verification segment, obtain the status of the second control signal line:

[0057] If the second control signal line is in an invalid state, it means that the transmission was successful;

[0058] If the second control signal line is active, it indicates that the transmission has failed.

[0059] Alternatively, a response segment for one clock cycle can be sent as a diagnostic cycle. All nodes that receive normal data will send their own IDs to the bus. The node sending the message will XOR the bus data with the destination ID in the message frame to obtain the ID of the faulty node.

[0060] Furthermore, in step S8, monitoring the transmission status and performing corresponding operations based on the transmission result, the specific steps of performing corresponding operations based on the transmission result are as follows:

[0061] S81. If the message is sent successfully, remove it from the sending queue and return to the receiving status.

[0062] S82. If sending fails:

[0063] S821. If the number of retries is less than the preset value, then retry sending;

[0064] S822. If multiple transmissions fail, retransmit at a reduced speed according to the reduced clock frequency.

[0065] S823. If the number of retries is exhausted, discard the message, remove the message from the sending queue, and return to the receiving status.

[0066] According to another aspect of the present invention, a synchronous parallel bus communication method based on three control lines includes:

[0067] The initialization module is used to determine the default state of all signal lines and initialize the first control signal line, the second control signal line, the third control signal line, the clock signal line, and the data signal line.

[0068] The bus monitoring module is used to continuously monitor the control signal lines on the bus when the device is in a receiving state.

[0069] The data frame detection module is used to detect valid data frames and store them in the receive queue.

[0070] The control bus module is used for devices to send data. It controls the bus and enters the arbitration segment according to the level of data being sent.

[0071] The bus arbitration module is used by devices to send their own node arbitration ID to participate in bus arbitration;

[0072] The arbitration module is used to determine the arbitration outcome.

[0073] The data transmission module is used for the device control bus and transmits data in frame structure.

[0074] The monitoring and sending module is used to monitor the sending status and perform corresponding operations based on the sending results.

[0075] According to another aspect of the present invention, an electronic device is provided, the electronic device comprising:

[0076] At least one processor; and a memory communicatively connected to said at least one processor;

[0077] The memory stores a computer program that can be executed by the at least one processor, and the computer program is executed by the at least one processor to enable the at least one processor to execute the synchronous parallel bus communication method based on three control lines described in this invention.

[0078] According to another aspect of the present invention, a computer-readable storage medium is provided, the computer-readable storage medium storing a computer program,

[0079] The computer program is used to enable the processor to implement the synchronous parallel bus communication method based on three control lines described in this invention when executed.

[0080] Compared with existing technologies, the beneficial effects of this invention are as follows: This invention discloses a synchronous parallel bus communication method based on three control lines. It adopts a preemptive bus arbitration mechanism to determine when multiple nodes simultaneously preempt the bus. The bus is controlled and enters the arbitration segment to participate in bus arbitration, determining the device that ultimately acquires the bus, thereby improving bus utilization and reducing response latency. At the same time, the dual-mode arbitration method not only meets the low-latency requirements of small-scale systems but also supports large-scale networking, resolving the contradiction between node scale and real-time performance in traditional buses. Secondly, by dividing the data transmission level into ordinary-level messages and privileged-level messages, privileged-level messages can forcibly interrupt the transmission of ordinary-level messages and send them first, ensuring zero-latency response to emergency events, greatly improving system response speed, and enabling rapid interaction of analog quantities, control commands, and other information in the field of industrial control. Attached Figure Description

[0081] The specific embodiments of the present invention will be further described in detail below with reference to the accompanying drawings, wherein:

[0082] Figure 1 This is a flowchart of a synchronous parallel bus communication method based on three control lines disclosed in this invention;

[0083] Figure 2 This invention discloses a bus state transition diagram for a synchronous parallel bus communication method based on three control lines.

[0084] Figure 3 This is a statistical chart showing the average number of arbitrations in 1000 arbitrations conducted using a synchronous parallel bus communication method based on three control lines disclosed in this invention.

[0085] Figure 4 This is a waveform diagram of a single communication operation of a synchronous parallel bus communication method based on three control lines, as disclosed in this invention.

[0086] Figure 5 This is a block diagram of a synchronous parallel bus communication system based on three control lines disclosed in this invention;

[0087] Figure 6 This is a schematic diagram of the structure of an electronic device according to the present invention. Detailed Implementation

[0088] To enable those skilled in the art to better understand the present invention, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are merely some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention. The preferred embodiments of the present invention will be described below with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are for illustration and explanation only and are not intended to limit the present invention.

[0089] This embodiment discloses a synchronous parallel bus communication method based on three control lines, including the following steps:

[0090] S1. Determine the default state of all signal lines and initialize the first control signal line, the second control signal line, the third control signal line, the clock signal line, and the data signal line;

[0091] S2. The device is in receiving mode and continuously listens to the control signal lines on the bus.

[0092] S3. If a valid data frame is detected, it is stored in the receive queue;

[0093] S4. If the device needs to send data, control the bus and enter the arbitration segment according to the level of data transmission.

[0094] S5. The device sends its own node arbitration ID to participate in bus arbitration;

[0095] S51. If the highest bit of ID is 0, then the first arbitration method shall be adopted;

[0096] S52. If the highest bit of ID is 1, then the second arbitration method shall be adopted;

[0097] S6. Determine the arbitration result:

[0098] S61. If the arbitration is successful, the bus control is obtained and the system enters the transmit state.

[0099] S62. If arbitration fails, return to the receiving state and continue listening;

[0100] S7, the device control bus, transmits data in a frame structure, which includes an information segment, a data segment, a check segment, and a response segment.

[0101] S8. Monitor the sending status and perform corresponding operations based on the sending results.

[0102] This embodiment discloses a synchronous parallel bus communication method based on three control lines. It employs a preemptive bus arbitration mechanism, determining that when multiple nodes simultaneously preempt the bus, the bus is controlled and enters the arbitration segment to participate in bus arbitration, ultimately determining the device that acquires the bus. This improves bus utilization and reduces response latency. Furthermore, the dual-mode arbitration method not only meets the low-latency requirements of small-scale systems but also supports large-scale networking, resolving the contradiction between node scale and real-time performance in traditional buses. Secondly, by dividing the data transmission levels into ordinary-level messages and privileged-level messages, privileged-level messages can forcibly interrupt ordinary-level message transmission and prioritize their transmission, ensuring zero-latency response to emergency events and significantly improving system response speed. This enables rapid interaction of analog quantities, control commands, and other information in industrial control fields.

[0103] This embodiment initializes three control signal lines, one clock signal line, and sixteen data signal lines. The control signal lines, clock signal lines, and data signal lines in step S1 are specifically as follows:

[0104] The control signal lines include: a first control signal line indicating the bus working state, namely the control signal line busy; a second control signal line indicating the bus data state and the return status, namely the control signal line flag; and a third control signal line forcing a node to release the bus, namely the control signal line init.

[0105] The clock signal line is used for the clock signal of the synchronization bus, i.e., the clock signal line clk;

[0106] The data signal lines include: data0-data15, a sixteen-bit parallel data signal line.

[0107] In this embodiment, the device in step S2 is in a receiving state and continuously listens to the control signal line on the bus, specifically:

[0108] Based on the state of the second control signal line, the data received by the data signal line is stored in the FIFO. After verification, the data frame in the FIFO is sent to the receiving queue and the FIFO is cleared.

[0109] If the rising edge of the first control signal line is received, the receiving state needs to be reset;

[0110] If a falling edge of the second control signal line is received, bus data needs to be received twice consecutively on the falling edge of the clock signal line, and the received data should be stored in the FIFO.

[0111] If a rising edge of the third control signal line is received, the bus needs to be released and the receiving state reset.

[0112] Upon receiving a frame matching the length in the information segment or receiving a flag verification status, the received information segment, data segment, and verification segment need to be checked. If the verification is correct, the corresponding output is made to the bus in the verification segment and response segment, and the frame is sent to the receive queue. This embodiment processes the control signal lines one-to-one. When the rising edge of the first control signal line is received, the receive state needs to be reset. The purpose is to quickly respond to abnormal states (such as bus conflicts) and ensure communication continuity. When the falling edge of the second control signal line is received, bus data needs to be received and stored in the FIFO on the falling edges of the next two clock signal lines. The purpose is that the data signal lines in the bus have a total of 16 bits, and one data is 32 bits, occupying two clock cycles. Furthermore, the period of the second control signal line is twice that of the clock signal lines, allowing for effective bus state determination through sampling of the second control signal line. When the rising edge of the third control signal line is received, the bus needs to be released and the receive state reset. The purpose is to immediately release resources when priority is reversed (such as privileged message preemption), ensuring high-privilege message high-speed response; secondly, it also indicates the end of bus transmission. Because of the forced bus release, if a node believes the bus transmission is incomplete due to its own reasons, then receiving a rising edge on the third control signal line also indicates that the bus transmission has ended, and its own message frame is incorrect. Since this node did not participate in the response segment output, the node that sent the message can immediately detect the fault.

[0113] In this embodiment, if the device needs to send data in step S4, the bus is controlled and the arbitration segment is entered according to the level of data transmission, specifically as follows:

[0114] The data transmission levels include normal-level messages and privileged-level messages, and the control bus includes the following steps:

[0115] S41, determine the bus operating status based on the first control signal line and the third control signal line;

[0116] When the first control signal line and the third control signal line of S411 are both at a low level, it means that the bus is not occupied and can immediately send a normal-level message or a privileged-level message to enter the arbitration segment.

[0117] S412, when the first control signal line is high and the third control signal line is low, it indicates that the bus is occupied. Check the message level and the level of the message to be sent on the bus, specifically:

[0118] S4121, If ​​the level of the message on the bus is a normal level message, and the level of the message to be sent is a privileged level message, then the third control signal line is used to interrupt the current bus transmission, preempt the sending permission, and enter the arbitration segment;

[0119] S4122, If the level of the message on the bus is a privileged message, and the level of the message to be sent is also a privileged message, then after the message on the bus is sent, the arbitration segment is entered;

[0120] S4123, If the level of the message on the bus is a normal-level message, and the level of the message to be sent is also a normal-level message, then after the message on the bus is sent, the arbitration segment is entered.

[0121] This embodiment uses the coordinated detection of the first and third control signal lines, specifically judging the bus's working state (idle or occupied) through a combination of level states. An idle bus can immediately initiate data transmission of any priority, improving bus utilization. Occupancy is divided into ordinary message occupancy and privileged message occupancy. This embodiment employs hierarchical message priority management, establishing a two-tier message system of ordinary and privileged levels. Privileged messages have preemption rights, and messages of the same level are automatically queued, ensuring both the real-time performance of privileged messages and maintaining fairness among messages of the same level.

[0122] In practical applications, if a serious fault occurs in the system and a rapid response is required, waiting for other nodes to query or participate in arbitration will be relatively slow. For emergency communications, using privileged messages can enable the system to respond faster.

[0123] To further ensure smooth message delivery, when the device needs to send normal-level or privileged-level messages:

[0124] Sending a normal message only requires setting the first control signal line to the active state; that is, setting the busy control signal line to a high level is equivalent to occupying the main line.

[0125] Privileged message transmission requires both the first and third control signal lines to be active simultaneously. This means setting the init and busy control signal lines to high. A rising edge on the init control signal line forces other nodes to release the bus, allowing the current node to directly occupy the bus. After approximately one clock cycle, the third control signal line is set to 0 to ensure that other nodes can receive and respond to the bus normally before the privileged message is sent.

[0126] In this embodiment, the first arbitration method is applicable to systems with no more than 15 nodes, and the arbitration segment requires one clock cycle to complete; the second arbitration method is applicable to systems with more than 15 nodes but no more than 32768 nodes, and the arbitration segment is completed in 2n-1 clock cycles, where n is the number of arbitration attempts, and n≥1, until arbitration is successful. In a system, nodes applicable to both the first and second arbitration methods can coexist, and nodes of different types can communicate normally without affecting the arbitration result. Figure 3As shown, Figure 3 This is a statistical chart showing the average number of arbitrations per 1000 arbitrations conducted using a synchronous parallel bus communication method based on three control lines disclosed in this invention. Figure 3 The horizontal axis represents the number of nodes participating in arbitration simultaneously, and the vertical axis represents the average number of arbitrations in 1000 arbitrations, which is n in 2n-1.

[0127] The first and second arbitration methods of this embodiment will be further described below:

[0128] (1) First arbitration method;

[0129] If the highest bit of ID is 0 in step S51, then the first arbitration method is adopted, specifically as follows:

[0130] Within one clock cycle, the node requiring arbitration sends its ID to the data signal line on the rising edge of the clock. On the falling edge of the clock, each node acquires data from the data signal line, XORs the acquired data with its own ID to obtain ID1, and then compares ID with ID1.

[0131] If ID > ID1, the bus is obtained directly, and the second control signal line is set to the active state.

[0132] If ID < ID1, the bus is lost.

[0133] (2) Second arbitration method;

[0134] If the highest bit of ID is 1 in step S52, then the second arbitration method is adopted, specifically as follows:

[0135] Within 2n-1 clock cycles, where n is the number of arbitrations; on the rising edge of the first clock cycle of each round of arbitration, the respective arbitration ID1 is sent to the data signal line, and the initial state of ID1 is equal to its own ID; on the falling edge, the bus data is read and XORed with ID1 to obtain ID2;

[0136] If ID2 equals 0, the bus is acquired, the second control signal line is set to the active state, and the arbitration segment ends.

[0137] If ID2 is greater than ID1, the bus is lost;

[0138] If the second control signal line is detected to be invalid before the start of the second clock cycle of each round, the second clock cycle needs to be entered. On the rising edge of the second clock cycle, the node that has not lost the bus needs to send ID2 to the data bus, obtain the bus data ID3 on the falling edge, set ID1 to the value of ID3-ID2, and then proceed with the next round of arbitration.

[0139] In the second arbitration method, the single-round arbitration steps are the same, each round requires two clock cycles, and the last round only requires one clock cycle to occupy the bus.

[0140] The dual-mode arbitration method implemented in this embodiment determines which device can acquire the bus when multiple nodes simultaneously compete for it. This not only meets the low-latency requirements of small-scale systems but also supports large-scale networking, resolving the conflict between node size and real-time performance inherent in traditional buses.

[0141] In practical applications, chassis-based solutions typically have 15 or fewer boards, allowing the first arbitration method to be used. This improves communication efficiency and supports broadcasting, enabling multiple identical devices to operate synchronously, such as for simultaneous sampling. For complex systems with more than 15 nodes, the second arbitration method can be used, supporting up to 32,768 devices. Alternatively, some devices can use the first arbitration method to achieve synchronous operation of multiple identical devices.

[0142] This embodiment employs a preemptive bus mechanism. The frame structure includes an information segment, a data segment, and a checksum segment. The information segment stores information and indicates the message's ownership; the data segment allows for a custom communication protocol; and the checksum segment verifies the data's correctness. The frame structure of this embodiment is further explained below:

[0143] In step S7, the device control bus sends data according to a frame structure, which includes an information segment, a data segment, a check segment, and a response segment, specifically:

[0144] The information segment consists of four clock cycles and two data segments, including the source ID of one clock cycle, the target ID of one clock cycle, the index value of one clock cycle, and the data length of one clock cycle.

[0145] The data segment consists of several 32-bit data, and it takes two clock cycles to send one data segment.

[0146] The verification segment performs CRC32 verification on all data in the information segment and data segment, which requires two clock cycles, and the node response status is obtained in the second clock cycle.

[0147] The response segment consists of the IDs of each node that has correctly received the information and requires one clock cycle.

[0148] The source ID and destination ID of the information segment indicate where the information comes from and where it goes; the index value is the ID of the information. When the bus continuously sends multiple messages that all require a response, the corresponding message can be matched based on the index value. The data length is the number of 32 bits of data in the data segment.

[0149] The data segment can use a custom communication protocol. If the number of bytes in the protocol is less than a multiple of 4, zeros need to be padded at the end to make it a multiple of 4.

[0150] The check segment uses CRC32 check, which is an existing technology. It is a 32-bit cyclic redundancy check that generates a 4-byte check code through polynomial calculation to detect data transmission errors and has high reliability.

[0151] The response segment is optional; it can be absent or not used. Alternatively, the bus can be terminated by controlling the init signal line after the verification segment is completed.

[0152] The following is a view of the clock cycles corresponding to each segment of the frame structure:

[0153] Section Name Arbitration Section Information segment Data segment Check segment Response segment clock cycle 1 or 2 * number of arbitrations - 1 4 Data length * 2 2 1

[0154] As those skilled in the art will know, in some current communication bus technologies, there is no response to sent messages. After a message is sent, it is unclear whether it has been processed, received, or by whom. This embodiment provides a response confirmation mechanism (verification segment end flag status and response segment), which can more clearly identify which node has a problem. Furthermore, when broadcast information is retransmitted, nodes that have correctly received the message can be removed, reducing bus usage and improving bus utilization.

[0155] Furthermore, in practical terms, this embodiment generates its own clock when a message is received. In many synchronous buses, the clock is generated by a single master device, and if the master device fails, the entire system becomes inoperable. In this embodiment, each node generates its own clock, so the failure of any one device does not affect the interaction between other devices. This has a significant advantage in hot standby systems, especially in industrial applications where downtime losses are substantial.

[0156] In this embodiment, it should be noted that if the bus controller of the transmitting node is not already active before the control clock signal line and the second control signal line are active, the node loses the bus. This setting ensures priority for low-speed communication because the system sets a higher communication speed during initialization. Some messages trigger a slowdown retransmission mechanism, ensuring that a message that has failed to be transmitted multiple times is sent as early as possible. The bus controller of the transmitting node confirms the period of the clock signal line based on the information in the transmitted message and generates a clock signal. After arbitration is completed in the arbitration segment, only one node determines its ownership of the bus. The transmitting node generates its own clock and operates the control signal line and data signal line according to regulations. The above regulations are specifically as follows:

[0157] 1. The period of the clock signal line is confirmed by the information in the transmitted message;

[0158] 2. The transmitting node sends data on the rising edge of the clock and acquires and checks the data on the bus on the falling edge of the clock;

[0159] 3. The sending node needs to send and receive bus data in the following order: arbitration segment (completed), information segment, data segment, check segment, and response segment;

[0160] 4. The period of the control signal line flag is twice the clock cycle. That is, sending one 32-bit data (the bus is 16-bit, so it requires 2 clock cycles) completes one cycle change of the flag. See details. Figure 4 As shown in the figure, from top to bottom, they are: first control signal line (control signal line busy), clock signal line clk, second control signal line (control signal line flag), third control signal line (control signal line init), and data signal line data. Figure 4 This displays the overall communication process. One node uses broadcasting to read information from both nodes; arbitration is performed at the stage indicated by the cursor in the diagram.

[0161] 5. The control signal line flag is set to high level when the arbitration segment node acquires the bus; the information segment and data segment are set to low level for one clock cycle and high level for one clock cycle; the check segment is set to low level for two clock cycles; and the response segment is set to low level for one clock cycle.

[0162] 6. If it is necessary to stop or terminate message transmission due to reasons such as completion of transmission or detection of errors, the control signal line init will be set to the active state.

[0163] The above are the sending steps of the sending end. The receiving end receives messages according to the rules in the above steps, and the receiving end needs to output data and status to the bus in the check segment and response segment.

[0164] To further ensure real-time error detection and accurate fault location, step S8 monitors the transmission status and performs the monitoring of transmission status in the corresponding operation based on the transmission result, specifically:

[0165] At the end of the verification segment, obtain the status of the second control signal line:

[0166] If the second control signal line is 0, it means the transmission was successful;

[0167] If the second control signal line is 1, it means that the transmission failed;

[0168] Alternatively, one clock cycle can be sent as a diagnostic cycle. All nodes that receive normal data will send their own IDs to the bus. The node that sends the message will perform an XOR operation between the bus data and the destination ID in the message frame to obtain the ID of the faulty node.

[0169] This embodiment sets up dynamic node diagnosis. Normal nodes actively send back their IDs during the diagnosis cycle. The sending node quickly locates the unresponsive node through an XOR operation (target ID ⊕ response ID). The location accuracy is high and the impact on the system is minimized. The diagnosis cycle only takes one clock cycle and has a very low impact on bus throughput.

[0170] In this embodiment, step S8, which involves monitoring the transmission status and performing corresponding operations based on the transmission result, specifically includes:

[0171] S81. If the message is sent successfully, remove it from the sending queue and return to the receiving status.

[0172] S82. If sending fails:

[0173] S821. If the number of retries is less than the preset value, then retry sending;

[0174] S822. If multiple transmissions fail, retransmit at a reduced speed according to the reduced clock frequency.

[0175] S823. If the number of retries is exhausted, discard the message, remove the message from the sending queue, and return to the receiving status.

[0176] This embodiment sets up a retransmission mechanism and a reduced-speed retransmission mechanism. Upon initial failure, a retry is immediately initiated (step S821) to resolve momentary interference and correct occasional errors. The reduced-speed retransmission mechanism (step S822) uses the reduced-speed retransmission period for the clock signal line if the number of retries equals a preset value and the message specifies a reduced-speed retransmission period. After the number of retries is exhausted, the packet is quickly discarded (step S823) to prevent invalid data from blocking the bus and ensure the passage of other messages.

[0177] This embodiment provides a synchronous parallel bus communication method based on three control lines. The synchronous parallel bus communication system based on three control lines includes the aforementioned synchronous parallel bus communication method based on three control lines. Figure 5 As shown, the synchronous parallel bus communication system based on three control lines includes:

[0178] The initialization module is used to determine the default state of all signal lines and initialize the first control signal line, the second control signal line, the third control signal line, the clock signal line, and the data signal line.

[0179] The bus monitoring module is used to continuously monitor the control signal lines on the bus when the device is in a receiving state.

[0180] The data frame detection module is used to detect valid data frames and store them in the receive queue.

[0181] The control bus module is used for devices to send data. It controls the bus and enters the arbitration segment according to the level of data being sent.

[0182] The bus arbitration module is used by devices to send their own node arbitration ID to participate in bus arbitration;

[0183] The arbitration module is used to determine the arbitration outcome.

[0184] The data transmission module is used for the device control bus and transmits data in frame structure.

[0185] The monitoring and sending module is used to monitor the sending status and perform corresponding operations based on the sending results.

[0186] This embodiment provides an electronic device, the electronic device comprising:

[0187] At least one processor; and a memory communicatively connected to said at least one processor;

[0188] The memory stores a computer program that can be executed by the at least one processor, and the computer program is executed by the at least one processor to enable the at least one processor to execute the synchronous parallel bus communication method based on three control lines described in this invention.

[0189] This embodiment provides a computer-readable storage medium storing a computer program.

[0190] The computer program is used to enable the processor to implement the synchronous parallel bus communication method based on three control lines described in this invention when executed.

[0191] Figure 6 A schematic block diagram of an example electronic device 600 that can be used to implement embodiments of the present invention is shown. Electronic device 600 is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device may also represent various forms of mobile devices, such as personal digital assistants, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the invention described and / or claimed herein.

[0192] like Figure 6As shown, the electronic device 600 includes a computing unit 601, which can perform various appropriate actions and processes based on a computer program stored in a read-only memory (ROM) 602 or a computer program loaded from a storage unit 608 into a random access memory (RAM) 603. The RAM 603 may also store various programs and data required for the operation of the device 600. The computing unit 601, ROM 602, and RAM 603 are interconnected via a bus 604. An input / output (I / O) interface 605 is also connected to the bus 604.

[0193] Various components in electronic device 600 are connected to I / O interface 605, including: input unit 606, such as keyboard, mouse, etc.; output unit 607, such as various types of display, speaker, etc.; storage unit 608, such as disk, optical disk, etc.; and communication unit 609, such as network card, modem, wireless transceiver, etc. Communication unit 609 allows electronic device 600 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0194] The computing unit 601 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 601 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 601 performs the various methods and processes described above, such as a synchronous parallel bus communication method based on three control lines. For example, in some embodiments, a synchronous parallel bus communication method based on three control lines can be implemented as a computer software program tangibly contained in a machine-readable medium, such as storage unit 608. In some embodiments, part or all of the computer program can be loaded and / or installed on device 600 via ROM 602 and / or communication unit 609. When the computer program is loaded into RAM 603 and executed by the computing unit 601, one or more steps of a synchronous parallel bus communication method based on three control lines described above can be performed. Alternatively, in other embodiments, computing unit 601 may be configured by any other suitable means (e.g., by means of firmware) to perform a synchronous parallel bus communication method based on three control lines.

[0195] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0196] The program code used to implement the methods of the present invention can be written in any combination of one or more programming languages. This program code can be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing device, such that when executed by the processor or controller, the functions / operations specified in the flowcharts and / or block diagrams are implemented. The program code can be executed entirely on the machine, partially on the machine, as a standalone software package partially on the machine and partially on a remote machine, or entirely on a remote machine or server.

[0197] In the context of this invention, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. Machine-readable media can include, but are not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include, based on one or more wires of electrical connection, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0198] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device for displaying information to the user (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor); and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the computer. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0199] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as a data server), or computing systems that include middleware components (e.g., an application server), or computing systems that include frontend components (e.g., a user computer with a graphical user interface or web browser through which a user can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., a communication network). Examples of communication networks include local area networks (LANs), wide area networks (WANs), and the Internet.

[0200] Computer systems can include clients and servers. Clients and servers are generally located far apart and typically interact via communication networks. Client-server relationships are created by computer programs running on the respective computers and having a client-server relationship with each other. Servers can be cloud servers, servers in distributed systems, or servers incorporating blockchain technology.

[0201] Other structures of the synchronous parallel bus communication method, apparatus, device, and storage medium based on three control lines described in this embodiment are available in the prior art.

[0202] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0203] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Therefore, any modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.

Claims

1. A synchronous parallel bus communication method based on three control lines, characterized in that, include: S1. Determine the default state of all signal lines and initialize the first control signal line, the second control signal line, the third control signal line, the clock signal line, and the data signal line; The control signal lines include: a first control signal line indicating the bus operating state, a second control signal line indicating the bus data state and the return status, and a third control signal line forcing a node to release the bus; S2. The device is in receiving mode and continuously listens to the control signal lines on the bus. In step S2, the device is in a receiving state and continuously listens to the control signal lines on the bus, specifically as follows: Based on the state of the second control signal line, the data received by the data signal line is stored in the FIFO. After verification, the data frame in the FIFO is sent to the receiving queue and the FIFO is cleared. If the rising edge of the first control signal line is received, the receiving state needs to be reset; If a falling edge of the second control signal line is received, bus data needs to be received twice consecutively on the falling edge of the clock signal line, and the received data should be stored in the FIFO. If a rising edge of the third control signal line is received, the bus needs to be released and the receiving state reset. S3. If a valid data frame is detected, it is stored in the receive queue; S4. If the device needs to send data, control the bus and enter the arbitration segment according to the level of data transmission. Specifically, step S4, which controls the bus according to the level of the transmitted data, involves: The data transmission levels include normal-level messages and privileged-level messages, and the control bus includes the following steps: S41, determine the bus operating status based on the first control signal line and the third control signal line; When the first control signal line and the third control signal line of S411 are both at a low level, it means that the bus is not occupied and can immediately send a normal-level message or a privileged-level message to enter the arbitration segment. S412, when the first control signal line is high and the third control signal line is low, it indicates that the bus is occupied. Check the message level and the level of the message to be sent on the bus, specifically: S4121, If ​​the level of the message on the bus is a normal level message, and the level of the message to be sent is a privileged level message, then the third control signal line is used to interrupt the current bus transmission, preempt the sending permission, and enter the arbitration segment; S4122, If the level of the message on the bus is a privileged message, and the level of the message to be sent is also a privileged message, then after the message on the bus is sent, the arbitration segment is entered; S4123, If the level of the message on the bus is a normal-level message, and the level of the message to be sent is also a normal-level message, then after the message on the bus is sent, the arbitration segment is entered; S5. The device sends its own node arbitration ID to participate in bus arbitration; S6. Determine the arbitration result: S61. If the arbitration is successful, the bus control is obtained and the system enters the transmit state. S62. If arbitration fails, return to the receiving state and continue listening.

2. The synchronous parallel bus communication method based on three control lines according to claim 1, characterized in that: The clock signal line and data signal line in step S1 are specifically as follows: The clock signal line is used for the clock signal of the synchronization bus; The data signal lines include: data0-data15, a sixteen-bit parallel data signal line.

3. The synchronous parallel bus communication method based on three control lines according to claim 1, characterized in that, Step S5, in which the device sends its own node arbitration ID to participate in bus arbitration, specifically includes: S51. If the highest bit of ID is 0, then the first arbitration method shall be adopted; S52. If the highest bit of ID is 1, then the second arbitration method shall be adopted.

4. The synchronous parallel bus communication method based on three control lines according to claim 3, characterized in that: If the highest bit of ID is 0 in step S51, then the first arbitration method is adopted, specifically as follows: Within one clock cycle, the node requiring arbitration sends its ID to the data signal line on the rising edge of the clock. On the falling edge of the clock, each node acquires data from the data signal line, XORs the acquired data with its own ID to obtain ID1, and then compares ID with ID1. If ID > ID1, the bus is obtained directly, and the second control signal line is set to the active state. If ID < ID1, the bus is lost.

5. The synchronous parallel bus communication method based on three control lines according to claim 3, characterized in that: If the highest bit of ID is 1 in step S52, then the second arbitration method is adopted, specifically as follows: Within 2n-1 clock cycles, where n is the number of arbitrations; on the rising edge of the first clock cycle of each round of arbitration, the respective arbitration ID1 is sent to the data signal line, and the initial state of ID1 is equal to its own ID; on the falling edge, the bus data is read and XORed with ID1 to obtain ID2; If ID2 equals 0, the bus is acquired, the second control signal line is set to the active state, and the arbitration segment ends. If ID2 is greater than ID1, the bus is lost; If the second control signal line is detected to be invalid before the start of the second clock cycle of each round, the second clock cycle needs to be entered. On the rising edge of the second clock cycle, the node that has not lost the bus needs to send ID2 to the data bus, obtain the bus data ID3 on the falling edge, set ID1 to the value of ID3-ID2, and then proceed with the next round of arbitration.

6. The synchronous parallel bus communication method based on three control lines according to claim 1, characterized in that: When the device needs to send a normal-level message or a privileged-level message Sending a normal message only requires setting the first control signal line to the active state; Privileged message sending requires both the first and third control signal lines to be enabled, and the third control signal line to be disabled after one clock cycle.

7. The synchronous parallel bus communication method based on three control lines according to claim 1, characterized in that: In step S7, the device control bus sends data according to a frame structure, which includes an information segment, a data segment, a check segment, and a response segment, specifically: The information segment consists of four clock cycles and two data segments, including the source ID of one clock cycle, the target ID of one clock cycle, the index value of one clock cycle, and the data length of one clock cycle. The data segment consists of several 32-bit data, and it takes two clock cycles to send one data segment. The verification segment performs CRC32 verification on all data in the information segment and data segment, which requires two clock cycles, and the node response status is obtained in the second clock cycle. The response segment consists of the IDs of each node that has correctly received the information and requires one clock cycle.

8. The synchronous parallel bus communication method based on three control lines according to claim 1, characterized in that: S7, the device control bus, sends data in a frame structure, which includes an information segment, a data segment, a check segment, and a response segment. S8. Monitor the sending status and perform corresponding operations based on the sending results.

9. A synchronous parallel bus communication method based on three control lines according to claim 8, characterized in that: In step S8, monitoring the transmission status and performing corresponding operations based on the transmission result, the monitoring of the transmission status specifically includes: At the end of the verification segment, obtain the status of the second control signal line: If the second control signal line is in an invalid state, it means that the transmission was successful; If the second control signal line is active, it indicates that the transmission has failed. Alternatively, a response segment for one clock cycle can be sent as a diagnostic cycle. All nodes that receive normal data will send their own IDs to the bus. The node sending the message will XOR the bus data with the destination ID in the message frame to obtain the ID of the faulty node.

10. A synchronous parallel bus communication method based on three control lines according to claim 9, characterized in that: In step S8, which monitors the transmission status and performs corresponding operations based on the transmission result, the specific steps of performing corresponding operations based on the transmission result are as follows: S81. If the message is sent successfully, remove it from the sending queue and return to the receiving status. S82. If sending fails: S821. If the number of retries is less than the preset value, then retry sending; S822. If multiple transmissions fail, retransmit at a reduced speed according to the reduced clock frequency. S823. If the number of retries is exhausted, discard the message, remove the message from the sending queue, and return to the receiving status.

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