Data encoding method and apparatus, electronic device, and storage medium

Abstract

The application provides a data encoding method and device, electronic equipment and storage medium, the method comprises: obtaining a target bit matrix corresponding to an original encoding matrix, and a plurality of data elements corresponding to to-be-written data; obtaining a plurality of XOR output expressions according to the correspondence between the target bit matrix and the plurality of data elements; performing structured analysis on each XOR output expression to obtain a reusable sub-expression; rearranging and reconstructing the XOR output expression containing the reusable sub-expression according to the reusable sub-expression to obtain a reconstructed expression; and generating an encoding result of the to-be-written data according to the reconstructed expression and the XOR output expression not containing the reusable sub-expression. The calculation complexity is reduced through XOR operation, and the number of redundant XOR operations is reduced through the rearrangement algorithm by reusing intermediate results, thereby realizing logical optimization of the encoding matrix calculation process, and reducing the number of overall XOR operations while ensuring encoding accuracy.

Description

Technical Field

[0001] This application relates to the field of storage technology, and more specifically, to a data encoding method, apparatus, electronic device, and storage medium. Background Technology

[0002] In current large-scale data storage and processing scenarios, distributed storage architecture has become the mainstream technical solution to meet the requirements of high availability and high performance data access. However, the failure of storage nodes in a distributed storage system can lead to data loss or a decrease in system reliability.

[0003] In related technologies, data redundancy coding techniques (such as multiple copy mechanisms or erasure coding techniques) are typically used to encode and store the original data in order to achieve data recovery and reconstruction when storage nodes fail.

[0004] However, the finite field multiplication operations involved in the above data redundancy coding process have a large overhead, which significantly increases the coding complexity, reduces coding efficiency, and leads to high consumption of computing resources. Summary of the Invention

[0005] In view of this, embodiments of this application provide a data encoding method, apparatus, electronic device, and storage medium to solve the problem that the finite field multiplication operations involved in the existing data redundancy encoding process have a large overhead, which leads to a significant increase in encoding complexity, a reduction in encoding efficiency, and a high consumption of computing resources.

[0006] In a first aspect, embodiments of this application provide a data encoding method, including: Obtain the target bit matrix corresponding to the original encoding matrix, and the multiple data elements corresponding to the data to be written; Based on the correspondence between the target bit matrix and the multiple data elements, multiple XOR output expressions are obtained, wherein the value of the corresponding element of the data element in the target bit matrix indicates whether the data element participates in the XOR operation; The XOR output expressions are subjected to structured analysis to obtain reusable sub-expressions; Based on the reusable sub-expression, the XOR output expression containing the reusable sub-expression is arranged and reconstructed to obtain the reconstructed expression; The encoding result of the data to be written is generated based on the reconstructed expression and the XOR output expression that does not contain the reusable subexpression.

[0007] In an optional implementation, obtaining the target bit matrix corresponding to the original encoding matrix and the multiple data elements corresponding to the data to be written includes: Based on the finite field width, the field elements in the original encoding matrix are converted into binary to obtain the target bit matrix. In the target bit matrix, the element with a value of 1 is used to indicate that the corresponding data element participates in the XOR operation, and the element with a value of 0 is used to indicate that the corresponding data element does not participate in the XOR operation. Based on the finite field width, the data to be written is structurally divided to obtain multiple data blocks, wherein each data block is divided into one or more data elements.

[0008] In an optional implementation, the step of performing structured analysis on each of the XOR output expressions to obtain reusable sub-expressions includes: The XOR output expressions are subjected to structured analysis to obtain a combination of sub-expressions; The reusable subexpression is obtained based on the number of times each subexpression appears in the subexpression combination.

[0009] In an optional implementation, after obtaining the reusable subexpression based on the frequency of occurrence of each subexpression in the subexpression combination, the method further includes: If there is variable overlap between at least two reusable sub-expressions, then the sub-expression with the largest occurrence is determined from the at least two reusable sub-expressions based on the occurrence count of the at least two reusable sub-expressions, and a first intermediate node is constructed based on the sub-expression with the largest occurrence, and a second intermediate node is constructed based on the other sub-expressions in the at least two reusable sub-expressions; The step of rearranging and reconstructing the XOR output expression containing the reusable sub-expression based on the reusable sub-expression to obtain a reconstructed expression includes: Based on the first intermediate node, the XOR output expression that simultaneously contains at least two of the reusable sub-expressions or the XOR output expression that only contains the sub-expression with the largest number is arranged and reconstructed to obtain the first reconstructed expression; Based on the second intermediate node, the XOR output expression containing only the other sub-expressions is rearranged and reconstructed to obtain the second reconstructed expression.

[0010] In an optional implementation, the step of rearranging and reconstructing the XOR output expression that simultaneously contains at least two of the reusable sub-expressions or the XOR output expression that only contains the sub-expression with the largest frequency, based on the first intermediate node, to obtain a first reconstructed expression, includes: Using the first intermediate node, replace the subexpression with the largest frequency in the XOR output expression that simultaneously contains at least two of the reusable subexpressions or in the XOR output expression that only contains the subexpression with the largest frequency; The step of rearranging and reconstructing the XOR output expression containing only the other sub-expressions based on the second intermediate node to obtain the second reconstructed expression includes: Using the second intermediate node, the other sub-expressions are replaced in the XOR output expression that contains only the other sub-expressions.

[0011] In an optional implementation, after rearranging and reconstructing the XOR output expression containing the reusable subexpression according to the reusable subexpression to obtain the reconstructed expression, the method further includes: Iteratively perform structured analysis on the reconstructed expression and the XOR output expression that does not contain the reusable sub-expression until no new reusable expression appears, and determine the previous round of reconstructed expression as the final reconstructed expression; The step of generating the encoded result of the data to be written based on the reconstructed expression and the XOR output expression that does not contain the reusable sub-expression includes: Based on the final reconstruction expression and the other XOR output expressions, the final encoding result of the data to be written is generated.

[0012] In an optional implementation, generating the encoded result of the data to be written based on the reconstructed expression and the XOR output expression that does not contain the reusable subexpression includes: In response to an XOR instruction, according to a parallel scheduling strategy, multiple XOR operations are performed in parallel in the reconstructed expression and the XOR output expression that does not contain the reusable subexpression to generate the encoded result of the data to be written. The XOR instruction includes a three-input XOR instruction or a two-input XOR instruction.

[0013] In an optional implementation, in response to the XOR instruction, according to a parallel scheduling strategy, multiple XOR operations are performed in parallel in the reconstructed expression and the XOR output expression that does not contain the reusable subexpression to generate the encoded result of the data to be written, including: Determine the undependent XOR terms in the reconstructed expression and the XOR output expression that does not contain the reusable subexpression; In response to the XOR instruction, according to the parallel scheduling strategy, multiple XOR operations are performed in parallel in the XOR terms that have no dependencies, and the parallel XOR result is obtained. In response to the XOR instruction, the XOR operation is performed sequentially on the XOR terms that have dependencies in the reconstructed expression and the XOR output expression that does not contain the reusable subexpression to obtain other XOR results; The encoding result of the data to be written is generated based on the parallel XOR result and the other XOR results.

[0014] Secondly, embodiments of this application also provide a data encoding device, including: The acquisition module is used to acquire the target bit matrix corresponding to the original encoding matrix, as well as multiple data elements corresponding to the data to be written; The acquisition module is further configured to acquire multiple XOR output expressions based on the correspondence between the target bit matrix and the multiple data elements, wherein the value of the corresponding element of the data element in the target bit matrix indicates whether the data element participates in the XOR operation; The processing module is used to perform structured analysis on each of the XOR output expressions to obtain reusable sub-expressions; The processing module is further configured to arrange and reconstruct the XOR output expression containing the reusable subexpression according to the reusable subexpression to obtain a reconstructed expression; The generation module is further configured to generate the encoding result of the data to be written based on the reconstructed expression and the XOR output expression that does not contain the reusable subexpression.

[0015] Thirdly, embodiments of this application also provide an electronic device, including: an encoding controller, a storage controller, and a memory, wherein the memory stores machine-readable instructions executable by the encoding controller, and the encoding controller executes the machine-readable instructions to perform the method described in any one of the first aspects, and the storage controller is used to write multiple data elements corresponding to the data to be written and the encoding result into the memory.

[0016] Fourthly, embodiments of this application also provide a computer-readable storage medium storing a computer program, which, when executed by a processor, performs the method described in any of the first aspects.

[0017] This application provides a data encoding method, apparatus, electronic device, and storage medium. The method includes: obtaining a target bit matrix corresponding to the original encoding matrix and multiple data elements corresponding to the data to be written; obtaining multiple XOR output expressions based on the correspondence between the target bit matrix and the multiple data elements; performing structured analysis on each XOR output expression to obtain reusable sub-expressions; arranging and reconstructing the XOR output expressions containing the reusable sub-expressions based on the reusable sub-expressions to obtain reconstructed expressions; and generating the encoding result of the data to be written based on the reconstructed expressions and the XOR output expressions that do not contain reusable sub-expressions. By reducing computational complexity through XOR operations and by reusing intermediate results through an arrangement algorithm, the number of redundant XOR operations is reduced, thereby optimizing the logic of the encoding matrix calculation process and reducing the overall number of XOR operations while ensuring encoding correctness. Attached Figure Description

[0018] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 A schematic diagram of the conversion and calculation of existing finite field matrix representations. Figure 1 ; Figure 2 A schematic diagram of the conversion and calculation of existing finite field matrix representations. Figure 2 ; Figure 3 This is a schematic diagram of the architecture of the data encoding system provided in the embodiments of this application; Figure 4 Flowchart of the data encoding method provided in the embodiments of this application Figure 1 ; Figure 5 A schematic diagram of data block division provided for embodiments of this application; Figure 6 A schematic diagram of the target bit matrix and data block provided in the embodiments of this application; Figure 7 This is a schematic diagram illustrating the specific effect of the original encoding matrix after arrangement, as provided in the embodiments of this application. Figure 8 Flowchart of the data encoding method provided in the embodiments of this application Figure 2 ; Figure 9 Flowchart of the data encoding method provided in the embodiments of this application Figure 3 ; Figure 10 Flowchart of the data encoding method provided in the embodiments of this application Figure 4 ; Figure 11 This is a schematic diagram comparing instructions provided for embodiments of this application; Figure 12 This is a schematic diagram of the structure of the data encoding device provided in the embodiments of this application; Figure 13 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0021] Figure 1 A schematic diagram of the conversion and calculation of existing finite field matrix representations. Figure 1 , Figure 2 A schematic diagram of the conversion and calculation of existing finite field matrix representations. Figure 2 .

[0022] like Figure 1 As shown, the encoding operation is performed in the finite field GF(2^w). In this example, w=4, K=4, and P=2. The four data blocks D1, D2, D3, and D4 are encoded to generate two parity blocks P1 and P2.

[0023] like Figure 2 As shown, to reduce the computational complexity caused by finite field multiplication, the field elements (E11, E12, E13, E14, E21, E22, E23, E24) in the original encoding matrix (the matrix of PxK) are mapped to the corresponding binary bit matrix representation. That is, the encoding matrix is ​​expanded into a bit matrix of size (Pxw)x(Kxw). In the figure, dark cells represent the value of the element as 1, and light cells represent the value of the element as 0, which is used to intuitively show the structural features of the encoding matrix after transformation.

[0024] In this example, the expanded matrix has a size of 8x16. At the same time, each data block is divided into 4 sub-data units (D10-D13, D20-D23, D30-D33, D40-D43) with a width of w=4, so that the multiplication operation originally required in the encoding process can be equivalently transformed into multiple sets of XOR operations.

[0025] In existing data redundancy schemes, data redundancy coding techniques typically involve a large number of finite field multiplication operations. These operations account for the main overhead in encoding matrix calculations, mapping elements in the finite field to their corresponding binary matrix representations. Building upon this, the complex finite field multiplication operations that originally required table lookups can be replaced with equivalent XOR operations to reduce computational complexity and the overhead of accessing lookup tables. However, this type of finite field-to-binary matrix conversion method often suffers from insufficient bit matrix sparsity, leading to the need for numerous XOR operations during matrix operations. Consequently, the overall encoding and decoding performance improvement is limited, and computational efficiency remains constrained by the high XOR operation overhead.

[0026] Based on this, this application provides a data encoding method that replaces the complex finite field multiplication operation originally implemented by table lookup with an equivalent XOR operation to reduce computational complexity and reduce the overhead of accessing the lookup table. Furthermore, it introduces an automated orchestration algorithm to reduce the number of redundant XOR operations by reusing intermediate results, thereby optimizing the logic of the encoding matrix calculation process. Through dynamic optimization and merging of intermediate calculation paths, the overall number of XOR operations can be significantly reduced while ensuring the correctness of the encoding.

[0027] It should be noted that the data encoding method provided in this application is applicable to a variety of storage and communication systems with high requirements for data reliability and transmission throughput. This method can be deployed in distributed storage systems and object storage clusters to improve the execution efficiency of data redundancy protection and enhance the system's fault tolerance, thereby meeting the requirements for high performance and high stability in large-scale data processing scenarios.

[0028] Figure 3 This is a schematic diagram of the architecture of the data encoding system provided in the embodiments of this application, such as... Figure 3 As shown, the data encoding system of this application embodiment includes: at least one server and one or more storage nodes. The server generates data to be written and sends the data to the storage nodes through a communication network. The communication network can be a local area network, a wide area network, the internal network of a data center, or any combination thereof, and this application does not impose any restrictions.

[0029] In this embodiment, each storage node is equipped with an encoding controller and a storage controller, which are used to implement data redundancy encoding processing and data write management, respectively. The storage node may also include one or more memories for storing data blocks and parity blocks. This application does not limit the type of memory; the storage area can be a hard disk drive (HDD), a solid-state drive (SSD), non-volatile memory (NVM), storage-class memory (SCM), or other media capable of storing data.

[0030] The encoding controller and storage controller can be integrated into the processor, which can be, for example, a central processing unit (CPU), a field-programmable gate array (FPGA), or an application-specific integrated circuit (ASIC).

[0031] It should be noted that the technical solution of this application is also applicable to other distributed storage or cloud storage architectures, such as object storage systems, distributed file systems, or database systems with data redundancy capabilities. Figure 3 This is merely an illustrative application scenario used to illustrate the system environment that this application can achieve, and should not be construed as any limitation on the scope of protection of this application.

[0032] Taking erasure coding with a ratio of K+P of 4+2 as an example, K represents the number of data blocks, which are the basic storage units after the original data is divided, and P represents the number of parity blocks, which are the parity blocks generated by the erasure coding algorithm and used to achieve fault tolerance and recovery when some data blocks are lost. In this example, the data to be written is divided into 4 data blocks (D1, D2, D3, D4). Based on these 4 data blocks, the encoding controller encodes 2 parity blocks (P1, P2) according to the selected encoding matrix or encoding rules. This allows for data reconstruction using the remaining blocks (including the unlost data blocks and the parity blocks) even if a maximum of 2 data blocks are lost. After the encoding process is completed, the storage controller writes the 4 data blocks and 2 parity blocks to 6 memories according to the node or memory distribution strategy.

[0033] Figure 4 Flowchart of the data encoding method provided in the embodiments of this application Figure 1 In this embodiment, the execution subject can be an electronic device, such as the aforementioned storage node.

[0034] like Figure 4 As shown, the method may include: S101. Obtain the target bit matrix corresponding to the original encoding matrix, and multiple data elements corresponding to the data to be written.

[0035] The original encoding matrix is ​​the matrix used for encoding calculation, and the target bit matrix corresponding to the original encoding matrix refers to the bit matrix obtained by mapping the field elements (matrix elements) in the original encoding matrix into binary form.

[0036] The data to be written is the data to be encoded, and the multiple data elements corresponding to the data to be written refer to the smallest processing unit that will ultimately participate in the XOR operation.

[0037] In an optional implementation, step S101 above, obtaining the target bit matrix corresponding to the original encoding matrix and the multiple data elements corresponding to the data to be written, may include: Based on the finite field width, the field elements in the original encoding matrix are converted into binary form to obtain the target bit matrix; Based on the finite field width, the data to be written is structurally divided into multiple data blocks.

[0038] Wherein, the finite field bit width is w in the finite field GF(2^w). Based on the finite field bit width, the field elements in the original encoding matrix are converted into binary to obtain the target bit matrix. In the target bit matrix, the element with a value of 1 is used to indicate that the corresponding data element participates in the XOR operation, and the element with a value of 0 is used to indicate that the corresponding data element does not participate in the XOR operation.

[0039] Based on the finite field width, the data to be written is structurally divided into multiple data blocks. The number of data blocks is consistent with the finite field width w. For example, if w=4, the data to be written is structurally divided into 4 data blocks.

[0040] Each data block is divided into one or more data elements. Specifically, each data block can be structurally divided according to the bit width of the vector register to obtain one or more data elements. The bit width of the vector register is the same as the bit width of the data element. If the bit width of the vector register is 128 bits, then the bit width of the data element is 128 bits.

[0041] It should be noted that this application does not impose any restrictions on the length of data blocks and data elements. For example, for a 256-bit vector register, the data element can be divided into 256 bits to further enhance parallel processing capabilities and achieve more efficient XOR operations. Furthermore, compared to the traditional scheme using 64 bits as data elements, the amount of data processed in a single operation is doubled.

[0042] In this context, each row element in the target bit matrix is ​​considered as an index to multiple data elements, and corresponds one-to-one with each of the multiple data elements.

[0043] The data to be written is divided into w data blocks according to the bit width w of the finite field GF(2^w). Figure 5 This is a schematic diagram of data block division provided in an embodiment of this application, as shown below. Figure 5 As shown, for contiguous data to be written stored in memory, in a GF(2^4)-based implementation, the data can be divided into four equal-length data blocks based on w=4. Within each sub-block, the data block is further represented as multiple smallest processing units, i.e., data elements, such as D. 01 D 03 ...D 08 As shown, this is used to support subsequent encoding bit matrix mapping and bitwise XOR operations.

[0044] In addition, during the encoding process, data elements are usually loaded into the vector register before participating in the encoding calculation.

[0045] Taking the division of each data block into a data element as an example, that is, one data block as one data element, the data to be written is divided into data blocks D0, D1, D2, and D3. Figure 6 This is a schematic diagram of the target bit matrix and data block provided in the embodiments of this application, as shown below. Figure 6 As shown, each row in the target bit matrix is ​​considered as an index of four data blocks, corresponding one-to-one. That is, each row in the target bit matrix corresponds to D0, D1, D2, and D3 respectively. The first column in the target bit matrix corresponds to D0, the second column corresponds to D1, the third column corresponds to D2, and the fourth column corresponds to D3 (i.e., matrix multiplication). The index of the first row is (1,2,3,), indicating that D1, D2, and D3 participate in the operation. The index of the second row is (0,1,2), indicating that D0, D1, and D2 participate in the XOR operation.

[0046] S102. Based on the correspondence between the target bit matrix and multiple data elements, obtain multiple XOR output expressions.

[0047] The correspondence between the target bit matrix and multiple data elements refers to the mapping relationship between each row element in the target bit matrix and multiple data elements, thereby establishing a unified index mapping mechanism for multiple data elements.

[0048] Based on the correspondence between the target bit matrix and multiple data elements, an XOR operation is performed on the data elements corresponding to the elements with a value of 1 in the target bit matrix to obtain the XOR output expression. The value of the corresponding element in the target bit matrix indicates whether the data element participates in the XOR operation; an element with a value of 1 indicates that the corresponding data element participates in the XOR operation, and an element with a value of 0 indicates that the corresponding data element does not participate in the XOR operation.

[0049] See Figure 6 Multiple XOR output expressions are R0=D1^D2^D3 and R1=D0^D1^D2, where ^ represents the XOR operation.

[0050] S103. Perform structured analysis on the XOR output expressions to obtain reusable sub-expressions.

[0051] The XOR output expressions are subjected to structured analysis to obtain reusable subexpressions. A reusable subexpression refers to an XOR term consisting of the same operands in at least two XOR output expressions. An XOR term is an expression obtained by XORing two or more operands.

[0052] In some embodiments, a sliding window approach is used to traverse each XOR output expression to obtain all sub-expressions contained in each XOR output expression.

[0053] In an optional implementation, step S102 above, which involves performing structured analysis on the XOR output expressions to obtain reusable sub-expressions, may include: Perform structured analysis on the XOR output expressions to obtain combinations of subexpressions; Reusable subexpressions are obtained by counting the occurrences of each subexpression in the subexpression combination.

[0054] The XOR output expressions are subjected to structured analysis to obtain a combination of subexpressions. The combination of subexpressions includes the subexpressions contained in the XOR output expressions. A subexpression refers to an XOR term consisting of two or more operands. The size of the subexpression is not limited and can include binary (an XOR term consisting of two operands), ternary (an XOR term consisting of three operands), or quaternary variable combinations (an XOR term consisting of four operands) to capture a wider range of implicit structural features.

[0055] For example, if multiple XOR output expressions are R0=D1^D2^D3 and R1=D0^D1^D2, then all binary subexpressions in R0 can be traversed as: Tmp0=D1^D2, Tmp1=D1^D3, Tmp2=D2^D3, and all binary subexpressions in R1 can be traversed as: Tmp3=D0^D1, Tmp4=D0^D2, Tmp5=D1^D2.

[0056] By constructing subexpression combinations (i.e., a pool of candidate subexpressions), and then determining the subexpressions that appear more than or equal to 2 times from the subexpression combinations as reusable subexpressions based on the number of times each subexpression appears in the subexpression combination.

[0057] For example, if the candidate subexpression pool contains subexpressions Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, and Tmp5, count the occurrences of each subexpression. Among them, D1^D2 appears twice, and the rest appear once. Therefore, if the occurrence count is greater than 1, the subexpression can be considered reusable. That is, D1^D2 is a reusable subexpression.

[0058] S104. Based on the reusable subexpression, the XOR output expression containing the reusable subexpression is rearranged and reconstructed to obtain the reconstructed expression.

[0059] After identifying the reusable subexpression, determine the XOR output expression containing the reusable subexpression from multiple XOR output expressions, and construct the corresponding intermediate node based on the reusable subexpression. The intermediate node refers to the logical subexpression commonly referenced by the XOR output expressions containing the reusable subexpression.

[0060] Then, the intermediate node corresponding to the reusable subexpression is used to replace the reusable subexpression in the XOR output expression containing the reusable subexpression, resulting in the reconstructed expression corresponding to the XOR output expression containing the reusable subexpression. The reconstructed expression is essentially also an XOR output expression. This reduces the overall XOR computation load.

[0061] In other words, after generating intermediate nodes, the XOR output expression is rewritten by replacing the reusable sub-expressions (i.e., variable combinations) in the XOR output expression containing reusable sub-expressions with intermediate nodes. The reconstructed expression consists of two types of signals: one is the multiplexed signal from the intermediate nodes, and the other is the remaining variables not included in any intermediate nodes.

[0062] For example, D1 ^ D2 is a reusable subexpression of the XOR output expression of R0, R1, and R2. By constructing an intermediate node T0 corresponding to D1 ^ D2, where T0 = D1 ^ D2, we determine whether multiple XOR output expressions contain all operands corresponding to this intermediate node to decide whether to use this intermediate node for replacement calculation. Specifically, if R0 = D1 ^ D2 ^ D3 contains T0, then the reconstructed expression is R0 = T0 ^ D3; if R1 = D0 ^ D1 ^ D2 contains T0, then the reconstructed expression is R1 = D0 ^ T0; and if R2 = D2 ^ D4 ^ D5 does not contain T0, then there is no reconstructed expression for R2.

[0063] For example, given R0 = D1^D2^D3 and R1 = D0^D1^D2, we know from the example above that D1^D2 appears the most frequently. Therefore, we let the intermediate node T0 = D1^D2, and the reconstructed expression obtained by replacing the original XOR output expression is: R0 = T0^D3 and R1 = D0^T0. This reduces the original four XOR calculations to three.

[0064] Figure 7 This is a schematic diagram illustrating the specific effect of the original encoding matrix after arrangement, as provided in the embodiments of this application. Figure 7 As shown, the left figure is the target bit matrix of the original encoding matrix, and the right figure is the arrangement and reconstruction matrix.

[0065] A 4+2 original encoding matrix under the GF(2^4) finite field is adopted and converted into a target bit matrix. In the figure, dark cells represent elements with a value of 1, and light cells represent elements with a value of 0. The target bit matrix (dark represents 1, light represents 0) is as follows: [ [1000 1000 1000 1000] [0100 0100 0100 0100] [0010 0010 0010 0010] [0001 0001 0001 0001] [0100 1101 1110 1100] [0110 1011 0001 0010] [0011 0101 1000 0001] [1001 1010 1100 1000] ] Assuming multiple data blocks are D0-D15, after orchestration and reconstruction, the elements in the target bit matrix (an 8×16 bit matrix) are distinguished by different colors to identify reusable sub-expressions automatically extracted during the orchestration process.

[0066] The XOR output expression for the first row of the target bit matrix is: R0 = D0^D4^D8^D12 (3 XOR operations), the XOR output expression for the second row is: R1 = D1^D5^D9^D13 (3 XOR operations), and so on. There are a total of 45 ones in the target bit matrix, so the calculation requires (45 - 8 (rows)) = 37 XOR operations. After arrangement and reconstruction, the intermediate nodes are constructed as follows: t1 = D4^D8^D12, t2 = D7^D11, t3 = D2^D6^D14. The optimized output expressions are: R0 = t1^D0, R1 = D1^D5^D9^D13, R2 = D10^t3, R3 = t2^D3^D15, R4 = D7^D10^t1^r1, R5 = D1^D4^ t2 ^ t3, R6 = D2 ^ D5 ^ D8 ^ D11 ^ r3, R7 = D3 ^ D6 ^ D9 ^ r0. It can be seen that only 25 XOR operations are needed to complete the same calculation operation. It can be seen that the target bit matrix before optimization contained 37 XOR operations. After reconstruction by the orchestration algorithm, the number of XOR operations was reduced to 25, and the amount of computation was reduced by about 32.4%. This orchestration algorithm can effectively reduce the complexity of encoding computation and improve the overall performance of the encoding process.

[0067] S105. Generate the encoded result of the data to be written based on the reconstructed expression and the XOR output expression that does not contain reusable subexpressions.

[0068] Among them, multiple XOR output expressions include: reconstructed expressions and XOR output expressions that do not contain reusable subexpressions.

[0069] The reconstructed expression is XORed, and the XOR output expression that does not contain reusable subexpressions is XORed to obtain multiple check blocks, which in turn generate the encoded result of the data to be written, wherein the encoded result of the data to be written includes multiple check blocks.

[0070] For example, R0=T0^D3 and R1=D0^T0 are reconstruction expressions, and R2=D2^D4^D5 is an XOR output expression that does not contain reusable subexpressions. The three expressions are operated on separately to obtain the encoded result of the data to be written.

[0071] In this embodiment, the computational complexity is reduced by using XOR operations, and the number of redundant XOR operations is reduced by using an orchestration algorithm to reuse intermediate results, thereby optimizing the logic of the encoding matrix calculation process and reducing the overall number of XOR operations while ensuring the correctness of the encoding.

[0072] Figure 8 Flowchart of the data encoding method provided in the embodiments of this application Figure 2 ,like Figure 8 As shown, in an optional implementation, after obtaining the reusable subexpression based on the frequency of occurrence of each subexpression in the subexpression combination in step S103, the method may further include: S201. If there is variable overlap between at least two reusable subexpressions, then determine the subexpression with the largest frequency from the at least two reusable subexpressions based on the frequency of occurrence of the at least two reusable subexpressions, construct a first intermediate node based on the subexpression with the largest frequency, and construct a second intermediate node based on the other subexpressions in the at least two reusable subexpressions.

[0073] Other subexpressions refer to the subexpressions other than the one with the highest frequency among at least two reusable subexpressions.

[0074] Variable overlap refers to at least two reusable subexpressions containing the same operands. For example, in a subexpression combination, subexpression D1^D2 appears 3 times and subexpression D2^D3 appears 2 times, so D1^D2 and D2^D3 are reusable subexpressions. However, since both D1^D2 and D2^D3 use D2, there is variable overlap between D1^D2 and D2^D3. The number of occurrences of D1^D2 is greater than the number of occurrences of D2^D3. The first intermediate node is constructed based on D1^D2, and the second intermediate node is constructed based on D2^D3.

[0075] Step S103 above involves rearranging and reconstructing the XOR output expression containing reusable subexpressions based on the reusable subexpressions to obtain a reconstructed expression, which may include: S202. Based on the first intermediate node, the XOR output expression that contains at least two reusable sub-expressions or the XOR output expression that contains only the sub-expression with the largest number of occurrences is arranged and reconstructed to obtain the first reconstructed expression.

[0076] In this process, a first intermediate node can be used to replace the subexpression with the largest frequency in either an XOR output expression that contains at least two reusable subexpressions or an XOR output expression that contains only the subexpression with the largest frequency.

[0077] For an XOR output expression that contains at least two reusable subexpressions, based on the principle of priority of occurrence, the subexpression with the highest occurrence is replaced in the XOR output expression that contains at least two reusable subexpressions, according to the first intermediate node corresponding to the subexpression with the highest occurrence.

[0078] For example, in the XOR output expressions R0, R1, R2, and R3, D1^D2 is included, and R3 and R4 contain D2^D3. Since D1^D2 and D2^D3 have variable overlap, and since D1^D2 appears more often than T1, D1^D2 is reused first. The first intermediate node T0 corresponding to D1^D2 is constructed, and T0 is used to replace D1^D2 in R0, R1, R2, and R3. Since R3 and R4 contain both T0 and T1, after replacing D1^D2 in R3 and R4, D2 has been consumed. Introducing the second intermediate node T1 corresponding to D2^D3 would cause a conflict. Therefore, T0, which appears more often, is chosen first, and T1 is abandoned.

[0079] An XOR output expression containing only the subexpression with the largest quantity refers to an XOR output expression that contains only the subexpression with the largest quantity among at least two reusable subexpressions. It should be noted that this XOR output expression may contain other subexpressions besides the subexpression with the largest quantity, in addition to the at least two reusable subexpressions.

[0080] For such an XOR output expression, based on the first intermediate node, the subexpression with the largest frequency is replaced in the XOR output expression containing only the subexpression with the largest frequency.

[0081] S203. Based on the second intermediate node, the XOR output expression containing only other sub-expressions is rearranged and reconstructed to obtain the second reconstructed expression.

[0082] In this approach, a second intermediate node can be used to replace other sub-expressions in the XOR output expression that contains only other sub-expressions.

[0083] An XOR output expression that contains only other subexpressions refers to an XOR output expression that contains only the other subexpressions from at least two reusable subexpressions. It should be noted that this XOR output expression may contain additional subexpressions besides the aforementioned other subexpressions.

[0084] For such an XOR output expression, the other subexpression is replaced in the XOR output expression containing only other subexpressions, based on the second intermediate node.

[0085] For example, in the XOR output expression R0, R1, R2, R3, R0, R1, and R2 all contain D1^D2, and R3 and R4 contain D2^D3. Since D1^D2 and D2^D3 do not appear in the same XOR output expression, there will be no conflict. Therefore, the first intermediate node T0 corresponding to D1^D2 can be used to replace D1^D2 in R0, R1, and R2, and the second intermediate node T1 corresponding to D2^D3 can be used to replace D2^D3 in R3 and R4. In other words, T0 and T1 are not used simultaneously in the same XOR output expression, so the conditions can be reused in parallel. Even if there is variable overlap, both intermediate nodes can be reused and can still be used as intermediate nodes.

[0086] Of course, if there is no variable overlap between at least two reusable subexpressions, then each reusable subexpression is directly used, and in the XOR output expression containing each reusable subexpression, each reusable subexpression is replaced.

[0087] In this embodiment, the construction of intermediate nodes follows the principle of avoiding variable overlap and conflict. When there is variable overlap between at least two reusable sub-expressions and they appear in the same XOR output expression, a frequency-first mechanism based on a greedy strategy is adopted. The reusable sub-expression with the highest occurrence frequency is selected from the at least two reusable sub-expressions to construct intermediate nodes for reconstruction and arrangement. If they do not appear in the same XOR output expression, intermediate nodes can be constructed separately for reconstruction and arrangement, thereby maximizing reuse efficiency.

[0088] Figure 9 Flowchart of the data encoding method provided in the embodiments of this application Figure 3 ,like Figure 9 As shown, in an optional implementation, after step S104, which involves rearranging and reconstructing the XOR output expression containing the reusable subexpression based on the reusable subexpression to obtain the reconstructed expression, further includes: S301. Iteratively execute the structured analysis of the reconstructed expression and the XOR output expression that does not contain reusable subexpressions until no new reusable expression appears, and determine the previous round of reconstructed expression as the final reconstructed expression.

[0089] After the initial orchestration and reconstruction are completed, a reconstructed expression is obtained. This reconstructed expression may expose previously undetected combinations of repeated variables. Therefore, a structured analysis can be performed again on the reconstructed expression and the XOR output expression that does not contain reusable subexpressions to further explore the reconstructed expression and the XOR output expression that does not contain reusable subexpressions, in order to generate more reusable intermediate nodes. This process is repeated multiple times until no new reusable expressions appear, and the previous round of reconstructed expression is determined as the final reconstructed expression, thereby achieving the optimal or near-optimal solution for global optimization.

[0090] It should be noted that the process of iteratively performing structured analysis can be found in step S103 above, and will not be repeated here.

[0091] Step S105 above, which generates the encoded result of the data to be written based on the reconstructed expression and the XOR output expression that does not contain reusable subexpressions, may include: S302. Based on the final reconstruction expression and other XOR output expressions, generate the final encoded result of the data to be written.

[0092] Among them, other XOR output expressions are reconstruction expressions that did not have new reusable expressions in the previous round of orchestration and reconstruction, or XOR output expressions that do not contain reusable sub-expressions.

[0093] The final reconstructed expression is XORed, as are other XOR output expressions, to obtain multiple check blocks, which in turn generate the final encoded result of the data to be written.

[0094] In this embodiment, structured analysis is performed through deep iterative optimization to achieve the optimal or near-optimal solution for global optimization, further reducing the number of overall XOR operations.

[0095] In an optional implementation, step S105 above, which generates the encoded result of the data to be written based on the reconstructed expression and the XOR output expression that does not contain reusable subexpressions, may include: In response to the XOR instruction, according to the parallel scheduling strategy, multiple XOR operations are performed in parallel in the reconstructed expression and the XOR output expression that does not contain reusable subexpressions, to generate the encoded result of the data to be written.

[0096] The XOR instruction includes either a three-input XOR instruction or a two-input XOR instruction. The three-input XOR instruction indicates an XOR operation involving three operands, while the two-input XOR instruction indicates an XOR operation involving two operands.

[0097] In response to the XOR instruction, according to the parallel scheduling strategy, the XOR terms corresponding to the three-input XOR instruction and the XOR terms corresponding to the two-input XOR instruction are determined from the reconstructed expression and the XOR output expression that does not contain reusable subexpressions. Specifically, the XOR term corresponding to the three-input XOR instruction contains an XOR operation on three operands, and the XOR term corresponding to the two-input XOR instruction contains an XOR operation on two operands.

[0098] Then, the three-input XOR instruction is used in parallel to perform XOR operation on the XOR terms corresponding to the three-input XOR instruction, and the two-input XOR instruction is used to perform XOR operation on the XOR terms corresponding to the two-input XOR instruction. This allows the XOR operation of multiple XOR terms to be performed in parallel in the reconstructed expression and the XOR output expression that does not contain reusable subexpressions, so as to obtain the encoded result of the data to be written.

[0099] Figure 10 Flowchart of the data encoding method provided in the embodiments of this application Figure 4 ,like Figure 10 As shown, in an optional implementation, in response to an XOR instruction, according to a parallel scheduling strategy, multiple XOR operations are performed in parallel in the reconstructed expression and the XOR output expression that does not contain reusable subexpressions to generate the encoded result of the data to be written, which may include: S401. Determine the undependent XOR terms in the refactored expression and the XOR output expression that does not contain reusable subexpressions.

[0100] In this context, an XOR term without dependencies refers to an XOR term in an XOR output expression that does not contain reusable subexpressions. In other words, the execution of this XOR term, which does not contain reusable subexpressions, does not depend on other XOR results. For example, the XOR term in R1 = D1 ^ D5 ^ D9 ^ D13 does not depend on other XOR results.

[0101] A dependent XOR term refers to an XOR term in an XOR output expression that contains reusable subexpressions (i.e., the XOR term corresponding to an intermediate node). In other words, the execution of the XOR term in the XOR output expression containing reusable subexpressions requires other XOR results. For example, R0 = T0^D3, T0 = D1^D2. Since the execution of R0 = T0^D3 depends on T0 = D1^D2, T0^D3 and D1^D2 are dependent XOR terms.

[0102] S402. In response to the XOR instruction, according to the parallel scheduling strategy, multiple XOR operations are performed in parallel in XOR terms that have no dependencies, and the parallel XOR result is obtained.

[0103] In response to the XOR instruction, according to the parallel scheduling strategy, the XOR terms corresponding to the three-input XOR instruction and the XOR terms corresponding to the two-input XOR instruction are determined from the XOR terms with no dependencies. Then, the three-input XOR instruction is used in parallel to perform XOR operation on the XOR terms corresponding to the three-input XOR instruction, and the two-input XOR instruction is used to perform XOR operation on the XOR terms corresponding to the two-input XOR instruction, so as to obtain the parallel XOR result.

[0104] S403. In response to the XOR instruction, perform XOR operations sequentially on the XOR terms that have dependencies in the reconstructed expression and the XOR output expression that does not contain reusable subexpressions, and obtain other XOR results.

[0105] In response to an XOR instruction, the XOR terms with dependencies are determined from the reconstructed expression and the XOR output expression that does not contain reusable subexpressions. From these dependent XOR terms, the XOR terms corresponding to the three-input XOR instruction and the two-input XOR instruction are determined. Then, based on the dependencies, XOR operations are performed sequentially to obtain other XOR results. For example, T0 = D1^D2 is executed first, followed by R0 = T0^D3.

[0106] S404. Generate the encoded result of the data to be written based on the parallel XOR result and other XOR results.

[0107] The encoding results of the data to be written include parallel XOR results and other XOR results.

[0108] Figure 11 This is a schematic diagram comparing instructions provided for embodiments of this application, such as... Figure 11 As shown, EOR represents a two-input XOR instruction, and EOR3 represents a three-input XOR instruction.

[0109] Within processing cycle 0 or processor cycle 1, a typical implementation can execute two XOR instructions simultaneously in one processing cycle, thus processing two pairs of 64-bit data elements within a single cycle. The total output data volume per cycle is 2 x 2 x 64 bits = 256 bits. Here, data element 1 / 5 represents data element 1 and data element 5 participating in the XOR operation in processing cycle 0, data element 2 / 6 represents data element 2 and data element 6 participating in the XOR operation in processing cycle 0, and so on.

[0110] To further improve the overall XOR operation throughput, this application adopts an instruction-level parallel scheduling strategy, enabling three-input XOR instructions and two-input XOR instructions to be issued and executed in parallel within the same period under the condition of no data dependency (no dependence). By introducing three-input XOR instructions, three 128-bit data elements can be read simultaneously in a single instruction, multiple data (SIMD) stream. This instruction mechanism folds two consecutive XOR operations into one at the hardware level, effectively reducing the number of instructions.

[0111] In some embodiments, when there is no operand dependency between the three-input and two-input XOR instructions, the scheduler can allocate the three-input and two-input XOR instructions to different execution ports to achieve true parallel issuance, thereby processing multiple vector XOR instructions in a single cycle and significantly improving Boolean operation performance.

[0112] In some embodiments, the encoding controller can automatically resolve the dependencies of XOR terms and dynamically select the XOR terms that need to participate in the XOR operation in each round of calculation. The encoding controller automatically identifies data elements belonging to the same logical calculation link and integrates these data elements according to the underlying register resource status and the instruction type expected to be executed in this round.

[0113] In actual execution, the encoding controller is responsible for loading the data elements of the selected XOR term into the vector register and preparing the corresponding two or three operands for the upcoming two-input XOR instruction and three-input XOR instruction, respectively. The encoding controller also ensures that there is no data dependency between XOR terms, so that a two-input XOR instruction and a three-input XOR instruction can be executed in parallel within the same cycle, maximizing the utilization of hardware resources.

[0114] In this embodiment, the encoding controller executes simultaneously in each execution cycle: one 128-bit XOR instruction for two inputs and one 128-bit XOR instruction for three inputs. This parallel execution method increases the amount of data processed per cycle from 256 bits in the traditional scheme to (2 x 128 bits) + (3 x 128 bits). (128 bits) = 640 bits, with a single-cycle data processing capability approximately 2.5 times that of traditional implementations, significantly improving the overall throughput of encoding computation. Furthermore, the three-input XOR instruction reduces the total number of instructions and decreases the occupancy of the vector register by intermediate results, further expanding the instruction scheduling space, which helps reduce pipeline stall probability and improve microarchitecture resource utilization efficiency. Additionally, the instruction-level parallel execution further enhances the overall throughput of XOR operations, significantly reducing computational overhead during data encoding and decoding, and improving the overall encoding efficiency and hardware execution performance of the system. Therefore, this application's solution achieves higher computational efficiency and resource utilization while maintaining encoding reliability, making it suitable for various scenarios such as high-performance data storage, distributed file systems, and communication systems.

[0115] Meanwhile, in the selection of data bit width, Single Instruction, Multiple Data (SIMD) technology can be fully utilized to enable each XOR operation to process a wider data bit width, thereby significantly improving the parallelism and efficiency of the operation.

[0116] Figure 12 This is a schematic diagram of the structure of a data encoding device provided in an embodiment of this application. This device can be integrated into an electronic device.

[0117] like Figure 12 As shown, the device may include: The acquisition module 501 is used to acquire the target bit matrix corresponding to the original encoding matrix, and multiple data elements corresponding to the data to be written; The acquisition module 501 is also used to acquire multiple XOR output expressions based on the correspondence between the target bit matrix and multiple data elements, wherein the value of the corresponding element of the data element in the target bit matrix indicates whether the data element participates in the XOR operation; Processing module 502 is used to perform structured analysis on each XOR output expression to obtain reusable sub-expressions; The processing module 502 is also used to arrange and reconstruct the XOR output expression containing the reusable subexpression according to the reusable subexpression to obtain the reconstructed expression; The generation module 503 is also used to generate the encoded result of the data to be written based on the reconstructed expression and the XOR output expression that does not contain reusable subexpressions.

[0118] In an optional implementation, the acquisition module 501 is specifically used for: Based on the finite field width, the field elements in the original encoding matrix are converted into binary to obtain the target bit matrix. In the target bit matrix, the element with a value of 1 is used to indicate that the corresponding data element participates in the XOR operation, and the element with a value of 0 is used to indicate that the corresponding data element does not participate in the XOR operation. Based on the finite field width, the data to be written is structurally divided into multiple data blocks, each of which is divided into one or more data elements.

[0119] In an optional implementation, the processing module 502 is specifically used for: Perform structured analysis on the XOR output expressions to obtain combinations of subexpressions; Reusable subexpressions are obtained by counting the occurrences of each subexpression in the subexpression combination.

[0120] In an optional implementation, the processing module 502 is further configured to: If there is variable overlap between at least two reusable subexpressions, then the subexpression with the largest occurrence is determined from the at least two reusable subexpressions based on the occurrence count of the at least two reusable subexpressions, and a first intermediate node is constructed based on the subexpression with the largest occurrence, and a second intermediate node is constructed based on the other subexpressions in the at least two reusable subexpressions. Processing module 502 is specifically used for: Based on the first intermediate node, the XOR output expression that contains at least two reusable sub-expressions or the XOR output expression that contains only the sub-expression with the largest number is arranged and reconstructed to obtain the first reconstructed expression. Based on the second intermediate node, the XOR output expression containing only other sub-expressions is rearranged and reconstructed to obtain the second reconstructed expression.

[0121] In an optional implementation, the processing module 502 is specifically used for: Using the first intermediate node, in the XOR output expression that contains at least two reusable subexpressions or the XOR output expression that contains only the subexpression with the largest number of occurrences, replace the subexpression with the largest number of occurrences. Using a second intermediate node, replace other subexpressions in the XOR output expression that contains only other subexpressions.

[0122] In an optional implementation, the processing module 502 is further configured to: Iterative execution performs structured analysis on the refactored expression and the XOR output expression that does not contain reusable subexpressions until no new reusable expressions appear, and the previous round of refactored expression is determined as the final refactored expression; The generation module 503 is specifically used to generate the final encoded result of the data to be written based on the final reconstruction expression and other XOR output expressions.

[0123] In an optional implementation, the processing module 502 is specifically used for: In response to the XOR instruction, according to the parallel scheduling strategy, multiple XOR operations are performed in parallel in the reconstructed expression and the XOR output expression that does not contain reusable subexpressions to generate the encoded result of the data to be written. The XOR instruction includes: a three-input XOR instruction or a two-input XOR instruction.

[0124] In an optional implementation, the processing module 502 is specifically used for: Identify the dependency-free XOR terms in the refactored expression and the XOR output expression that does not contain reusable subexpressions; In response to the XOR instruction, according to the parallel scheduling strategy, multiple XOR operations are performed in parallel in XOR terms that have no dependencies, and the parallel XOR result is obtained. In response to the XOR instruction, XOR operations are performed sequentially on the XOR terms that have dependencies in the reconstructed expression and the XOR output expression that does not contain reusable subexpressions, to obtain other XOR results. Based on the parallel XOR result and other XOR results, generate the encoded result of the data to be written.

[0125] The processing flow of each module in the device and the interaction flow between each module can be referred to the relevant descriptions in the above method embodiments, and will not be detailed here.

[0126] Figure 13 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. The device can be implemented using the aforementioned storage node.

[0127] like Figure 13 As shown, the device may include an encoding controller 601, a storage controller 602, and a memory 603. The memory 603 stores machine-readable instructions that can be executed by the encoding controller 601. The encoding controller 601 executes the machine-readable instructions to perform the above method. The storage controller 602 is used to write multiple data elements corresponding to the data to be written and the encoding result into the memory 603.

[0128] In some embodiments, the encoding controller 601 and the storage controller 602 are integrated into the processor.

[0129] This application also provides a computer-readable storage medium storing a computer program, which is executed by a processor to perform the above-described method.

[0130] In this embodiment, the computer program, when run by the processor, can also execute other machine-readable instructions to perform other methods as described in the embodiments. For details on the specific execution steps and principles, please refer to the description of the embodiments, which will not be repeated here.

[0131] In the embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. Furthermore, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Additionally, the displayed or discussed mutual couplings, direct couplings, or communication connections may be through some communication interfaces; indirect couplings or communication connections between devices or units may be electrical, mechanical, or other forms.

[0132] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0133] In addition, the functional units in the embodiments provided in this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0134] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0135] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. In addition, the terms "first", "second", "third", etc. are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0136] Finally, it should be noted that the above-described embodiments are merely specific implementations of this application, used to illustrate the technical solutions of this application, and not to limit them. The protection scope of this application is not limited thereto. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features, within the scope of the technology disclosed in this application; and these modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application. All should be covered within the protection scope of this application. Therefore, the protection scope of this application should be determined by the protection scope of the claims.

Claims

1. A data encoding method, characterized in that, include: Obtain the target bit matrix corresponding to the original encoding matrix, and the multiple data elements corresponding to the data to be written; Based on the correspondence between the target bit matrix and the multiple data elements, multiple XOR output expressions are obtained, wherein the value of the corresponding element of the data element in the target bit matrix indicates whether the data element participates in the XOR operation; The XOR output expressions are subjected to structured analysis to obtain reusable sub-expressions; Based on the reusable sub-expression, the XOR output expression containing the reusable sub-expression is arranged and reconstructed to obtain the reconstructed expression; The encoding result of the data to be written is generated based on the reconstructed expression and the XOR output expression that does not contain the reusable subexpression.

2. The method according to claim 1, characterized in that, The step of obtaining the target bit matrix corresponding to the original encoding matrix and the multiple data elements corresponding to the data to be written includes: Based on the finite field width, the field elements in the original encoding matrix are converted into binary to obtain the target bit matrix. In the target bit matrix, the element with a value of 1 is used to indicate that the corresponding data element participates in the XOR operation, and the element with a value of 0 is used to indicate that the corresponding data element does not participate in the XOR operation. Based on the finite field width, the data to be written is structurally divided to obtain multiple data blocks, wherein each data block is divided into one or more data elements.

3. The method according to claim 1, characterized in that, The structured analysis of each of the XOR output expressions to obtain reusable sub-expressions includes: The XOR output expressions are subjected to structured analysis to obtain a combination of sub-expressions; The reusable subexpression is obtained based on the number of times each subexpression appears in the subexpression combination.

4. The method according to claim 3, characterized in that, After obtaining the reusable subexpression based on the frequency of occurrence of each subexpression in the subexpression combination, the method further includes: If there is variable overlap between at least two reusable sub-expressions, then the sub-expression with the largest occurrence is determined from the at least two reusable sub-expressions based on the occurrence count of the at least two reusable sub-expressions, and a first intermediate node is constructed based on the sub-expression with the largest occurrence, and a second intermediate node is constructed based on the other sub-expressions in the at least two reusable sub-expressions; The step of rearranging and reconstructing the XOR output expression containing the reusable sub-expression based on the reusable sub-expression to obtain a reconstructed expression includes: Based on the first intermediate node, the XOR output expression that simultaneously contains at least two of the reusable sub-expressions or the XOR output expression that only contains the sub-expression with the largest number is arranged and reconstructed to obtain the first reconstructed expression; Based on the second intermediate node, the XOR output expression containing only the other sub-expressions is rearranged and reconstructed to obtain the second reconstructed expression.

5. The method according to claim 4, characterized in that, The step of rearranging and reconstructing the XOR output expression that simultaneously contains at least two of the reusable sub-expressions or the XOR output expression that only contains the sub-expression with the largest frequency, based on the first intermediate node, to obtain the first reconstructed expression includes: Using the first intermediate node, replace the subexpression with the largest frequency in the XOR output expression that simultaneously contains at least two of the reusable subexpressions or in the XOR output expression that only contains the subexpression with the largest frequency; The step of rearranging and reconstructing the XOR output expression containing only the other sub-expressions based on the second intermediate node to obtain the second reconstructed expression includes: Using the second intermediate node, the other sub-expressions are replaced in the XOR output expression that contains only the other sub-expressions.

6. The method according to claim 1, characterized in that, After rearranging and reconstructing the XOR output expression containing the reusable subexpression according to the reusable subexpression to obtain the reconstructed expression, the method further includes: Iteratively perform structured analysis on the reconstructed expression and the XOR output expression that does not contain the reusable sub-expression until no new reusable expression appears, and determine the previous round of reconstructed expression as the final reconstructed expression; The step of generating the encoded result of the data to be written based on the reconstructed expression and the XOR output expression that does not contain the reusable sub-expression includes: Based on the final reconstruction expression and the other XOR output expressions, the final encoding result of the data to be written is generated.

7. The method according to claim 1, characterized in that, The step of generating the encoded result of the data to be written based on the reconstructed expression and the XOR output expression that does not contain the reusable sub-expression includes: In response to an XOR instruction, according to a parallel scheduling strategy, multiple XOR operations are performed in parallel in the reconstructed expression and the XOR output expression that does not contain the reusable subexpression to generate the encoded result of the data to be written. The XOR instruction includes a three-input XOR instruction or a two-input XOR instruction.

8. The method according to claim 7, characterized in that, In response to the XOR instruction, according to the parallel scheduling strategy, multiple XOR operations are performed in parallel in the reconstructed expression and the XOR output expression that does not contain the reusable sub-expression to generate the encoded result of the data to be written, including: Determine the undependent XOR terms in the reconstructed expression and the XOR output expression that does not contain the reusable subexpression; In response to the XOR instruction, according to the parallel scheduling strategy, multiple XOR operations are performed in parallel in the XOR terms that have no dependencies, and the parallel XOR result is obtained. In response to the XOR instruction, the XOR operation is performed sequentially on the XOR terms that have dependencies in the reconstructed expression and the XOR output expression that does not contain the reusable subexpression to obtain other XOR results; The encoding result of the data to be written is generated based on the parallel XOR result and the other XOR results.

9. A data encoding device, characterized in that, include: The acquisition module is used to acquire the target bit matrix corresponding to the original encoding matrix, as well as multiple data elements corresponding to the data to be written; The acquisition module is further configured to acquire multiple XOR output expressions based on the correspondence between the target bit matrix and the multiple data elements, wherein the value of the corresponding element of the data element in the target bit matrix indicates whether the data element participates in the XOR operation; The processing module is used to perform structured analysis on each of the XOR output expressions to obtain reusable sub-expressions; The processing module is further configured to arrange and reconstruct the XOR output expression containing the reusable subexpression according to the reusable subexpression to obtain a reconstructed expression; The generation module is further configured to generate the encoding result of the data to be written based on the reconstructed expression and the XOR output expression that does not contain the reusable subexpression.

10. An electronic device, characterized in that, include: The system includes an encoding controller, a storage controller, and a memory, wherein the memory stores machine-readable instructions executable by the encoding controller, and the encoding controller executes the machine-readable instructions to perform the method according to any one of claims 1 to 8, and the storage controller is used to write multiple data elements corresponding to the data to be written and the encoding result into the memory.

11. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by the encoding controller, performs the method according to any one of claims 1 to 8.

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