A heat effect driven core particle layout planning method, device, equipment and medium

Abstract

This application discloses a thermal effect-driven chip layout planning method, apparatus, device, and medium, relating to the field of integrated circuit automated planning technology based on reinforcement learning. The method includes: generating an initial chip layout based on a chip configuration file; constructing a state vector by combining the layout information, line length, and simulation operating temperature of the initial chip layout; inputting the state vector into a pre-constructed deep Q-network to adjust and obtain a new chip layout; calculating a reward function based on the new chip layout; determining the target chip layout and corresponding type label for the current iteration based on the reward function; if the iteration threshold is not reached, continuing iteration until the threshold is reached; and determining the optimal chip layout based on the type label of the target chip layout for each iteration. This application effectively overcomes the shortcomings of traditional methods, such as low optimization efficiency, slow convergence, and susceptibility to local optima. It enables self-learning and rapid convergence in the optimization process, significantly reducing runtime overhead.

Description

Technical Field

[0001] This application relates to the field of integrated circuit automated planning technology based on reinforcement learning, and in particular to a thermal effect-driven chip layout planning method, apparatus, device and medium. Background Technology

[0002] In recent years, with the continuous evolution of integrated circuit technology, the design scale and complexity of System-on-Chip (SoC) have been steadily increasing, and the requirements for performance, power consumption, and integration density have also been rising. However, as Moore's Law gradually approaches its physical limits, the manufacturing of single chips faces multiple challenges, including physical constraints, soaring costs, and extended design cycles. Against this backdrop, chiplet technology has emerged, providing a new technological path for continuing to improve system performance and reducing design and manufacturing costs by breaking down complex systems into multiple reusable functional chiplet modules and achieving heterogeneous integration with advanced packaging technologies.

[0003] Chip layout optimization is a key step in the design of advanced packaging and heterogeneous integrated systems. As the number of integrated chips increases and the requirements for interconnect density and signal integrity continue to rise, the system is prone to problems such as increased power consumption and heat dissipation difficulties. By rationally planning chip layout and interconnection, the critical path can be shortened, signal delay and crosstalk can be reduced, heat distribution can be balanced, and local hot spots can be reduced, thereby achieving a comprehensive improvement in the overall system performance, power efficiency and thermal reliability, and thus achieving a balance between high performance and high reliability at the system level.

[0004] Currently, core layout planning optimization mainly relies on traditional methods such as heuristic algorithms and exact algorithms based on mathematical programming. Although these methods can achieve certain optimization results when the number of cores is limited and the constraints are relatively simple, as the system scale increases and thermal design and electrical constraints become increasingly complex, traditional methods gradually reveal limitations such as low optimization efficiency, slow convergence speed, and susceptibility to getting trapped in local optima. Especially when multiple objectives such as interconnect length, area utilization, and heat distribution need to be optimized simultaneously, traditional methods often struggle to obtain a globally optimal solution within an acceptable time and cannot fully adapt to the high-dimensional, dynamic, and strongly constrained modern core integration design scenarios.

[0005] Therefore, there is an urgent need to introduce a more intelligent, efficient layout method with global optimization capabilities. Summary of the Invention

[0006] This application provides a thermally driven chip layout planning method, apparatus, device, and medium to overcome the shortcomings of the aforementioned related technologies. The technical solution is as follows: In a first aspect, this application provides a thermally driven chip layout planning method, comprising: An initial core layout is generated based on the input core configuration file using a simulated annealing algorithm. Calculate the line length and simulation operating temperature of the initial core layout, and construct a state vector by combining the layout information, line length and simulation operating temperature of the initial core layout; The state vector is input into a pre-constructed deep Q-network, and the core layout corresponding to the state vector is adjusted to obtain a new core layout. The reward function is calculated based on the line length and simulation running temperature of the new core particle layout; Compare the reward function with zero, and determine the target core layout and the type label of the target core layout for the current iteration based on the comparison result; Determine whether the current iteration round has reached the round threshold. If not, construct a state vector based on the current target core layout and proceed to the step of inputting the state vector into the pre-constructed deep Q network for the next iteration round. Continue until the iteration round reaches the round threshold. Optimal core layout is obtained by filtering based on the type label of the target core layout in each iteration round.

[0007] In one alternative embodiment of the first aspect, generating the initial core layout based on the input core configuration file using a simulated annealing algorithm includes: The core configuration file is parsed, and an initial core layout is generated based on the parsed core quantity, core size parameters, core function parameters, and connection relationships between cores. Calculate the cost function for the initial core layout; Initialize the annealing temperature and search step size, and adjust the initial core layout based on the search step size to generate candidate core layouts; Calculate the cost function of the candidate core layout; The cost functions of the candidate core layout and the initial core layout are compared. If the cost function of the candidate core layout is greater than or equal to the cost function of the initial core layout, then proceed to the step of adjusting the initial core layout based on the search step size. Otherwise, update the candidate core layout to the new initial core layout; The annealing temperature is updated based on the preset cooling rate. If the updated annealing temperature is greater than or equal to the temperature threshold, the process proceeds to the step of adjusting the initial core layout based on the search step size. Otherwise, stop the iteration and output the initial core layout.

[0008] In one alternative of the first aspect, the cost function is calculated based on the line length, layout range, and power of the chip layout, and is expressed as follows: ; in, Represents the cost function; Weighted penalty for line length. As area penalty weight, Power penalty weight; The half-perimeter line length of the core particle layout is calculated based on the line length of the core particle layout; The area of ​​the layout range for the core particle; Power penalty for chip layout; The maximum half-circumference line length is determined based on the core configuration file. This is the minimum half-circumference line length determined based on the core configuration file; This represents the maximum area of ​​the layout range determined based on the core configuration file. This represents the minimum area of ​​the layout range determined based on the core configuration file. This is the maximum power penalty determined based on the chip configuration file. This is the minimum power penalty determined based on the chip configuration file.

[0009] In one alternative embodiment of the first aspect, constructing the corresponding state vector by combining the layout information of the initial core layout, the line length, and the simulation running temperature includes: Based on the layout information of the initial core layout, determine the position information of each core, and flatten the position information of each core. The layout mesh corresponding to the initial core layout is converted into a one-dimensional array. The flattened position information, line length, and simulation running temperature are merged with the one-dimensional array to construct the state vector.

[0010] In one alternative embodiment of the first aspect, adjusting the core layout corresponding to the state vector to obtain a new core layout includes: Sampling is performed using the empirical replay pool of the deep Q-network, and the Q-value is calculated based on the sampling results and the state vector. The calculated Q value is compared with the preset Q value for each action type. If the preset Q value for any action type is equal to the calculated Q value, the corresponding action type adjustment action is executed to adjust the core layout corresponding to the state vector, and a new core layout is obtained.

[0011] In one alternative to the first aspect, the reward function calculated based on the new core layout line length and simulation operating temperature is expressed as follows: ; ; ; Where R represents the reward function; Indicates temperature parameter, Indicates the line length parameter; This indicates the simulation operating temperature of the new core particle layout. This represents the maximum simulation operating temperature of the core particle layout across all iteration rounds. This represents the minimum simulation operating temperature of the core particle layout across all iteration rounds; This indicates the line length of the new core layout. This represents the maximum line length of the core particle layout across all iteration rounds. This represents the minimum line length of the core layout across all iterations.

[0012] In one alternative of the first aspect, determining the target core layout and the type label of the target core layout based on the comparison result includes: If the reward function is greater than zero, the new core layout is taken as the target core layout for the current iteration, and the optimal solution label is added to the target core layout. Otherwise, based on the reward function of the new core layout and the exploration rate of the deep Q-network, the acceptance function is calculated using the following formula: ; The generated value falls within the interval A random number is generated within the range, and the value of the random number is compared with that of the acceptance function; If the value of the acceptance function is greater than the random number, the new core layout is taken as the target core layout for the current iteration, and a local solution label is added to the target core layout. Otherwise, proceed to the step of adjusting the core layout corresponding to the state vector.

[0013] Secondly, this application also provides a thermally driven chip layout planning device, comprising: The data configuration unit is used to generate an initial core layout based on the input core configuration file using a simulated annealing algorithm; The data configuration unit is also used to calculate the line length and simulation operating temperature of the initial core layout, and to construct a state vector by combining the layout information, line length and simulation operating temperature of the initial core layout. The core layout planning unit is used to input the state vector into the pre-constructed deep Q network and adjust the core layout corresponding to the state vector to obtain a new core layout. The core layout planning unit is also used to calculate the reward function based on the line length and simulation running temperature of the new core layout; The core layout planning unit is also used to compare the numerical values ​​of the reward function and zero, and to determine the target core layout and the type label of the target core layout for the current iteration based on the comparison results. The core particle layout planning unit is also used to determine whether the current iteration round has reached the round threshold. If it has not reached the threshold, the data configuration unit constructs a state vector based on the current target core particle layout, and the core particle layout planning unit inputs the state vector into the pre-constructed deep Q network to proceed to the next iteration round until the iteration round reaches the round threshold. The core particle layout planning unit is also used to select the optimal core particle layout according to the type label of the target core particle layout in each iteration round.

[0014] Thirdly, this application also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the method provided by the first aspect of this application or any implementation thereof.

[0015] Fourthly, this application also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the method provided by the first aspect of this application or any implementation thereof.

[0016] The beneficial effects of the technical solution provided in this application include at least the following: This application provides a thermal effect-driven core layout planning method. It generates an initial core layout through simulated annealing algorithm, constructs a state vector by combining line length and thermal simulation temperature, and uses a deep Q-network for iterative optimization and reward function evaluation. Finally, when the round threshold is reached, the target core layout is output as the optimal core layout. This method effectively overcomes the shortcomings of traditional core layout planning, such as low optimization efficiency, slow convergence speed, and easy getting trapped in local optima. By replacing the traditional heuristic algorithm with a deep Q-network, the optimization process achieves self-learning and fast convergence, which greatly reduces the runtime overhead.

[0017] Simultaneously, the target chip layout obtained based on this method can simultaneously optimize the interconnect length and thermal distribution of the chip using this target chip layout. This can shorten the critical path, reduce the chip's signal delay, and balance the thermal field, reducing local hotspots, thereby significantly improving the chip's performance, power efficiency, and thermal reliability at the system level. The method provided in this application can adapt to the high-dimensional, dynamic, and strongly constrained modern chip integration design scenarios, providing technical support for efficient and intelligent layout planning. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in this application or related technologies, the drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is one of the flowcharts illustrating a thermally driven chip layout planning method provided in this application embodiment; Figure 2 This is a second schematic flowchart of a thermal effect-driven chip layout planning method provided in an embodiment of this application; Figure 3 This is the third flowchart illustrating a thermal effect-driven chip layout planning method provided in this application embodiment; Figure 4 This is a schematic diagram comparing the effects of a thermally driven chip layout planning method provided in an embodiment of this application; Figure 5 This is a schematic diagram of a thermally driven chip layout planning device provided in an embodiment of this application; Figure 6 This is a schematic diagram of the structure of the electronic device provided in the embodiments of this application. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0021] The terms "comprising" and "having," and any variations thereof, in the specification, claims, and accompanying drawings of this application are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or modules is not limited to the steps or modules listed, but may optionally include steps or modules not listed, or may optionally include other steps or modules inherent to such process, method, product, or apparatus.

[0022] It should be noted that the terms "first" and "second" used in this application are merely to distinguish similar objects and do not represent a specific ordering of the objects. It is understood that "first" and "second" can be interchanged in a specific order or sequence where permitted. It should be understood that the objects distinguished by "first" and "second" can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in an order other than those described or illustrated herein.

[0023] The present application will now be described in detail with reference to specific embodiments.

[0024] Next, combine Figure 1This application introduces a thermally driven chip layout planning method provided by an embodiment of the present application. For details, please refer to... Figure 1 , Figure 1 This illustration shows a flowchart of a thermally driven chip layout planning method provided in an embodiment of this application. Figure 1 As shown, the method includes the following steps: S101 generates an initial core layout based on the input core configuration file using a simulated annealing algorithm.

[0025] Specifically, a chip configuration file can be generated based on the design requirements of the actual system-on-a-chip. The chip configuration file is used to set the number of chips, chip size parameters, chip function parameters, and the connection relationships between chips. Among them, the chip size parameters are specifically the cross-sectional dimensions of the chip, namely the height and width of the chip. The chip function parameters include the chip power and the chip type. The chip type can include a central processing unit (CPU), dynamic random access memory (DRAM), etc.

[0026] In some embodiments, such as Figure 2 The diagram shown illustrates the process of generating the initial core layout. The process of generating the initial core layout specifically includes the following steps: S201, parse the core configuration file, and generate an initial core layout based on the parsed core quantity, core size parameters, core function parameters, and connection relationships between cores. .

[0027] S202, calculate the cost function for the initial core layout.

[0028] Specifically, the cost function is expressed as follows: ; in, Represents the cost function; Weighted penalty for line length. As area penalty weight, Power penalty weight; The half-perimeter line length of the core particle layout is calculated based on the line length of the core particle layout; The area of ​​the layout range for the core particle; Power penalty for chip layout; The maximum half-circumference line length is determined based on the core configuration file. This is the minimum half-circumference line length determined based on the core configuration file; This represents the maximum area of ​​the layout range determined based on the core configuration file. This represents the minimum area of ​​the layout range determined based on the core configuration file. This is the maximum power penalty determined based on the chip configuration file. This is the minimum power penalty determined based on the chip configuration file.

[0029] It should be noted that the maximum value of the half-circumference line length Minimum length of half perimeter line Maximum area of ​​the layout range Minimum area of ​​the layout range Maximum power penalty and minimum power penalty All of these can be determined through the core configuration file.

[0030] It should be noted that the heat generated by a chip during operation is positively correlated with the chip's power. The power penalty value can reflect the degree to which the chip is affected by heat generation when operating at a certain power. The larger the power penalty value, the more susceptible the chip is to temperature effects at a certain power.

[0031] S203, Initial annealing temperature and search step size.

[0032] S204, Adjust the initial core layout based on the search step size. Generate candidate core layout .

[0033] S205, calculate the cost function of the candidate core layout. .

[0034] Specifically, the calculation formula is the same as that for S202, and will not be repeated here.

[0035] S206, compare the cost functions of the candidate core layout and the initial core layout.

[0036] If the cost function of candidate core layout The cost function is greater than or equal to the initial core layout. If the condition is met, proceed to S204 and execute S204 and the subsequent steps.

[0037] If the cost function of candidate core layout Cost function less than the initial core layout Then perform the following steps: S207, the candidate chip layout Updated to the new initial core layout .

[0038] S208, based on a preset cooling rate Update the annealing temperature, applying the formula: ← ; in, This refers to the cooling rate.

[0039] S209, compare the updated annealing temperature and temperature threshold.

[0040] If the updated annealing temperature Greater than or equal to the temperature threshold If the condition is met, proceed to S204 and execute S204 and the subsequent steps.

[0041] If the updated annealing temperature Less than the temperature threshold Then perform the following steps: S210, stop iteration, output initial core layout.

[0042] Further, the steps in S102 include: S102, calculate the line length and simulation operating temperature of the initial core layout, and construct a state vector by combining the layout information, line length and simulation operating temperature of the initial core layout.

[0043] Specifically, the simulation operating temperature can be obtained by simulating the core layout using the open-source HotSpot thermal simulation tool; the optimal wiring solution of the initial core layout can be obtained by modeling and solving the layout information recorded in the initial core layout (which can be understood as the topological relationship between cores) using a mixed integer linear programming solver, thus obtaining the line length of the initial core layout.

[0044] Specifically, the process of constructing the state vector includes: Based on the layout information of the initial core layout, determine the position information of each core, and flatten the position information of each core. The layout mesh corresponding to the initial core layout is converted into a one-dimensional array. The flattened position information, line length, and simulation running temperature are merged with the one-dimensional array to construct the state vector.

[0045] Next, the initial core layout is iterated using a pre-constructed deep Q-network, and the iteration rounds are recorded. The optimal core layout is constructed through subsequent iterative calculations, specifically including: S103, input the state vector into the pre-built deep Q network.

[0046] The input state vector is processed through a pre-built deep Q-network.

[0047] S104, by adjusting the core particle layout corresponding to the state vector through a pre-constructed deep Q-network, a new core particle layout is obtained, specifically including: Sampling is performed using the empirical replay pool of the deep Q-network, and the Q-value is calculated based on the sampling results and the state vector. The calculated Q value is compared with the preset Q value for each action type. If the preset Q value for any action type is equal to the calculated Q value, the corresponding action type adjustment action is executed to adjust the core layout corresponding to the state vector, and a new core layout is obtained.

[0048] Specifically, the types of adjustment actions include translation, flipping, and jumping. Each time, one of the adjustment actions can be selected based on the calculated Q value to adjust the core layout corresponding to the input state vector in S103.

[0049] Next, for the new core particle layout generated in S104, the line length and simulation operating temperature of the new core particle layout can be calculated using the thermal simulator and solver in S102. The reward function is then used to determine whether to accept the new core particle layout generated in S104, including: S105, the reward function is calculated based on the line length and simulation operating temperature of the new core particle layout, expressed by the formula: ; ; ; Where R represents the reward function; Indicates temperature parameter, Indicates the line length parameter; This indicates the simulation operating temperature of the new core particle layout. This represents the maximum simulation operating temperature of the core particle layout across all iteration rounds. This represents the minimum simulation operating temperature of the core particle layout across all iteration rounds; This indicates the line length of the new core layout. This represents the maximum line length of the core particle layout across all iteration rounds. This represents the minimum line length of the core layout across all iterations.

[0050] Next, the value of the reward function can be used to determine whether to accept the new core layout generated by S104.

[0051] S106, compare the value of the reward function with zero.

[0052] S107, Determine the target core layout and the type label of the target core layout for the current iteration based on the comparison results.

[0053] like Figure 3 As shown, Figure 3 This example illustrates the flowchart for determining the target core layout in the current iteration round. Figure 3 The steps S104 and S105 shown are the same as the steps described above, and will not be repeated here. S107 specifically includes the following sub-steps: If the reward function is greater than zero as determined by S106, then S1071 is executed: S1071, the new core layout is used as the current iteration round. The target core layout is determined, and an optimal solution label is added to the target core layout. That is, the new core layout generated by S104 is marked as the current iteration round by the optimal solution label. The optimal solution.

[0054] If S106 determines that the reward function is less than or equal to zero, an acceptance function can be further set to prevent the algorithm from getting stuck in a local optimum loop, thus avoiding the local optimum solution. Then, S1072 is executed, including: S1072, based on the reward function of the new core layout and the exploration rate of the deep Q-network. Calculate the acceptor function using the formula: ; in, Indicates the exploration rate. The function that represents the calculation of exponents.

[0055] S1073, the generated value falls within the interval Random numbers within.

[0056] S1074, compare the value of the random number with the value of the acceptance function.

[0057] If the value of the accept function is greater than the random number, then execute S1075: S1075, the new core layout is used as the current iteration round. The target core layout is determined, and local unlabeling is added to the target core layout.

[0058] Local unlabeling means accepting only the current target core layout, without updating the target core layout to the current iteration. The optimal solution; If the value of the acceptance function is less than or equal to the random number, proceed to S104 and execute S104 and subsequent steps to regenerate the core layout.

[0059] Execute S108 to determine whether the current iteration round has reached the round threshold. .

[0060] If the round threshold is not reached Then execute S109: S109, construct a state vector based on the target core layout of the current iteration round i.

[0061] The process of constructing the state vector is the same as described in step S102 above. Please refer to the relevant description in S102 for details, which will not be repeated here.

[0062] Then, update the ordinal number of the iteration round: Record the iteration rounds ; Proceed to step S103 to proceed to the next iteration round.

[0063] If the number of iterations reaches the iteration threshold Then execute S110: S110: The optimal core layout is obtained by filtering the target core layout type label in each iteration round.

[0064] Specifically, according to the aforementioned steps, in step S106, if the reward function is determined to be greater than zero, an optimal solution label is added to the target core layout. That is, the corresponding core layout is marked as the current iteration using the optimal solution label. The optimal solution.

[0065] If the acceptance function is greater than the random number in S1074, a local solution label is added to the target core layout, indicating that only the new core layout generated by S104 is accepted, but the layout is not taken as the optimal solution.

[0066] Specifically, when selecting the optimal core layout, all target core layouts with local unlabeled labels are first excluded. The ordinal number of the iteration round corresponding to each target core layout with the optimal unlabeled label is determined. The target core layout with the largest iteration round ordinal number and the optimal unlabeled label is selected as the optimal core layout.

[0067] In some embodiments, the model parameters of the deep Q network can be updated according to a preset update frequency. If it is determined in S108 that the current iteration round has not reached the round threshold, it can be determined whether to update the parameters based on the sequence number of the iteration round. For example, the model parameters can be updated once every 5 iterations.

[0068] For example, the initial exploration rate can be set to 1.0, which means that the initial exploration is completely random. The exploration rate is reduced by 10% after each cycle, so as to retain at least 1% of the exploration rate and prevent getting trapped in local optima.

[0069] In addition, the experience replay pool can be updated accordingly with each iteration.

[0070] For example, in each iteration, if the acceptance function is greater than the random number in S1074, the new core layout generated in S104 can be put into the experience replay pool of the deep Q network; if the current iteration does not reach the iteration threshold in S108, the experience replay pool of the deep Q network can be updated. Specifically, the target core layout in S1071 and S1075 can be put into the experience replay pool of the deep Q network.

[0071] This enables real-time updates in the experience replay pool, leveraging the experience replay characteristics of deep Q-networks to achieve self-learning in the optimization process, accelerating the convergence speed of layout iterations, and thus reducing runtime.

[0072] In one specific embodiment, please refer to Figure 4 , Figure 4 An example is shown in the comparison diagram of the effect of the optimal chip layout and the ordinary chip layout generated by the thermal effect driven chip layout planning method provided in the embodiments of this application. The chip layout includes chips CPU0, CPU1, CPU2, CPU3, DRAM0, DRAM1, DRAM2, and DRAM3.

[0073] like Figure 4 As shown, Figure 4 The left side shows a typical chip layout. The thermal distribution of CPU0, CPU1, CPU2, and CPU3 can be observed in this layout. There is obvious heat concentration in the areas where CPU0, CPU1, CPU2, and CPU3 are located. The areas where DRAM0, DRAM1, DRAM2, and DRAM3 are located are also affected by the temperature of the CPU area, indicating that the thermal reliability of this layout is poor. Figure 4 The right side shows the optimal chip layout obtained by this application. It is easy to see that this application only has some hot spots at each CPU unit. There is no heat concentration caused by multiple CPU units clustered together. The heat generated by the CPU operation will not affect the memory unit DRAM. Therefore, the optimal chip layout generated by the thermal effect driven chip layout planning method provided by this application embodiment has higher thermal reliability than the existing layout method.

[0074] The following are apparatus embodiments of this application, which can be used to execute the method embodiments of this application. For details not disclosed in the apparatus embodiments of this application, please refer to the method embodiments of this application.

[0075] Please see below. Figure 5 This is a schematic diagram of a thermally driven chip layout planning device provided as an exemplary embodiment of this application. The device includes: The data configuration unit is used to generate an initial core layout based on the input core configuration file using a simulated annealing algorithm; The data configuration unit is also used to calculate the line length and simulation operating temperature of the initial core layout, and to construct a state vector by combining the layout information, line length and simulation operating temperature of the initial core layout. The core layout planning unit is used to input the state vector into the pre-constructed deep Q network and adjust the core layout corresponding to the state vector to obtain a new core layout. The core layout planning unit is also used to calculate the reward function based on the line length and simulation running temperature of the new core layout; The core layout planning unit is also used to compare the numerical values ​​of the reward function and zero, and to determine the target core layout and the type label of the target core layout for the current iteration based on the comparison results. The core particle layout planning unit is also used to determine whether the current iteration round has reached the round threshold. If it has not reached the threshold, the data configuration unit constructs a state vector based on the current target core particle layout, and the core particle layout planning unit inputs the state vector into the pre-constructed deep Q network to proceed to the next iteration round until the iteration round reaches the round threshold. The core particle layout planning unit is also used to select the optimal core particle layout according to the type label of the target core particle layout in each iteration round.

[0076] It should be noted that the apparatus provided in the above embodiments, when executing a thermally driven chip layout planning method, is only illustrated by the division of the above functional modules. In practical applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above. Furthermore, the apparatus and method embodiments provided in the above embodiments belong to the same concept, and their implementation process is detailed in the method embodiments, which will not be repeated here.

[0077] This application also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the steps of any of the methods described above.

[0078] Please see Figure 6 This is a structural block diagram of an electronic device provided in an embodiment of this application.

[0079] like Figure 6 As shown, the electronic device includes a processor and a memory.

[0080] In this embodiment, the processor is the control center of the computer system, and can be a processor of a physical machine or a processor of a virtual machine. The processor may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor can be implemented using at least one hardware form of DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), or PLA (Programmable Logic Array).

[0081] A processor can also include a main processor and a coprocessor. The main processor is used to process data in the wake-up state and is also called the CPU (Central Processing Unit). The coprocessor is a low-power processor used to process data in the standby state.

[0082] The memory may include one or more computer-readable storage media, which may be non-transitory. The memory may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices or flash memory devices. In some embodiments of this application, the non-transitory computer-readable storage media in the memory are used to store at least one instruction, which is executed by a processor to implement the methods in the embodiments of this application.

[0083] In some embodiments, the electronic device further includes a peripheral device interface and at least one peripheral device. The processor, memory, and peripheral device interface are connected via a bus or signal line. Each peripheral device is connected to the peripheral device interface via a bus, signal line, or circuit board. Specifically, the peripheral device includes: a display screen, a camera, and audio circuitry. The peripheral device interface can be used to connect at least one I / O (Input / Output) related peripheral device to the processor and memory.

[0084] In some embodiments of this application, the processor, memory, and peripheral device interfaces are integrated on the same chip or circuit board; in other embodiments of this application, any one or two of the processor, memory, and peripheral device interfaces can be implemented on separate chips or circuit boards. This application does not specifically limit the implementation in this regard.

[0085] The electronic device structural block diagrams shown in the embodiments of this application do not constitute a limitation on the electronic device. The electronic device may include more or fewer components than shown, or combine certain components, or use different component arrangements.

[0086] This application also provides a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the steps of the methods in any of the foregoing embodiments. The computer-readable storage medium may include, but is not limited to, any type of disk, including floppy disks, optical disks, DVDs, CD-ROMs, microdrives, as well as magneto-optical disks, ROMs, RAMs, EPROMs, EEPROMs, DRAMs, VRAMs, flash memory devices, magnetic cards or optical cards, nanosystems (including molecular memory ICs), or any type of medium or device suitable for storing instructions and / or data.

[0087] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the parts that contribute to the related technology, can be embodied in the form of software products. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0088] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A thermally driven chip layout planning method, characterized in that, include: An initial core layout is generated based on the input core configuration file using a simulated annealing algorithm. Calculate the line length and simulation operating temperature of the initial core layout, and construct a state vector by combining the layout information, line length and simulation operating temperature of the initial core layout; The state vector is input into a pre-constructed deep Q-network, and the core layout corresponding to the state vector is adjusted to obtain a new core layout. The reward function is calculated based on the line length and simulation running temperature of the new core particle layout; Compare the reward function with zero, and determine the target core layout and the type label of the target core layout for the current iteration based on the comparison result; Determine whether the current iteration round has reached the round threshold. If not, construct a state vector based on the current target core layout and proceed to the step of inputting the state vector into the pre-constructed deep Q network for the next iteration round. Continue until the iteration round reaches the round threshold. Optimal core layout is obtained by filtering based on the type label of the target core layout in each iteration round.

2. The thermally driven chip layout planning method according to claim 1, characterized in that, The process of generating an initial core layout based on the input core configuration file using a simulated annealing algorithm includes: The core configuration file is parsed, and an initial core layout is generated based on the parsed core quantity, core size parameters, core function parameters, and connection relationships between cores. Calculate the cost function for the initial core layout; Initialize the annealing temperature and search step size, and adjust the initial core layout based on the search step size to generate candidate core layouts; Calculate the cost function of the candidate core layout; The cost functions of the candidate core layout and the initial core layout are compared. If the cost function of the candidate core layout is greater than or equal to the cost function of the initial core layout, then proceed to the step of adjusting the initial core layout based on the search step size. Otherwise, update the candidate core layout to the new initial core layout; The annealing temperature is updated based on the preset cooling rate. If the updated annealing temperature is greater than or equal to the temperature threshold, the process proceeds to the step of adjusting the initial core layout based on the search step size. Otherwise, stop the iteration and output the initial core layout.

3. The thermally driven chip layout planning method according to claim 2, characterized in that, The cost function is calculated based on the line length, layout range, and power of the core layout, and is expressed by the following formula: ； in, Represents the cost function; Weighted penalty for line length. As area penalty weight, Power penalty weight; The half-perimeter line length of the core particle layout is calculated based on the line length of the core particle layout; The area of ​​the layout range for the core particle; Power penalty for chip layout; The maximum half-circumference line length is determined based on the core configuration file. This is the minimum half-circumference line length determined based on the core configuration file; This represents the maximum area of ​​the layout range determined based on the core configuration file. This represents the minimum area of ​​the layout range determined based on the core configuration file. This is the maximum power penalty determined based on the chip configuration file. This is the minimum power penalty determined based on the chip configuration file.

4. The thermally driven chip layout planning method according to claim 1, characterized in that, The construction of the corresponding state vector by combining the layout information of the initial core particle layout, line length, and simulation running temperature includes: Based on the layout information of the initial core layout, determine the position information of each core, and flatten the position information of each core. The layout mesh corresponding to the initial core layout is converted into a one-dimensional array. The flattened position information, line length, and simulation running temperature are merged with the one-dimensional array to construct the state vector.

5. The thermally driven chip layout planning method according to claim 1, characterized in that, The adjustment of the core layout corresponding to the state vector to obtain a new core layout includes: Sampling is performed using the empirical replay pool of the deep Q-network, and the Q-value is calculated based on the sampling results and the state vector. The calculated Q value is compared with the preset Q value for each action type. If the preset Q value for any action type is equal to the calculated Q value, the corresponding action type adjustment action is executed to adjust the core layout corresponding to the state vector, and a new core layout is obtained.

6. A thermally driven chip layout planning method according to claim 1 or 5, characterized in that, The reward function calculated based on the new core layout line length and simulation operating temperature is expressed as follows: ； ； ； Where R represents the reward function; Indicates temperature parameter, Indicates the line length parameter; This indicates the simulation operating temperature of the new core particle layout. This represents the maximum simulation operating temperature of the core particle layout across all iteration rounds. This represents the minimum simulation operating temperature of the core particle layout across all iteration rounds; This indicates the line length of the new core layout. This represents the maximum line length of the core particle layout across all iteration rounds. This represents the minimum line length of the core layout across all iterations.

7. The thermally driven chip layout planning method according to claim 6, characterized in that, The step of determining the target core layout and the type label of the target core layout for the current iteration based on the comparison results includes: If the reward function is greater than zero, the new core layout is taken as the target core layout for the current iteration, and the optimal solution label is added to the target core layout. Otherwise, based on the reward function of the new core layout and the exploration rate of the deep Q-network, the acceptance function is calculated using the following formula: ； The generated value falls within the interval A random number is generated within the range, and the value of the random number is compared with that of the acceptance function; If the value of the acceptance function is greater than the random number, then the new core layout is taken as the target core layout for the current iteration, and a local solution label is added to the target core layout. Otherwise, proceed to the step of adjusting the core layout corresponding to the state vector.

8. A thermally driven chip layout planning device, characterized in that, include: The data configuration unit is used to generate an initial core layout based on the input core configuration file using a simulated annealing algorithm; The data configuration unit is also used to calculate the line length and simulation operating temperature of the initial core layout, and to construct a state vector by combining the layout information, line length and simulation operating temperature of the initial core layout. The core layout planning unit is used to input the state vector into the pre-constructed deep Q network and adjust the core layout corresponding to the state vector to obtain a new core layout. The core layout planning unit is also used to calculate the reward function based on the line length and simulation running temperature of the new core layout; The core layout planning unit is also used to compare the numerical values ​​of the reward function and zero, and to determine the target core layout and the type label of the target core layout for the current iteration based on the comparison results. The core particle layout planning unit is also used to determine whether the current iteration round has reached the round threshold. If it has not reached the threshold, the data configuration unit constructs a state vector based on the current target core particle layout, and the core particle layout planning unit inputs the state vector into the pre-constructed deep Q network to proceed to the next iteration round until the iteration round reaches the round threshold. The core particle layout planning unit is also used to select the optimal core particle layout according to the type label of the target core particle layout in each iteration round.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the program, it implements the steps of the method as described in any one of claims 1 to 7.

10. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method as described in any one of claims 1 to 7.

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