A mapping optimization method for a quantum circuit and a related device

Abstract

This invention discloses a mapping optimization method and related apparatus for quantum circuits, belonging to the field of quantum computing technology. The method includes: acquiring multiple quantum circuits containing different numbers of logical bits; calling a search algorithm according to the different number of logical bits contained in each quantum circuit to find the target qubit block that maps the logical bits of the quantum circuit to the physical bits of the quantum processor according to a certain number of hops, and storing the target qubit block in memory; performing the mapping operation from the logical bits of the quantum circuit to the physical bits of the quantum processor based on the target mapping region of the target qubit block of the quantum processor. This application first finds the target qubit block by calling a graph search algorithm, and then performs the mapping operation on the local mapping region of the target qubit block, aiming to improve the mapping efficiency and mapping quality of qubits in quantum circuits, thereby improving the overall computing efficiency of quantum computing.

Description

Technical Field

[0001] This invention belongs to the field of quantum computing technology, specifically a mapping optimization method and related apparatus for quantum circuits. Background Technology

[0002] Quantum computing, as an emerging field of computing, uses quantum circuits as a representation, which describe the execution sequence of a series of quantum operations (such as quantum gates) on a series of qubits. A quantum processor is the hardware device that actually executes these quantum circuits. Before a quantum processor executes a quantum circuit, the logical bits in the quantum circuit need to be mapped to the physical bits of the quantum processor. Traditional mapping operations are generally performed within the global physical bit region of the quantum processor. The larger mapping range increases the spatial complexity and difficulty of the mapping operation, resulting in lower efficiency and lower quality of the mapping results.

[0003] Therefore, the urgent technical problem to be solved is to propose a new quantum circuit mapping optimization method, which aims to improve the mapping efficiency and mapping quality of qubits in quantum circuits, thereby improving the overall computational efficiency of quantum computing. Summary of the Invention

[0004] The purpose of this invention is to provide a mapping optimization method and related apparatus for quantum circuits, which aims to improve the mapping efficiency and mapping quality of quantum bits in quantum circuits, thereby improving the overall computational efficiency of quantum computing.

[0005] One embodiment of the present invention provides a mapping optimization method for quantum circuits, the method comprising:

[0006] Obtain multiple quantum circuits containing different numbers of logical bits;

[0007] Based on the different number of logical bits contained in each quantum circuit, a search algorithm is invoked to find the target qubit block that maps the logical bits of the quantum circuit to the physical bits of the quantum processor according to a certain number of hops, and the target qubit block is stored in memory;

[0008] The mapping operation from the logical bits of the quantum circuit to the physical bits of the quantum processor is performed based on the target mapping region of the target qubit block of the quantum processor.

[0009] Optionally, the step of calling a search algorithm to find the target qubit block that maps the logical bits of the quantum circuit to the physical bits of the quantum processor according to a certain number of hops, based on the different number of logical bits contained in each quantum circuit, includes:

[0010] The search algorithm is invoked based on the number of logical bits in each quantum circuit. The search algorithm sets a starting point for the quantum bit search, sequentially traverses the physical bits of the quantum processor according to a certain number of hops, and determines the target quantum bit block that maps the logical bits of the quantum circuit to the physical bits of the quantum processor according to the weight configuration of the search path of the physical bits of the quantum processor and the fidelity of the physical bits.

[0011] Optionally, determining the target qubit block from the logical bits of the quantum circuit to the physical bits of the quantum processor based on the weighted configuration of the search path of the physical bits of the quantum processor and the fidelity of the physical bits includes:

[0012] Based on the search path of the physical bits of the quantum processor and the fidelity of the physical bits, the weight values ​​of one or more qubit blocks are obtained.

[0013] The one or more qubit blocks found are sorted according to their weight values ​​to obtain the target qubit block; the target qubit block is the qubit block with the highest weight value.

[0014] Optionally, the method further includes:

[0015] The obtained target qubit block is stored in memory, and it is determined whether the topology of the physical bits of the quantum processor and the performance parameters of the physical bits have changed.

[0016] Since the topology of the physical bits of the quantum processor and the performance parameters of the physical bits remain unchanged, when a quantum circuit to be mapped is received, if the number of logical bits of the quantum circuit to be mapped is equal to the number of logical bits corresponding to the target quantum bit block, the target quantum bit block is directly called from memory to perform the mapping operation.

[0017] Optionally, the hop count is determined based on the number of logical bits in the quantum circuit and the number of physical bits in the quantum processor.

[0018] Optionally, the search algorithm is a graph search algorithm.

[0019] Optionally, the method further includes:

[0020] In response to changes in the topology of the physical bits of the quantum processor and the performance parameters of the physical bits, all the target qubit blocks that have been saved are cleared from memory. When the quantum circuit to be mapped is received, the target qubit blocks are searched again based on the physical bits of the quantum processor and stored in memory to perform the mapping operation.

[0021] Another embodiment of the present invention provides a mapping optimization device for quantum circuits, the device comprising:

[0022] Acquisition unit, used to acquire multiple quantum circuits containing different numbers of logical bits;

[0023] The determining unit is used to call a search algorithm according to the different number of logical bits contained in each quantum circuit to find the target quantum bit block that maps the logical bits of the quantum circuit to the physical bits of the quantum processor according to a certain number of hops, and to store the target quantum bit block in memory;

[0024] An execution unit is configured to perform a mapping operation from the logical bits of the quantum circuit to the physical bits of the quantum processor based on the target mapping region of the target qubit block of the quantum processor.

[0025] Another embodiment of the present invention provides an electronic device, wherein the computer-readable storage medium stores a computer program, the computer program including program instructions, which, when executed by a processor, perform the methods described in any of the above embodiments.

[0026] Another embodiment of the present invention provides a computer-readable storage medium storing a computer program, the computer program including program instructions that, when executed by a processor, perform the methods described in any of the above embodiments.

[0027] Another embodiment of the present invention provides a quantum computer operating system, which implements quantum circuit mapping optimization according to the method described in any of the above embodiments.

[0028] Compared with the prior art, the present invention first obtains multiple quantum circuits containing different numbers of logical bits; then, according to the different number of logical bits contained in each quantum circuit, a search algorithm is called to find the target qubit block that maps the logical bits of the quantum circuit to the physical bits of the quantum processor according to a certain number of hops, and the target qubit block is stored in memory; finally, the mapping operation from the logical bits of the quantum circuit to the physical bits of the quantum processor is performed based on the target mapping region of the target qubit block of the quantum processor.

[0029] This invention first acquires multiple quantum circuits containing different numbers of logical bits. Acquiring these multiple quantum circuits provides the operational basis and prerequisites for all subsequent operations. Then, based on the different numbers of logical bits contained in each quantum circuit, a search algorithm is invoked to find the target qubit block that maps the logical bits of the quantum circuit to the physical bits of the quantum processor according to a certain number of hops, and the target qubit block is stored in memory. Based on the number of logical bits contained in each quantum circuit, the search algorithm is invoked to find the optimal target qubit block suitable for each quantum circuit. Searching according to a certain number of hops reduces the search space, improves search efficiency, and speeds up the mapping process. Storing the target qubit block in memory facilitates subsequent computational resource management and scheduling, allowing for quick access and use of this information, ensuring effective resource utilization, reducing redundant calculations, and improving overall computational efficiency. Finally, based on the target mapping region of the target qubit block in the quantum processor, the mapping operation from the logical bits of the quantum circuit to the physical bits of the quantum processor is performed. By performing the mapping operation within the target mapping region of the found target qubit block, the mapping space is reduced, ensuring more reliable execution of the quantum circuit on the quantum processor, reducing the error rate, and improving computational accuracy. Attached Figure Description

[0030] Figure 1 This is a network block diagram of a quantum circuit mapping optimization system provided in an embodiment of the present invention.

[0031] Figure 2 This is a flowchart of a quantum circuit mapping optimization method provided in an embodiment of the present invention.

[0032] Figure 3 A flowchart illustrating a method for determining a target qubit block, as provided in an embodiment of the present invention.

[0033] Figure 4 A flowchart illustrating a target qubit block resource management method provided in an embodiment of the present invention.

[0034] Figure 5 This is a structural diagram of a quantum circuit mapping optimization device provided in an embodiment of the present invention.

[0035] Figure 6 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention. Detailed Implementation

[0036] The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0037] Figure 1This is a network block diagram of a quantum circuit mapping optimization system provided in an embodiment of the present invention. The quantum circuit mapping optimization system may include a network 110, a server 120, a wireless device 130, a client 140, storage 150, a classical computing unit 160, a quantum computing unit 170, and may also include additional memory, a classical processor, a quantum processor, and other devices (not shown).

[0038] Network 110 is a medium used to provide communication links between various devices and computers connected together within a quantum circuit mapping optimization system, including but not limited to the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof, and the connection method can be wired, wireless communication links, or fiber optic cables.

[0039] Server 120, wireless device 130, and client 140 are conventional data processing systems that may contain data and application programs or software tools that perform conventional computational processes. Client 140 may be a personal computer or a network computer, so the data may also be provided by server 120. Wireless device 130 may be a smartphone, tablet, laptop, smart wearable device, etc. Storage unit 150 may include database 151, which can be configured to store data such as qubit parameters, quantum logic gate parameters, quantum circuits, and quantum programs.

[0040] The classical computing unit 160 (quantum computing unit 170) may include a classical processor 161 (quantum processor 171) for processing classical data (quantum data) and a memory 162 (memory 172) for storing classical data (quantum data). The classical data (quantum data) may be a boot file, an operating system image, and an application program 163 (application program 173). The application program 163 (application program 173) may be used to implement a quantum algorithm compiled by the quantum circuit mapping optimization method provided in the embodiments of the present invention.

[0041] Any data or information stored or generated in the classical computing unit 160 (quantum computing unit 170) can also be configured to be stored or generated in another classical (quantum) processing system in a similar manner, and any application executed therein can also be configured to be executed in another classical (quantum) processing system in a similar manner.

[0042] It should be noted that a true quantum computer has a hybrid structure, which includes at least... Figure 1 The system consists of two main parts: the classical computing unit 160, which is responsible for performing classical calculations and control; and the quantum computing unit 170, which is responsible for running quantum programs to achieve quantum computing.

[0043] The aforementioned classical computing unit 160 and quantum computing unit 170 can be integrated into a single device or distributed across two different devices. For example, a first device including the classical computing unit 160 runs a classical computer operating system, providing quantum application development tools and services, as well as the storage and network services required for quantum applications. Users develop quantum programs using the quantum application development tools and services on the second device, and send these quantum programs to a second device including the quantum computing unit 170 via the network services. The second device runs a quantum computer operating system, which parses and compiles the quantum program's code into instructions that the quantum processor 170 can recognize and execute. The quantum processor 170 then implements the quantum algorithm corresponding to the quantum program based on these instructions.

[0044] The computing units of the classic processor 161 within the classic computing unit 160 are based on CMOS transistors on a silicon chip. These computing units are not limited by time or coherence; that is, they are available at any time without time constraints. Furthermore, the number of such computing units in a silicon chip is sufficient; currently, a single classic processor 161 contains tens of thousands of computing units. Given this sufficient number and the fixed selectable computing logic of the CMOS transistors (e.g., AND logic), computational performance is achieved by combining a large number of CMOS transistors with a limited set of logic functions during operation.

[0045] In the quantum computing unit 170, the basic computing unit of the quantum processor 171 is the qubit. The input of a qubit is limited by coherence and coherence time; that is, a qubit is limited by its available usage time and is not always readily available. Making full use of qubits within their available usage time is a key challenge in quantum computing. Furthermore, the number of qubits in a quantum computer is one of the representative indicators of its performance. Each qubit performs computational functions through on-demand configured logical functions. Given the limited number of qubits and the diverse logical functions available in quantum computing, such as Hadamard gates (H gates), Pauli-X gates (X gates), Pauli-Y gates (Y gates), Pauli-Z gates (Z gates), X gates, RY gates, RZ gates, CNOT gates, CR gates, iSWAP gates, Tofoli gates, etc., quantum computing requires combining a limited number of qubits with diverse logical function combinations to achieve computational effects.

[0046] Based on these differences, the design of classical logic functions applied to CMOS transistors and the design of quantum logic functions applied to qubits are significantly and fundamentally different. The design of classical logic functions applied to CMOS transistors does not need to consider the individuality of CMOS transistors. For example, the representation of a CMOS transistor in a silicon chip is its individual identifier, location, and usable time of each CMOS transistor. Therefore, classical algorithms composed of classical logic functions only express the operational relationship of the algorithm, not the algorithm's dependence on individual CMOS transistors.

[0047] Quantum logic functions applied to qubits need to consider the individuality of each qubit, such as its position within the quantum chip, its relationship with surrounding qubits, and the duration of its usable time. Therefore, quantum algorithms composed of quantum logic functions not only express the computational relationships within the algorithm but also its dependence on the individual qubits.

[0048] A quantum chip can include qubits and channels for controlling them. Quantum logic gates are implemented using analog signals. Different combinations of analog signals are applied to the qubits through these channels, thereby creating quantum circuits with different functions to process data. Therefore, the design of quantum logic functions in the qubits (including the design of whether qubits are used and the design of the efficiency of each qubit) is crucial for improving the computational performance of quantum computers and requires special design. This is the unique characteristic of quantum algorithms based on quantum logic functions, and it is fundamentally and significantly different from classical algorithms based on classical logic functions. The aforementioned design considerations for qubits are technical problems that ordinary computing devices do not need to consider or address.

[0049] Quantum computing, as an emerging field of computing, uses quantum circuits as a representation, which describe the execution sequence of a series of quantum operations (such as quantum gates) on a series of qubits. A quantum processor is the hardware device that actually executes these quantum circuits. Before a quantum processor executes a quantum circuit, the logical bits in the quantum circuit need to be mapped to the physical bits of the quantum processor. Traditional mapping operations are generally performed within the global physical bit region of the quantum processor. The larger mapping range increases the spatial complexity and difficulty of the mapping operation, resulting in lower efficiency and lower quality of the mapping results.

[0050] Therefore, the urgent technical problem to be solved is to propose a new quantum circuit mapping optimization method, which aims to improve the mapping efficiency and mapping quality of qubits in quantum circuits, thereby improving the overall computational efficiency of quantum computing.

[0051] See Figure 2 , Figure 2A quantum circuit mapping optimization method provided in this embodiment of the invention includes the following steps:

[0052] Step S201: Obtain multiple quantum circuits containing different numbers of logical bits.

[0053] Specifically, this is achieved by first acquiring multiple quantum circuits containing different numbers of logical bits.

[0054] Step S202: Based on the different number of logical bits contained in each quantum circuit, call the search algorithm to find the target quantum bit block that maps the logical bits of the quantum circuit to the physical bits of the quantum processor according to a certain number of hops, and store the target quantum bit block in memory.

[0055] The target qubit block consists of physical bits of the target mapping region to perform the mapping operation.

[0056] Specifically, based on the different number of logical bits contained in each quantum circuit, a search algorithm is invoked to sequentially search the physical bit region of the quantum processor to find the logical bits of the quantum circuit that are mapped to the physical bits of the quantum processor to obtain the target quantum bit block, and then the target quantum bit block is stored in memory.

[0057] For example, suppose there is a quantum computer whose quantum processor consists of 100 physical bits. Now there is a quantum program containing three different quantum circuits, which need to be mapped onto the physical bits of the quantum processor to perform mapping operations. The number of logical bits in these three quantum circuits are 4, 8 and 6 respectively. First, for the first quantum circuit containing 4 logical bits, a search algorithm is called. The search algorithm searches for a consecutive 4 physical bits as the target qubit block in the 100 physical bits of the quantum processor according to a certain number of hops. Suppose the target qubit block found is physical bit 10 to physical bit 13. Then the target information is stored in memory. Subsequently, the logical bits of quantum circuit 1 will perform mapping operations on physical bits 10 to physical bit 13.

[0058] Step S203: Perform a mapping operation from the logical bits of the quantum circuit to the physical bits of the quantum processor based on the target mapping region of the target qubit block of the quantum processor.

[0059] Specifically, based on the target mapping region of the target quantum block of the quantum processor found in step S202 above, the mapping operation from the logical bits of the quantum circuit to the physical bits of the quantum processor is performed.

[0060] In summary, this invention first acquires multiple quantum circuits containing different numbers of logical bits; this step provides the operational basis and prerequisites for all subsequent operations. Then, based on the different numbers of logical bits contained in each quantum circuit, a search algorithm is invoked to find the target qubit block that maps the logical bits of the quantum circuit to the physical bits of the quantum processor according to a certain number of hops, and the target qubit block is stored in memory. Based on the number of logical bits contained in each quantum circuit, the search algorithm is invoked to find the optimal target qubit block suitable for each quantum circuit. Searching according to a certain number of hops reduces the search space, improves search efficiency, and speeds up the mapping process. By storing the target qubit block in memory, this information can be quickly accessed and used, facilitating subsequent computational resource management and scheduling, ensuring effective resource utilization, reducing redundant calculations, and improving overall computational efficiency. Finally, based on the target mapping region of the target qubit block in the quantum processor, the mapping operation from the logical bits of the quantum circuit to the physical bits of the quantum processor is performed. By performing the mapping operation within the target mapping region of the found target qubit block, the mapping space is reduced, ensuring more reliable execution of the quantum circuit on the quantum processor, reducing the error rate, and improving computational accuracy.

[0061] In one embodiment of this application, the step of calling a search algorithm according to a certain number of hops to find the target qubit block that maps the logical bits of the quantum circuit to the physical bits of the quantum processor includes:

[0062] The search algorithm is invoked based on the number of logical bits in each quantum circuit. The search algorithm sets a starting point for the quantum bit search, sequentially traverses the physical bits of the quantum processor according to a certain number of hops, and determines the target quantum bit block that maps the logical bits of the quantum circuit to the physical bits of the quantum processor according to the weight configuration of the search path of the physical bits of the quantum processor and the fidelity of the physical bits.

[0063] Among them, the search path of a physical bit refers to the depth of the search path of a physical bit in a quantum processor, such as minimizing the number of insertion SWAP gates and minimizing the communication distance or interference between physical bits; the fidelity of a quantum bit refers to the degree of similarity between the actual state and the ideal state of a quantum bit after quantum operations or time evolution.

[0064] Specifically, a search algorithm is invoked based on the number of logical bits in each quantum circuit. The search algorithm starts by setting a quantum bit as the search starting point and sequentially traverses the physical bits of the quantum processor according to a certain number of hops. Then, based on the combined weight information of the search path of the physical bits of the quantum processor and the fidelity of the physical bits, the target quantum bit block that maps the logical bits of the quantum circuit to the physical bits of the quantum processor is obtained.

[0065] For example, suppose a quantum computing task involves three different quantum circuits, each requiring 4, 6, and 8 logical bits respectively. These logical bits need to be physically implemented on a quantum processor, and these physical bits differ in physical layout and performance. For each quantum circuit, a search algorithm is first invoked based on the number of logical bits. The search algorithm starts from a predefined physical bit (e.g., physical bit 0) on the quantum processor as the starting point. By setting a reasonable number of hops, such as performing 3 hops between physical bits each time, it iterates sequentially to find all suitable blocks of qubits. During the traversal, the algorithm... The algorithm calculates the search path depth for each potential physical bit block, including the number of SWAP gates to be inserted and factors such as minimizing communication distance or interference between physical bits. For each found physical bit block, the algorithm also considers its fidelity information (some physical bits have low fidelity due to manufacturing defects or environmental factors). Based on the combined weight information of search path and fidelity, the algorithm selects the best (or near-best) target qubit block that maps the logical bits of each quantum circuit to the physical bits of the quantum processor. For example, for a quantum circuit with 4 logical bits, the algorithm may select physical bits 5 to 8 as the target qubit block.

[0066] It is important to emphasize that, assuming the quantum processor has 72 qubits and a quantum circuit has 8 logical bits, when searching for qubits in the quantum processor, the hop count is set to 9. The search begins with physical bit 0 as the starting point within the search range. If the target qubit block is not found within the search range, the search starts again with physical bit 1 as the starting point. If the target qubit block is still not found, the search continues with physical bit 2 as the starting point, and so on, until the target qubit block is found. Assuming the target qubit block is found on physical bit 3, the search continues with hop counts at intervals. That is, the search for the next qubit block starts from 3 + 9 = 12, i.e., physical bit 12 as the starting point within the search range. Then, the search continues with physical bits 21, 30, 39, 48... as the starting points within the search range until the last physical bit is reached.

[0067] In summary, the search algorithm is invoked based on the number of logical bits in each quantum circuit. Therefore, for quantum circuits of different sizes, this method can automatically adjust the search strategy to adapt to different logical bit requirements. It sequentially traverses the physical bits of the quantum processor according to a certain number of hops, efficiently searching for suitable qubit blocks in the physical bit space. This ordered search method avoids blind attempts, thereby improving search efficiency and reducing the waste of computational resources. By considering the weighted configuration of the search path and fidelity of the physical bits in the quantum processor, and comprehensively considering the performance differences of the physical bits, it selects qubit blocks that both meet the logical bit mapping requirements and have good fidelity, which helps to improve the execution efficiency and accuracy of quantum circuits.

[0068] See Figure 3 , Figure 3 A flowchart of a method for determining a target qubit block provided in an embodiment of the present invention, the method comprising:

[0069] Step S301: Based on the search path of the physical bits of the quantum processor and the fidelity of the physical bits, obtain the weight values ​​of one or more qubit blocks.

[0070] Specifically, based on the combined weight information of the search path of the physical bits and the fidelity of the physical bits in the quantum processor, the weight values ​​of one or more qubit blocks can be calculated.

[0071] Step S302: Sort the found one or more qubit blocks according to their weight values ​​to obtain the target qubit block; the target qubit block is the qubit block with the highest weight value.

[0072] Specifically, the weight values ​​of one or more qubit blocks obtained from the calculation are sorted according to their weight values ​​from highest to lowest, and the optimal qubit block with the highest weight value is selected as the target qubit block.

[0073] For example, suppose there is a quantum processor whose physical bits are arranged in a two-dimensional grid structure, each physical bit having a specific fidelity value, and a quantum circuit containing a certain number of logical bits. By calculating the weight value of each qubit block, which is a comprehensive index that takes into account both fidelity and the depth of the search path or the communication overhead of the quantum circuit, suppose there are two qubit blocks A and B, where A has higher physical bit fidelity but a longer path, while B has slightly lower physical bit fidelity but a shorter search path and a tighter connection. Based on the comprehensive weight information, the weight value of B is calculated to be higher than that of A, so qubit block B is selected as the target qubit block.

[0074] In summary, by comprehensively considering the search path and fidelity of the physical bits of the quantum processor, a more refined decision-making basis is provided for determining the target qubit block. This comprehensive consideration helps to select physical bit blocks that have both shorter communication paths (or fewer SWAP gate insertions) and good fidelity, thereby optimizing the execution efficiency and accuracy of quantum circuits.

[0075] See Figure 4 , Figure 4 A flowchart of a target qubit block resource management method provided in an embodiment of the present invention includes:

[0076] Step S401: Store the obtained target qubit block in memory and determine whether the topology of the physical bits of the quantum processor and the performance parameters of the physical bits have changed.

[0077] Specifically, the target qubit block is stored in memory, and then it is further determined whether the topology of the physical bits of the quantum processor and the performance parameters of the physical bits have changed.

[0078] For example, suppose there is a quantum computing system containing a quantum processor and quantum computing software. The quantum processor has multiple physical bits arranged in a certain topology, and each physical bit has its specific performance parameters, such as fidelity and coherence time. Before the quantum computing task begins, a target block of qubits is found by some method (possibly based on a search algorithm or heuristic method). The information of the target block of qubits is stored in memory for quick access during task execution. At the same time, a monitoring mechanism is set up to continuously detect whether the topology and performance parameters of the physical bits of the quantum processor have changed. Such changes may be caused by hardware failure, environmental factors (such as temperature fluctuations), or natural degradation of the quantum processor. The connection status of the physical bits is checked in real time by reading the hardware registers of the quantum processor to determine whether their arrangement has changed.

[0079] In step S402, in response to the fact that the topology of the physical bits of the quantum processor and the performance parameters of the physical bits do not change, when receiving the quantum circuit to be mapped, if the number of logical bits of the quantum circuit to be mapped is equal to the number of logical bits corresponding to the target quantum bit block, the target quantum bit block is directly called from memory to perform the mapping operation.

[0080] Specifically, if the monitoring mechanism in step S401 determines that the topology of the physical bits of the quantum processor and the performance parameters of the physical bits have not changed within a period of time, when the quantum circuit to be mapped is received again, if the number of logical bits of the quantum circuit to be mapped is equal to the number of logical bits corresponding to the target quantum block that has been saved, the target quantum bit block is directly called from memory to perform subsequent mapping operations.

[0081] For example, suppose a quantum computing system includes a quantum processor and quantum computing software. In the previous step S401, a set of target qubit blocks has been found and their information has been stored in memory. At the same time, a monitoring mechanism is set up to continuously detect whether the topology and performance parameters of the physical bits of the quantum processor have changed. After the monitoring mechanism has been running for a period of time, no significant changes have been found in the topology and performance parameters of the physical bits of the quantum processor. This means that the state of the quantum processor is stable and the previously found target qubit blocks are still valid. In this stable state of the quantum processor, a quantum circuit to be mapped is received. The number of logical bits of this quantum circuit to be mapped is checked and found to be exactly equal to the number of logical bits corresponding to the previously stored target qubit blocks. This means that this quantum circuit to be mapped can be directly mapped to the target qubit blocks without any adjustment or optimization. Since the information of the target qubit blocks has been stored in memory, they can be directly called from memory to perform the mapping operation. The whole process is very fast because it avoids the need to search for or optimize the qubit blocks again.

[0082] In summary, by pre-searching and storing target qubit blocks suitable for different numbers of logical bits, when a quantum circuit is received, the corresponding target qubit block can be directly called from memory for mapping, avoiding a real-time and complex search process, thus significantly improving mapping efficiency. By continuously monitoring the physical bit state of the quantum processor and directly calling the target qubit block for mapping when the state is stable, the stability of the system is enhanced. This helps reduce mapping errors caused by hardware failures, environmental factors, or natural degradation, thereby improving the reliability of quantum computing. Stable system state monitoring helps reduce the overall cost of quantum computing and reduces the additional computation time and resource consumption caused by mapping errors or resource waste.

[0083] In one embodiment of this application, the hop count is determined based on the number of logical bits of the quantum circuit and the number of physical bits of the quantum processor.

[0084] The hop count refers to the step size of the time interval for searching qubits on a quantum processor.

[0085] Specifically, the hop count is calculated by combining the number of logical bits in the quantum circuit with the number of physical bits in the quantum processor.

[0086] For example, if the current quantum processor has 72 physical bits and the quantum circuit has 8 logical bits, then the hop count is calculated to be 9 bits.

[0087] In one embodiment of this application, the search algorithm is a graph search algorithm.

[0088] In one embodiment of this application, the method further includes:

[0089] In response to changes in the topology of the physical bits of the quantum processor and the performance parameters of the physical bits, all the target qubit blocks that have been saved are cleared from memory. When the quantum circuit to be mapped is received, the target qubit blocks are searched again based on the physical bits of the quantum processor and stored in memory to perform the mapping operation.

[0090] Specifically, if the topology of the physical bits of the quantum processor and the performance parameters of the physical bits change within a period of time, all the target qubit block information that has been saved in memory is cleared. When the quantum circuit to be mapped is received again, the target qubit block needs to be searched again from the physical bits of the quantum processor and stored in memory to perform subsequent mapping operations.

[0091] In summary, by introducing a response mechanism to changes in the physical bit state of the quantum processor, the system's adaptability is significantly enhanced. When the physical bit topology or performance parameters of the quantum processor change, the system can automatically adjust the mapping strategy to ensure the effectiveness and accuracy of the mapping operation and reduce mapping errors caused by changes in the physical bit state.

[0092] See Figure 5 , Figure 5 A quantum circuit mapping optimization device is provided in an embodiment of the present invention. The device includes an acquisition unit 501, a determination unit 502, and an execution unit 503.

[0093] Acquisition unit 501 is used to acquire multiple quantum circuits containing different numbers of logical bits.

[0094] The determining unit 502 is used to call a search algorithm according to the different number of logical bits contained in each quantum circuit to find the target quantum bit block that maps the logical bits of the quantum circuit to the physical bits of the quantum processor according to a certain number of hops, and to store the target quantum bit block in memory.

[0095] Specifically, the step of calling a search algorithm according to the different number of logical bits contained in each quantum circuit to find the target qubit block that maps the logical bits of the quantum circuit to the physical bits of the quantum processor according to a certain number of hops includes:

[0096] The search algorithm is invoked based on the number of logical bits in each quantum circuit. The search algorithm sets a starting point for the quantum bit search, sequentially traverses the physical bits of the quantum processor according to a certain number of hops, and determines the target quantum bit block that maps the logical bits of the quantum circuit to the physical bits of the quantum processor according to the weight configuration of the search path of the physical bits of the quantum processor and the fidelity of the physical bits.

[0097] Specifically, determining the target qubit block from the logical bits of the quantum circuit to the physical bits of the quantum processor, based on the weighted configuration of the search path of the physical bits of the quantum processor and the fidelity of the physical bits, includes:

[0098] Obtain the weight values ​​of one or more qubit blocks. Based on the search path of the physical bits of the quantum processor and the fidelity of the physical bits,

[0099] The one or more qubit blocks found are sorted according to their weight values ​​to obtain the target qubit block; the target qubit block is the qubit block with the highest weight value.

[0100] Specifically, the method further includes:

[0101] The obtained target qubit block is stored in memory, and it is determined whether the topology of the physical bits of the quantum processor and the performance parameters of the physical bits have changed.

[0102] Since the topology of the physical bits of the quantum processor and the performance parameters of the physical bits remain unchanged, when a quantum circuit to be mapped is received, if the number of logical bits of the quantum circuit to be mapped is equal to the number of logical bits corresponding to the target quantum bit block, the target quantum bit block is directly called from memory to perform the mapping operation.

[0103] Specifically, the hop count is determined based on the number of logical bits in the quantum circuit and the number of physical bits in the quantum processor.

[0104] Specifically, the search algorithm is a graph search algorithm.

[0105] Specifically, the method further includes:

[0106] In response to changes in the topology of the physical bits of the quantum processor and the performance parameters of the physical bits, all the target qubit blocks that have been saved are cleared from memory. When the quantum circuit to be mapped is received, the target qubit blocks are searched again based on the physical bits of the quantum processor and stored in memory to perform the mapping operation.

[0107] The execution unit 503 is used to perform a mapping operation from the logical bits of the quantum circuit to the physical bits of the quantum processor based on the target mapping region of the target qubit block of the quantum processor.

[0108] The specific functions and effects of the quantum circuit mapping optimization device described above can be explained by referring to other embodiments in this specification, and will not be repeated here. Each module in the quantum circuit mapping optimization device can be implemented entirely or partially through software, hardware, or a combination thereof. Each module can be embedded in or independent of the processor in a computer device in hardware form, or it can be stored in the memory of a computer device in software form, so that the processor can call and execute the operations corresponding to each module.

[0109] Please see Figure 6 This specification also provides an electronic device, including a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the quantum circuit mapping optimization method in any of the above embodiments. Please refer to [link to documentation]. Figure 6 The electronic device can be a classical computer or a quantum computer.

[0110] This specification also provides a computer-readable storage medium storing a computer program thereon, which, when executed by a computer, causes the computer to perform the quantum circuit mapping optimization method in any of the above embodiments.

[0111] This invention also provides a quantum computer operating system, which implements quantum circuit mapping optimization according to any of the above-described method embodiments provided in this invention.

[0112] It is understood that the specific examples in this specification are only intended to help those skilled in the art better understand the implementation methods described herein, and are not intended to limit the scope of the invention.

[0113] It is understood that in the various embodiments of this specification, the sequence number of each process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not limit the implementation process of the embodiments of this specification in any way.

[0114] It is understood that the various implementation methods described in this specification can be implemented individually or in combination, and the implementation methods in this specification are not limited in this respect.

[0115] Unless otherwise stated, all technical and scientific terms used in the embodiments of this specification have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the scope of this specification. The term "and / or" as used in this specification includes any and all combinations of one or more of the associated listed items. The singular forms "a," "the," and "the" as used in the embodiments of this specification and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0116] It is understood that the processor in the embodiments of this specification can be an integrated circuit chip with signal processing capabilities. In implementation, each step of the above method embodiments can be completed by integrated logic circuits in the processor's hardware or by instructions in software form. The processor can be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this specification. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this specification can be directly implemented by a hardware decoding processor, or by a combination of hardware and software modules in the decoding processor. The software modules can reside in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory; the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above methods.

[0117] It is understood that the memory in the embodiments of this specification may be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. Non-volatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory may be random access memory (RAM). It should be noted that the memory in the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0118] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this specification.

[0119] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the aforementioned method implementations, and will not be repeated here.

[0120] In the several embodiments provided in this specification, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0121] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment, depending on actual needs.

[0122] In addition, the functional units in the various embodiments of this specification can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0123] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solutions of this specification, in essence, or the parts that contribute to the prior art, or parts of the technical solutions, can be embodied in the form of software products. These computer software products are stored in a storage medium and include several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this specification. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0124] The above description is merely a specific embodiment of this specification, but the scope of protection of this invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this specification should be included within the scope of protection of this specification. Therefore, the scope of protection of this invention should be determined by the scope of the claims.

Claims

1. A mapping optimization method for quantum circuits, characterized in that, The method includes: Obtain multiple quantum circuits containing different numbers of logical bits; Based on the different number of logical bits contained in each quantum circuit, a search algorithm is invoked to find the target qubit block that maps the logical bits of the quantum circuit to the physical bits of the quantum processor according to a certain number of hops, and the target qubit block is stored in memory; The mapping operation from the logical bits of the quantum circuit to the physical bits of the quantum processor is performed based on the target mapping region of the target qubit block of the quantum processor.

2. The method according to claim 1, characterized in that, The step of calling a search algorithm according to the different number of logical bits contained in each quantum circuit to find the target qubit block that maps the logical bits of the quantum circuit to the physical bits of the quantum processor according to a certain number of hops includes: The search algorithm is invoked based on the number of logical bits in each quantum circuit. The search algorithm sets a starting point for the quantum bit search, sequentially traverses the physical bits of the quantum processor according to a certain number of hops, and determines the target quantum bit block that maps the logical bits of the quantum circuit to the physical bits of the quantum processor according to the weight configuration of the search path of the physical bits of the quantum processor and the fidelity of the physical bits.

3. The method according to claim 2, characterized in that, The step of determining the target qubit block from the logical bits of the quantum circuit to the physical bits of the quantum processor, based on the weighted configuration of the search path of the physical bits of the quantum processor and the fidelity of the physical bits, includes: Based on the search path of the physical bits of the quantum processor and the fidelity of the physical bits, the weight values ​​of one or more qubit blocks are obtained. The one or more qubit blocks found are sorted according to their weight values ​​to obtain the target qubit block; the target qubit block is the qubit block with the highest weight value.

4. The method according to claim 1, characterized in that, The method further includes: The obtained target qubit block is stored in memory, and it is determined whether the topology of the physical bits of the quantum processor and the performance parameters of the physical bits have changed. Since the topology of the physical bits of the quantum processor and the performance parameters of the physical bits remain unchanged, when a quantum circuit to be mapped is received, if the number of logical bits of the quantum circuit to be mapped is equal to the number of logical bits corresponding to the target quantum bit block, the target quantum bit block is directly called from memory to perform the mapping operation.

5. The method according to claim 1 or 2, characterized in that, The hop count is determined based on the number of logical bits in the quantum circuit and the number of physical bits in the quantum processor.

6. The method according to claim 1, characterized in that, The search algorithm is a graph search algorithm.

7. The method according to claim 4, characterized in that, The method further includes: In response to changes in the topology of the physical bits of the quantum processor and the performance parameters of the physical bits, all the target qubit blocks that have been saved are cleared from memory. When the quantum circuit to be mapped is received, the target qubit blocks are searched again based on the physical bits of the quantum processor and stored in memory to perform the mapping operation.

8. A mapping optimization device for quantum circuits, characterized in that, The device includes: Acquisition unit, used to acquire multiple quantum circuits containing different numbers of logical bits; The determining unit is used to call a search algorithm according to the different number of logical bits contained in each quantum circuit to find the target quantum bit block that maps the logical bits of the quantum circuit to the physical bits of the quantum processor according to a certain number of hops, and to store the target quantum bit block in memory; An execution unit is configured to perform a mapping operation from the logical bits of the quantum circuit to the physical bits of the quantum processor based on the target mapping region of the target qubit block of the quantum processor.

9. An electronic device, characterized in that, include: Processor and memory; The processor is connected to a memory, wherein the memory is used to store a computer program, and the processor is used to invoke the computer program to execute the method as described in claims 1-7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, the computer program including program instructions that, when executed by a processor, perform the method as described in claims 1-7.

11. A quantum computer operating system, characterized in that, The quantum computer operating system implements quantum circuit mapping optimization according to any one of claims 1-7.

Images