A method for checking quantum bit mapping and related apparatus

Abstract

This invention discloses a method and related apparatus for verifying qubit mapping, comprising: determining the initial mapping, the mapping line, and the final mapping of the qubit mapping algorithm based on the original quantum circuit; traversing the mapping line based on the initial mapping to obtain the traversed mapping result and the bit gate sequence of the mapping line; determining whether the traversed mapping result is equal to the final mapping obtained by the qubit mapping algorithm, and whether the bit gate sequence of the mapping line is equal to the bit gate sequence obtained by traversing the original quantum circuit; and verifying the mapping of the qubits of the original quantum circuit based on the judgment results. This application, based on the initial mapping and mapping line obtained by the qubit mapping algorithm, verifies the mapping from two perspectives: the mapping relationship and the bit gate sequence obtained by traversing the mapping line, aiming to improve the mapping quality of qubits and the reliability and accuracy of the mapping process.

Description

Technical Field

[0001] This invention belongs to the field of quantum computing technology, specifically a method and related apparatus for verifying qubit mapping. Background Technology

[0002] In the field of quantum computing, quantum circuit mapping is an important step. By mapping logical bits to physical bits, it is possible to adapt to the topology of actual quantum processors. With the development of quantum computing technology, new quantum bit mapping algorithms are constantly emerging. These algorithms may have advantages in theory, but in practical applications, mapping deviations may occur in different mapping scenarios.

[0003] Therefore, the urgent technical problem to be solved is to propose a new mapping and verification method for qubits, which aims to improve the mapping quality of qubits and the reliability and accuracy of the mapping process. Summary of the Invention

[0004] The purpose of this invention is to provide a method and related apparatus for verifying quantum bit mapping, aiming to improve the mapping quality of quantum bits and the reliability and accuracy of the mapping process.

[0005] One embodiment of the present invention provides a method for verifying a quantum bit mapping, the method comprising:

[0006] The algorithm for determining the qubit mapping is based on the initial mapping, the mapping circuit, and the final mapping of the original quantum circuit;

[0007] Based on the initial mapping, the mapping line is traversed to obtain the traversed mapping result and the bit gate sequence of the mapping line;

[0008] Determine whether the mapping result after traversal is equal to the final mapping obtained by the quantum bit mapping algorithm, and whether the bit gate sequence of the mapping circuit is equal to the bit gate sequence obtained by traversing the original quantum circuit.

[0009] The mapping verification of the qubits of the original quantum circuit is achieved based on the judgment result.

[0010] Optionally, the algorithm for determining the qubit mapping is based on the initial mapping of the original quantum circuit, the mapped circuit, and the final mapping, and includes:

[0011] The output parameters of the qubit mapping algorithm are determined based on the original quantum circuit and the topology of the quantum chip; wherein, the output parameters include the initial mapping, the mapping circuit, and the final mapping.

[0012] Optionally, the step of traversing the mapping line based on the initial mapping to obtain the traversed mapping result and the bit gate sequence of the mapping line includes:

[0013] The initialization algorithm for the qubit mapping is based on the initial mapping of the original quantum circuit and the current mapping relationship is recorded. The mapping circuit is traversed based on the initial mapping to obtain the mapping result after traversal and the bit gate sequence of the mapping circuit. The mapping relationship after traversal and the bit gate sequence of the mapping circuit during the traversal are recorded.

[0014] Optionally, traversing the mapped line based on the initial mapping includes:

[0015] Based on the initial mapping, the mapping line is traversed. If the physical bits of the quantum processor are available and the quantum bit double gates are adjacent during the traversal, the step is to further determine whether the current quantum bit double gate is a SWAP gate.

[0016] In response to the fact that the current qubit dual gate is a SWAP gate, the mapping relationship of the qubits is transformed and the qubit gate sequence is swapped.

[0017] Optionally, the method further includes:

[0018] If the current qubit dual gate is not a SWAP gate, then the qubit gate sequence is appended and the steps continue to traverse the mapping circuit.

[0019] Optionally, the qubit mapping algorithm includes the OLSQ2 mapping algorithm or the OBMT mapping algorithm.

[0020] Optionally, determining whether the mapping result after traversal is equal to the final mapping obtained by the qubit mapping algorithm, and whether the bit gate sequence of the mapped circuit is equal to the bit gate sequence obtained by traversing the original quantum circuit, includes:

[0021] Based on the final mapping obtained by the quantum bit mapping algorithm as a reference execution result, determine whether the mapping result after the mapping line traversal is equal to the final mapping obtained by the quantum bit mapping algorithm;

[0022] And determine whether the bit gate sequence completed by the mapping circuit is equal to the bit gate sequence completed by the original quantum circuit; wherein, the bit gate sequence includes the number of qubit gates, the order of qubit gates, and the type of qubit gates.

[0023] Another embodiment of the present invention provides a verification device for a quantum bit mapping, the device comprising:

[0024] The determining unit is used to determine the initial mapping and mapping circuit of the qubit mapping algorithm based on the original quantum circuit;

[0025] The traversal unit is used to traverse the mapping line based on the initial mapping to obtain the traversed mapping result and the bit gate sequence of the mapping line;

[0026] The judgment unit is used to judge whether the mapping result after traversal is equal to the final mapping obtained by the quantum bit mapping algorithm, and whether the bit gate sequence of the mapping line is equal to the bit gate sequence obtained by traversing the original quantum line.

[0027] A verification unit is used to perform mapping verification of the qubits of the original quantum circuit based on the judgment result.

[0028] Another embodiment of the present invention provides an electronic device, wherein the computer-readable storage medium stores a computer program, the computer program including program instructions, which, when executed by a processor, perform the methods described in any of the above embodiments.

[0029] Another embodiment of the present invention provides a computer-readable storage medium storing a computer program, the computer program including program instructions that, when executed by a processor, perform the methods described in any of the above embodiments.

[0030] Another embodiment of the present invention provides a quantum computer operating system, which implements the mapping and verification of qubits according to the method described in any of the above embodiments.

[0031] Compared with existing technologies, this invention first determines the initial mapping, the mapped circuit, and the final mapping of the qubit mapping algorithm based on the original quantum circuit; secondly, it traverses the mapped circuit based on the initial mapping to obtain the traversed mapping result and the bit gate sequence of the mapped circuit; then, it determines whether the traversed mapping result is equal to the final mapping obtained by the qubit mapping algorithm, and whether the bit gate sequence of the mapped circuit is equal to the bit gate sequence obtained by traversing the original quantum circuit; finally, it verifies the mapping of the qubits of the original quantum circuit based on the judgment results.

[0032] In this invention, firstly, the initial mapping, mapping circuit, and final mapping of the qubit mapping algorithm based on the original quantum circuit are determined. Obtaining the initial mapping and mapping circuit provides the premise and foundation for subsequent verification operations. Secondly, the mapping circuit is traversed based on the initial mapping to obtain the traversed mapping result and the bit gate sequence of the mapping circuit. By traversing the mapping circuit, the traversed mapping result and the bit gate sequence of the mapping circuit can be obtained, providing data support for the subsequent comparison and verification process. Then, the traversed mapping result and the final mapping are compared with the original quantum circuit. The final mapping obtained by the bit mapping algorithm, and whether the bit gate sequence of the mapped circuit is equal to the bit gate sequence obtained by traversing the original quantum circuit, ensures the accuracy and reliability of the quantum mapping algorithm when performing the mapping operation. Finally, based on the judgment result, the mapping verification of the qubits of the original quantum circuit is realized. Through the judgment result, errors in the mapping process of the qubit mapping algorithm can be detected and corrected in a timely manner to improve the fault tolerance of quantum computing. As an important part of the qubit mapping algorithm's mapping operation, mapping verification can continuously optimize and improve the performance of the qubit mapping algorithm and enhance its practical application value in the field of quantum computing. Attached Figure Description

[0033] Figure 1 This is a network block diagram of a verification system for qubit mapping provided in an embodiment of the present invention.

[0034] Figure 2 A flowchart illustrating a verification method for quantum bit mapping provided in an embodiment of the present invention.

[0035] Figure 3 This is a schematic diagram of a primitive quantum circuit provided in an embodiment of the present invention.

[0036] Figure 4 This is a schematic diagram of a quantum chip topology provided in an embodiment of the present invention.

[0037] Figure 5 This is a schematic diagram of a mapping circuit provided in an embodiment of the present invention.

[0038] Figure 6 This is a flowchart of a mapping line traversal method provided in an embodiment of the present invention.

[0039] Figure 7 A detailed flowchart of a quantum bit mapping verification method provided in an embodiment of the present invention.

[0040] Figure 8 This is a schematic diagram of a mapping relationship and bit gate sequence verification provided in an embodiment of the present invention.

[0041] Figure 9 This is a structural diagram of a verification device for quantum bit mapping provided in an embodiment of the present invention.

[0042] Figure 10 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention. Detailed Implementation

[0043] The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0044] Figure 1 This is a network block diagram of a qubit mapping verification system provided in an embodiment of the present invention. The qubit mapping verification system may include a network 110, a server 120, a wireless device 130, a client 140, a storage 150, a classical computing unit 160, a quantum computing unit 170, and may also include additional memory, a classical processor, a quantum processor, and other devices not shown.

[0045] Network 110 is a medium used to provide communication links between various devices and computers connected together within a verification system for quantum bit mapping, including but not limited to the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof. The connection method can be wired, wireless communication links, or fiber optic cables.

[0046] Server 120, wireless device 130, and client 140 are conventional data processing systems that may contain data and application programs or software tools that perform conventional computational processes. Client 140 may be a personal computer or a network computer, so the data may also be provided by server 120. Wireless device 130 may be a smartphone, tablet, laptop, smart wearable device, etc. Storage unit 150 may include database 151, which can be configured to store data such as qubit parameters, quantum logic gate parameters, quantum circuits, and quantum programs.

[0047] The classical computing unit 160 (quantum computing unit 170) may include a classical processor 161 (quantum processor 171) for processing classical data (quantum data) and a memory 162 (memory 172) for storing classical data (quantum data). The classical data (quantum data) may be a boot file, an operating system image, and an application program 163 (application program 173). The application program 163 (application program 173) may be used to implement a quantum algorithm compiled according to a quantum bit mapping verification method provided in an embodiment of the present invention.

[0048] Any data or information stored or generated in the classical computing unit 160 (quantum computing unit 170) can also be configured to be stored or generated in another classical (quantum) processing system in a similar manner, and any application executed therein can also be configured to be executed in another classical (quantum) processing system in a similar manner.

[0049] It should be noted that a true quantum computer has a hybrid structure, which includes at least... Figure 1 The system consists of two main parts: the classical computing unit 160, which is responsible for performing classical calculations and control; and the quantum computing unit 170, which is responsible for running quantum programs to achieve quantum computing.

[0050] The aforementioned classical computing unit 160 and quantum computing unit 170 can be integrated into a single device or distributed across two different devices. For example, a first device including the classical computing unit 160 runs a classical computer operating system, providing quantum application development tools and services, as well as the storage and network services required for quantum applications. Users develop quantum programs using the quantum application development tools and services on the second device, and send these quantum programs to a second device including the quantum computing unit 170 via the network services. The second device runs a quantum computer operating system, which parses and compiles the quantum program's code into instructions that the quantum processor 170 can recognize and execute. The quantum processor 170 then implements the quantum algorithm corresponding to the quantum program based on these instructions.

[0051] The computing units of the classic processor 161 within the classic computing unit 160 are based on CMOS transistors on a silicon chip. These computing units are not limited by time or coherence; that is, they are available at any time without time constraints. Furthermore, the number of such computing units in a silicon chip is sufficient; currently, a single classic processor 161 contains tens of thousands of computing units. Given this sufficient number and the fixed selectable computing logic of the CMOS transistors (e.g., AND logic), computational performance is achieved by combining a large number of CMOS transistors with a limited set of logic functions during operation.

[0052] In the quantum computing unit 170, the basic computing unit of the quantum processor 171 is the qubit. The input of a qubit is limited by coherence and coherence time; that is, a qubit is limited by its available usage time and is not always readily available. Making full use of qubits within their available usage time is a key challenge in quantum computing. Furthermore, the number of qubits in a quantum computer is one of the representative indicators of its performance. Each qubit performs computational functions through on-demand configured logical functions. Given the limited number of qubits and the diverse logical functions available in quantum computing, such as Hadamard gates (H gates), Pauli-X gates (X gates), Pauli-Y gates (Y gates), Pauli-Z gates (Z gates), X gates, RY gates, RZ gates, CNOT gates, CR gates, iSWAP gates, Tofoli gates, etc., quantum computing requires combining a limited number of qubits with diverse logical function combinations to achieve computational effects.

[0053] Based on these differences, the design of classical logic functions applied to CMOS transistors and the design of quantum logic functions applied to qubits are significantly and fundamentally different. The design of classical logic functions applied to CMOS transistors does not need to consider the individuality of CMOS transistors. For example, the representation of a CMOS transistor in a silicon chip is its individual identifier, location, and usable time of each CMOS transistor. Therefore, classical algorithms composed of classical logic functions only express the operational relationship of the algorithm, not the algorithm's dependence on individual CMOS transistors.

[0054] Quantum logic functions applied to qubits need to consider the individuality of each qubit, such as its position within the quantum chip, its relationship with surrounding qubits, and the duration of its usable time. Therefore, quantum algorithms composed of quantum logic functions not only express the computational relationships within the algorithm but also its dependence on the individual qubits.

[0055] A quantum chip can include qubits and channels for controlling them. Quantum logic gates are implemented using analog signals. Different combinations of analog signals are applied to the qubits through these channels, thereby creating quantum circuits with different functions to process data. Therefore, the design of quantum logic functions in the qubits (including the design of whether qubits are used and the design of the efficiency of each qubit) is crucial for improving the computational performance of quantum computers and requires special design. This is the unique characteristic of quantum algorithms based on quantum logic functions, and it is fundamentally and significantly different from classical algorithms based on classical logic functions. The aforementioned design considerations for qubits are technical problems that ordinary computing devices do not need to consider or address.

[0056] In the field of quantum computing, the mapping operation of quantum circuits is an important step. By mapping logical bits to physical bits, the topology of actual quantum processors can be adapted. With the development of quantum computing technology, new mapping algorithms are constantly emerging. These algorithms may have advantages in theory, but in practical applications, mapping deviations may occur in different mapping scenarios.

[0057] Therefore, the urgent technical problem to be solved is to propose a new mapping and verification method for qubits, which aims to improve the mapping quality of qubits and the reliability and accuracy of the mapping process.

[0058] See Figure 2 , Figure 2 A method for verifying a quantum bit mapping provided in this embodiment of the invention includes the following steps:

[0059] Step S201: Determine the initial mapping, mapping circuit, and final mapping of the qubit mapping algorithm based on the original quantum circuit.

[0060] The initial mapping is a mapping relationship between the logical bits of the original quantum circuit and the physical bits of the quantum processor, which is set based on the mapping operation required by the original quantum circuit. The mapped circuit is a circuit structure that conforms to the topology of the quantum processor and is used to implement the quantum algorithm, which is obtained by performing the mapping operation on the original quantum circuit. The final mapping is the actual mapping relationship that conforms to the topology of the quantum processor, which is obtained based on the logical bits of the original quantum circuit and the physical bits of the quantum processor.

[0061] Specifically, the initial mapping, mapped circuit, and final mapping of the original quantum circuit are obtained according to the quantum bit mapping algorithm.

[0062] Step S202: Traverse the mapping line based on the initial mapping to obtain the traversed mapping result and the bit gate sequence of the mapping line.

[0063] The mapping result refers to the final mapping relationship obtained by traversing the mapping line based on the initial mapping relationship; the bit gate sequence refers to the topological structure of the qubit gate corresponding to the qubit during the traversal process.

[0064] Specifically, the mapping lines are traversed based on the initial mapping to obtain the traversed mapping relationship and the bit gate sequence of the mapping lines.

[0065] For example, suppose a mapping line Q1 based on the initial mapping is obtained through a qubit mapping algorithm. If the initial mapping is {0:1,1:0,2:2,3:4}, the mapping line Q1 is traversed based on the initial mapping relationship to obtain the mapping result {0:1,1:0,2:4,3:2} and the corresponding bit gate sequence obtained by traversing the mapping line is {0:"U3|U3|CZ|CZ|CZ|U3|",1:"U3|CZ|CZ|CZ|U3|",2:"CZ|CZ|U3|",4:"U3|CZ|CZ|U3|"}.

[0066] Step S203: Determine whether the mapping result after traversal is equal to the final mapping obtained by the quantum bit mapping algorithm, and whether the bit gate sequence of the mapping circuit is equal to the bit gate sequence obtained by traversing the original quantum circuit.

[0067] Specifically, we need to determine whether the mapping result obtained after traversing the mapping circuit is equal to the final mapping obtained by the quantum bit mapping algorithm, and whether the bit gate sequence obtained after traversing the mapping circuit is equal to the bit gate sequence obtained after traversing the original quantum circuit.

[0068] For example, suppose a mapping line Q1 based on the initial mapping is obtained through a qubit mapping algorithm. If the initial mapping is {0:1,1:0,2:2,3:4}, the final mapping obtained through the qubit mapping algorithm is {0:1,1:0,2:4,3:2}, and the mapping result obtained by traversing the mapping line Q1 based on the initial mapping is {0:1,1:0,2:4,3:2}. The bit gate sequence obtained by traversing the mapping line Q1 is {0:"U3|U3|CZ|CZ|CZ|U3|",1:"U3|CZ|CZ|CZ|U3|",2:"CZ|CZ|U3|",4:"U3|CZ|CZ|U3|"}.

[0069] Then, the original quantum circuit is traversed in the same way. Assuming the traversed bit gate sequence is {0:"U3|CZ|CZ|CZ|U3|",1:"U3|U3|CZ|CZ|CZ|U3|",2:"U3|CZ|CZ|U3|",3:"CZ|CZ|U3|"}, then it is determined whether the final mapping obtained by the quantum bit mapping algorithm is equal to the mapping result obtained after traversing the mapping circuit, and whether the bit gate sequence obtained after traversing the mapping circuit is equal to the bit gate sequence obtained after traversing the original quantum circuit.

[0070] Step S204: Based on the judgment result, the mapping verification of the qubits of the original quantum circuit is realized.

[0071] Specifically, the accuracy of the quantum bit mapping algorithm's mapping execution is verified based on the judgment result of step S203 above.

[0072] In summary, this invention first determines the initial mapping, the mapped circuit, and the final mapping of the qubit mapping algorithm based on the original quantum circuit. Obtaining the initial mapping and the mapped circuit provides the premise and foundation for subsequent verification operations. Secondly, the mapped circuit is traversed based on the initial mapping to obtain the traversed mapping result and the bit gate sequence of the mapped circuit. Traversing the mapped circuit provides data support for the subsequent comparison and verification process, providing a reference execution result. Then, the traversed mapping result is compared with the final mapping. The final mapping obtained by the qubit mapping algorithm, and whether the bit gate sequence of the mapped circuit is equal to the bit gate sequence obtained by traversing the original quantum circuit, ensures the accuracy and reliability of the quantum mapping algorithm when performing the mapping operation. Finally, based on the judgment result, the mapping verification of the qubits of the original quantum circuit is realized. Through the judgment result, errors in the qubit mapping algorithm during the mapping process can be detected and corrected in a timely manner, thereby improving the fault tolerance of quantum computing. As an important part of the qubit mapping algorithm's mapping operation, mapping verification can continuously optimize and improve the performance of the qubit mapping algorithm, and enhance its practical application value in the field of quantum computing.

[0073] In one embodiment of the present invention, the algorithm for determining the qubit mapping is based on the initial mapping of the original quantum circuit, the mapped circuit, and the final mapping, and includes:

[0074] The output parameters of the qubit mapping algorithm are determined based on the original quantum circuit and the topology of the quantum chip; wherein, the output parameters include the initial mapping, the mapping circuit, and the final mapping.

[0075] Specifically, the topology of the original quantum circuit and the quantum chip of the quantum processor is used as input variables to the quantum bit mapping algorithm to obtain the output variables of the quantum bit mapping algorithm, where the output variables include the initial mapping, the mapping circuit and the final mapping.

[0076] For example, see Figure 3 , Figure 3 This is a schematic diagram of a primitive quantum circuit provided in an embodiment of the present invention. It is assumed that in this embodiment, a mapping operation is performed based on the OLSQ2 qubit mapping algorithm, mapping the primitive quantum circuit and the topology of the quantum chip (see...). Figure 4As shown, the input variables are fed into the OLSQ2 qubit mapping algorithm to obtain the output variables. The output variables include the initial mapping, the mapping line, and the final mapping. Assuming the initial mapping is {0:1, 1:0, 2:2, 3:4} and the final mapping is {0:1, 1:0, 2:4, 3:2}, the obtained mapping line can be found in [reference needed]. Figure 5 As shown, Figure 5 This is a schematic diagram of a mapping circuit provided in an embodiment of the present invention.

[0077] In summary, by explicitly defining the output variables, including the initial mapping, the mapping path, and the final mapping, the verification process becomes more standardized and explicit. Directly comparing these parameters during the verification process allows for detailed recording of each step of the mapping algorithm, facilitating subsequent debugging and optimization.

[0078] In one embodiment of the present invention, the step of traversing the mapped line based on the initial mapping to obtain the traversed mapping result and the bit gate sequence of the mapped line includes:

[0079] The initialization algorithm for the qubit mapping is based on the initial mapping of the original quantum circuit and the current mapping relationship is recorded. The mapping circuit is traversed based on the initial mapping to obtain the mapping result after traversal and the bit gate sequence of the mapping circuit. The mapping relationship after traversal and the bit gate sequence of the mapping circuit during the traversal are recorded.

[0080] Specifically, the initial mapping of the qubit mapping algorithm based on the original quantum circuit is initialized, and the current initial mapping relationship is recorded. Based on the initial mapping, the mapping circuit is traversed until the last qubit gate of the mapping circuit is traversed, and the mapping result after traversal and the bit gate sequence of the mapping circuit are obtained. The mapping relationship after traversal and the bit gate sequence of the mapping circuit during the traversal are recorded.

[0081] For example, taking the OLSQ2 qubit mapping algorithm, assume the initial mapping is set to {0:1,1:0,2:2,3:4} and the current mapping relationship is recorded. Based on the initial mapping, the mapping line is traversed until the last qubit gate of the mapping line is traversed. The traversed mapping result is {0:1,1:0,2:4,3:2} and the bit gate sequence of the mapping line is {0:"U3|U3|CZ|CZ|CZ|U3|",1:"U3|CZ|CZ|CZ|U3|",2:"CZ|CZ|U3|",4:"U3|CZ|CZ|U3|"}. The traversed mapping relationship and the bit gate sequence of the mapping line are recorded.

[0082] See Figure 6 , Figure 6A flowchart of a mapping line traversal method provided in an embodiment of the present invention includes:

[0083] Step S601: Based on the initial mapping, the mapping line is traversed. If the physical bits of the quantum processor are available and the quantum bit double gates are adjacent during the traversal, then the step is executed to further determine whether the current quantum bit double gate is a SWAP gate.

[0084] Specifically, if the mapping line is traversed according to the initial mapping and it is determined during the traversal that the physical bits of the quantum processor are available and the quantum bit gates are adjacent, then the next step is to determine whether the current quantum bit gate is a SWAP gate.

[0085] In step S602, in response to the fact that the current qubit dual gate is a SWAP gate, the mapping relationship of the qubits is changed and the qubit gate sequence is swapped.

[0086] Specifically, if the current qubit dual gate is a SWAP gate, then the mapping relationship of the qubits is changed and the qubit gate sequence corresponding to the qubits is swapped.

[0087] For example, see Figure 7 , Figure 7 This is a flowchart illustrating a quantum bit mapping verification method provided in an embodiment of the present invention, based on the mapping circuit. Figure 7 The process shown is iterated. After the first U3 is traversed, the bit gate sequence is {0:"U3|"}. After the second U3 is traversed, the bit gate sequence is {0:"U3",1:"U3"}, ..., until the fourth U3 is traversed, the bit gate sequence is {0:"U3|U3|",1:"U3|",2:"U3|"}. Until the first SWAP gate is encountered, the bit gate sequence is: {0:"U3|U3|CZ|CZ|",1:"U3|CZ|CZ|",2:"U3|CZ|CZ|"}, and so on until the SWAP gate is traversed. When encountering two swapped bits q[2] and q[4], the gate sequences on q[2] and q[4] are swapped to obtain the latest bit gate sequence as {0:"U3|U3|CZ|CZ|",1:"U3|CZ|CZ|",2:"",4:"U3|CZ|CZ|"} (the values ​​of q[2] and q[4] are swapped. During the swap, q[4] does not exist but is regarded as existing and its value is empty). At the same time, the mapping relationship from logical bits to physical bits changes from {0:1,1:0,2:2,3:4} to {0:1,1:0,2:4,3:2}.

[0088] In summary, by checking the availability of physical bits and the adjacency of qubit double gates during the traversal process, the accuracy of the traversal is improved, the processing of the SWAP gate is optimized, the reliability of the verification is enhanced, and the transparency of the algorithm is increased. This makes the verification method for qubit mapping more robust and efficient, and better adapted to practical quantum computing environments.

[0089] In one embodiment of the present invention, the method further includes:

[0090] If the current qubit dual gate is not a SWAP gate, then the qubit gate sequence is appended and the steps continue to traverse the mapping circuit.

[0091] Specifically, if the current qubit gate is not a SWAP gate, then a qubit gate sequence is added and the process of traversing the mapping circuit continues.

[0092] For example, applying to mapped lines Figure 7 The process is traversed as shown. After the first U3 is traversed, the bit gate sequence is {0:"U3|"}. Since no SWAP gate is encountered, the qubit gate sequence is further appended and the process continues to traverse the mapping circuit. After the second U3 is traversed, the sequence is {0:"U3",1:"U3"},.... After the fourth U3 is traversed, the bit sequence is {0:"U3|U3|",1:"U3|",2:"U3|"}. The process continues to append bit gate sequences until the first SWAP gate is encountered.

[0093] In summary, by improving the above traversal process, the accuracy and reliability of the verification process are enhanced, and the versatility and adaptability of the method are increased, making the verification method for qubit mapping more complete and efficient.

[0094] In one embodiment of the present invention, the qubit mapping algorithm includes the OLSQ2 mapping algorithm or the OBMT mapping algorithm.

[0095] In one embodiment of the present invention, determining whether the mapping result after traversal is equal to the final mapping obtained by the qubit mapping algorithm, and whether the bit gate sequence of the mapped circuit is equal to the bit gate sequence obtained by traversing the original quantum circuit, includes:

[0096] Based on the final mapping obtained by the aforementioned qubit mapping algorithm as a reference execution result, it is determined whether the mapping result after the mapping line traversal is completed is equal to the final mapping obtained by the aforementioned qubit mapping algorithm.

[0097] Specifically, based on the final mapping obtained by the qubit mapping algorithm as a reference execution result, it is determined whether the mapping result after the mapping line traversal is equal to the final mapping obtained by the qubit mapping algorithm.

[0098] For example, suppose the initial mapping of the qubit mapping algorithm is {0:1,1:0,2:2,3:4}, the final mapping obtained based on the initial mapping is {0:1,1:0,2:4,3:2}, and the mapping result after traversing the mapping line based on the initial mapping is {0:1,1:0,2:4,3:2}. By judgment, the two are consistent.

[0099] And determine whether the bit gate sequence completed by the mapping circuit is equal to the bit gate sequence completed by the original quantum circuit; wherein, the bit gate sequence includes the number of qubit gates, the order of qubit gates, and the type of qubit gates.

[0100] Specifically, the bit gate sequence after the mapping circuit traversal is completed is used as a reference execution result to determine whether it is equal to the bit gate sequence after the original quantum circuit traversal is completed; where the bit gate sequence includes the number of qubit gates, the order of qubit gates, and the type of qubit gates.

[0101] For example, suppose the bit gate sequence obtained by traversing the mapping circuit based on the initial mapping relationship is {0:"U3|U3|CZ|CZ|CZ|U3|",1:"U3|CZ|CZ|CZ|U3|",2:"CZ|CZ|U3|",4:"U3|CZ|CZ|U3|"}; then, traversing the original quantum circuit in the same way, the traversed bit gate sequence is {0:"U3|CZ|CZ|CZ|U3|",1:"U3|U3|CZ|CZ|CZ|U3|",2:"U3|CZ|CZ|U3|",3:"CZ|CZ|U3|"}. The final mapping obtained based on the above quantum bit mapping algorithm and the mapping result after traversing the mapping circuit based on the above initial mapping are shown in [reference needed]. Figure 8 , Figure 8 This is a schematic diagram of a mapping relationship and bit gate sequence verification provided by an embodiment of the present invention. Based on the mapping relationship {0:1,1:0,2:4,3:2}, it is determined whether the number of qubits, the order of qubits, and the type of qubits in the bit gate sequence obtained after traversing the mapping circuit are consistent with those in the bit gate sequence obtained after traversing the original quantum circuit.

[0102] In summary, by clarifying the verification process, the aim is to improve the mapping quality and performance of the qubit mapping algorithm, as well as the reliability and accuracy of the mapping process.

[0103] See Figure 9 , Figure 9 A verification device for a quantum bit mapping provided in an embodiment of the present invention includes a determination unit 901, a traversal unit 902, a judgment unit 903, and a verification unit 904.

[0104] Unit 901 is defined to determine the initial mapping, mapping circuit, and final mapping of the qubit mapping algorithm based on the original quantum circuit.

[0105] The initial mapping is a mapping relationship between the logical bits of the original quantum circuit and the physical bits of the quantum processor, which is set based on the mapping operation required by the original quantum circuit. The mapped circuit is a circuit structure that conforms to the topology of the quantum processor and is used to implement the quantum algorithm, which is obtained by performing the mapping operation on the original quantum circuit. The final mapping is the actual mapping relationship that conforms to the topology of the quantum processor, which is obtained based on the logical bits of the original quantum circuit and the physical bits of the quantum processor.

[0106] Specifically, the algorithm for determining the qubit mapping is based on the initial mapping of the original quantum circuit, the mapping circuit, and the final mapping, including:

[0107] The output parameters of the qubit mapping algorithm are determined based on the original quantum circuit and the topology of the quantum chip; wherein, the output parameters include the initial mapping, the mapping circuit, and the final mapping.

[0108] Traversal unit 902 traverses the mapping line based on the initial mapping to obtain the traversed mapping result and the bit gate sequence of the mapping line.

[0109] Specifically, the step of traversing the mapping line based on the initial mapping to obtain the traversed mapping result and the bit gate sequence of the mapping line includes:

[0110] The initialization algorithm for the qubit mapping is based on the initial mapping of the original quantum circuit and the current mapping relationship is recorded. The mapping circuit is traversed based on the initial mapping to obtain the mapping result after traversal and the bit gate sequence of the mapping circuit. The mapping relationship after traversal and the bit gate sequence of the mapping circuit during the traversal are recorded.

[0111] Specifically, traversing the mapped line based on the initial mapping includes:

[0112] Based on the initial mapping, the mapping line is traversed. If the physical bits of the quantum processor are available and the quantum bit double gates are adjacent during the traversal, the step is to further determine whether the current quantum bit double gate is a SWAP gate.

[0113] In response to the fact that the current qubit dual gate is a SWAP gate, the mapping relationship of the qubits is transformed and the qubit gate sequence is swapped.

[0114] Specifically, the method further includes:

[0115] If the current qubit dual gate is not a SWAP gate, then the qubit gate sequence is appended and the steps continue to traverse the mapping circuit.

[0116] Specifically, the quantum bit mapping algorithm includes the OLSQ2 mapping algorithm or the OBMT mapping algorithm.

[0117] Specifically, determining whether the mapping result after traversal is equal to the final mapping obtained by the qubit mapping algorithm, and whether the bit gate sequence of the mapped circuit is equal to the bit gate sequence obtained by traversing the original quantum circuit, includes:

[0118] Based on the final mapping obtained by the quantum bit mapping algorithm as a reference execution result, determine whether the mapping result after the mapping line traversal is equal to the final mapping obtained by the quantum bit mapping algorithm;

[0119] And determine whether the bit gate sequence completed by the mapping circuit is equal to the bit gate sequence completed by the original quantum circuit; wherein, the bit gate sequence includes the number of qubit gates, the order of qubit gates, and the type of qubit gates.

[0120] Verification unit 904 is used to perform mapping verification of the qubits of the original quantum circuit based on the judgment result.

[0121] The specific functions and effects of the aforementioned qubit mapping verification device can be explained by referring to other embodiments in this specification, and will not be repeated here. Each module in the qubit mapping verification device can be implemented entirely or partially through software, hardware, or a combination thereof. Each module can be embedded in or independent of the processor in a computer device in hardware form, or it can be stored in the memory of a computer device in software form, so that the processor can call and execute the operations corresponding to each module.

[0122] Please see Figure 10 This specification also provides an electronic device, including a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the quantum bit mapping verification method in any of the above embodiments. Please refer to [link to documentation]. Figure 10 The electronic device can be a classical computer or a quantum computer.

[0123] This specification also provides a computer-readable storage medium storing a computer program thereon, which, when executed by a computer, causes the computer to perform the quantum bit mapping verification method in any of the above embodiments.

[0124] This invention also provides a quantum computer operating system, which implements the mapping and verification of qubits according to any of the above-described method embodiments provided in this invention.

[0125] It is understood that the specific examples in this specification are only intended to help those skilled in the art better understand the implementation methods described herein, and are not intended to limit the scope of the invention.

[0126] It is understood that in the various embodiments of this specification, the sequence number of each process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not limit the implementation process of the embodiments of this specification in any way.

[0127] It is understood that the various implementation methods described in this specification can be implemented individually or in combination, and the implementation methods in this specification are not limited in this respect.

[0128] Unless otherwise stated, all technical and scientific terms used in the embodiments of this specification have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the scope of this specification. The term "and / or" as used in this specification includes any and all combinations of one or more of the associated listed items. The singular forms "a," "the," and "the" as used in the embodiments of this specification and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0129] It is understood that the processor in the embodiments of this specification can be an integrated circuit chip with signal processing capabilities. In implementation, each step of the above method embodiments can be completed by integrated logic circuits in the processor's hardware or by instructions in software form. The processor can be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this specification. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this specification can be directly implemented by a hardware decoding processor, or by a combination of hardware and software modules in the decoding processor. The software modules can reside in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory; the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above methods.

[0130] It is understood that the memory in the embodiments of this specification may be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. Non-volatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory may be random access memory (RAM). It should be noted that the memory in the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0131] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this specification.

[0132] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the aforementioned method implementations, and will not be repeated here.

[0133] In the several embodiments provided in this specification, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0134] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment, depending on actual needs.

[0135] In addition, the functional units in the various embodiments of this specification can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0136] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solutions of this specification, in essence, or the parts that contribute to the prior art, or parts of the technical solutions, can be embodied in the form of software products. These computer software products are stored in a storage medium and include several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this specification. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0137] The above description is merely a specific embodiment of this specification, but the scope of protection of this invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this specification should be included within the scope of protection of this specification. Therefore, the scope of protection of this invention should be determined by the scope of the claims.

Claims

1. A method for verifying qubit mappings, characterized in that, The method includes: The algorithm for determining the qubit mapping is based on the initial mapping, the mapping circuit, and the final mapping of the original quantum circuit; Based on the initial mapping, the mapping line is traversed to obtain the traversed mapping result and the bit gate sequence of the mapping line; Determine whether the mapping result after traversal is equal to the final mapping obtained by the quantum bit mapping algorithm, and whether the bit gate sequence of the mapping circuit is equal to the bit gate sequence obtained by traversing the original quantum circuit. The mapping verification of the qubits of the original quantum circuit is achieved based on the judgment result.

2. The method according to claim 1, characterized in that, The algorithm for determining the qubit mapping is based on the initial mapping of the original quantum circuit, the mapping circuit, and the final mapping, including: The output parameters of the qubit mapping algorithm are determined based on the original quantum circuit and the topology of the quantum chip; wherein, the output parameters include the initial mapping, the mapping circuit, and the final mapping.

3. The method according to claim 1, characterized in that, The step of traversing the mapped line based on the initial mapping to obtain the traversed mapping result and the bit gate sequence of the mapped line includes: The initialization algorithm for the qubit mapping is based on the initial mapping of the original quantum circuit and the current mapping relationship is recorded. The mapping circuit is traversed based on the initial mapping to obtain the mapping result after traversal and the bit gate sequence of the mapping circuit. The mapping relationship after traversal and the bit gate sequence of the mapping circuit during the traversal are recorded.

4. The method according to claim 3, characterized in that, The traversal of the mapped line based on the initial mapping includes: Based on the initial mapping, the mapping line is traversed. If the physical bits of the quantum processor are available and the quantum bit double gates are adjacent during the traversal, the step is to further determine whether the current quantum bit double gate is a SWAP gate. In response to the fact that the current qubit dual gate is a SWAP gate, the mapping relationship of the qubits is transformed and the qubit gate sequence is swapped.

5. The method according to claim 4, characterized in that, The method further includes: If the current qubit dual gate is not a SWAP gate, then the qubit gate sequence is appended and the steps continue to traverse the mapping circuit.

6. The method according to claim 1, characterized in that, The qubit mapping algorithm includes the OLSQ2 mapping algorithm or the OBMT mapping algorithm.

7. The method according to claim 1, characterized in that, The determination of whether the mapping result after traversal is equal to the final mapping obtained by the qubit mapping algorithm, and whether the bit gate sequence of the mapped circuit is equal to the bit gate sequence obtained by traversing the original quantum circuit, includes: Based on the final mapping obtained by the quantum bit mapping algorithm as a reference execution result, determine whether the mapping result after the mapping line traversal is equal to the final mapping obtained by the quantum bit mapping algorithm; And determine whether the bit gate sequence completed by the mapping circuit is equal to the bit gate sequence completed by the original quantum circuit; wherein, the bit gate sequence includes the number of qubit gates, the order of qubit gates, and the type of qubit gates.

8. A verification device for quantum bit mapping, characterized in that, The device includes: The determining unit is used to determine the initial mapping, mapping circuit, and final mapping of the qubit mapping algorithm based on the original quantum circuit; The traversal unit is used to traverse the mapping line based on the initial mapping to obtain the traversed mapping result and the bit gate sequence of the mapping line; The judgment unit is used to judge whether the mapping result after traversal is equal to the final mapping obtained by the quantum bit mapping algorithm, and whether the bit gate sequence of the mapping line is equal to the bit gate sequence obtained by traversing the original quantum line. A verification unit is used to perform mapping verification of the qubits of the original quantum circuit based on the judgment result.

9. An electronic device, characterized in that, include: Processor and memory; The processor is connected to a memory, wherein the memory is used to store a computer program, and the processor is used to invoke the computer program to execute the method as described in claims 1-7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, the computer program including program instructions that, when executed by a processor, perform the method as described in claims 1-7.

11. A quantum computer operating system, characterized in that, The quantum computer operating system implements the mapping verification of qubits according to any one of claims 1-7.

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