Graphics processor and resource access method, and terminal device

Abstract

A graphics processor and resource access method and terminal device, the graphics processor comprises: a stream processor, an adapter, a general-purpose channel and a unified resource memory, wherein: the stream processor comprises N operation execution units divided into M groups; the adapter is adapted to receive a shader resource access instruction and distribute the shader resource access instruction to the M groups; each group comprises at least one operation execution unit; the adapter is adapted to process the shader resource access instruction output by the corresponding group to obtain a unified access instruction and output the unified access instruction to the general-purpose channel corresponding to the corresponding group; the general-purpose channel is adapted to access the unified resource memory based on the received unified access instruction; and the number of general-purpose channels is M. The above scheme can effectively balance different types of shader resources, avoid waste of hardware resources of the graphics processor and improve the performance of the graphics processor.

Description

Technical Field

[0001] This invention relates to the field of graphics processor technology, and in particular to a graphics processor, a resource access method, and a terminal device. Background Technology

[0002] To achieve optimal rendering effects and performance, modern Graphics Processing Units (GPUs) frequently access shader resources such as sampled textures, shared memory, and loaded / stored UAV images. For textures and loaded / stored UAV images, GPU cores typically have caches to buffer data from external memory. For shared memory resources, GPU cores typically have buffers to cache data from external memory.

[0003] In different application scenarios, the demand for the three different shader resources mentioned above may be different, which leads to an imbalance in the use of different types of shader resources, resulting in a waste of graphics processor hardware resources (Cache, Buffer, etc.) and indirectly causing a decrease in graphics processor performance. Summary of the Invention

[0004] The purpose of this invention is at least to provide a graphics processor and a resource access control method and terminal device that can effectively balance different types of shader resources, avoid wasting graphics processor hardware resources, and improve graphics processor performance.

[0005] In a first aspect, the present invention provides a graphics processor, comprising: a stream processor, an adapter, a general-purpose path, and a unified resource memory, wherein: the stream processor comprises N execution units, the N execution units being divided into M groups; adapted to receive shader resource access instructions and sequentially distribute the shader resource access instructions to the M groups; each group comprises at least one execution unit; N and M are both positive integers and N > M > 1; the adapter is adapted to process the shader resource access instructions output by the corresponding group to obtain unified access instructions, and output the unified access instructions to the general-purpose path corresponding to the corresponding group; the general-purpose path is adapted to access the unified resource memory based on the received unified access instructions; the number of general-purpose paths is M, and each of the M groups corresponds one-to-one.

[0006] After receiving a shader resource access instruction, the stream processor distributes it sequentially to M groups. This distribution by the stream processor balances the distribution of shader resource access instructions received by different groups. An adapter processes the shader resource access instructions output from different groups to obtain a unified access instruction, which is then used by a general-purpose path to access the unified resource memory. Therefore, different types of shader resource access instructions, after processing by the adapter, can access the unified resource memory via the same general-purpose path, thus the general-purpose path is not affected by the type of shader resource access instruction. In summary, this graphics processor can utilize graphics processor hardware resources in a balanced manner, avoiding waste and improving the overall performance of the graphics processor.

[0007] Optionally, the adapter is adapted to acquire common information present in different types of shader resource access instructions to form the unified access instruction.

[0008] Optionally, the shader resource access instruction is a read operation instruction, and the corresponding unified access instruction includes the address information corresponding to the read operation instruction; the shader resource access instruction is a write operation instruction, and the corresponding unified access instruction includes the address information corresponding to the write operation instruction and the data to be written.

[0009] Optionally, the adapter is also adapted to add non-public information from the corresponding shader resource access instructions to the corresponding unified access instructions, wherein in the corresponding unified access instructions, the area where the public information is located is located before the area where the non-public information is located.

[0010] Optionally, the unified resource storage includes: a shared memory storage area, a vertex buffer area, and a shader resource cache area; wherein the sizes of the shared memory storage area, the vertex buffer area, and the shader resource cache area are dynamically adjusted based on the currently running application.

[0011] Optionally, the shared memory storage area, the vertex buffer area, and the shader resource cache area may be adjusted based on the type of the storage area corresponding to the currently running application; the type of the storage area includes at least one of the following: buffer type, cache type, and memory type.

[0012] Optionally, when the currently running application does not use the shared memory storage area and the vertex buffer area, the storage area of ​​the unified resource memory is used as the shader resource cache area.

[0013] Based on the type of storage area corresponding to the currently running application, the shared memory storage area, vertex buffer area, and shader resource cache area are dynamically adjusted to make full use of the unified resource memory and further improve the performance of the graphics processor.

[0014] Optionally, the value of M is 2; the stream processor is adapted to group even-numbered operation execution units into a first group and odd-numbered operation execution units into a second group.

[0015] Optionally, the stream processor is adapted to poll and distribute the shader resource access instructions to the first group and the second group.

[0016] Optionally, the graphics processor further includes: a level 1 cache connected to the unified resource memory; when the unified access instruction misses in the unified resource memory, it accesses the level 1 cache.

[0017] Secondly, the present invention also provides a resource access method, comprising: a stream processor sequentially allocating received shader resource access instructions to M groups; the stream processor comprising N execution units, the N execution units being divided into the M groups, each group comprising at least one execution unit; N and M being positive integers and N > M > 1; an adapter processing the received shader resource access instructions of the corresponding group to obtain a unified access instruction, and outputting the unified access instruction to the general path corresponding to the corresponding group; the corresponding general path accessing the unified resource memory based on the received unified access instruction; the number of general paths being M, and corresponding one-to-one with the M groups.

[0018] Optionally, the resource access method further includes: adjusting the size of the shader resource cache area in the unified resource memory based on the currently running application.

[0019] Optionally, the unified resource storage includes a shared memory storage area, a vertex buffer area, and a shader resource cache area; adjusting the shader resource cache area in the unified resource storage based on the currently running application includes: adjusting the shared memory storage area, the vertex buffer area, and the shader resource cache area based on the type of storage area corresponding to the currently running application; the type of storage area includes at least one of the following: buffer type, cache type, and memory type.

[0020] Thirdly, the present invention also provides a terminal device including any of the graphics processors described above.

[0021] Fourthly, the present invention also provides a computer-readable storage medium, which is a non-volatile storage medium or a non-transient storage medium, on which a computer program is stored, wherein the computer program, when executed by a processor, performs the steps of any of the resource access methods described above. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of the structure of a graphics processor according to an embodiment of the present invention;

[0023] Figure 2 This is a schematic diagram of the structure of another graphics processor in an embodiment of the present invention;

[0024] Figure 3 This is a schematic diagram of the structure of a unified resource storage device according to an embodiment of the present invention;

[0025] Figure 4 This is a flowchart of a resource access method according to an embodiment of the present invention. Detailed Implementation

[0026] As described in the background section, the requirements for the three different shader resources may vary in different application scenarios. For example, in some scenarios, there is a greater emphasis on loading / storing UAV image resources; in other scenarios, there is a greater emphasis on texture resources.

[0027] In existing technologies, a typical approach for different application scenarios involves allocating independent caches or buffers for different types of shader resources, with each cache or buffer having its own independent pipe path. This approach is simple and easy to implement, but it can easily lead to a waste of graphics processor hardware resources when the use of various shader resources is uneven.

[0028] In another typical approach, different types of shader resources share a common, large-capacity cache, and their respective pipeline paths are designed based on the type of shader resource accessed by the shader resource access instructions. However, since the pipeline paths are set according to the type of shader resource, when different types of shader resources are used unevenly, the effectiveness of pipeline paths with lower usage ratios will decrease, indirectly causing a decline in the performance of the graphics processor.

[0029] In summary, the demand for the three different types of shader resources may vary in different application scenarios, leading to an imbalance in the use of different types of shader resources. This results in a waste of graphics processor hardware resources and indirectly causes a decline in graphics processor performance.

[0030] In this embodiment of the invention, after receiving a shader resource access instruction, the stream processor sequentially distributes the instruction to M groups. This distribution by the stream processor balances the shader resource access instructions received by different groups. An adapter processes the shader resource access instructions output from different groups to obtain a unified access instruction, which is then used by a general path to access the unified resource memory. Therefore, different types of shader resource access instructions, after being processed by the adapter, can access the unified resource memory via the same general path, thus the general path is not affected by the type of shader resource access instruction. In summary, the above-described graphics processor can utilize graphics processor hardware resources in a balanced manner, avoiding waste and improving the overall performance of the graphics processor.

[0031] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0032] This invention provides a graphics processor, referring to... Figure 1 .

[0033] In this embodiment of the invention, the graphics processor includes: a stream processor 101, an adapter 102, a general-purpose path 103, and a unified resource memory 104.

[0034] In this embodiment of the invention, the stream processor 101 may include N process blocks, and the N process blocks are divided into M groups.

[0035] Stream processor 101 receives input shader resource access instructions. Stream processor 101 can sequentially assign the received shader resource access instructions to M groups. Each of the M groups includes at least one computation execution unit. N and M are both positive integers, and N > M > 1.

[0036] Adapter 102 can process the shader resource access instructions output by the corresponding group to obtain a unified access instruction, and output the unified access instruction to the general path 103 corresponding to the corresponding group. After receiving the unified access instruction, the general path 103 can access the unified resource memory 104 based on the received unified access instruction.

[0037] In practice, the aforementioned shader resource access instructions can be used to access shader resources of the same type or shader resources of different types. Different types of shader resources can include texture resources, shared memory resources, load / store UAV image resources, etc.

[0038] In practice, when dividing N execution units into M groups, the N execution units can be divided into M equal groups, meaning that each group contains the same number of execution units. When a group contains two or more execution units, the identifiers corresponding to the different execution units can be consecutive or non-consecutive.

[0039] In some embodiments, the N execution units can be divided into two groups. The execution units identified as even-numbered are assigned to the first group, and the execution units identified as odd-numbered are assigned to the second group.

[0040] For example, N takes the value of 4 and M takes the value of 2, meaning that the stream processor 101 includes 4 execution units, namely execution unit 0 to execution unit 3. The 4 execution units are divided into 2 groups, the first group including execution unit 0 and execution unit 2, and the second group including execution unit 1 and execution unit 3.

[0041] In other embodiments, the top N / 2 execution units with the smallest identifiers may be assigned to the first group, and the top N / 2 execution units with the largest identifiers may be assigned to the second group.

[0042] As in the example above, the four operation execution units are divided into two groups. The first group includes operation execution unit 0 and operation execution unit 1, and the second group includes operation execution unit 2 and operation execution unit 3.

[0043] It is understood that the values ​​of N and M are not limited to the examples above. In some embodiments, the value of N can also be 8, and the value of M can be 4. In this case, execution units 0 and 1 are assigned to the first group, execution units 2 and 3 are assigned to the second group, execution units 4 and 5 are assigned to the third group, and execution units 6 and 7 are assigned to the fourth group.

[0044] It is understood that the method of grouping N computational execution units is not limited to the relevant descriptions in the above embodiments, and the N computational execution units can be grouped according to actual application requirements.

[0045] In this embodiment of the invention, the stream processor 101 sequentially distributes the shader resource access instructions to M groups, which can mean that the stream processor 101 distributes the shader resource access instructions to the M groups in a round-robin manner.

[0046] Specifically, when the N execution units are divided into a first group and a second group, the stream processor 101 sends the shader resource access instructions to the first group and the second group respectively through a polling distribution method.

[0047] For example, the four execution units are divided into a first group and a second group. After receiving the first shader resource access instruction, the stream processor 101 assigns the first shader resource access instruction to the first group; upon receiving the second shader resource access instruction, it assigns the second shader resource access instruction to the second group; upon receiving the third shader resource access instruction, it assigns the third shader resource access instruction to the first group, and so on.

[0048] Therefore, after receiving a shader resource access instruction, the stream processor 101 can distribute the shader resource access instruction evenly to different groups, thereby ensuring that the utilization rate of each group is the same and achieving a balance of shader resource access instructions received by different groups.

[0049] In practice, any shader resource access instruction output by any group can be used to access different types of shader resources, including Texture resources, Shared Memory resources, Load / Store UAV image resources, etc.

[0050] In other words, any group can receive different types of shader resource access instructions.

[0051] In this embodiment of the invention, the adapter 102 can be used to process the shader resource access instructions output by each group, remove the differences between different types of shader resource access instructions, and obtain a unified access instruction.

[0052] In practice, the aforementioned unified access instruction can be an instruction formed from common information extracted from different types of shader resource access instructions.

[0053] In practical applications, it is known that when the shader resource access instruction is a read operation instruction, the address information corresponding to the read operation instruction exists in different types of shader resource access instructions; when the shader resource access instruction is a write operation instruction, the address information corresponding to the write operation instruction and the data to be written exist in different types of shader resource access instructions.

[0054] Based on this, after receiving a shader resource access instruction, the adapter can detect the type of the instruction. If the shader resource access instruction is a read operation instruction, the adapter can obtain the address information corresponding to the read operation instruction and add the address information to the corresponding unified access instruction.

[0055] If the shader resource access instruction is a write operation instruction, the adapter 102 can obtain the address information corresponding to the write operation instruction and the data to be written, and add the address information corresponding to the write operation and the data to be written to the corresponding unified access instruction.

[0056] In other words, regardless of whether the shader resource corresponding to the shader resource access instruction is a Texture resource, a SharedMemory resource, or a Load / Store UAV image resource, the adapter 102 converts the received shader resource access instruction into a unified access instruction.

[0057] As can be seen, the unified access instruction can be used to indicate whether the shader resource access instruction performs a read operation or a write operation, as well as related address information, data to be written, and other content.

[0058] In practice, different types of shader resource access instructions may contain non-public information in addition to the aforementioned public information. For example, the non-public information carried in shader resource access instructions that access Texture resources includes texture filtering methods, texture wrapping modes, texture declarations, and bindings.

[0059] In some embodiments, for non-public information carried in shader resource access instructions, the adapter can add it to the corresponding unified access instruction. In the corresponding unified access instruction, the area containing public information can be placed before the area containing non-public information.

[0060] In this embodiment of the invention, there are M general paths 103, and each path corresponds one-to-one with one of the M groups.

[0061] For example, if the four execution units in the stream processor 101 are divided into a first group and a second group, then the number of general paths 103 is 2, namely general path 1 and general path 2, and general path 1 corresponds to the first group and general path 2 corresponds to the second group.

[0062] After receiving the unified access instruction, the general access path 103 can perform access operations on the unified resource memory 104 to read or write corresponding data from or to the unified resource memory 104.

[0063] In other words, in this embodiment of the invention, regardless of what type of shader resource the shader resource access instruction is used to access, the general path 103 can access the unified resource memory 104 based on the unified access instruction.

[0064] In other words, through adapter 102, the general path 103 can treat different types of shader resource access instructions as a uniform type of shader resource access instructions, and can process different types of shader resource access instructions.

[0065] Reference Figure 2 The present invention provides a schematic diagram of the structure of another graphics processor in an embodiment of the present invention.

[0066] Figure 2 In this embodiment, the stream processor 101 includes four execution units, namely execution unit 0 to execution unit 3. There are two general-purpose paths 103, namely general-purpose path 1 and general-purpose path 2.

[0067] In the stream processor 101, execution units 0 and 2 are grouped into a first group, and execution units 1 and 3 are grouped into a second group. The stream processor 101 distributes the received shader resource access instructions sequentially to the first and second groups using a round-robin distribution method.

[0068] The shader resource access instructions received by the first group are output to adapter 102. After processing the shader resource access instructions output by the first group, adapter 102 outputs the resulting unified access instruction to general path 1. General path 1 accesses the unified resource memory 104 based on the received unified access instruction.

[0069] Accordingly, the shader resource access instructions received by the second group are output to adapter 102. After processing the shader resource access instructions output by the second group, adapter 102 outputs the resulting unified access instruction to general path 2. General path 2 accesses the unified resource memory 104 based on the received unified access instruction.

[0070] like Figure 3 The diagram shows a structural schematic of a unified resource storage 104 according to an embodiment of the present invention. Figure 3 In the unified resource storage 104, there are a shared memory storage area 301, a vertex buffer area 302, and a shader resource cache area 303.

[0071] In a practical implementation, the shared memory storage area 301 can be used to store shared memory resources. The vertex buffer area can be used to store the shader execution results of the graphics front end. The shader resource cache area 303 can be used to store texture resources and load / store UAV image resources.

[0072] In some embodiments, the storage space size of the unified resource storage 104 can be 128KB, 256KB, 512KB, etc.

[0073] It is understandable that the storage space size of the unified resource storage 104 can be set based on specific application scenarios, and is not limited to the values ​​in the examples above.

[0074] In practice, different types of storage regions in the unified resource storage 104 can be pre-configured with corresponding storage regions.

[0075] Specifically, based on the application scenario, the storage areas corresponding to the shared memory storage area 301, the vertex buffer area 302, and the shader resource cache area 303 can be configured separately. In different application scenarios, the sizes of these different types of storage areas can be the same or different.

[0076] In some application scenarios, shader resource access instructions are mainly used to access Texture resources. In this case, a larger storage area can be configured for the shader resource cache area 303, while a smaller storage area can be configured for the vertex buffer area 302 and the shared memory storage area 301.

[0077] In other application scenarios, the shader resource access instructions corresponding to shared memory are used less frequently, so a smaller storage area can be configured for the shared memory storage area 301, and a larger storage area can be configured for the vertex buffer area 302 and the shader resource cache area 303.

[0078] In practice, pre-configuring different types of storage areas in the unified resource storage 104 may not be suitable for different application scenarios.

[0079] For example, in some application scenarios, shader resource access instructions corresponding to shared memory are used less frequently, while in other application scenarios, they may be used extensively. In this scenario, if a small shared memory storage area 301 is set, the storage area may be insufficient; if a large shared memory storage area 301 is set, the storage area may be wasted.

[0080] In this embodiment of the invention, the size of each type of storage area in the unified resource storage 104 can be dynamically adjusted based on the currently running application.

[0081] In other words, the size of each type of storage area in the unified resource storage 104 is not fixed, but can be adaptively adjusted based on specific application scenarios.

[0082] In practice, the sizes of the shared memory storage area 301, the vertex buffer area, and the shader resource cache area 303 can be adjusted based on the type of storage area corresponding to the currently running application.

[0083] The storage area type may include at least one of the following: buffer type, cache type, and memory type; wherein, the buffer type corresponds to the vertex buffer area, the cache type corresponds to the shader resource cache area 303, and the memory type corresponds to the shared memory storage area 301.

[0084] For example, if the currently running application (such as a game app) accesses Texture resources frequently, the shader resource cache area 303 can be increased, while the shared memory storage area 301 and the vertex buffer area can be reduced accordingly.

[0085] For example, if the currently running application accesses the shared memory storage area 301 frequently, the shared memory storage area 301 can be increased or decreased accordingly.

[0086] In some embodiments, if the currently running application does not use the shared memory storage area 301 and the vertex buffer area, then the entire storage area of ​​the unified resource memory 104 can be used as the shader resource cache area 303.

[0087] In this embodiment of the invention, the graphics processor may further include a level 1 cache 105, which is connected to a unified resource memory 104. When a unified access instruction fails to be hit in the unified resource memory 104, the level 1 cache 105 can be accessed to retrieve the data corresponding to the unified access instruction from the level 1 cache 105.

[0088] The graphics processor may also include a general-purpose register (GPR) resource 106, which is a source / destination storage component during the processing of the stream processor 101, used to support warp scheduling and thread concurrency. A warp may include 32 threads.

[0089] In summary, in this embodiment of the invention, after receiving a shader resource access instruction, the stream processor sequentially distributes the instruction to M groups. The adapter processes the shader resource access instructions output by different groups to obtain a unified access instruction, which is then used to access the unified resource memory. Therefore, only the unified access instruction is received on the general path, thus avoiding the impact of different shader resource access instruction types. This allows for balanced use of the graphics processor's hardware resources, preventing waste and improving the overall performance of the graphics processor.

[0090] Reference Figure 4 This invention provides a resource access method according to an embodiment of the present invention. The resource access method can be executed by the graphics processor provided in the above embodiments. The specific steps are described in detail below.

[0091] Step 401: The stream processor sequentially distributes the received shader resource access instructions to M groups.

[0092] Step 402: The adapter processes the received shader resource access instructions for the corresponding group to obtain a unified access instruction, and outputs the unified access instruction to the general path corresponding to the corresponding group.

[0093] Step 403: The corresponding general path accesses the unified resource memory based on the received unified access instruction.

[0094] In a specific implementation, the resource access method further includes: adjusting the size of the shader resource cache area in the unified resource memory based on the currently running application.

[0095] In a specific implementation, the unified resource storage includes a shared memory storage area, a vertex buffer area, and a shader resource cache area. Adjusting the size of the shader resource cache area in the unified resource storage based on the currently running application includes: adjusting the shared memory storage area, the vertex buffer area, and the shader resource cache area based on the type of storage area corresponding to the currently running application. The type of storage area includes at least one of the following: buffer type, cache type, and memory type.

[0096] In specific implementation, the specific execution process of steps 401 to 403 above can be referred to the graphics processor provided in the above embodiments, and will not be repeated here.

[0097] This invention also provides a terminal device, including the graphics processor provided in any of the above embodiments.

[0098] This invention also provides a computer-readable storage medium, which is a non-volatile storage medium or a non-transient storage medium, on which a computer program is stored. When the computer program is run by a processor, it executes the steps of the resource access method provided in any of the above embodiments.

[0099] Those skilled in the art will understand that all or part of the steps in the various methods of the above embodiments can be performed by a program instructing related hardware. The program can be stored in a computer-readable storage medium, which may include ROM, RAM, disk, or optical disk, etc.

[0100] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A graphics processor, characterized in that, include: Stream processors, adapters, general-purpose paths, and unified resource memory, among which: The stream processor includes N execution units, which are divided into M groups; it is adapted to receive shader resource access instructions and distribute the shader resource access instructions to the M groups in a round-robin fashion; each group includes at least one execution unit; N and M are both positive integers and N > M > 1; The adapter is adapted to process the shader resource access instructions output by the corresponding group to obtain a unified access instruction, and output the unified access instruction to the general path corresponding to the corresponding group; the unified access instruction is formed by the adapter obtaining common information that exists in different types of shader resource access instructions; The general path is adapted to access the unified resource memory based on the received unified access instruction; the number of general paths is M, and they correspond one-to-one with the M groups; the unified resource memory includes: a shared memory storage area, a vertex buffer area, and a shader resource cache area; wherein, the size of the shared memory storage area, the vertex buffer area, and the shader resource cache area is dynamically adjusted based on the currently running application.

2. The graphics processor as described in claim 1, characterized in that, The shader resource access instruction output by the corresponding group is a read operation instruction, and the corresponding unified access instruction includes the address information corresponding to the read operation instruction; the shader resource access instruction output by the corresponding group is a write operation instruction, and the corresponding unified access instruction includes the address information corresponding to the write operation instruction and the data to be written.

3. The graphics processor as described in claim 1, characterized in that, The adapter is also adapted to add non-public information from the corresponding shader resource access instructions to the corresponding unified access instructions, wherein in the corresponding unified access instructions, the area where the public information is located is located before the area where the non-public information is located.

4. The graphics processor as described in claim 1, characterized in that, Based on the type of storage region corresponding to the currently running application, the shared memory storage region, the vertex buffer region, and the shader resource cache region are adjusted; the type of storage region includes at least one of the following: buffer type, cache type, and memory type.

5. The graphics processor as described in claim 4, characterized in that, When the currently running application does not use the shared memory storage area and the vertex buffer area, the storage area of ​​the unified resource memory is used as the shader resource cache area.

6. The graphics processor as described in claim 1, characterized in that, The value of M is 2; in the stream processor, the operation execution units identified by even numbers are classified as the first group, and the operation execution units identified by odd numbers are classified as the second group.

7. The graphics processor as described in claim 6, characterized in that, The stream processor is adapted to poll and distribute the shader resource access instructions to the first group and the second group.

8. The graphics processor as claimed in claim 1, characterized in that, Also includes: A level-one cache is connected to the unified resource memory; when the unified access instruction misses in the unified resource memory, it accesses the level-one cache.

9. A resource access method, characterized in that, include: The stream processor polls and distributes the received shader resource access instructions to M groups; the stream processor includes N execution units, which are divided into the M groups, and each group includes at least one execution unit; N and M are both positive integers and N > M > 1; The adapter processes the shader resource access instructions received from the corresponding group to obtain a unified access instruction, and outputs the unified access instruction to the general path corresponding to the corresponding group; the unified access instruction is formed by the adapter obtaining common information that exists in different types of shader resource access instructions; The corresponding general path accesses the unified resource memory based on the received unified access instruction; The number of general paths is M, and each of the M groups corresponds one-to-one; The unified resource storage includes: a shared memory storage area, a vertex buffer area, and a shader resource cache area; wherein the sizes of the shared memory storage area, the vertex buffer area, and the shader resource cache area are dynamically adjusted based on the currently running application.

10. The resource access method as described in claim 9, characterized in that, Based on the currently running application, the size of the shader resource cache region in the unified resource memory is adjusted, including: Based on the type of storage region corresponding to the currently running application, the shared memory storage region, the vertex buffer region, and the shader resource cache region are adjusted; the type of storage region includes at least one of the following: buffer type, cache type, and memory type.

11. A terminal device, characterized in that, Including the graphics processor as described in any one of claims 1 to 8.

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