Gate driving unit, gate driving circuit, display panel and electronic device

Abstract

This application discloses a gate driving unit, a gate driving circuit, a display panel, and an electronic device. The gate driving unit includes a first input terminal, an output terminal, an output transistor, a pull-down transistor, a first output control module, and a pull-down control module. The first connection terminal of the output transistor is electrically connected to the first input terminal, the second connection terminal of the output transistor is electrically connected to the output terminal, and the control terminal of the output transistor is electrically connected to a first node. The first connection terminal of the pull-down transistor is electrically connected to the output terminal, the second connection terminal of the pull-down transistor is used to receive a first low-level voltage, and the control terminal of the pull-down transistor is electrically connected to a second node. A first capacitor exists between the first connection terminal and the control terminal of the pull-down transistor. The first output control module is electrically connected to the first node, and the pull-down control module is electrically connected to the second node. The gate driving unit provided by this application can avoid intermediate potential plateaus in the output gate driving signal.

Description

Technical Field

[0001] This application relates to the field of display panel technology, and in particular to a gate driving unit, a gate driving circuit, a display panel, and an electronic device. Background Technology

[0002] The gate drive circuit is one of the essential circuits for driving the display panel. Currently, it is mostly integrated into the display substrate using gate drive on array (GOA) technology to facilitate narrow bezel designs. Correspondingly, the gate drive circuit is also called the GOA circuit.

[0003] In related technologies, GOA circuits typically include multiple cascaded GOA units. These GOA units are coupled to multiple rows of pixels in the display panel via their output terminals, and are used to output gate drive signals to each row of pixels sequentially. This enables row scanning drive to illuminate multiple rows of pixels one by one, allowing the display panel to display the image. To achieve a narrow bezel, GOA units typically include multiple P-type LTPS (low-temperature polysilicon), and pixels typically include multiple N-type transistors.

[0004] However, P-type LTPS (Low-Temperature Polycrystalline Silicon) cannot be rapidly pulled down from a high potential to a low potential. This results in an intermediate potential plateau in the gate drive signal output by the GOA (Gateway Aperture Array) unit, falling between the normal high and low potentials of the drive signal. Since the height of this intermediate potential plateau varies among different GOA units, it causes uneven brightness and horizontal stripes on the display panel. Therefore, reducing or eliminating this intermediate potential plateau in the gate drive signal has become a pressing problem. Summary of the Invention

[0005] This application provides a gate driving unit, a gate driving circuit, a display panel, and electronic devices, which can reduce or eliminate intermediate potential plateaus in the gate driving signal and improve the display effect of the display panel.

[0006] In a first aspect, a gate driving unit is provided, wherein the gate driving unit operates at least sequentially in a first stage, a second stage, and a third stage in each driving cycle, and the gate driving unit includes a first input terminal, a first node, a second node, an output terminal, an output transistor, a pull-down transistor, a first output control module, and a pull-down control module. The first input terminal is used to receive a first clock signal; wherein, the first clock signal is a first low-level voltage in the first stage and the third stage, and a first high-level voltage in the second stage; the output terminal is used to output a gate drive signal; the output transistor includes a first connection terminal, a second connection terminal, and a control terminal; the first connection terminal of the output transistor is electrically connected to the first input terminal, the second connection terminal of the output transistor is electrically connected to the output terminal, and the control terminal of the output transistor is electrically connected to the first node; the pull-down transistor includes a first connection terminal, a second connection terminal, and a control terminal; wherein, the first connection terminal of the pull-down transistor is electrically connected to the output terminal, the second connection terminal of the pull-down transistor is used to receive the first low-level voltage, the control terminal of the pull-down transistor is electrically connected to the second node, and a first capacitor exists between the first connection terminal and the control terminal of the pull-down transistor; both the output transistor and the pull-down transistor are P-type transistors; the first output control module is electrically connected to the first node; the pull-down control module is electrically connected to the second node; in the first stage, the first output control module makes the voltage of the first node a second high-level voltage, causing the output transistor to turn off, and the pull-down... The pull-up control module pulls the voltage of the second node up to the first high-level voltage, causing the pull-down transistor to turn off, and the gate drive signal remains at the voltage of the last stage in the previous driving cycle; wherein, the second high-level voltage is lower than or equal to the first high-level voltage; in the second stage, the first output control module pulls down the voltage of the first node, causing the output transistor to turn on, and the output terminal obtains a first clock signal at the first high-level voltage from the first input terminal through the turned-on output transistor, thereby outputting the gate drive signal at the first high-level voltage; the first capacitor keeps the second node at the first high-level voltage, thereby keeping the pull-down transistor off; in the third stage, the first output control module pulls up the voltage of the first node, causing the output transistor to turn off, and the pull-down control module and the first capacitor cooperate to pull down the voltage of the second node to the second low-level voltage, causing the pull-down transistor to turn on completely, thereby allowing the output terminal to obtain the first low-level voltage through the turned-on pull-down transistor and output the gate drive signal at the first low-level voltage; wherein, the second low-level voltage is lower than the first low-level voltage.

[0007] The gate driving unit provided in this application, in the second stage, pulls down the voltage of the first node through the first output control module, so that the output terminal outputs the first high-level voltage in the second stage. In the third stage, through the pull-down action of the pull-down control module and the bootstrap characteristic of the first capacitor, the voltage of the second node is pulled down to the second low-level voltage, so that the pull-down transistor is fully turned on, thereby enabling the output terminal to fully output the first low-level voltage in the third stage. This allows the gate driving signal output from the output terminal to be quickly pulled down from the first high-level voltage to the first low-level voltage, thereby avoiding the appearance of an intermediate level plateau in the output gate driving signal, and thus improving the display effect of the display panel.

[0008] In conjunction with the first aspect, in some embodiments, the gate driving unit further includes a second output control module, which is electrically connected to both the first node and the pull-down control module; the gate driving unit operates in a fourth stage after the third stage in each driving cycle; in the third stage, the second output control module outputs the first high-level voltage to the first node under the control of the pull-down control module, thereby turning off the output transistor; in the fourth stage, the second output control module continues to output the first high-level voltage to the first node, thereby keeping the output transistor off, and thus keeping the gate driving signal output from the output terminal at the first low-level voltage.

[0009] In this way, when other gate driving units in the display panel scan other row pixel units, the gate driving signal output by this gate driving unit can be kept at the first low level voltage, thereby ensuring that the scanning transistor in the pixel unit corresponding to this gate driving unit will not be mis-turned on.

[0010] In conjunction with the first aspect, in some embodiments, the gate driving unit further includes a second input terminal for receiving a start signal, wherein the start signal is a first high-level voltage in the first stage and a first low-level voltage in the third stage; the pull-down control module is also electrically connected to the first input terminal and the second input terminal; in the first stage, under the control of the first clock signal, the pull-down control module outputs the start signal (which is the first high-level voltage) received at the second input terminal to the second node, thereby pulling up the voltage of the second node to the first high-level voltage; in the third stage, under the control of the first clock signal, the pull-down control module also outputs the start signal (which is the first low-level voltage) received at the second input terminal to the second node, thereby working with the first capacitor to pull down the voltage of the second node to the second low-level voltage.

[0011] Thus, by controlling the pull-down control module through the first clock signal and the start signal, the voltage of the second node can be pulled up to the first high-level voltage in the first stage, and the voltage of the second node can be pulled down to the second low-level voltage in the third stage. The control logic is simple and easy to implement.

[0012] In conjunction with the first aspect, in some embodiments, the pull-down control module includes a first transistor, the first transistor including a first connection terminal, a second connection terminal and a control terminal, the first connection terminal of the first transistor being electrically connected to the second input terminal, the second connection terminal of the first transistor being electrically connected to the second node, and the control terminal of the first transistor being electrically connected to the first input terminal; wherein, the first transistor is a P-type transistor.

[0013] Thus, the pull-down control module can consist of only the first transistor, resulting in a simple circuit structure.

[0014] In conjunction with the first aspect, in some embodiments, the second output control module includes a second transistor; the second transistor includes a first connection terminal, a second connection terminal, and a control terminal, the control terminal of the second transistor is electrically connected to the second node, the first connection terminal of the second transistor is used to receive the first high-level voltage, and the second connection terminal of the second transistor is electrically connected to the first node; wherein, the second transistor is a P-type transistor.

[0015] Thus, the second output control module can consist of only the second transistor, resulting in a simple circuit structure.

[0016] In conjunction with the first aspect, in some embodiments, the pull-down control module further includes an isolation unit electrically connected between the control terminal of the second transistor and the second node. The isolation unit is used to disconnect the electrical connection between the control terminal of the second transistor and the second node when the voltage of the second node is the second low-level voltage, so as to protect the second transistor.

[0017] Thus, by setting the isolation unit between the control terminal of the second transistor and the second node, the transmission of the second low-level voltage to the control terminal of the second transistor can be blocked, thereby protecting the second transistor.

[0018] In conjunction with the first aspect, in some embodiments, the isolation unit includes a third transistor, the third transistor including a first connection terminal and a second connection terminal, the first connection terminal of the third transistor being electrically connected to the second connection terminal of the first transistor, the second connection terminal of the third transistor being electrically connected to the second node, and the control terminal of the third transistor being used to receive the first low-level voltage; wherein, the third transistor is a P-type transistor.

[0019] Thus, the isolation unit can consist of only a third transistor, resulting in a simple circuit structure.

[0020] In conjunction with the first aspect, in some embodiments, the gate driving unit further includes a third input terminal for receiving a second clock signal; the first output control module is also electrically connected to the first input terminal and the third input terminal, and under the control of the first clock signal and the second clock signal, the first output control module makes the voltage of the first node a second high-level voltage in the first stage, pulls down the voltage of the first node in the second stage, and pulls up the voltage of the first node in the third stage; wherein, the second clock signal is the first high-level voltage in the first stage and the third stage, and the first low-level voltage in the second stage.

[0021] Thus, by controlling the first output control module through the first clock signal and the second clock signal, it is possible to make the voltage of the first node a second high-level voltage in the first stage, pull down the voltage of the first node in the second stage, and pull up the voltage of the first node in the third stage. The control logic is simple and easy to implement.

[0022] In conjunction with the first aspect, in some embodiments, the first output control module includes a fourth transistor and a fifth transistor. The fourth transistor includes a first connection terminal, a second connection terminal, and a control terminal. The first connection terminal of the fourth transistor is used to receive the first high-level voltage. The second connection terminal of the fourth transistor is electrically connected to the first node, and the control terminal of the fourth transistor is electrically connected to the first input terminal. The fifth transistor includes a first connection terminal, a second connection terminal, and a control terminal. The first connection terminal of the fifth transistor is electrically connected to the third input terminal. The second connection terminal of the fifth transistor is electrically connected to the first node, and the control terminal of the fifth transistor is electrically connected to the second node. The fourth transistor is a P-type transistor, and the fifth transistor is an N-type transistor.

[0023] Thus, the first output control module can consist of only two transistors, resulting in a simple circuit structure.

[0024] In conjunction with the first aspect, in some embodiments, the gate driving unit further includes a third input terminal for receiving a second clock signal; the first output control module is also electrically connected to the second input terminal and the third input terminal, and under the control of the second clock signal and the start signal, the first output control module makes the voltage of the first node a second high-level voltage in the first stage, pulls down the voltage of the first node in the second stage, and pulls up the voltage of the first node in the third stage; wherein, the second clock signal is the first high-level voltage in the first stage and the third stage, and the first low-level voltage in the second stage.

[0025] Thus, by controlling the first output control module through the second clock signal and the start signal, it is possible to make the voltage of the first node a second high-level voltage in the first stage, pull down the voltage of the first node in the second stage, and pull up the voltage of the first node in the third stage. The control logic is simple and easy to implement.

[0026] In conjunction with the first aspect, in some embodiments, the first output control module includes a sixth transistor, a seventh transistor, a second capacitor, and a third capacitor. The sixth transistor includes a first connection terminal, a second connection terminal, and a control terminal; the first connection terminal of the sixth transistor is electrically connected to the third input terminal, and the control terminal of the sixth transistor is electrically connected to the second input terminal. The seventh transistor includes a first connection terminal, a second connection terminal, and a control terminal; the second connection terminal of the seventh transistor is electrically connected to the first node, and the control terminal of the seventh transistor is electrically connected to the second connection terminal of the sixth transistor. The second capacitor is electrically connected between the first connection terminal and the control terminal of the seventh transistor. The third capacitor is electrically connected between the first connection terminal and the control terminal of the output transistor. Both the sixth and seventh transistors are P-type transistors.

[0027] Thus, the first output control module can consist of only two transistors, resulting in a simple circuit structure.

[0028] In conjunction with the first aspect, in some embodiments, the first capacitor is the parasitic capacitance of the pull-down transistor.

[0029] Therefore, there is no need to add an additional capacitor between the first connection terminal and the control terminal of the pull-down transistor, making the circuit structure simpler.

[0030] In a second aspect, a gate driving circuit is provided, the gate driving circuit including the gate driving unit described in the first aspect or any embodiment of the first aspect, wherein the gate driving units in the gate driving circuit are cascaded.

[0031] In conjunction with the second aspect, in some embodiments, the gate driving circuit further includes a first signal line, a second signal line, a third signal line, and a fourth signal line; wherein the first signal line is used to transmit a first signal, the second signal line is used to transmit a second signal, the third signal line is used to transmit a third signal, and the fourth signal line is used to transmit a fourth signal; wherein the first signal to the fourth signal are all clock signals with the same period, and the subsequent signal lags behind the preceding signal by a preset time interval; the gate driving circuit includes n gate driving units, wherein when the gate driving unit includes a third input terminal, the first input terminal of the 4*i+1th gate driving unit is connected to the first signal line. Electrical connections are made as follows: the third input terminal of the 4*i+1th gate driving unit is electrically connected to the second signal line; the first input terminal of the 4*i+2th gate driving unit is electrically connected to the second signal line, and the third input terminal of the 4*i+2th gate driving unit is electrically connected to the third signal line; the first input terminal of the 4*i+3th gate driving unit is electrically connected to the third signal line, and the third input terminal of the 4*i+3rd gate driving unit is electrically connected to the fourth signal line; the first input terminal of the 4*i+4th gate driving unit is electrically connected to the fourth signal line, and the third input terminal of the 4*i+4th gate driving unit is electrically connected to the first signal line; where i≥0, n≥4*i+4.

[0032] Thirdly, a display panel is provided, the display panel including at least two rows of pixel units and a gate driving circuit as described in the second aspect above or any embodiment of the second aspect above; the at least two gate driving units are electrically connected to the at least two rows of pixel units in a one-to-one correspondence, and are used to output gate driving signals to the at least two rows of pixel units to drive the at least two rows of pixel units to emit light.

[0033] Fourthly, an electronic device is provided, the electronic device comprising the display panel described in the third aspect above. Attached Figure Description

[0034] Figure 1 This is a topology diagram of the gate driving unit provided in an embodiment of this application;

[0035] Figure 2 This is a first circuit structure diagram of the gate driving unit provided in an embodiment of this application;

[0036] Figure 3 for Figure 2The signal timing diagram shown is a diagram of the gate drive unit during operation.

[0037] Figure 4 for Figure 2 The diagram shows the circuit state when the gate drive unit is operating in the first stage.

[0038] Figure 5 for Figure 2 The diagram shows the circuit state when the gate drive unit is operating in the second stage.

[0039] Figure 6 for Figure 2 The diagram shows the circuit state when the gate drive unit is operating in the third stage.

[0040] Figure 7 for Figure 2 The diagram shows the circuit state when the gate drive unit is operating in the fourth stage.

[0041] Figure 8 This is a second circuit structure diagram of the gate driving unit provided in the embodiments of this application;

[0042] Figure 9 for Figure 8 The signal timing diagram shown is a diagram of the gate drive unit during operation.

[0043] Figure 10 for Figure 8 The diagram shows the circuit state when the gate drive unit is operating in the first stage.

[0044] Figure 11 for Figure 8 The diagram shows the circuit state when the gate drive unit is operating in the second stage.

[0045] Figure 12 for Figure 8 The diagram shows the circuit state when the gate drive unit is operating in the third stage.

[0046] Figure 13 for Figure 8 The diagram shows the circuit state when the gate drive unit is operating in the fourth stage.

[0047] Figure 14 This is a topology diagram of the display panel provided in an embodiment of this application;

[0048] Figure 15 for Figure 14 The diagram shown illustrates the signal timing of the display panel during operation.

[0049] Figure 16 This is a topology diagram of an electronic device provided in an embodiment of this application. Detailed Implementation

[0050] In the description of the embodiments of this application, the terminology used in the following embodiments is for the purpose of describing specific embodiments only and is not intended to be a limitation of this application. As used in the specification and appended claims of this application, the singular expressions "a," "the," "the," "the," and "this" are intended to also include expressions such as "one or more," unless the context clearly indicates otherwise. It should also be understood that in the following embodiments of this application, "at least one" and "one or more" refer to one or more (including two). The term "and / or" is used to describe the relationship between related objects, indicating that three relationships can exist; for example, A and / or B can indicate: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "Pull up / pull down the voltage of node A to the voltage of B" does not mean that it is absolutely stable at the voltage of B, and some fluctuation is allowed.

[0051] References to "one embodiment" or "some embodiments" in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized. The term "connection" includes direct connections and indirect connections, unless otherwise stated. "First" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated.

[0052] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design that is described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0053] In the embodiments of this application, a transistor refers to a device that includes at least three terminals: a gate, a source, and a drain. When using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source" and "drain" are sometimes interchanged; that is, the "source" and "drain" can be switched. In the embodiments of this application, for any transistor, one of the "source" and "drain" is referred to as the first connection terminal of the transistor, and the other is referred to as the second connection terminal of the transistor, and the gate is referred to as the control terminal of the transistor.

[0054] Please refer to the following: Figures 1-3 , Figure 1 This is a topology diagram of the gate driving unit provided in an embodiment of this application. Figure 2 This is a first circuit structure diagram of the gate driving unit provided in an embodiment of this application. Figure 3 for Figure 2 The signal timing diagram shown is a diagram of the gate drive unit during operation.

[0055] like Figure 1 As shown, the gate driving unit GOA provided in this application includes a first input terminal CK, a first node N1, a second node N2, an output terminal OUT, an output transistor Tm, a pull-down transistor Tn, a first output control module 11, and a pull-down control module 12. The gate driving unit GOA operates at least sequentially in a first stage t1, a second stage t2, and a third stage t3 during each driving cycle.

[0056] Wherein, the first input terminal CK is used to receive the first clock signal CK. For example... Figure 3 As shown, the first clock signal CK is a first low-level voltage VGL in the first stage t1 and the third stage t3, and a first high-level voltage VGH in the second stage t2.

[0057] The output terminal OUT is used to output the gate drive signal.

[0058] The output transistor Tm includes a first connection terminal, a second connection terminal, and a control terminal. The first connection terminal of the output transistor Tm is electrically connected to the first input terminal CK, the second connection terminal of the output transistor Tm is electrically connected to the output terminal OUT, and the control terminal of the output transistor Tm is electrically connected to the first node N1.

[0059] The pull-down transistor Tn includes a first connection terminal, a second connection terminal, and a control terminal. The first connection terminal of the pull-down transistor Tn is electrically connected to the output terminal OUT. The second connection terminal of the pull-down transistor Tn is used to receive the first low-level voltage VGL. The control terminal of the pull-down transistor Tn is electrically connected to the second node N2. A first capacitor C1 exists between the first connection terminal and the control terminal of the pull-down transistor Tn. Both the output transistor Tm and the pull-down transistor Tn are P-type transistors.

[0060] The first output control module 11 is electrically connected to the first node N1.

[0061] The pull-down control module 12 is electrically connected to the second node N2.

[0062] In the first stage t1, the first output control module 11 sets the voltage of the first node N1 to the second high-level voltage VGH1, thereby turning off the output transistor Tm. Meanwhile, the pull-down control module 12 pulls the voltage of the second node N2 up to the first high-level voltage VGH, turning off the pull-down transistor Tn. The gate drive signal remains at the voltage of the last stage of the previous drive cycle, wherein the second high-level voltage VGH1 is lower than or equal to the first high-level voltage VGH. At this time, the gate-source voltage Vgs of the output transistor Tm = VGH1 - VGL > Vthm, thus turning off the output transistor Tm, where Vthm is the threshold voltage of the output transistor Tm.

[0063] In the second stage t2, the first output control module 11 pulls down the voltage of the first node N1, causing the output transistor Tm to turn on. The output terminal OUT obtains the first clock signal CK at the first high-level voltage VGH from the first input terminal CK through the turned-on output transistor Tm. That is, the first clock signal CK at the first high-level voltage VGH received by the first input terminal CK is output to the output terminal OUT through the turned-on output transistor Tm, thereby making the gate drive signal output by the output terminal OUT the first high-level voltage VGH. The pull-down control module 12 stops pulling up, and the first capacitor C1 maintains the first high-level voltage VGH at the second node N2 based on its voltage holding characteristic, thereby keeping the pull-down transistor Tn off.

[0064] In the third stage t3, the first output control module 11 pulls up the voltage of the first node N1, causing the output transistor Tm to turn off. The pull-down control module 12 and the first capacitor C1 cooperate to pull down the voltage of the second node N2 to the second low-level voltage VGL1, causing the pull-down transistor Tn to be fully turned on. This allows the output terminal OUT to obtain the first low-level voltage VGL through the turned-on pull-down transistor Tn and output the gate drive signal of the first low-level voltage VGL. The second low-level voltage VGL1 is lower than the first low-level voltage VGL.

[0065] Specifically, the pull-down control module 12 pulls the second node N2 down to the first low-level voltage VGL, causing the pull-down transistor Tn to enter a critical conduction state in response to the second node N2 being at the first low-level voltage VGL. The pull-down transistor Tn, in the critical conduction state, attenuates the first low-level voltage VGL received at its second connection terminal, resulting in a third low-level voltage output from the first connection terminal of the pull-down transistor Tn to the output terminal OUT. This third low-level voltage VGL2 is higher than the first low-level voltage VGL; specifically, VGL2 = VGL - Vthn, where Vthn is the threshold voltage of the pull-down transistor Tn, which is negative, for example, -2V. At the instant the pull-down transistor Tn enters the critical conduction state, the voltage at the output terminal OUT jumps from the first high-level voltage VGH to the third low-level voltage. The first capacitor C1, based on its bootstrap characteristics, couples the voltage of the second node N2 down from the first low-level voltage VGL to the second low-level voltage VGL1. Where VGL1-VGL≤Vthn, the pull-down transistor Tn is fully turned on and outputs the first low-level voltage VGL completely to the output terminal OUT. It should be noted that, since the first capacitor C1 can couple the voltage of the second node N2 down to the second low-level voltage VGL1 at the instant the pull-down transistor Tn is turned on, the duration of the third low-level voltage is extremely short and can be ignored. Therefore, the gate drive signal output from the output terminal OUT can be quickly pulled down from the first high-level voltage VGH to the first low-level voltage VGL, thereby avoiding an intermediate potential plateau in the output gate drive signal, preventing uneven brightness and horizontal stripes on the display panel, and thus improving the display effect of the display panel.

[0066] The output terminal OUT of the gate driving unit GOA is electrically connected to a row of pixel units P in the display panel. The gate driving unit GOA, also known as the scan driving unit, outputs a gate driving signal, also known as a scan signal, which is used to scan the pixel units P electrically connected to the gate driving unit GOA. Specifically, when the gate driving signal is the first high-level voltage VGH, the scan transistor in the corresponding pixel unit P is turned on.

[0067] Each driving cycle of the gate driving unit GOA is the cycle for driving one frame of display. During the process of driving one frame of display, the gate driving unit GOA works sequentially in the first stage, the second stage, the third stage, etc., to realize the driving display of one frame of display.

[0068] The gate drive unit GOA provided in this application, in the second stage t2, pulls down the voltage of the first node N1 through the first output control module 11, so that the output terminal OUT outputs the first high-level voltage VGH in the second stage t2. In the third stage t3, through the pull-down action of the pull-down control module 12 and the bootstrap characteristic of the first capacitor C1, the voltage of the second node N2 is pulled down to the second low-level voltage VGL1, so that the pull-down transistor Tn is fully turned on, thereby enabling the output terminal OUT to fully output the first low-level voltage VGL in the third stage t3. This allows the gate drive signal output by the output terminal OUT to be quickly pulled down from the first high-level voltage VGH to the first low-level voltage VGL, thereby avoiding the appearance of an intermediate potential plateau in the output gate drive signal, and thus improving the display effect of the display panel.

[0069] In some embodiments, the first capacitor C1 is the parasitic capacitance of the pull-down transistor Tn.

[0070] Therefore, there is no need to add an additional capacitor between the first connection terminal and the control terminal of the pull-down transistor Tn, making the circuit structure simpler.

[0071] In other embodiments, to improve the coupling capability of the first capacitor C1, the first capacitor C1 can also be a capacitor composed of the parasitic capacitance of the pull-down transistor Tn connected in parallel with other capacitors. It should be noted that the larger the capacitance value of the first capacitor C1, the stronger the coupling capability of the first capacitor C1 to the second node N2 in the third stage t3, and the lower the voltage value of the second low-level voltage VGL1 will be. Taking the first high-level voltage VGH as 7V and the first low-level voltage VGL as -7V as an example, when the first capacitor C1 is only the parasitic capacitance of the pull-down transistor Tn, the first capacitor C1 can couple the voltage of the second node N2 down to -10V in the third stage t3. When the first capacitor C1 is a capacitor composed of the parasitic capacitance of the pull-down transistor Tn connected in parallel with other capacitors, the first capacitor C1 can couple the voltage of the second node N2 down to -20V in the third stage t3.

[0072] In some embodiments, the gate drive unit GOA further includes a second output control module 13, which is electrically connected to the first node N1 and the pull-down control module 12.

[0073] The gate drive unit GOA operates in a fourth stage t4 after the third stage t3 in each drive cycle. In the third stage t3, the second output control module 13 outputs the first high-level voltage VGH to the first node N1 under the control of the pull-down control module 12, causing the output transistor Tn to turn off. In the fourth stage t4, the second output control module 13 continues to output the first high-level voltage VGH to the first node N1, thereby keeping the output transistor Tm off, and thus keeping the gate drive signal output by the output terminal OUT at the first low-level voltage VGL.

[0074] Thus, when other gate driving units (GOAs) in the display panel scan other row pixel units (P), the gate driving signal output by the current gate driving unit (GOA) can be maintained at the first low-level voltage VGL, thereby ensuring that the scanning transistor in the pixel unit (P) corresponding to the current gate driving unit (GOA) will not be mis-turned on.

[0075] like Figure 2 As shown, in some embodiments, the gate drive unit GOA further includes a second input terminal IN, which is used to receive a start signal IN. Figure 3 As shown, the start signal IN is the first high-level voltage VGH in the first stage t1, and the first low-level voltage VGL in the second stage t2 to the fourth stage t4.

[0076] The pull-down control module 12 is also electrically connected to the first input terminal CK and the second input terminal IN. In the first stage t1, under the control of the first clock signal CK, the pull-down control module 12 outputs the start signal IN, which receives a voltage of the first high-level voltage VGH, to the second node N2, thereby pulling up the voltage of the second node N2 to the first high-level voltage VGH. In the third stage t3, under the control of the first clock signal CK, the pull-down control module 12 also outputs the start signal IN, which receives a voltage of the first low-level voltage VGL, to the second node N2, thereby working with the first capacitor C1 to pull down the voltage of the second node N2 to the second low-level voltage VGL1.

[0077] Thus, by controlling the pull-down control module 12 through the first clock signal CK and the start signal IN, the voltage of the second node N2 can be pulled up to the first high-level voltage VGH in the first stage t1, and the voltage of the second node N2 can be pulled down to the second low-level voltage VGL1 in the third stage t3. The control logic is simple and easy to implement.

[0078] like Figure 2 As shown, in some embodiments, the pull-down control module 12 includes a first transistor T1. The first transistor T1 includes a first connection terminal, a second connection terminal, and a control terminal. The first connection terminal of the first transistor T1 is electrically connected to the second input terminal IN, the second connection terminal of the first transistor T1 is electrically connected to the second node N2, and the control terminal of the first transistor T1 is electrically connected to the first input terminal CK. The first transistor T1 is a P-type transistor.

[0079] Thus, the pull-down control module 12 can consist of only the first transistor T1, resulting in a simple circuit structure.

[0080] In some embodiments, the second output control module 13 includes a second transistor T2. The second transistor T2 includes a first connection terminal, a second connection terminal, and a control terminal. The control terminal of the second transistor T2 is electrically connected to the second node N2. The first connection terminal of the second transistor T2 is used to receive the first high-level voltage VGH. The second connection terminal of the second transistor T2 is electrically connected to the first node N1. The second transistor T2 is a P-type transistor.

[0081] Thus, the second output control module 13 can consist of only the second transistor T2, resulting in a simple circuit structure.

[0082] In some embodiments, the pull-down control module 12 further includes an isolation unit 121, which is electrically connected between the control terminal of the second transistor T2 and the second node N2. The isolation unit 121 is used to disconnect the electrical connection between the control terminal of the second transistor T2 and the second node N2 when the voltage of the second node N2 is the second low-level voltage VGL1, thereby protecting the second transistor T2. In other embodiments, the isolation unit 121 may not be provided, that is, the control terminal of the second transistor T2, the second node N2, and the second connection terminal of the first transistor T1 are electrically connected.

[0083] As mentioned above, in the third stage, the voltage at the first connection terminal of the second transistor T2 is the first high-level voltage VGH (e.g., 7V), and the second node N2 is pulled down to the second low-level voltage VGL1. Since the voltage value of the second low-level voltage VGL1 is low, reaching -10V to -20V, if the second low-level voltage VGL1 is directly output to the control terminal of the second transistor T2, it will cause the gate-source voltage Vgs of the second transistor T2 to be too large, which may cause damage to the second transistor T2. In this embodiment, the isolation unit 121 is set between the control terminal of the second transistor T2 and the second node N2, which can block the transmission of the second low-level voltage VGL1 to the control terminal of the second transistor T2, thereby protecting the second transistor T2.

[0084] In some embodiments, the isolation unit 121 includes a third transistor T3. The third transistor T3 includes a first connection end and a second connection end. The first connection end of the third transistor T3 is electrically connected to the second connection end of the first transistor T1. The second connection end of the third transistor T3 is electrically connected to the second node N2. The control end of the third transistor T3 is used to receive the first low-level voltage VGL. Wherein, the third transistor T3 is a P-type transistor. As described above, in the first stage t1 and the second stage t2, the voltage of the second node N2 is the first high-level voltage VGH. At this time, the gate-source voltage Vgs of the third transistor T3 is VGL - VGH < Vth3, so that the third transistor T3 is turned on, that is, the electrical connection between the control end of the second transistor T2 and the second node N2 is turned on. Wherein, Vth3 is the threshold voltage of the third transistor T3. In the third stage t3, the third transistor T3 is first turned on. The second input terminal IN receives the first low-level voltage VGL, and pulls down the voltage of the second node N2 through the turned-on first transistor T1 and the turned-on third transistor T3, thereby triggering the pull-down transistor Tn to turn on. At the moment when the pull-down transistor Tn is turned on, the voltage of the second node N2 is coupled and pulled down to the second low-level voltage VGL1 by the first capacitor C1. At this time, the gate-source voltage Vgs of the third transistor T3 is VGL - VGL1 > Vth3, so that the third transistor T3 is turned off, that is, the electrical connection between the control end of the second transistor T2 and the second node N2 is disconnected. That is to say, in the third stage t3, the third transistor T3 is first turned on and then turned off. In the fourth stage t4, the voltage of the second node N2 is the second low-level voltage VGL1, so that the third transistor T3 remains turned off.

[0085] Thus, the isolation unit 121 can only include the third transistor T3, and the circuit structure is simple.

[0086] As Figure 2 shown, in some embodiments, the gate driving unit GOA further includes a third input terminal CB. The third input terminal CB is used to receive a second clock signal CB. The first output control module 11 is also electrically connected to the first input terminal CK and the third input terminal CB. The first output control module 11 controls the voltage of the first node N1 to be the second high-level voltage VGH1 in the first stage t1 under the control of the first clock signal CK and the second clock signal CB, pulls down the voltage of the first node N1 in the second stage t2, and pulls up the voltage of the first node N1 in the third stage t3. As Figure 3As shown, the second clock signal CB is the first high-level voltage VGH in the first stage t1 and the third stage t3, and the first low-level voltage VGL in the second stage t2 and the fourth stage t4. In this embodiment, the second high-level voltage VGH1 is equal to the first high-level voltage VGH.

[0087] Thus, by controlling the first output control module 11 through the first clock signal CK and the second clock signal CB, it is possible to make the voltage of the first node N1 the second high-level voltage VGH1 in the first stage t1, pull down the voltage of the first node N1 in the second stage t2, and pull up the voltage of the first node N1 in the third stage t3. The control logic is simple and easy to implement.

[0088] like Figure 2 As shown, in some embodiments, the first output control module 11 includes a fourth transistor T4 and a fifth transistor T5.

[0089] The fourth transistor T4 includes a first connection terminal, a second connection terminal, and a control terminal. The first connection terminal of the fourth transistor T4 is used to receive the first high-level voltage VGH. The second connection terminal of the fourth transistor T4 is electrically connected to the first node N1. The control terminal of the fourth transistor T4 is electrically connected to the first input terminal CK.

[0090] The fifth transistor T5 includes a first connection terminal, a second connection terminal, and a control terminal. The first connection terminal of the fifth transistor T5 is electrically connected to the third input terminal CB, the second connection terminal of the fifth transistor T5 is electrically connected to the first node N1, and the control terminal of the fifth transistor T5 is electrically connected to the second node N2. In this embodiment, the control terminal of the fifth transistor T5 is electrically connected to the second node N2 through the third transistor T3.

[0091] The fourth transistor T4 is a P-type transistor, and the fifth transistor T5 is an N-type transistor.

[0092] In the third stage t3 and the fourth stage t4, the isolation unit 121 can also block the transmission of the second low-level voltage VGL1 to the control terminal of the fifth transistor T5, and can also protect the fifth transistor T5.

[0093] Thus, the first output control module 11 can include only two transistors, resulting in a simple circuit structure.

[0094] The following is combined with Figures 3-7 ,right Figure 2The workflow of the gate drive unit GOA shown is described in detail.

[0095] like Figure 3 As shown, the first clock signal CK is a low-level voltage VGL in the first stage t1 and the third stage t3, and a high-level voltage VGH in the second stage t2 and the fourth stage t4. The start signal IN is a high-level voltage VGH in the first stage t1, and a low-level voltage VGL in the second stage t2 to the fourth stage t4. The second clock signal CB is a high-level voltage VGH in the first stage t1 and the third stage t3, and a low-level voltage VGL in the second stage t2 and the fourth stage t4.

[0096] like Figure 4 As shown, in the first stage t1, the first transistor T1 turns on in response to the first clock signal CK being the first low-level voltage VGL, causing the second input terminal IN to output the start signal IN, which has a voltage of the first high-level voltage VGH, to the second node N2 through the turned-on first transistor T1 and the turned-on third transistor T3. The pull-down transistor Tn and the second transistor T2 both turn off in response to the voltage of the second node N2 being the first high-level voltage VGH. The fifth transistor T5 turns on in response to the voltage of the second node N2 being the first high-level voltage VGH, causing the third input terminal CB to output the second clock signal CB, which has a voltage of the first high-level voltage VGH, to the first node N1 through the turned-on fifth transistor T5. Simultaneously, the fourth transistor T4 turns on in response to the first clock signal CK being the first low-level voltage VGL, thereby outputting the first high-level voltage VGH received at its first connection terminal to the first node N1. The output transistor Tm turns off in response to the voltage of the first node N1 being the first high-level voltage VGH. At this time, based on the voltage holding characteristic of the first capacitor C1, the voltage of the gate drive signal output by the output terminal OUT is held to be the same as the voltage of the fourth stage t4 of the previous frame, which is the first low-level voltage VGL.

[0097] like Figure 5As shown, in the second stage t2, both the first transistor T1 and the fourth transistor T4 are turned off in response to the first clock signal CK being the first high-level voltage VGH. The second node N2 is floating, and the first capacitor C1, based on its voltage holding characteristic, maintains the voltage of the second node N2 at the first high-level voltage VGH, thereby keeping the pull-down transistor Tn and the second transistor T2 off, and keeping the fifth transistor T5 on. This allows the third input terminal CB to output the received second clock signal CB, which is the first low-level voltage VGL, to the first node N1 through the on-state fifth transistor T5. The output transistor Tm is turned on in response to the first node N1 being the first low-level voltage VGL, thereby allowing the first input terminal CK to output the received first clock signal CK, which is the first high-level voltage VGH, to the output terminal OUT through the on-state output transistor Tm. That is, the gate drive signal output by the output terminal OUT changes from the first low-level voltage VGL to the first high-level voltage VGH.

[0098] like Figure 6As shown, in the third stage t3, the fourth transistor T4 turns on in response to the first clock signal CK being the first low-level voltage VGL, thereby outputting the first high-level voltage VGH received at its first connection terminal to the first node N1. The output transistor Tm turns off in response to the voltage of the first node N1 being the first high-level voltage VGH. The first transistor T1 turns on in response to the first clock signal CK being the first low-level voltage VGL, causing the second input terminal IN to output the start signal IN, which is the first low-level voltage VGL, to the second node N2 through the turned-on first transistor T1 and the turned-on third transistor T3. The pull-down transistor Tn enters a critical conduction state in response to the second node N2 being at the first low-level voltage VGL. The pull-down transistor Tn in the critical conduction state attenuates the first low-level voltage VGL received at its second connection terminal, thereby the voltage output from the first connection terminal of the pull-down transistor Tn to the output terminal OUT is a third low-level voltage. At the instant the pull-down transistor Tn enters the critical conduction state, the voltage at the output terminal OUT jumps from the first high-level voltage VGH to the third low-level voltage. Based on its bootstrap characteristic, the first capacitor C1 couples the voltage at the second node N2 from the first low-level voltage VGL to the second low-level voltage VGL1, thereby fully turning on the pull-down transistor Tn and completely outputting the first low-level voltage VGL to the output terminal OUT. That is, the gate drive signal output by the output terminal OUT is rapidly pulled down from the first high-level voltage VGH to the first low-level voltage VGL. Simultaneously, the second transistor T2 turns on in response to the voltage at the second node N2 being the second low-level voltage VGL1, thereby outputting the first high-level voltage VGH received at its first connection terminal to the first node N1. The fifth transistor T5 turns off in response to the voltage at the second node N2 being the second low-level voltage VGL1. Specifically, after the voltage of the second node N2 is pulled down to the second low-level voltage VGL1, the gate-source voltage Vgs of the third transistor T3 = VGL - VGL1 > Vth3, thereby turning off the third transistor T3. That is, in the third stage t3, the third transistor T3 first turns on and then turns off.

[0099] like Figure 7As shown, in the fourth stage t4, both the first transistor T1 and the fourth transistor T4 are turned off in response to the first clock signal CK being the first high-level voltage VGH. The second node N2 is floating, and the first capacitor C1, based on its voltage holding characteristic, keeps the voltage of the second node N2 at the second low-level voltage VGL1, thereby keeping the pull-down transistor Tn on and keeping the third transistor T3 off. The control terminal of the second transistor T2 is floating, thus maintaining its state at the end of the third stage t3, i.e., the second transistor T2 remains on, continuously outputting the first high-level voltage VGH to the first node N1. The control terminal of the fifth transistor T5 is floating, thus the fifth transistor T5 remains in its state at the end of the third stage t3, i.e., remains off. At this time, the gate drive signal output by the output terminal OUT remains at the first low-level voltage VGL.

[0100] Please see Figure 8 , Figure 8 This is a second circuit structure diagram of the gate driving unit provided in an embodiment of this application. Figure 8 The gate drive unit shown is Figure 2 The circuit structures of the gate drive units shown are similar, with the only difference being the circuit structure of their first output control module 11.

[0101] Specifically, Figure 8 The gate drive unit GOA shown also includes a third input terminal CB, which is used to receive a second clock signal CB. The first output control module 11 is also electrically connected to the second input terminal IN and the third input terminal CB. Under the control of the second clock signal CB and the start signal IN, the first output control module 11 sets the voltage of the first node N1 to a second high-level voltage VGH1 in the first stage t1, pulls down the voltage of the first node N1 in the second stage t2, and pulls up the voltage of the first node N1 in the third stage t3.

[0102] In this embodiment, the second clock signal CB is the first high-level voltage VGH in the first stage t1 and the third stage t3, and the first low-level voltage VGL in the second stage t2 and the fourth stage t4. The start signal IN is the first high-level voltage VGH in the first stage t1, and the first low-level voltage VGL in the second stage t2 to the fourth stage t4. In this embodiment, the second high-level voltage VGH1 is lower than the first high-level voltage VGH.

[0103] Thus, by controlling the first output control module 11 through the second clock signal CB and the start signal IN, it is possible to make the voltage of the first node N1 the second high-level voltage VGH1 in the first stage t1, pull down the voltage of the first node N1 in the second stage t2, and pull up the voltage of the first node N1 in the third stage t3. The control logic is simple and easy to implement.

[0104] in, Figure 8 The circuit structures of the second output control module 13 and the pull-down control module 12 in the gate drive unit GOA shown have been... Figure 2 The embodiments shown are described in detail and will not be repeated here.

[0105] like Figure 8 As shown, in some embodiments, the first output control module 11 includes a sixth transistor T6, a seventh transistor T7, a second capacitor C2, and a third capacitor C3.

[0106] The sixth transistor T6 includes a first connection terminal, a second connection terminal, and a control terminal. The first connection terminal of the sixth transistor T6 is electrically connected to the third input terminal CB, and the control terminal of the sixth transistor T6 is electrically connected to the second input terminal IN. Both the sixth transistor T6 and the seventh transistor T7 are P-type transistors.

[0107] The seventh transistor T7 includes a first connection terminal, a second connection terminal, and a control terminal. The second connection terminal of the seventh transistor T7 is electrically connected to the first node N1, and the control terminal of the seventh transistor T7 is electrically connected to the second connection terminal of the sixth transistor T6.

[0108] The second capacitor C2 is electrically connected between the first connection terminal of the seventh transistor T7 and the control terminal of the seventh transistor T7.

[0109] The third capacitor C3 is electrically connected between the first connection terminal of the output transistor Tm and the control terminal of the seventh transistor T7. Specifically, during the first stage t1, the third capacitor C3, based on its voltage holding characteristic, maintains the voltage of the first node N1 at the same level as the voltage of the previous frame's fourth stage t4, which is the first high-level voltage VGH.

[0110] Thus, the first output control module 11 can include only two transistors, resulting in a simple circuit structure.

[0111] In some embodiments, the third capacitor C3 is the parasitic capacitance of the output transistor Tm.

[0112] Therefore, there is no need to add an additional capacitor between the first connection terminal and the control terminal of the output transistor Tm, making the circuit structure simpler.

[0113] In other embodiments, in order to improve the coupling capability of the third capacitor C3, the third capacitor C3 may also be a capacitor composed of the parasitic capacitance of the output transistor Tm connected in parallel with other capacitors.

[0114] The following is combined with Figures 9-13 ,right Figure 8 The workflow of the gate drive unit GOA shown is described in detail.

[0115] like Figure 9 As shown, the first clock signal CK is a low-level voltage VGL in the first stage t1 and the third stage t3, and a high-level voltage VGH in the second stage t2 and the fourth stage t4. The start signal IN is a high-level voltage VGH in the first stage t1, and a low-level voltage VGL in the second stage t2 to the fourth stage t4. The second clock signal CB is a high-level voltage VGH in the first stage t1 and the third stage t3, and a low-level voltage VGL in the second stage t2 and the fourth stage t4.

[0116] like Figure 10As shown, in the first stage t1, the first transistor T1 is turned on in response to the first clock signal CK being the first low-level voltage VGL, causing the second input terminal IN to output the received start signal IN, which is the first high-level voltage VGH, to the second node N2 through the turned-on first transistor T1 and the turned-on third transistor T3. The pull-down transistor Tn and the second transistor T2 are both turned off in response to the voltage of the second node N2 being the first high-level voltage VGH. The sixth transistor T6 is turned off in response to the voltage of the second input terminal IN being the first high-level voltage VGH. The first terminal (electrically connected to the control terminal of the seventh transistor T7) and the second terminal (electrically connected to the first connection terminal of the seventh transistor T7) of the second capacitor C2 are both floating, so that the second capacitor C2, based on the voltage holding characteristic, keeps the seventh transistor T7 in the state of the previous frame, that is, in the on state. At this time, the voltage VC2 between the first and second terminals of the second capacitor C2 remains the same as that in the fourth stage t4 of the previous frame. Specifically, VC2 = VGH - (VGL - Vth7), where Vth7 is the threshold voltage of the seventh transistor T7. Taking VGH = 7V, VGL = -7V, and Vth7 = -2V as an example, VC2 = 12V. At the instant of entering the first stage t1, because the first clock signal CK jumps from VGH to VGL, the third capacitor C3 will couple down the voltage of the first node N1 from the first high-level voltage VGH to the second high-level voltage VGH1, for example, VGH1 = 4V. Simultaneously, the voltage change of the first node N1 will be coupled to the control terminal of the seventh transistor T7 through the conducting seventh transistor T7 and the second capacitor C2. The output transistor Tm turns off in response to the voltage of the first node N1 being the second high-level voltage VGH1. At this time, the gate drive signal output by the output terminal OUT remains the same as the voltage of the fourth stage t4 of the previous frame, which is the first low-level voltage VGL.

[0117] like Figure 11As shown, in the second stage t2, the first transistor T1 turns off in response to the first clock signal CK being at the first high-level voltage VGH. The second node N2 floats, and the first capacitor C1 causes the second node N2 to maintain the first high-level voltage VGH based on its voltage holding characteristic, thereby keeping the pull-down transistor Tn and the second transistor T2 turned off. The sixth transistor T6 turns on in response to the voltage of the second input terminal IN being at the first low-level voltage VGL, so that the third input terminal CB outputs the second clock signal CB, which is at the first low-level voltage VGL and received, to the control terminal of the seventh transistor T7 through the turned-on sixth transistor T6, thereby causing the seventh transistor T7 to turn on. Further, the third input terminal CB outputs the second clock signal CB, which is at the first low-level voltage VGL and received, to couple and pull down the voltage of the first node N1 to the fourth low-level voltage VGL3 through the turned-on sixth transistor T6, the second capacitor C2, and the turned-on seventh transistor T7. For example, VGL3 = 1V. At this time, the gate-source voltage Vgs of the output transistor Tm = VGL3 - VGH < Vthm. Thus, the output transistor Tm turns on, enabling the first input terminal CK to output the first clock signal CK, which is at the first high-level voltage VGH and received, to the output terminal OUT through the turned-on output transistor Tm, that is, the voltage of the gate drive signal output by the output terminal OUT is pulled up to the first high-level voltage VGH.

[0118] As Figure 12As shown, in the third stage t3, the first transistor T1 turns on in response to the first clock signal CK being the first low-level voltage VGL, causing the second input terminal IN to output the received start signal IN, which is the first low-level voltage VGL, to the second node N2 through the turned-on first transistor T1 and the turned-on third transistor T3. The second transistor T2 turns on in response to the voltage of the second node N2 being the second low-level voltage VGL1, thereby outputting the first high-level voltage VGH received at its first connection terminal to the first node N1. The sixth transistor T6 turns on in response to the start signal IN being the first low-level voltage VGL, causing the third input terminal CB to output the received second clock signal CB, which is the first high-level voltage VGH, to the control terminal of the seventh transistor T7 through the turned-on sixth transistor T6, thereby turning off the seventh transistor T7. The output transistor Tm turns off in response to the voltage of the first node N1 being the first high-level voltage VGH. Simultaneously, in response to the second node N2 being at the first low-level voltage VGL, the pull-down transistor Tn enters a critical conduction state. While in this critical conduction state, the pull-down transistor Tn attenuates the first low-level voltage VGL received at its second connection terminal, resulting in the voltage output from the first connection terminal of the pull-down transistor Tn to the output terminal OUT being a third low-level voltage. At the instant the pull-down transistor Tn enters the critical conduction state, the voltage at the output terminal OUT jumps from the first high-level voltage VGH to the third low-level voltage. The first capacitor C1, based on its bootstrap characteristic, couples the voltage of the second node N2 from the first low-level voltage VGL to the second low-level voltage VGL1, thereby fully turning on the pull-down transistor Tn and completely outputting the first low-level voltage VGL to the output terminal OUT. In other words, the gate drive signal output by the output terminal OUT is rapidly pulled down from the first high-level voltage VGH to the first low-level voltage VGL. Specifically, after the voltage of the second node N2 is pulled down to the second low-level voltage VGL1, the gate-source voltage Vgs of the third transistor T3 = VGL - VGL1 > Vth3, thereby turning off the third transistor T3. That is, in the third stage t3, the third transistor T3 first turns on and then turns off.

[0119] like Figure 13As shown, in the fourth stage t4, the first transistor T1 is turned off in response to the first clock signal CK being the first high-level voltage VGH. The second node N2 is floating, and the first capacitor C1, based on its voltage holding characteristic, keeps the second node N2 at the second low-level voltage VGL1, thereby keeping the pull-down transistor Tn on and the third transistor T3 off. The control terminal of the second transistor T2 is floating, thus the second transistor T2 remains in its state at the end of the third stage t3, i.e., it remains on, continuously outputting the first high-level voltage VGH to the first node N1. The sixth transistor T6 is turned on in response to the first clock signal CK being the first low-level voltage VGL, thereby causing the third input terminal CB to output the received second clock signal CB, which is the first low-level voltage VGL, to the control terminal of the seventh transistor T7 through the turned-on sixth transistor T6, thereby turning on the seventh transistor T7. At this time, the gate drive signal output by the output terminal OUT remains at the first low-level voltage VGL.

[0120] It should be noted that, Figure 2 and Figure 8 The gate drive units (GOAs) shown each contain only 7 transistors. The small number of transistors and simple circuit structure are beneficial for the narrow bezel design of the display panel.

[0121] The transistors in this application may be LTPS (Low Temperature Poly-Silicon), LTPO (Low Temperature Polycrystalline Oxide), or other types of transistors, which are not limited here.

[0122] Please see Figure 14 This application also provides a gate driving circuit 100, which includes at least two gate driving units GOA, wherein the gate driving unit GOA is the gate driving unit described in any of the above embodiments. The gate driving units GOA in the gate driving circuit 100 are cascaded.

[0123] In some embodiments, the gate driving circuit 100 further includes a first signal line S1, a second signal line S2, a third signal line S3, and a fourth signal line S4. The first signal line S1 transmits a first signal S1, the second signal line S2 transmits a second signal S2, the third signal line S3 transmits a third signal S3, and the fourth signal line S4 transmits a fourth signal S4. Figure 15As shown, the first signal S1 to the fourth signal S4 are all clock signals with the same period, and the latter signal lags behind the former signal by a preset time interval.

[0124] The gate driving circuit 100 includes n gate driving units GOA, wherein when a gate driving unit GOA includes a third input terminal CB, the first input terminal CK of the 4*i+1th gate driving unit GOA is electrically connected to the first signal line S1, and the third input terminal CB of the 4*i+1th gate driving unit GOA is electrically connected to the second signal line S2. The first input terminal CK of the 4*i+2th gate driving unit GOA is electrically connected to the second signal line S2, and the third input terminal CB of the 4*i+2th gate driving unit GOA is electrically connected to the third signal line S3. The first input terminal CK of the 4*i+3th gate driving unit GOA is electrically connected to the third signal line S3, and the third input terminal CB of the 4*i+3rd gate driving unit GOA is electrically connected to the fourth signal line S4. The first input terminal CK of the 4*i+4th gate driving unit GOA is electrically connected to the fourth signal line S4, and the third input terminal CB of the 4*i+4th gate driving unit GOA is electrically connected to the first signal line S1. Where i≥0, n≥4*i+4.

[0125] The first gate drive unit GOA receives the start signal STV at its second output terminal IN. The second output terminal IN of the (m+1)th gate drive unit GOA is electrically connected to the output terminal OUT of the mth gate drive unit GOA, where m≥0 and n≥m+1.

[0126] Thus, the n gate drive units GOA can share the four clock signals S1 to S4 as the first clock signal CK and the second clock signal CB, resulting in simple control logic.

[0127] In addition, such as Figure 15 As shown, by setting the four sets of signals (S1, S2), (S2, S3), (S3, S4), and (S4, S1) to be used sequentially as the first clock signal CK and the second clock signal CB for each gate driving unit GOA, the gate driving signal output by each gate driving unit GOA can be maintained at the first high-level voltage VGH for a duration of 4H. Here, 1H represents the scan duration of a row of pixel units P.

[0128] Please refer to it again. Figure 14This application also provides a display panel 107, which includes at least two rows of pixel units P and the gate driving circuit 100 described in any of the above embodiments. The at least two gate driving units GOA are electrically connected to the at least two rows of pixel units P in a one-to-one correspondence, and are used to output gate driving signals to the at least two rows of pixel units P to drive the at least two rows of pixel units P to emit light.

[0129] Please see Figure 16 This application also provides an electronic device 1, which includes the display panel 107 described in any of the above embodiments.

[0130] For example, the electronic device 1 can be referred to as a terminal or a terminal device. The specific product form of the electronic device 1 can be a mobile phone, wearable device (such as a smart bracelet, smartwatch, earphone, etc.), tablet computer, laptop computer, handheld computer, laptop computer, ultra-mobile personal computer (UMPC), cellular phone, personal digital assistant (PDA), augmented reality (AR) / virtual reality (VR) device, etc. It can also be a television, large screen, printer, projector, etc. The embodiments of this application do not limit this.

[0131] Taking a mobile phone as an example, the electronic device 1 may further include a processor 101, a memory 102, a wireless communication module 103, a mobile communication module 104, an antenna 103A, an antenna 104A, a power switch 105, a sensor module 106, etc. The wireless communication module 103 may include a Wi-Fi communication module, a Bluetooth communication module, etc. All of the above components can transmit data via a bus.

[0132] Processor 101 may include one or more processing units, such as application processors (APs), modems, graphics processing units (GPUs), image signal processors (ISPs), controllers, video codecs, digital signal processors (DSPs), baseband processors, and / or neural network processing units (NPUs). These different processing units may be independent devices or integrated into one or more processors.

[0133] Memory 102 can be used to store computer executable program code, which may include instructions. Processor 101 executes various functional applications and data processing of electronic device 1 by running the instructions stored in memory 102. Memory 102 may include a program storage area and a data storage area. In specific implementations, memory 102 may include high-speed random access memory, and may also include non-volatile memory, such as one or more disk storage devices, flash memory devices, or other non-volatile solid-state storage devices.

[0134] The wireless communication function of electronic device 1 can be implemented through antenna 103A, antenna 104A, mobile communication module 104, wireless communication module 103, modem, and baseband processor.

[0135] Antennas 103A and 104A can be used to transmit and receive electromagnetic wave signals. Each antenna in electronic device 1 can be used to cover one or more communication frequency bands. Different antennas can also be reused to improve antenna utilization.

[0136] The mobile communication module 104 can provide solutions for wireless communication, including 2G / 3G / 4G / 5G, applied to the electronic device 1. The mobile communication module 104 may include at least one filter, switch, power amplifier, low noise amplifier (LNA), etc. The mobile communication module 104 can receive electromagnetic waves via antenna 104A, and perform filtering, amplification, and other processing on the received electromagnetic waves before transmitting them to a modem for demodulation. The mobile communication module 104 can also amplify the signal modulated by the modem and convert it into electromagnetic waves for radiation via antenna 104A. In some embodiments, at least some functional modules of the mobile communication module 104 may be housed in the processor 101. In some embodiments, at least some functional modules of the mobile communication module 104 and at least some modules of the processor 101 may be housed in the same device.

[0137] A modem may include a modulator and a demodulator. The modulator modulates a low-frequency baseband signal to be transmitted into a mid-to-high frequency signal. The demodulator demodulates the received electromagnetic wave signal into a low-frequency baseband signal. The demodulator then transmits the demodulated low-frequency baseband signal to a baseband processor for processing. After processing by the baseband processor, the low-frequency baseband signal is passed to an application processor. The application processor outputs sound signals through an audio device or displays images or videos through a display panel 107.

[0138] The wireless communication module 103 can provide solutions for wireless communication applications on the electronic device 1, including Wi-Fi, Bluetooth (BT), Global Navigation Satellite System (GNSS), Frequency Modulation (FM), Near Field Communication (NFC), and Infrared (IR). The wireless communication module 103 can be one or more devices integrating at least one communication processing module. The wireless communication module 103 receives electromagnetic waves via antenna 103A, performs frequency modulation and filtering of the electromagnetic wave signal, and sends the processed signal to processor 101. The wireless communication module 103 can also receive signals to be transmitted from processor 101, perform frequency modulation and amplification, and convert them into electromagnetic waves for radiation via antenna 103A.

[0139] In some embodiments, antenna 104A of electronic device 1 is coupled to mobile communication module 104, and antenna 103A is coupled to wireless communication module 103, enabling electronic device 1 to communicate with networks and other devices via wireless communication technology. The wireless communication technology may include Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Code Division Multiple Access (CDMA), Wideband Code Division Multiple Access (WCDMA), Time Division Code Division Multiple Access (TD-SCDMA), Long Term Evolution (LTE), BT, GNSS, WLAN, NFC, FM, and / or IR technologies, etc. The GNSS may include satellite-based augmentation systems (SBAS), global navigation satellite system (GLONASS), BeiDou navigation satellite system (BDS), Quasi-Zenith satellite system (QZSS), and / or satellite-based augmentation systems (SBAS).

[0140] In summary, the above description is merely an embodiment of the technical solution of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, improvements, etc., made based on the disclosure of this application should be included within the scope of protection of this application.

Claims

1. A gate driving unit, characterized in that, The gate driving unit operates at least sequentially in a first stage, a second stage, and a third stage during each driving cycle. The gate driving unit includes: A first input terminal is used to receive a first clock signal; wherein the first clock signal is a first low-level voltage in the first stage and the third stage, and a first high-level voltage in the second stage; First node; Second node; The output terminal is used to output the gate drive signal; An output transistor includes a first connection terminal, a second connection terminal, and a control terminal; the first connection terminal of the output transistor is electrically connected to the first input terminal, the second connection terminal of the output transistor is electrically connected to the output terminal, and the control terminal of the output transistor is electrically connected to the first node. A pull-down transistor includes a first connection terminal, a second connection terminal, and a control terminal; wherein, the first connection terminal of the pull-down transistor is electrically connected to the output terminal, the second connection terminal of the pull-down transistor is used to receive the first low-level voltage, the control terminal of the pull-down transistor is electrically connected to the second node, and a first capacitor exists between the first connection terminal and the control terminal of the pull-down transistor; both the output transistor and the pull-down transistor are P-type transistors; The first output control module is electrically connected to the first node; The pull-down control module is electrically connected to the second node; In the first stage, the first output control module sets the voltage of the first node to a second high-level voltage, thereby turning off the output transistor, and the pull-down control module pulls the voltage of the second node up to the first high-level voltage, thereby turning off the pull-down transistor, and the gate drive signal remains at the voltage of the last stage in the previous drive cycle; wherein, the second high-level voltage is lower than or equal to the first high-level voltage; In the second stage, the first output control module pulls down the voltage of the first node, causing the output transistor to turn on. The output terminal obtains a first clock signal at the first high level voltage from the first input terminal through the turned-on output transistor, thereby outputting the gate drive signal at the first high level voltage. The first capacitor causes the second node to maintain the first high level voltage, thereby keeping the pull-down transistor off. In the third stage, the first output control module pulls up the voltage of the first node, causing the output transistor to turn off. The pull-down control module and the first capacitor work together to pull down the voltage of the second node to a second low-level voltage, causing the pull-down transistor to be fully turned on. This allows the output terminal to obtain the first low-level voltage through the turned-on pull-down transistor and output the gate drive signal of the first low-level voltage. The second low-level voltage is lower than the first low-level voltage.

2. The gate driving unit according to claim 1, characterized in that, The gate driving unit further includes a second output control module, which is electrically connected to the first node and the pull-down control module. In each driving cycle, the gate driving unit operates in a fourth stage after the third stage. In the third stage, the second output control module outputs the first high-level voltage to the first node under the control of the pull-down control module, thereby turning off the output transistor. In the fourth stage, the second output control module continues to output the first high-level voltage to the first node, thereby keeping the output transistor off, and thus keeping the gate drive signal output by the output terminal at the first low-level voltage.

3. The gate driving unit according to claim 2, characterized in that, The gate driving unit further includes a second input terminal, which is used to receive a start signal, wherein the start signal is the first high-level voltage in the first stage and the first low-level voltage in the third stage; The pull-down control module is also electrically connected to the first input terminal and the second input terminal. In the first stage, under the control of the first clock signal, the pull-down control module outputs the start signal, which is the first high-level voltage received at the second input terminal, to the second node, thereby pulling up the voltage of the second node to the first high-level voltage. In the third stage, under the control of the first clock signal, the pull-down control module also outputs the start signal, which is the first low-level voltage received at the second input terminal, to the second node, thereby working with the first capacitor to pull down the voltage of the second node to the second low-level voltage.

4. The gate driving unit according to claim 3, characterized in that, The pull-down control module includes a first transistor, which includes a first connection terminal, a second connection terminal, and a control terminal. The first connection terminal of the first transistor is electrically connected to the second input terminal, the second connection terminal of the first transistor is electrically connected to the second node, and the control terminal of the first transistor is electrically connected to the first input terminal. The first transistor is a P-type transistor.

5. The gate driving unit according to claim 4, characterized in that, The second output control module includes a second transistor; the second transistor includes a first connection terminal, a second connection terminal, and a control terminal, the control terminal of the second transistor is electrically connected to the second node, the first connection terminal of the second transistor is used to receive the first high-level voltage, and the second connection terminal of the second transistor is electrically connected to the first node; wherein, the second transistor is a P-type transistor.

6. The gate driving unit according to claim 5, characterized in that, The pull-down control module also includes an isolation unit, which is electrically connected between the control terminal of the second transistor and the second node. The isolation unit is used to disconnect the electrical connection between the control terminal of the second transistor and the second node when the voltage of the second node is the second low-level voltage, so as to protect the second transistor.

7. The gate driving unit according to claim 6, characterized in that, The isolation unit includes a third transistor, which includes a first connection terminal and a second connection terminal. The first connection terminal of the third transistor is electrically connected to the second connection terminal of the first transistor, and the second connection terminal of the third transistor is electrically connected to the second node. The control terminal of the third transistor is used to receive the first low-level voltage. The third transistor is a P-type transistor.

8. The gate driving unit according to claim 3, characterized in that, The gate driving unit further includes a third input terminal for receiving a second clock signal; the first output control module is also electrically connected to the first input terminal and the third input terminal. Under the control of the first clock signal and the second clock signal, the first output control module makes the voltage of the first node a second high-level voltage in the first stage, pulls down the voltage of the first node in the second stage, and pulls up the voltage of the first node in the third stage; wherein, the second clock signal is the first high-level voltage in the first stage and the third stage, and the first low-level voltage in the second stage.

9. The gate driving unit according to claim 8, characterized in that, The first output control module includes: The fourth transistor includes a first connection terminal, a second connection terminal, and a control terminal. The first connection terminal of the fourth transistor is used to receive the first high-level voltage. The second connection terminal of the fourth transistor is electrically connected to the first node. The control terminal of the fourth transistor is electrically connected to the first input terminal. The fifth transistor includes a first connection terminal, a second connection terminal, and a control terminal. The first connection terminal of the fifth transistor is electrically connected to the third input terminal, the second connection terminal of the fifth transistor is electrically connected to the first node, and the control terminal of the fifth transistor is electrically connected to the second node. The fourth transistor is a P-type transistor, and the fifth transistor is an N-type transistor.

10. The gate driving unit according to claim 3, characterized in that, The gate driving unit further includes a third input terminal for receiving a second clock signal; the first output control module is also electrically connected to the second input terminal and the third input terminal. Under the control of the second clock signal and the start signal, the first output control module makes the voltage of the first node a second high-level voltage in the first stage, pulls down the voltage of the first node in the second stage, and pulls up the voltage of the first node in the third stage; wherein, the second clock signal is the first high-level voltage in the first stage and the third stage, and the first low-level voltage in the second stage.

11. The gate driving unit according to claim 10, characterized in that, The first output control module includes: The sixth transistor includes a first connection terminal, a second connection terminal, and a control terminal. The first connection terminal of the sixth transistor is electrically connected to the third input terminal, and the control terminal of the sixth transistor is electrically connected to the second input terminal. The seventh transistor includes a first connection terminal, a second connection terminal, and a control terminal. The second connection terminal of the seventh transistor is electrically connected to the first node, and the control terminal of the seventh transistor is electrically connected to the second connection terminal of the sixth transistor. The second capacitor is electrically connected between the first connection terminal of the seventh transistor and the control terminal of the seventh transistor. The third capacitor is electrically connected between the first connection terminal of the output transistor and the control terminal of the output transistor. Both the sixth transistor and the seventh transistor are P-type transistors.

12. The gate driving unit according to claim 1, characterized in that, The first capacitor is the parasitic capacitance of the pull-down transistor.

13. A gate driving circuit, characterized in that, It includes at least two gate driving units as described in any one of claims 1 to 12, wherein the gate driving units in the gate driving circuit are cascaded.

14. The gate driving circuit according to claim 13, characterized in that, The gate driving circuit further includes a first signal line, a second signal line, a third signal line, and a fourth signal line; wherein the first signal line is used to transmit a first signal, the second signal line is used to transmit a second signal, the third signal line is used to transmit a third signal, and the fourth signal line is used to transmit a fourth signal; wherein the first signal to the fourth signal are all clock signals with the same period, and the subsequent signal lags behind the previous signal by a preset time interval. The gate driving circuit includes n gate driving units, wherein, when a gate driving unit includes a third input terminal, the first input terminal of the 4*i+1th gate driving unit is electrically connected to the first signal line, and the third input terminal of the 4*i+1th gate driving unit is electrically connected to the second signal line; the first input terminal of the 4*i+2th gate driving unit is electrically connected to the second signal line, and the third input terminal of the 4*i+2th gate driving unit is electrically connected to the third signal line; the first input terminal of the 4*i+3th gate driving unit is electrically connected to the third signal line, and the third input terminal of the 4*i+3rd gate driving unit is electrically connected to the fourth signal line; the first input terminal of the 4*i+4th gate driving unit is electrically connected to the fourth signal line, and the third input terminal of the 4*i+4th gate driving unit is electrically connected to the first signal line; wherein, i≥0, n≥4*i+4.

15. A display panel, characterized in that, include: At least two rows of pixel units; The gate driving circuit as described in claim 13 or 14; the at least two gate driving units are electrically connected to the at least two rows of pixel units in a one-to-one correspondence, and are used to output gate driving signals to the at least two rows of pixel units to drive the at least two rows of pixel units to emit light.

16. An electronic device, characterized in that, Includes the display panel as described in claim 15.

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