In-memory computing array system based on ferroelectric domain walls and its information processing method

Abstract

This invention relates to an in-memory computing array system based on ferroelectric domain walls and its information processing method. The single-layer array of the system logically consists of a physical layer, a logic layer, and an application layer. The physical layer is a cross-array composed of ferroelectric thin-film device units, used to realize the complete neuron integration and firing process: current accumulation is achieved through pulse-driven evolution of conductive domain walls, charge injection generates current spikes to complete signal firing, and the shielding effect generated by charged defect migration achieves physical suppression of spontaneous current zeroing. When the logic layer receives external voltage pulse sequence excitation, it sequentially performs signal accumulation integration, intrinsic negative differential resistance effect firing, and physical self-suppression zeroing operations, utilizing the dynamic characteristics of the device units for computation. The application layer, based on the current spike signal and its spatiotemporal topological relationship, completes target extraction, classification, or behavior recognition. Compared with existing technologies, this invention has advantages such as ultra-low power consumption and microsecond-level response.

Description

Technical Field

[0001] This invention relates to the fields of semiconductor integrated circuits, memory and neuromorphic computing technologies, and in particular to a memory-computing integrated array system based on ferroelectric domain walls and its information processing method. Background Technology

[0002] With the rapid popularization of artificial intelligence, edge computing, and massive sensor networks, the demand for real-time processing of spatiotemporal information tasks such as high-speed video streams, high-frequency bioelectrical signals, and dynamic gesture recognition has exploded. These application scenarios require terminal devices to be able to process and classify unstructured, sparsely distributed dynamic data at nanosecond to millisecond speeds. However, traditional image recognition systems are deeply limited by the von Neumann architecture, in which sensors, memory, and processors are highly separated in physical space. This means that the perceived signals must undergo cumbersome analog-to-digital conversion and bus transmission before entering the computing unit. This inevitably encounters a severe "memory wall" bottleneck when processing high-bandwidth spatiotemporal data, resulting in huge data transfer energy consumption, processing latency, and high hardware costs. In order to break through this physical limit, in-memory computing and neuromorphic computing architectures have become the cutting-edge directions pursued by academia and industry. They attempt to completely subvert the traditional computing paradigm by simulating the low power consumption, high parallelism, and event-driven characteristics of biological neural networks. In in-memory computing solutions, leveraging the unique polarization reversal properties and rich domain structures of ferroelectric materials to achieve neuromorphic computing shows great potential. Devices based on the conductivity of ferroelectric domain walls, in particular, possess ultra-high integration density, nanosecond-level response speed, and excellent non-volatility due to their conductive channels located at the nanoscale domain wall interface. They are considered core candidates for realizing highly integrated synapses and neurons. For example, Chinese patent CN121001560A discloses a ferroelectric domain wall neural synapse device, its control method, and a neural network device. However, current research on ferroelectric domain wall devices and their array applications, similar to this technology, still faces technical challenges such as complex system integration, difficulty in achieving true full intrinsic physical computing, and a lack of automatic extraction and background suppression of spatiotemporal features. Furthermore, issues such as impulse response characteristics, consistent firing thresholds, and stable self-suppression time windows also severely restrict the key engineering obstacles for the industrial application of neuromorphic chips. The specific reasons are as follows: First, the core computational logic of biological neurons includes the time integration of signals, threshold firing, and self-inhibition after firing, i.e., the refractory period. Most existing ferroresistive switching devices can only achieve single storage or simple continuous conductance adjustment functions, lacking a complete intrinsic dynamic evolution process. To simulate the complete neuronal pulse timing logic, it is often necessary to construct complex external digital or analog CMOS control circuits for assistance. This not only negates the natural advantages of resistive switching devices in terms of integration and power consumption, but also greatly increases the complexity and area overhead of system integration, making it difficult to achieve true full intrinsic physical computation.

[0003] Secondly, the automatic extraction of spatiotemporal features and background suppression are the core challenges of brain-like vision. Traditional systems still heavily rely on complex differential algorithms, convolution operations, or deep learning models for post-processing. At the physical level, there is still a lack of mature and robust physical implementation solutions for precisely controlling the formation of ferroelectric domain walls, the injection and capture of charge carriers, and the migration and distribution of charged defects (such as oxygen vacancies), and for using these multi-field coupled micro-dynamic processes to directly filter out static interference, identify motion trajectories, and extract dynamic edge envelopes within the array.

[0004] Furthermore, in terms of large-scale array integration, ferroelectric domain wall devices face serious challenges in performance consistency and process robustness. Since the generation and annihilation of domain walls have a certain degree of randomness, ensuring that thousands of computing units in the array exhibit highly uniform impulse response characteristics, consistent firing thresholds, and stable self-suppression time windows is a key engineering obstacle restricting the industrial application of ferroelectric neuromorphic chips. At the same time, how to achieve true event-driven operation logic while maintaining extremely high sensitivity, so that inactive regions can be automatically shut down based on the intrinsic properties of materials rather than relying on an external power management system, thereby reducing system power consumption to an extremely low level, is also a technical high ground that urgently needs to be broken through in the current field of in-memory computing technology. Summary of the Invention

[0005] The purpose of this invention is to address the "memory wall" bottleneck caused by the separation of sensing, storage and computing units in the existing von Neumann computing architecture, as well as the problems of high energy consumption, high latency and high complexity of back-end algorithms faced by traditional image processing systems when processing high-frequency spatiotemporal information. The invention provides a memory-computing integrated array system based on ferroelectric domain walls and its information processing method. It aims to utilize the intrinsic multi-field coupling dynamics of ferroelectric thin films to directly realize the nonlinear integration, saliency feature emission and self-suppression zeroing of signals at the physical level, thereby constructing an intrinsic neuromorphic computing hardware with ultra-low power consumption and microsecond-level response.

[0006] The objective of this invention can be achieved through the following technical solutions: A memory computing array system based on ferroelectric domain walls, wherein the single-layer array of the system logically consists of a physical layer, a logic layer, and an application layer, wherein... The physical layer is a cross array composed of M×N ferroelectric thin film device units, where M and N are both greater than or equal to 2. Each device unit has the characteristics of conductive domain wall evolution induced by electric field, instantaneous charge injection, and formation of charged defect dynamics, which are used to realize the complete neuron integration and firing process: current accumulation is realized by driving the evolution of conductive domain walls through pulses, current spikes are generated by charge injection to complete signal firing, and the shielding effect generated by charged defect migration is combined to realize the physical suppression of the current spontaneously returning to zero. When the logic layer receives an external voltage pulse sequence excitation, it performs signal accumulation and integration, intrinsic negative differential resistance (NDR) emission, and physical self-inhibition to zero operations in a time sequence without the intervention of the external control circuit, and performs calculations using the dynamic characteristics of the device unit. The application layer intrinsically performs target extraction, classification, or behavior recognition at the physical level based on the current spike signal and its spatiotemporal topological relationship generated after processing by the logic layer.

[0007] The system utilizes the microscopic physical evolution of ferroelectric thin-film device units to achieve the following three-stage intrinsic calculation: Integration stage: Under the initial pulse drive, the electric field induces the formation of charged domain walls, so that the unit conductance exhibits a step-like non-volatile integral with the input pulse; Release phase: When the domain wall evolution reaches the intrinsic trigger threshold, the NDR effect is triggered by the interface barrier modulation induced by polarization reversal, releasing the instantaneous current spike. Suppression phase: Under continuous excitation after the release phase, the output current spontaneously drops to zero by utilizing the shielding effect generated by the migration of charged defects or the complete flipping of domain configuration, thereby realizing the automatic shutdown of the computing channel.

[0008] The system selectively filters the spatiotemporal characteristic frequencies of target behavior by adjusting the frequency, pulse width, or amplitude of the input pulse and combining this with the intrinsic physical relaxation time of the device units. Specifically, this includes: Time-domain filtering based on frequency and relaxation time: The system achieves filtering by adjusting the frequency of the input pulse sequence and utilizing the dynamic competition between the time interval between adjacent pulses and the relaxation time of the conductive domain walls induced inside the device unit after the external electric field is removed. The system uses an energy threshold selection mechanism based on pulse width and amplitude to control the energy density injected into the device. When the amplitude or pulse width of the input pulse is lower than the intrinsic trigger threshold, the device unit only performs non-volatile conductance integral accumulation at the physical level and does not enter the NDR release state. When the amplitude or pulse width of the input pulse reaches or exceeds the intrinsic trigger threshold and the pulse frequency matches the relaxation time, the system triggers the NDR effect and releases the current spike, thereby completing the locking of specific spatiotemporal characteristic frequency targets and the physical shielding of background noise.

[0009] The size of the cross array is scalable: For small-scale arrays of 2×2 and above but less than 64×64, the in-memory computing array system acts as an intrinsic logic gate or alarm trigger, directly outputting a response to a specific frequency signal. For large-scale arrays of 64×64 and above, the in-memory computing array system serves as a spatiotemporal feature processor, utilizing numerous units to achieve multi-target, complex morphological analysis.

[0010] The ferroelectric thin film device unit is selected from ferroelectric materials with in-plane polarization components, including but not limited to any one or a combination of bismuth ferrite, bismuth ferrite doped with rare earth elements, lead zirconate titanate, lithium tantalate, or lithium niobate, or a heterostructure of multiple materials.

[0011] The system utilizes the implicit computing power of the Crossbar architecture and the coupling of device integrated power supply logic to achieve parallel spatial filtering function. Specifically, when processing video streams or sensor array signals, the input pulse and the array conductance matrix interact at the intersection. Based on the suppression characteristics of ferroelectric domain wall device units, pixels in the static background or inside objects automatically turn off power consumption due to physical charge shielding or defect accumulation, exhibiting a high impedance state.

[0012] Each device unit adopts a vertical structure, which includes, from bottom to top, a substrate, a bottom electrode thin film layer, a ferroelectric thin film layer, and a top electrode. The bottom electrode thin film layer is fabricated as a horizontally extending word line, and the top electrode is fabricated as a vertically arranged bit line.

[0013] The system possesses non-volatile spatiotemporal storage characteristics: the conductance state generated during the integration phase can still be maintained even without a power supply. The system utilizes this non-volatility to accumulate discontinuous spatiotemporal events across time windows, thereby maintaining computational continuity even under extremely low duty cycle signals.

[0014] An information processing method based on the system, the method comprising the following behavioral patterns: Target extraction mode: Utilize the physical suppression characteristics of device units to shield static background and internal signals, and capture the set of unit coordinates in the firing state in real time, thereby separating the spatial geometry or edge contour of the target at the physical level. Classification and recognition mode: By utilizing the sensitivity differences of the system dynamic response to different input features, the target category is determined at the intrinsic level by monitoring the frequency, number of pulses or current amplitude intensity of the current spike signal output by the system under specific pulse excitation and comparing it with a preset feature threshold. Behavior recognition mode: Real-time recording of the coordinate sequence of the current spike signal generated in the array space and its order on the time axis, and by constructing the target's motion trajectory, morphological envelope evolution or spatiotemporal fingerprint, to realize the logical judgment of the target's action characteristics.

[0015] The behavior recognition mode specifically includes the following steps connected in a time sequence: Event-driven background shielding: Utilizing the physical self-inhibition and zeroing characteristics of the device units, redundant background information or static interference signals in the array are automatically shielded, so that the system is in a monitoring state with extremely low power consumption. Characteristic frequency intrinsic capture: When the input excitation meets the resonance condition, causing the device unit to change from the step integration stage to the burst emission stage and release the instantaneous current spike signal, the high current ratio of the emission current to the background current is used as the basis for judging abnormal characteristics. Dynamic morphological envelope extraction: For the target that generates the current spike signal, the dynamic edge contour signal of the target is extracted in real time by utilizing the time difference between the device units in different regions entering the suppression phase and the emission phase. Spatiotemporal coordinate sequence mapping: Real-time recording of the sum of current spike signals on the row or column lines and their corresponding word line bit line coordinate sequences to construct the target's motion trajectory.

[0016] Compared with the prior art, the present invention has the following beneficial effects: (1) High degree of in-memory computing integration: This invention integrates sensing, storage and computing functions into the intrinsic physical evolution logic of ferroelectric domain wall units, breaking through the limitations of the "memory wall" and "power wall": integration is equivalent to in-memory computing, which can eliminate the frequent data transfer between the sensing end, storage end (memory) and computing end (CPU / GPU) in the traditional von Neumann architecture; and has extremely high area efficiency: the same Crossbar array point is both a receiver of light / electric signals (sensing), a memory for weights (storage), and an executor of nonlinear operations (computation), which greatly reduces the chip size and is suitable for implantable medical devices or micro UAVs; at the same time, it also has real-time performance and low latency: the physical response process of signal input is the output process of calculation results (time domain synchronization), without waiting for A / D conversion and complex algorithm iteration, and the response latency can reach the microsecond level; all units of the entire array evolve simultaneously according to the input signal, realizing hardware-level parallel processing. Parallel vector-matrix operations are performed using Ohm's law and Kirchhoff's law, completely eliminating the energy consumption of data transfer.

[0017] (2) Ultra-low system power consumption: Due to the physical self-inhibition and zero-return characteristics of the device units of the present invention, the array has extremely low current when processing non-significant signals or static backgrounds, realizing an "event-driven" operation mode. For implantable devices, near-zero power consumption passive monitoring can be achieved.

[0018] (3) Extremely fast response delay: The feature extraction and recognition of the present invention are based entirely on the intrinsic dynamics of the material (such as the NDR effect), and the response delay can reach the microsecond level or even lower, which is far superior to the traditional machine vision scheme based on frame-by-frame calculation.

[0019] (4) Hardware-level algorithm simplification: This invention does not require complex edge detection or trajectory tracking algorithms. The array can automatically output the dynamic envelope of the target through the physical layer's "center shutdown, edge distribution" logic, which greatly alleviates the burden on the back-end processor.

[0020] (5) Good scalability and consistency: This invention is applicable to everything from simple 2×2 logic gates to complex 100×100 vision processors. By precisely controlling the growth process of ferroelectric thin films such as BFO, the consistency of the firing threshold under large-area arrays is ensured, meeting the requirements of large-scale integrated circuits. Attached Figure Description

[0021] Figure 1 This is a cross-array architecture based on ferroelectric thin-film device units provided in the embodiments of the present invention; Figure 2 This is a typical current-voltage (current-voltage) reading of a single device unit based on conductive domain walls under scanning voltage in an embodiment of the present invention. IV Characteristic curves; Figure 3 The electrical response curves of the device unit in the embodiment of the present invention in the low voltage write range (2.2V to 3.6V) show the integral characteristics of the device's conductance increasing stepwise with the increase of pulse voltage during the signal accumulation stage. Figure 4 These are the electrical response curves of the device unit in the medium voltage write range (3.7V to 5.4V) in the embodiments of the present invention, which demonstrate the instantaneous pulse spike characteristics with significant peak current generated by the device during the intrinsic discharge phase; Figure 5 These are the electrical response curves of the device unit in the high-voltage writing range (5.5V to 9.5V) in the embodiments of the present invention, which demonstrate the dynamic characteristics of the device's current rapidly collapsing and physically returning to zero during the fully self-suppressed stage. Figure 6 The transient current response evolution curve of the device unit under continuous pulse excitation (amplitude 2.8V) in the embodiment of the present invention fully presents the dynamic evolution law of the device from non-volatile signal accumulation and integration, intrinsic NDR emission to physical self-inhibition and zeroing. Detailed Implementation

[0022] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments. These embodiments are based on the technical solution of the present invention and provide detailed implementation methods and specific operating procedures. However, the scope of protection of the present invention is not limited to the following embodiments.

[0023] Example 1: Structure and Physical Fabrication of an In-Memory Computing Array System This embodiment provides an in-memory computing array system based on ferroelectric domain walls. The single-layer array of the system logically consists of a physical layer, a logic layer, and an application layer. The physical layer provides physical devices for computing, and its material properties (ferroelectric domain walls) demonstrate the system's computing potential. The logic layer responds to external stimuli through the physical layer, and completes the data processing (integration, emission, and suppression) directly within the device without the need for additional computing units. The application layer extracts the current spike signals generated after processing by the logic layer, and directly outputs the target recognition or behavior determination results (whether a row or column outputs a large current at a specific time node) using the physical characteristics of the crossbar array.

[0024] Specifically, the physical layer is a cross array composed of M×N ferroelectric thin-film device units, where M and N are both greater than or equal to 2. Each device unit possesses characteristics based on the evolution of conductive domain walls induced by the electric field, instantaneous charge injection, and the dynamic formation of charged defects, used to realize the complete neuron integration and firing process: current accumulation is achieved through pulse-driven evolution of conductive domain walls, charge injection generates current spikes to complete signal firing, and the shielding effect generated by charged defect migration achieves physical suppression of spontaneous current zeroing. Figure 1 As shown, each device unit adopts a vertical structure, consisting of a substrate, a bottom electrode thin film layer, a ferroelectric thin film layer, and a top electrode from bottom to top. The bottom electrode thin film layer is fabricated as horizontally extending word lines, and the top electrode is fabricated as vertically arranged bit lines. First, the weight matrix to be calculated is stored in a cross array composed of the memory units in the form of non-volatile multi-valued conductance. Second, voltage signals are applied in parallel to the row lines (word lines 2) of the array. Finally, according to Kirchhoff's current law and Ohm's law, the total current output in parallel on the column lines (bit lines 4) of the array represents the result of the multiplication and summation operation of the input vector and the stored weight matrix in situ. This process achieves in-memory computation at the physical level, fundamentally avoiding the frequent data transfer between the processor and memory in traditional computing architectures.

[0025] When the logic layer receives an external voltage pulse sequence excitation, it performs signal accumulation integration, intrinsic NDR emission, and physical self-inhibition zeroing operations in sequence without the intervention of external control circuits, and performs calculations using the dynamic characteristics of the device unit.

[0026] Based on the current spike signal and its spatiotemporal topological relationship generated after processing by the logic layer, the application layer intrinsically completes target extraction, classification or behavior recognition at the physical level.

[0027] The specific fabrication of the device unit is as follows: Substrate and bottom electrode: A single-crystal oxide substrate 1 with (110) or (111) crystal orientation, such as SrTiO3 (STO) or SmScO3, is selected. A 20 nm thick (selectable range 5 nm-50 nm) strontium ruthenium oxide (SrRuO3, SRO) film is epitaxially grown at 700°C using pulsed laser deposition (PLD) technology as the bottom electrode thin film. SRO has both excellent conductivity and epitaxial growth quality, and is processed into word lines 2 extending parallel to the horizontal direction.

[0028] Ferroelectric functional layer: A 100 nm (optional range 30 nm-400 nm) bismuth ferrite (BiFeO3, BFO) thin film is further grown on the bottom electrode using PLD technology as ferroelectric thin film layer 3. In another preferred embodiment, the ferroelectric layer material can be selected from one or more of lead zirconate titanate (PZT), lithium tantalate (LiTaO3), lithium niobate (LiNbO3), doped hafnium oxide (HfO2), or barium titanate (BaTiO3).

[0029] Top electrode array: An array pattern is defined on the surface of the BFO thin film using electron beam lithography (EBL) or photolithography. Subsequently, a layer of platinum (Pt) or gold (Au) with a thickness of 50 nm (selectable range 20 nm-2 μm) is deposited as the top electrode by magnetron sputtering. The top electrode planar dimensions are preferably a square with a side length of 20 μm × 20 μm, and it is arranged perpendicular to the bottom electrode as bit lines 4.

[0030] In this embodiment, the size of the cross array is scalable: For small-scale arrays of 2×2 and above but less than 64×64, the in-memory computing array system acts as an intrinsic logic gate or alarm trigger, directly outputting a response to a specific frequency signal. For large-scale arrays of 64×64 and above, the in-memory computing array system serves as a spatiotemporal feature processor, utilizing numerous units to achieve multi-target, complex morphological analysis.

[0031] The "scalability" of an array is not merely about increasing or decreasing its physical size; more importantly, it's about the "adaptive evolution of functionality with scale." The following is a detailed explanation: 1. The reason why arrays are scalable.

[0032] Architectural Advantages (Crossbar Architecture): The crossbar architecture used in this embodiment is inherently modular. Each intersection of a "row" and a "column" is an independent ferroelectric computing unit. It can be scaled from 2×2 to 100×100 or even higher, like building blocks, by increasing the number of rows and columns, without changing the operating principle of individual devices.

[0033] Parallelism of computational principles: The array system in this embodiment utilizes Kirchhoff's current law for summation. Whether the array has 10 cells or 10,000 cells, the physical summation of currents in the conductors remains unchanged. This means that the computational logic of the physical layer will not collapse as the scale increases.

[0034] 2. "Scalability" is reflected in the scalability of arrays of different sizes as a leap from "point logic" to "surface recognition": Small-scale (2×2 and above): Focuses on the temporal response of a single or very few pixels, where the array acts like a "smart switch" or "logic gate". For example, detecting an ECG signal of a specific frequency (Example 9) triggers an alarm. This is a precise extraction of temporal features.

[0035] Large-scale (64×64 and above): The focus is on the synergistic effect of spatial distribution, where the array becomes a "visual processor." It can capture the outline, area, and expansion rate of a target through the "center shutdown and edge firing" of numerous units (Example 6). This is a morphological analysis of spatial and temporal dimensions.

[0036] Therefore, the core physical carrier of this invention—the cross array—is scalable. Based on the intrinsic dynamic characteristics of ferroelectric domain walls, the IFS (Integration-Releasing-Suppressing) logic of a single computing unit has a high degree of localization. By adjusting the number of word lines and bit lines, the array can be flexibly scaled according to application requirements: providing low-power logic touch and alarm functions in small-scale configurations; and providing high-performance parallel spatiotemporal feature processing capabilities in large-scale configurations.

[0037] Example 2: Three-stage calculation process of multi-field coupled intrinsic dynamics The in-memory computing array system proposed in Example 1 utilizes the microscopic physical evolution of ferroelectric thin-film device units to achieve the following three-stage intrinsic computation: a) Integration Stage (Pulse 1-3): Under the initial pulse, the electric field induces the formation of charged domain walls, causing the unit conductivity to exhibit a step-like non-volatile integral with the input pulse. Ferroelectric materials contain many "domains" (regions with aligned electric dipoles), and the boundaries between domains are called "domain walls." Domain walls in certain specific orientations (such as 109° domain walls) are conductive. Each input pulse induces the formation, movement, or growth of these conductive domain walls. The more domain walls there are, the stronger the conductivity. This achieves the process of increasing current (integration).

[0038] If the external pulse amplitude of the injection unit is set to 2.8V and the pulse width to 1ms, then during the integration phase, the vertical electric field drives the 109 Ω·cm inside the thin film. ∘Domain walls are stimulated to nucleate and gradually expand along the vertical or in-plane direction. Due to the extremely high intrinsic conductivity of conductive domain walls (such as in head-to-head configurations), charge undergoes non-volatile integration at the domain walls, resulting in a stepwise increase in device conductance. At this point, the read current exhibits the following evolution: I t1 ≈2.8μA, I t2 ≈5.6μA, I t3 ≈8.4μA.

[0039] b) Pulse 4: When domain wall evolution reaches the intrinsic triggering threshold, the NDR effect is triggered by polarization reversal-induced interface barrier modulation, releasing a transient current spike. When the voltage reaches the critical value, charges on the electrode surface rapidly enter the interior of the ferroelectric thin film or the interface. This sudden charge injection changes the interface barrier, causing a sudden surge in current (generating a current spike), which subsequently triggers the NDR effect. At this time, the current waveform exhibits a peak-valley structure with a rapid rise followed by a rapid fall, generating a peak value. I spike A transient current spike of approximately 50 μA.

[0040] c) Suppression Phase (Pulse 5 and subsequent): Under continuous excitation following the firing phase, the output current spontaneously drops to near zero due to the shielding effect generated by the migration of charged defects or the complete reversal of domain configuration, thus achieving automatic shutdown of the computing channel. Ferroelectric materials contain charged defects such as oxygen vacancies, which move slower than electrons. Under continuous pulses, these defects gradually accumulate at domain walls or electrode interfaces, generating a reverse electric field (shielding effect) that "blocks" the conductive channel, causing the current to spontaneously drop to a low current state. This process leads to the output current spontaneously dropping and tending towards 0 μA, achieving the physical shutdown and reset of the computing channel.

[0041] Figure 2 The typical current-voltage characteristic curve of a single negative differential resistance memory cell based on conductive domain walls in an embodiment of the present invention is shown. This curve characterizes the nonlinear electrical response of the device when a scanning voltage is applied between the bottom electrode layer (2) and the top electrode (4). As shown, when the forward voltage exceeds the coercive voltage threshold of the ferroelectric thin film, the device current experiences its first step increase, corresponding to the simultaneous formation of two 109° conductive domain walls in the ferroelectric thin film. The domain wall conductivity significantly enhances the local conductivity, causing a substantial increase in current. As the voltage continues to increase to its peak value... V pWithin a specific range after the voltage drop, the current exhibits a significant decreasing trend, directly demonstrating NDR characteristics. This decrease corresponds to the continuous reduction of the inner 109° domain wall due to the expansion of the polarization reversal region, leading to a reduction in the total area of ​​the effectively conductive domain walls within the system and a decrease in overall conductivity. After the voltage crosses the valley region, the current recovers and rises as the external stable domain wall structure is established. This NDR characteristic curve provides a physical basis for subsequent implementation of multi-value storage and simulation calculation functions.

[0042] Figure 3 The electrical response characteristics of the device cells in the low-voltage write range (2.2V to 3.6V) were demonstrated by applying gradually increasing write voltage pulses while uniformly maintaining the read current at 2.2V. The results show that the read current increases with increasing write voltage, but the rate of increase decreases, indicating that the conductive domain walls inside the device are undergoing excited nucleation and approaching physical saturation. With further increases in pulse voltage, the pulse current exhibits a limited increase after reaching a certain amplitude, and within the pulse, it shows a trend of first rising rapidly and then slowly decreasing. This stage corresponds to the "signal accumulation stage" of this invention, reflecting the device's initial non-volatile conductivity integration capability in response to external stimuli. At this point, the internal conductive channels are basically established, but the deep electric field shielding effect has not yet been triggered.

[0043] Figure 4 The electrical response characteristics of the device cell in the medium-voltage write range (3.7V to 5.4V) are demonstrated. When the write voltage pulse is increased to this range and maintained at a read voltage of 2.2V, the transient current exhibits a more dramatic nonlinear evolution. As the pulse voltage increases, the read current rises rapidly at the pulse onset, followed immediately by a rapid decline. Notably, although the current at the end of the pulse in this phase drops significantly from the peak value, it still remains at a certain level and does not completely drop to zero. This phenomenon indicates that the device has entered the "intrinsic discharge phase," where it releases characteristic spike signals using the NDR effect. At this point, internal charge injection and interface defect migration begin to provide partial shielding, but the conductive path is not completely blocked.

[0044] Figure 5The electrical response characteristics of the device cell in the high-voltage write range (5.5V to 9.5V) are demonstrated. Under this high-field excitation, the device exhibits extremely strong physical self-suppression capability. When the write voltage is further increased within the range of 5.5V to 9.5V, the read current at 2.2V exhibits a dynamic characteristic of "instantaneous surge followed by rapid collapse". After the pulse current rapidly rises and forms a peak, it is immediately subjected to severe physical suppression, causing the current to drop completely to zero (i.e., physical zeroing). This process corresponds to the "complete self-suppression stage" of this invention. Its physical essence lies in the fact that under high-voltage drive, defects such as oxygen vacancies accumulate at high density at the domain walls, generating extremely strong electric field shielding, or the domain configuration is completely restructured, leading to the complete annihilation of the conductive path. Figure 5 The data provides key physical criteria for the array's "center shutdown, edge extraction" logic when processing expanded targets, as well as its extremely low-power event-driven operation.

[0045] Figure 6 The transient current response curve of the device unit of the present invention under continuous pulse excitation is shown. By applying several square wave pulse sequences with an amplitude of 2.8V and a pulse width and interval of 1ms, the intrinsic dynamic evolution process of the device from signal accumulation to threshold emission and then to self-inhibition is fully revealed. In the early stage of pulse excitation, the current within a single pulse increases with the increase of voltage application time, and the rate of increase decreases from high to low. At the same time, with the increase of pulse count, the base value of pulse current increases stepwise, which corresponds to the nucleation and stimulated growth of conductive domain walls inside the ferroelectric thin film, reflecting the non-volatile integral characteristics of the device. As the number of pulses continues to increase, the current evolution enters the threshold transition region, which is characterized by a rapid rise and slow decline of the single pulse current, and the current value at the end of the pulse is lower than that at the end of the previous pulse, indicating that the NDR effect induced by internal polarization reversal begins to dominate. In the later stage of the pulse sequence, the device exhibits significant self-inhibition characteristics. The pulse current rises rapidly to form a characteristic spike and then drops rapidly, and the declining current can eventually return to zero physically. This dynamic evolution process perfectly simulates the action potential triggering and subsequent refractory period reset mechanism of biological neurons. Physically, it originates from the aggregation and shielding effect of charged defects at the domain walls or the complete reversal of domain configuration under high-frequency pulse drive, thus providing a core transient electrical criterion for the array to realize in-memory computing behavior trajectory recognition and dynamic edge extraction at the physical level.

[0046] Example 3: Selective Filtering Mechanism for Spatiotemporal Feature Frequencies Ferroelectric thin-film devices exhibit physical characteristics of an integrator with a forgetting effect. Their core logic is based on the spontaneous relaxation characteristics of conductive domain walls induced within the device after the removal of an external electric field; the time required for this process is defined as the intrinsic physical relaxation time. τThe system described in Example 1 achieves selective filtering of the spatiotemporal characteristic frequencies of target behavior by adjusting the frequency, pulse width, or amplitude of the input pulse and combining it with the intrinsic physical relaxation time of the device unit. Specifically, it includes: 1. Time-domain filtering based on frequency and relaxation time: By adjusting the frequency of the input pulse sequence, filtering is achieved by utilizing the dynamic competition between the time interval of adjacent pulses and the relaxation time of the conductive domain walls induced inside the device unit after the external electric field is removed.

[0047] The system adjusts the frequency of the input pulse sequence ( f ), utilizing the time interval between adjacent pulses (1 / f ) and relaxation time ( τ Filtering is achieved through the dynamic competition relationship between the input signal and the signal frequency. When the input signal frequency is low (1 / f > τ When the input frequency is high (1 / ), the device experiences significant conductance attenuation due to physical relaxation between adjacent pulses, preventing the conductance state from crossing the intrinsic trigger threshold, thus filtering out slowly moving background or static interference signals at the intrinsic level; only when the input frequency is high (1 / f ≤ τ Only when the conductivity is at a certain level can an effective step-by-step superposition be achieved.

[0048] 2. Energy threshold selection mechanism based on pulse width and amplitude: Based on the frequency matching described above, the system further adjusts the amplitude of the input pulse ( V ) or pulse width ( w This is used to control the energy density of the injected device, thereby defining the state boundary between "integration" and "emission": Low-energy accumulation state (integration only, no emission): If the amplitude or pulse width of the input pulse is lower than the intrinsic trigger threshold (i.e., the injected energy density is insufficient to induce interface barrier modulation or polarization reversal), the device unit only performs non-volatile conductance integration and accumulation at the physical level. In this state, although the device conductance increases stepwise with the pulse count, the weak single driving force fails to trigger the NDR effect to generate a current spike. Under these conditions, the system only performs "analog counting" or "multi-value storage" functions, remaining silent to weak interference signals of insufficient intensity.

[0049] High-energy trigger state (entering NDR state): Only when the input pulse amplitude or pulse width increases to cross the energy critical threshold, combined with the cumulative effect generated by frequency matching, can the domain configuration evolution inside the device unit reach the intrinsic trigger point, thereby rapidly jumping from the integration stage to the emission stage, releasing the high signal-to-noise ratio NDR instantaneous current spike, thereby completing the locking of specific spatiotemporal characteristic frequency targets and the physical shielding of background noise.

[0050] Through the above pulse parameters (f , w , V ) and the intrinsic relaxation time of the device ( τ By utilizing the nonlinear coupling of the array, this system establishes a dual identification filtering criterion based on frequency and energy. This enables the system to intrinsically identify target behaviors with specific motion patterns and adequate signal strength at the sensing front end, while simultaneously filtering out high-frequency weak interference or low-frequency background redundancy, significantly improving the accuracy of behavior recognition, response speed, and system energy efficiency.

[0051] Based on this, the system leverages the implicit computing capabilities of the Crossbar architecture and the coupling of device-integrated output logic to achieve parallel spatial filtering. Specifically, when processing video streams or sensor array signals, the input pulses interact with the array conductance matrix at the intersection. Based on the suppression characteristics of ferroelectric domain wall device units, pixels corresponding to static backgrounds or inside objects automatically shut off power consumption due to physical "fatigue" (charge shielding or defect accumulation), exhibiting a high-resistance state. Only newly added pixels at the forefront of object movement will excite NDR current spikes. This physical evolution of center suppression and edge triggering allows the total current signal output by the column lines to directly characterize the edge of the target, greatly reducing data bandwidth requirements and backend computational pressure.

[0052] The Crossbar architecture itself is an existing hardware topology, widely used in traditional memory (such as RRAM and MRAM) and in-memory computing. The core of this embodiment lies in utilizing the Crossbar architecture in conjunction with the integration-emission-self-suppression of the ferroelectric domain wall devices in this embodiment to achieve spatial filtering and dynamic edge extraction.

[0053] 1. Physical Summation (Vector-Matrix Operations): According to Kirchhoff's Current Law, the total current in a column is the sum of the currents in all cells of that column. This means that the system can instantly obtain the feature information of an entire row or column without scanning each pixel individually, possessing inherent parallelism.

[0054] 2. Intrinsic Background Removal: In traditional image processing, edge extraction requires complex frame difference algorithms. However, in the system of this embodiment: Center of the moving target: The area that has already been scanned is also in a low power state due to self-suppression.

[0055] Edge of moving target: The cell that has just been scanned is in the "discharge phase" and generates a high-energy current spike.

[0056] At this point, monitoring the row or column current reveals that, since the current in non-featured regions (background and center) is physically shielded, the total current signal is directly contributed by the "moving edges." Therefore, the system intrinsically completes edge extraction at the physical level, achieving a parallel filtering effect of center shutdown and edge emission.

[0057] Specifically, the intrinsic parallel vector matrix operations performed using the Crossbar architecture are as follows: Computation mechanism: External vector to be computed V As a voltage pulse sequence injected in parallel into the word line, the conductance of each device in the array G ij This represents the weight matrix of the storage.

[0058] Physical result: According to Ohm's law and Kirchhoff's laws, the total current output at the ends of each column line... I total_j =∑( V i × G ij This system transforms the cumbersome multiplication, accumulation, and addition operations of traditional computers into the instantaneous flow of physical electrical signals. With a 100×100 array, the latency of a single operation is less than 10μs.

[0059] In this embodiment, the system combines the sensing, storage, and computing units into one, changing the traditional pipeline logic of "sensing first, then transmitting, then computing". At the physical layer, a crossbar array structure is used to store the weights to be processed in a non-volatile conductance state of ferroelectric domain walls. G ij The form is pre-stored; upon receiving the input pulse voltage vector V i At that time, based on Ohm's law, a product current is generated in situ in each unit. I ij = V i × G ij And using Kirchhoff's laws, the current summation ∑ is automatically completed at the end of the potential line. I ij This allows the perceived external features to be directly converted into current outputs representing the computational results, thus achieving in-situ computation fusion. Specifically, when external spatiotemporal signals (such as changes in image brightness) act on the physical layer array, the ferroelectric domain wall units directly undergo electrical conduction changes based on their intrinsic dynamic characteristics (i.e., the sensing process). Because this evolutionary state is non-volatile due to being pinned by the ferroelectric barrier, the resulting state is latched in real-time (i.e., the storage process). During the readout cycle or under continuous excitation, the voltage vectors input to each row of the array and the array conductance matrix directly generate a sum of currents through multiplication and accumulation via physical laws (i.e., the computation process). This in-situ computation method completely eliminates the energy consumption of bus transport between the perceived signal and the computational unit, fundamentally breaking through the 'memory wall' bottleneck of the von Neumann architecture.

[0060] In this system, the domain wall structure for storing charge is itself a logic gate for performing nonlinear operations. After the array stores weights, there is no need to read the weights from memory into the arithmetic unit (such as a CPU / GPU) as in traditional architectures. The input signal vector and the stored charge state physically interact at the in-situ intersection, directly outputting a current signal characterizing the result.

[0061] Traditional image processing involves a lengthy process: photoelectric conversion (sensing) → ADC sampling → data transmission → temporary memory storage → computational unit operation. The back-and-forth data transfer between these units accounts for over 80% of the total energy consumption. In this invention, the array evolves according to intrinsic dynamics the instant an external signal is input, and performs complex vector-matrix multiplication (VMM) operations at the intrinsic level using simple physical laws (Ohm's law and Kirchhoff's laws).

[0062] This in-situ computation method eliminates the transmission burden of all intermediate buses. Experimental data shows that when performing convolutional feature extraction tasks of the same scale, the computation time of this system at the physical layer depends only on the nanosecond-level physical process of the domain wall response. Furthermore, because no data movement is required, its system energy efficiency is improved by more than three orders of magnitude compared to traditional CMOS digital systems. This demonstrates that highly integrated physical logic is key to achieving low-power, high-real-time behavior recognition.

[0063] Example 4: Information Processing Method This embodiment provides an information processing method based on the system described in Embodiment 1, the method including the following behavioral patterns: Target extraction mode: Utilize the physical suppression characteristics of device units to shield static background and internal signals, and capture the set of unit coordinates in the firing state in real time, thereby separating the spatial geometry or edge contour of the target at the physical level. Classification and recognition mode: By utilizing the sensitivity differences of the system dynamic response to different input features, the target category is determined at the intrinsic level by monitoring the frequency, number of pulses or current amplitude intensity of the current spike signal output by the system under specific pulse excitation and comparing it with a preset feature threshold. Behavior recognition mode: Real-time recording of the coordinate sequence of the current spike signal generated in the array space and its order on the time axis, and by constructing the target's motion trajectory, morphological envelope evolution or spatiotemporal fingerprint, to realize the logical judgment of the target's action characteristics.

[0064] In the behavior recognition mode, the following steps are specifically included, which are connected in a sequential logical sequence: S1, Event-Driven Background Masking: First, upon inputting the original signal, the system utilizes the physical self-suppression and zero-reset characteristics of the device units to automatically mask redundant background information or static interference signals in the array, putting the system in an extremely low-power monitoring state. This step is fundamental, ensuring that subsequent processing consists of "valid events" with high signal-to-noise ratios, while also achieving extremely low power consumption.

[0065] S2, Characteristic Frequency Intrinsic Capture: When the input excitation satisfies the resonance condition, causing the device unit to transition from the stepped integration stage to the burst emission stage and release an instantaneous current spike signal, the high current ratio of the emitted current to the background current is used as the basis for judging abnormal characteristics. In valid events, this step determines whether the signal frequency matches, and determines whether it is a legitimate target by the generation of a high current ratio (e.g., distinguishing between swaying leaves and human movement). If a high current ratio pulse is generated, it is judged as a specific / abnormal behavior, which is the core criterion for identifying the nature of the behavior.

[0066] S3, Dynamic Morphological Envelope Extraction: For the target generating the current spike signal, the dynamic edge contour signal of the target is extracted in real time by utilizing the time difference between the suppression and emission phases of device units in different regions. After confirming the target's legitimacy, this step physically extracts the contour using the time difference. This step obtains the geometric features of the target (e.g., whether it is a circular plume of smoke or a linear object), which is morphological evidence for identifying the scale of the behavior.

[0067] S4, Spatiotemporal Coordinate Sequence Mapping: This involves real-time recording of the sum of current spike signals on the row or column lines and their corresponding word / bit line coordinate sequences to construct the target's motion trajectory. This serves as the spatiotemporal fingerprint for identifying behavioral logic. The direction, speed, and curvature of the trajectory determine the meaning of the behavior. For example, a "circular" trajectory represents a gesture command to draw a circle; a "rapid straight-line movement" represents an intrusion alarm; and a "chaotic, stationary fluctuation" represents interference. The trajectory provides the system with the target's historical state, enabling the application layer to predict the target's position in the next second and achieve smooth tracking.

[0068] Finally, these signals with contours and frequency features are connected to form lines, and the resulting recognition results include a clean background, specific frequencies, dynamic contours, and motion trajectories.

[0069] Example 5: High-speed obstacle avoidance by unmanned aerial vehicles (UAVs) – salience detection and hazard assessment Scenario description: The drone is traveling at high speed through complex environments (such as forests or urban buildings) and needs to instantly distinguish between distant scenery (mountains, clouds) and sudden nearby obstacles (such as power lines, birds).

[0070] Spacetime Logic: Background signal: Distant mountains move extremely slowly in the field of view. For a specific pixel in the array, its stimulated pulse frequency is much lower than the device's relaxation time, and the conductance is always in stage 1 ( I <8.4μA).

[0071] Obstacle signal: When an obstacle approaches rapidly, due to the Looming Effect, the corresponding central area of ​​the image will cover the same pixel more than 4 times in a short period of time.

[0072] Matrix description (5x5 area cropped from the center of the array): t =4 (Detection instant): The center pixel (50,50) reaches the 4th pulse. Judgment: The system detected a 50μA burst, and determined that there is an extremely high-risk target at this coordinate. t =10 (behavior continues): The object continues to grow larger, and the center point enters the inhibition state due to the number of pulses > 5. Result: The array's physical output "dynamic profile (edge ​​release, center suppression)" is directly used as an obstacle avoidance command input to the flight control system.

[0073] Example 6: Security Monitoring – Intrusion Expansion and Background Reduction Scenario description: Warehouse monitoring requires distinguishing between randomly moving mosquitoes (harmless trajectories) and smoke diffusion, water leaks, or a person lying still on the ground (expanded risks).

[0074] Spatiotemporal logic: Mosquitoes fly across a single pixel at extremely high speeds, failing to meet the condition of "3 pulse integration + 1 pulse firing". However, fire smoke spreads continuously from a single point outwards, with the central area triggering firing earliest.

[0075] Matrix explanation (5x5 region extracted): t =4 (Alarm Start): The first spike occurs at the smoke center (20,20). t =12 (Feature Extraction): After the smoke diffuses, the background noise is physically shielded at the center point because the current returns to zero due to the self-suppression function. Significance: The array outputs a continuously expanding "emission ring," and this topological fingerprint is intrinsically identified as an "area expansion anomaly."

[0076] Example 7: Intelligent Interaction – “Double-click” and “Circle Drawing” Trajectory Fingerprint Recognition Scenario description: Smart cockpit gesture control.

[0077] Spatiotemporal logic: The system identifies commands by capturing the spatial coordinate sequence of 50μA current spikes.

[0078] Matrix Explanation (using the "draw a circle" gesture as an example) t 4 to t (7-pixel sequence of output) t =4: coordinates ( R i , C j ) Issuance.

[0079] t =5:( R i , C j Suppressing zeroing, adjacent coordinates ( R i+1 , C j+1 ) Issuance.

[0080] t =6:( R i+1 , C j+1 Return to zero, R i+2 , C j ) Issuance.

[0081] Trajectory matrix summary representation: Significance: This "coordinate-time" mapping forms a unique "behavioral trajectory fingerprint". The system recognizes this fingerprint and executes the corresponding instruction, and is physically immune to background light and shadow.

[0082] Example 8: High-speed production line inspection – intrinsic capture of defective product burrs Scenario description: The part moves at 10m / s, and micron-level burrs (high-frequency disturbance signals) on the surface are identified.

[0083] Spatiotemporal logic: When a normal smooth surface passes through, the excitation frequency of the pixel is extremely low. As an abnormal protrusion, a glitch will generate a high-frequency, dense local jitter pulse when it sweeps across the pixel.

[0084] Matrix Explanation (Detection Section): When a normal workpiece passes by: the matrix outputs a consistent low current accumulation state (approximately 2.8μA or 5.6μA) across the entire field.

[0085] The moment the burr appears: Application: The system captured this isolated 50μA anomaly. Due to its extremely high significance, it directly drove the hardware rejection mechanism, and the identification and decision-making were completed synchronously at the physical layer.

[0086] Example 9: Smart Healthcare – Intrinsic Early Warning of Cardiac Arrhythmias Scenario description: Implantable or wearable monitors that only trigger an alarm when there is tachycardia or ventricular fibrillation.

[0087] Spatiotemporal logic: In a normal heart rate (60~100 beats / min), the intervals are long. The BFO device uses physical relaxation time to allow the conductance to automatically decrease within the pulse interval, preventing the fourth accumulation from being reached. During arrhythmias, the frequency suddenly increases, and the pulse completes integration before relaxation.

[0088] Matrix explanation (taking a 1×10 monitoring bar as an example): Normal heart rate: M =[2.8,0,0,2.8,0,0,2.8,0…] μA.

[0089] Abnormal Outbreak: When four consecutive dense pulses arrive: M alarm =[0,0,0,50.0,0,0,0…] μA.

[0090] Core value: It achieves signal-driven passive monitoring. Under normal conditions, the system current is extremely low, consuming almost no power; only when an abnormal signal sufficient to trigger the physical NDR effect occurs will it "jump out" of the high current spike and activate the subsequent alarm module.

[0091] Example 10: Wearable Medical Devices – Intrinsic Monitoring of Parkinson's Tremor Scenario description: Real-time capture of limb tremor characteristics in Parkinson's patients by smart wearable devices.

[0092] Spatiotemporal logic: The frequency of normal limb movements (< 2Hz) is filtered by physical relaxation; the frequency of the patient's tremor signal (4-6Hz) resonates with the device's dynamic response, triggering a high current ratio discharge.

[0093] Matrix Explanation (Extracting 1×4 sensor mapping from the wristband): Normal operation: M=[2.8, 2.8, 0, 0] µA Tremor attacks: M=[50, 50, 0, 0] µA Significance: It achieves extremely low power consumption passive monitoring and utilizes the material's intrinsic frequency filtering mechanism to activate the alarm module only at the moment of vibration, significantly extending battery life.

[0094] Example 11: Power Industry - Online Early Warning of Power Grid Conductor Galloping Scene description: Capturing the dangerous galloping frequency of long-distance power transmission lines under extreme weather conditions.

[0095] Spatiotemporal logic: Static background cells are automatically turned off due to their physical self-inhibition properties (current tends to 0). When the conductor undergoes drastic displacement, pixels at the leading edge of the movement are excited by frequency matching, triggering NDR (Non-Diffuse Reduction) to generate dynamic edges.

[0096] Matrix Explanation (Screening of a 5x5 monitored area): Dangerous dancing (generating dynamic edge contours): Where 50.0 represents the edge of the conductor, 2.8 represents the integral residue that has just passed through, and 0 represents the background shielding area.

[0097] Significance: It greatly compresses the video transmission bandwidth, and only needs to record the high current coordinate sequence to determine the dancing level, without the need for back-end image processing.

[0098] Example 12: Security Measures – Soundprint Intrinsic Recognition for Broken Bank Counter Glass Scenario Description: Rapid identification of specific ultra-high frequency (>10kHz) sound waves of glass breaking.

[0099] Spatiotemporal logic: Low-frequency signals such as voice cannot reach the emission threshold due to their low energy density and frequency mismatch; the high-frequency sound wave pulse generated by glass breakage causes the device's conductivity to resonate intrinsically within 0.5ms and cross the threshold to trigger emission.

[0100] Matrix explanation (taking a 1×8 voiceprint mapping bar as an example): Ambient noise: M=[2.8, 5.6, 2.8, 0, 2.8, 5.6, 0, 0] µA At the moment of fragmentation: M = [2.8, 5.6, 2.8, 45, 2.8, 5.6, 0, 0] µA Significance: The physical layer directly completes the voiceprint feature extraction, reducing the recognition latency to the microsecond level and effectively avoiding false alarms due to environmental noise.

[0101] Example 13: Mechatronics – Intrinsic Detection of Robotic Skin Slip Edges Scenario description: Real-time detection of minute slippage during the process of a robotic arm grasping an object.

[0102] Spatiotemporal logic: The stable pressure region generates a shielding effect due to the migration of charged defects (center shutdown, current returns to zero); the pressure change at the edge caused by sliding triggers the "edge release" of new pixels.

[0103] Matrix Explanation (4x4 array extracted from fingertip): Stable grip (total inhibition): Slide to the right (edge ​​lights up instantly): Significance: It realizes "intrinsic event-driven haptics", which does not require scanning the entire pressure matrix and has a perception delay of less than 1μs.

[0104] Example 14: Assisted Driving – Parallel Recognition of Vehicle-mounted Tailgating Prevention Scenario description: Warning system for rapidly approaching vehicles in a vehicle rearview system.

[0105] Spatiotemporal logic: The array utilizes a crossbar architecture to perform vector-matrix operations. The shortening distance to the rear vehicle causes its projected area in the array to expand, triggering the parallel firing of edge pixels.

[0106] Matrix Explanation (Cut off 1×7 column line current output): Safe following distance (low-speed expansion): I _col =[0, 5.6, 8.4, 11.2, 8.4, 5.6, 0] µA Danger is approaching (edge ​​release superposition): I _col =[0, 100, 0, 0, 0, 100, 0] µA (current surge at both ends) Significance: The ranging algorithm is simplified to the determination of array edge current characteristics, which alleviates the pressure on backend computing power.

[0107] Example 15: Smart City – Long-Period Intrinsic Integral of Minor Leakage in Water Meters Scenario description: Online monitoring of extremely minute, continuous water leakage at the level of one drop per second.

[0108] Spatiotemporal logic: The intermittent large current generated by normal water use is completely physically relaxed during the interval; the weak electrical signal generated by continuous water leakage is accumulated over a long period using ferroelectric non-volatility.

[0109] Matrix description (using 1×8 cumulative bars): Normal water usage: M = [0, 0, 0, 0, 0, 0, 0, 0] µA Cumulative leakage (crossing threshold): M=[0, 0, 0, 30, 0, 0, 0, 0] µA Significance: It solves the high power consumption problem of electronic water meters under high-frequency sampling and realizes long-term monitoring with near-zero power consumption.

[0110] Example 16: Attendance Management – ​​Physical Determination of the Number of People "Unlawfully Tailing" in the Office Building Scenario description: Automatic recognition of the behavior of "one person swiping a card and two people entering" above the turnstile.

[0111] Spatiotemporal logic: Different human targets generate independent "edge emission rings", and the array lines output the sum of currents in parallel to form physical peaks.

[0112] Matrix Explanation (Sum of 1×10 currents extracted from column lines): Single-person passage (single peak): I _col =[0, 0, 50.0, 150, 50.0, 0, 0, 0, 0, 0] µA Double-person tailing (double peaks): I _col =[0, 100, 50.0, 0, 0, 50.0, 100, 50.0, 0, 0] µA Significance: Pure hardware-based number determination eliminates the need for complex image segmentation algorithms, significantly improving recognition accuracy.

[0113] Example 17: Industrial Inspection – Intrinsic Matching for “Bottle Shortage” in High-Speed ​​Packaging Lines Scenario description: High-speed interception of missing products on a conveyor belt (20m / s).

[0114] Spatiotemporal logic: The device is set to a characteristic frequency matching state. Normally passing products maintain resonant output; a missing bottle causes the excitation signal to be lost, the device relaxes rapidly, and the output current drops instantaneously.

[0115] Matrix description (using a 1×6 array): Normal flow rate: M=[0, 0, 50, 50, 0, 0] µA At the moment of bottle loss: M = [0, 0, 2.8, 2.8, 0, 0] µA Significance: This breakthrough overcomes the frame rate limitations of industrial cameras, enabling nanosecond-level feature mutation matching and detection.

[0116] Example 18: Environmental Monitoring – Fractal Extraction of Early Forest Fire Smoke Scenario description: Intrinsic extraction of smoke area expansion features under long-distance conditions.

[0117] Spatiotemporal logic: Utilizing the typical fractal characteristics of smoke diffusion to induce large-area resonance in the array, the physical self-inhibition mechanism automatically filters out motion interference such as point birds.

[0118] Matrix explanation (5x5 region extracted): Edge of smoke diffusion: Significance: By completing smoke recognition at the sensing front end, the false alarm rate is reduced by 90%, significantly improving the real-time performance of fire early warning.

[0119] Example 19: Biotechnology – Real-time Monitoring of Bacterial Colony Growth Dynamics Scenario description: Non-invasive automatic recording of the slow growth process of bacterial colonies at the bottom of the petri dish.

[0120] Spatiotemporal logic: By utilizing non-volatile integration across time windows, the slow growth boundary of several days is directly transformed into conductivity ladder evolution and distribution.

[0121] Matrix explanation (evolution of a 3×3 array): Day 1: M=2.8µA (full range) Day 3 Edge Reach: Significance: The growth boundary expansion curve can be directly output through the physical electrical signal of the array, which significantly reduces the research cost.

[0122] Example 20: Underwater Navigation – Target Classification Based on Acoustic Signal “Wavefront Topology” of a 256×256 Array Scenario Description: The submersible uses an array sonar to capture echoes. Amidst the noise of ocean currents and seabed reflections, the target attributes must be intrinsically determined based on the wavefront curvature of the echo signal: a spherical wavefront represents point source targets (such as schools of fish), while a planar wavefront represents large, regular structures (such as submarines or seawalls).

[0123] Spatiotemporal Logic: Cross-Time Window Accumulation: Acoustic echo energy is extremely weak. Utilizing ferroelectric nonvolatility, the system accumulates weak acoustic pulses over multiple periods. Only coherent echo signals can generate step integrals on the corresponding topological path of the array, while random ocean current noise is filtered out by physical relaxation. Parallel Spatial Curvature Recognition: Utilizing the vector-matrix multiplication function of the Crossbar architecture, the array is configured with block weights.

[0124] Center shutdown and wavefront extraction: When the echo envelope sweeps across the array, the central region of the wavefront enters the suppression state (shutdown) first because it has the longest excitation time. The output end retains only the coherent signal at the outermost edge of the wavefront, thus physically outlining the "echo topology arc".

[0125] Matrix Explanation (Extracting the total current from the 1×8 column lines at the moment of echo arrival) I _col contrast): Target A (point source, spherical wave): I _col=[0, 50, 25.0, 0, 0, 25.0, 50, 0] µA (Because the spherical wavefront projects an arc shape onto the array, the edge elements reach their peak value before the center elements, forming a bimodal characteristic.) Target B (planar target, straight wavefront): I _col =[0, 150, 150, 150, 150, 150, 150, 0] µA (The wavefronts arrive simultaneously, and multiple NDR units are superimposed, resulting in an extremely high current plateau.) Significance: The system replaces the time-consuming beamforming algorithm in traditional synthetic aperture sonar (SAS) with wavefront curvature intrinsic filtering at the physical layer. This enables the underwater vehicle to instantaneously identify target types based on the waveform distribution of physical current with almost no computational power consumption, improving energy efficiency by five orders of magnitude. Example 21: Aerospace—Dynamic Capture and Fingerprint Recognition of Tiny Space Debris Against a Star Map Background Based on a 128×128 Array Scenario Description: An autonomous monitoring system on a satellite or space station needs to identify and track high-speed passing microscopic space debris in real time against a complex deep-space background (containing numerous stars, nebulae, and cosmic ray interference). This mission requires the system to automatically and physically shield the extremely slow-moving "static" background star map and determine the debris's physical properties (such as size and spin frequency) based on the high-frequency flickering characteristics (brightness pulses caused by the debris's spin) generated when it passes by.

[0126] Spatiotemporal Logic: Physically Adaptive Shielding of Stellar Background: Stars in the deep space background move slowly with the satellite's attitude, and the pulse frequency they exert on the array pixels is extremely low (<0.1Hz). After being excited for several cycles, the corresponding unit's output current returns to zero due to the shielding electric field generated by oxygen vacancy migration, thus "extinguishing" the entire background star map at the physical level, achieving more than 99.9% background redundancy removal.

[0127] Intrinsic Resonance Extraction from High-Speed ​​Debris: Space debris sweeps across the field of view at speeds of several kilometers per second. The localized high-frequency excitation generated by the debris (typically 1kHz-5kHz due to rapid pixel switching caused by motion and brightness flickering caused by debris spin) and the intrinsic relaxation time of the device are discussed. τ Dynamic matching is achieved in approximately 200 μs, inducing nonlinear conductance integration and instantaneously releasing the NDR current spike.

[0128] Spin fingerprint sequence mapping: By recording the precise time interval (Time Gap) of current spikes generated at each coordinate point on the fragment path, the physical layer directly outputs the target's "photometric evolution fingerprint," thereby determining the fragment's spin stability at the intrinsic level.

[0129] Matrix Explanation (A 5x5 observation area is captured as the fragment passes through the path, and the result is displayed) t 1→ t (5 spatiotemporal characteristics) Background star position (physically shielded): M star ≈0μA.

[0130] The debris swept across the path ( t 1. Arrival, including one spin brightness jump in the middle): (Note: t The 75μA spike at point 3 represents the over-threshold energy release caused by enhanced target spin reflection, constituting the target's identity fingerprint. Significance: This method physically eliminates the processing burden of massive star map data at the sensing front end. Compared with the traditional CCD / CMOS combined with back-end DSP solution, this system reduces data bandwidth requirements by more than three orders of magnitude and can intrinsically identify dangerous targets with specific dynamic characteristics (such as specific spin frequencies), greatly improving the safety early warning capability of satellites in orbit.

[0131] In summary, this invention provides a negative differential resistance memory cell based on conductive domain wall dynamics and its operation method. The core advantage of this approach lies in achieving intrinsic NDR characteristics through domain flipping in ferroelectric thin films, and realizing the entire computational logic of signal accumulation integration, threshold feature delivery, and self-inhibition reset at the physical level based on conductive domain wall dynamics. By integrating this cell into a vertical crossbar array of a certain scale, this invention unifies multi-value storage and neuromorphic computing functions onto the same physical platform, intrinsically performing parallel vector-matrix operations at the array level using Ohm's law and Kirchhoff's laws.

[0132] In practical applications, this invention demonstrates superior behavior recognition capabilities. For example, in a high-speed obstacle avoidance embodiment for drones, by utilizing the intrinsic matching of the device's physical relaxation time and pulse frequency, the array can spontaneously filter distant background signals and accurately issue obstacle warning signals in the fourth frame. In a security monitoring and industrial inspection embodiment, by utilizing the physical time difference between the self-suppression and zeroing of the center pixel and the continuous issuance of edge pixels, the array can intrinsically output the target's dynamic contour and anomaly fingerprint without the need for a backend algorithm. This system has significant advantages such as simple structure, good process compatibility, high energy efficiency, and great parallel computing potential, providing a revolutionary implementation solution for in-memory computing and ultra-low-power edge intelligent hardware.

[0133] In the above description, directional terms (such as "top," "bottom," "horizontal," "vertical," etc.) and reference numerals are used for ease of explanation and understanding. These terms and numerals are only used to relatively describe and clarify embodiments of the present invention, and are not intended to limit any implementation of the present invention to the specific spatial orientation or absolute configuration shown in the accompanying drawings. Those skilled in the art can understand their meaning from the context. The layer thickness, dimensions, scale, and current values ​​(such as 2.8 μA, 50 μA, etc.) shown in the accompanying drawings may be exaggerated, simplified, or schematic for clarity and do not represent the precise dimensions or absolute electrical limits of the actual device.

[0134] The preferred embodiments of the present invention have been described in detail above. It should be understood that those skilled in the art can make numerous modifications and variations based on the concept of the present invention without creative effort. Therefore, all technical solutions that can be obtained by those skilled in the art based on the concept of the present invention through logical analysis, reasoning, or limited experimentation on the basis of existing technology should be within the scope of protection defined by the claims.

Claims

1. A memory-based computing array system based on ferroelectric domain walls, characterized in that, The single-layer array of the system logically consists of a physical layer, a logical layer, and an application layer. The physical layer is a cross array composed of M×N ferroelectric thin film device units, where M and N are both greater than or equal to 2. Each device unit has the characteristics of conductive domain wall evolution induced by electric field, instantaneous charge injection, and formation of charged defect dynamics, which are used to realize the complete neuron integration and firing process: current accumulation is realized by driving the evolution of conductive domain walls through pulses, current spikes are generated by charge injection to complete signal firing, and the shielding effect generated by charged defect migration is combined to realize the physical suppression of the current spontaneously returning to zero. When the logic layer receives an external voltage pulse sequence excitation, it performs signal accumulation and integration, intrinsic negative differential resistance effect emission, and physical self-suppression and zeroing operations in sequence without the intervention of the external control circuit, and performs calculations using the dynamic characteristics of the device unit. The application layer intrinsically performs target extraction, classification, or behavior recognition at the physical level based on the current spike signal and its spatiotemporal topological relationship generated after processing by the logic layer.

2. The in-memory computing array system based on ferroelectric domain walls according to claim 1, characterized in that, The system utilizes the microscopic physical evolution of ferroelectric thin-film device units to achieve the following three-stage intrinsic calculation: Integration stage: Under the initial pulse drive, the electric field induces the formation of charged domain walls, so that the unit conductance exhibits a step-like non-volatile integral with the input pulse; Release phase: When the domain wall evolution reaches the intrinsic trigger threshold, the NDR effect is triggered by the interface barrier modulation induced by polarization reversal, releasing the instantaneous current spike. Suppression phase: Under continuous excitation after the release phase, the output current spontaneously drops to zero by utilizing the shielding effect generated by the migration of charged defects or the complete flipping of domain configuration, thereby realizing the automatic shutdown of the computing channel.

3. The in-memory computing array system based on ferroelectric domain walls according to claim 1, characterized in that, The system selectively filters the spatiotemporal characteristic frequencies of target behavior by adjusting the frequency, pulse width, or amplitude of the input pulse and combining this with the intrinsic physical relaxation time of the device units. Specifically, this includes: Time-domain filtering based on frequency and relaxation time: The system achieves filtering by adjusting the frequency of the input pulse sequence and utilizing the dynamic competition between the time interval between adjacent pulses and the relaxation time of the conductive domain walls induced inside the device unit after the external electric field is removed. The system uses an energy threshold selection mechanism based on pulse width and amplitude to control the energy density injected into the device. When the amplitude or pulse width of the input pulse is lower than the intrinsic trigger threshold, the device unit only performs non-volatile conductance integral accumulation at the physical level and does not enter the NDR release state. When the amplitude or pulse width of the input pulse reaches or exceeds the intrinsic trigger threshold and the pulse frequency matches the relaxation time, the system triggers the NDR effect and releases the current spike, thereby completing the locking of specific spatiotemporal characteristic frequency targets and the physical shielding of background noise.

4. The in-memory computing array system based on ferroelectric domain walls according to claim 1, characterized in that, The size of the cross array is scalable: For small-scale arrays of 2×2 and above but less than 64×64, the in-memory computing array system acts as an intrinsic logic gate or alarm trigger, directly outputting a response to a specific frequency signal. For large-scale arrays of 64×64 and above, the in-memory computing array system serves as a spatiotemporal feature processor, utilizing numerous units to achieve multi-target, complex morphological analysis.

5. The in-memory computing array system based on ferroelectric domain walls according to claim 1, characterized in that, The ferroelectric thin-film device unit is selected from ferroelectric materials with in-plane polarization components, including but not limited to any one or a combination of bismuth ferrite salts, bismuth ferrite salts doped with rare earth elements, lead zirconate titanate salts, lithium tantalate salts, or lithium niobate, or heterostructures of multiple materials.

6. The in-memory computing array system based on ferroelectric domain walls according to claim 1, characterized in that, The system utilizes the implicit computing power of the Crossbar architecture and the coupling of device integrated power supply logic to achieve parallel spatial filtering function. Specifically, when processing video streams or sensor array signals, the input pulse and the array conductance matrix interact at the intersection. Based on the suppression characteristics of ferroelectric domain wall device units, pixels in the static background or inside objects automatically turn off power consumption due to physical charge shielding or defect accumulation, exhibiting a high impedance state.

7. The in-memory computing array system based on ferroelectric domain walls according to claim 1, characterized in that, Each device unit adopts a vertical structure, which includes, from bottom to top, a substrate, a bottom electrode thin film layer, a ferroelectric thin film layer, and a top electrode. The bottom electrode thin film layer is fabricated as a horizontally extending word line, and the top electrode is fabricated as a vertically arranged bit line.

8. The in-memory computing array system based on ferroelectric domain walls according to claim 2, characterized in that, The system possesses non-volatile spatiotemporal storage characteristics: the conductance state generated during the integration phase can still be maintained even without a power supply. The system utilizes this non-volatility to accumulate discontinuous spatiotemporal events across time windows, thereby maintaining computational continuity even under extremely low duty cycle signals.

9. An information processing method based on the system according to any one of claims 1-8, characterized in that, This method includes the following behavioral patterns: Target extraction mode: Utilize the physical suppression characteristics of device units to shield static background and internal signals, and capture the set of unit coordinates in the firing state in real time, thereby separating the spatial geometry or edge contour of the target at the physical level. Classification and recognition mode: By utilizing the sensitivity differences of the system dynamic response to different input features, the target category is determined at the intrinsic level by monitoring the frequency, number of pulses or current amplitude intensity of the current spike signal output by the system under specific pulse excitation and comparing it with a preset feature threshold. Behavior recognition mode: Real-time recording of the coordinate sequence of the current spike signal generated in the array space and its order on the time axis, and logical judgment of the target's action characteristics by constructing the target's motion trajectory, morphological envelope evolution or spatiotemporal fingerprint.

10. The information processing method according to claim 9, characterized in that, The behavior recognition mode specifically includes the following steps connected in a time sequence: Event-driven background shielding: Utilizing the physical self-inhibition and zeroing characteristics of the device units, redundant background information or static interference signals in the array are automatically shielded, so that the system is in a monitoring state with extremely low power consumption. Characteristic frequency intrinsic capture: When the input excitation meets the resonance condition, causing the device unit to change from the step integration stage to the burst emission stage and release the instantaneous current spike signal, the high current ratio of the emission current to the background current is used as the basis for judging abnormal characteristics. Dynamic morphological envelope extraction: For the target that generates the current spike signal, the dynamic edge contour signal of the target is extracted in real time by utilizing the time difference between the device units in different regions entering the suppression phase and the emission phase. Spatiotemporal coordinate sequence mapping: Real-time recording of the sum of current spike signals on the row or column lines and their corresponding word line bit line coordinate sequences to construct the target's motion trajectory.

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