An eMMC storage method for suppressing read disturb
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- JIANGSU XINSHENG INTELLIGENT TECH CO LTD
- Filing Date
- 2026-02-10
- Publication Date
- 2026-06-02
Smart Images
Figure CN122135758A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of embedded storage technology, and more specifically to an eMMC storage method for suppressing read interference. Background Technology
[0002] As NAND flash memory manufacturing processes continue to advance and cell spacing shrinks, read interference is increasingly becoming a key factor affecting data reliability and device lifespan. When a word line is frequently read, the applied read voltage acts as stress, interfering with the charge of adjacent word line cells and causing their threshold voltage V to drop. th Drift can occur, leading to bit errors, which may even exceed the error correction capabilities of ECC.
[0003] Existing technologies mainly employ two countermeasures, but both have significant drawbacks:
[0004] Passive reactive error correction: The system only initiates a high-latency data recovery process (such as reading the retry sequence or data migration) when the ECC decoder detects an uncorrectable error during data reading. By this time, the error may have accumulated in multiple units and reached a critical point, leading to a sharp drop in system performance and a degraded user experience.
[0005] Coarse-grained read count management: Existing wear leveling algorithms typically count reads on a block-by-block basis. Once the number of reads on any page within a block reaches a fixed global threshold, the entire block is migrated. This "one-size-fits-all" approach ignores the significant differences in access frequencies across different word lines within a block, resulting in numerous unnecessary write operations. This significantly exacerbates the write amplification factor (WAF), thereby shortening the lifespan of NAND flash memory.
[0006] Therefore, there is an urgent need in this field for a more refined, intelligent, and proactive read interference management solution to intervene before errors occur, thereby reducing error correction delays, minimizing unnecessary data migration, and ultimately improving the reliability and lifespan of eMMC. Summary of the Invention
[0007] The purpose of this invention is to overcome the shortcomings of the prior art and provide an eMMC storage method to suppress read interference. Through a three-level linkage mechanism of "monitoring-prediction-defense", it achieves a fundamental shift from passive error correction to active prevention, thereby solving problems such as high error correction latency, rough data migration, and large write amplification factor in the prior art.
[0008] The objective of this invention is achieved through the following technical solution:
[0009] An eMMC storage method for suppressing read interference is applied to an eMMC storage system. The eMMC storage system includes an eMMC controller and a NAND flash memory array. The NAND flash memory array includes multiple storage blocks for data storage. The eMMC controller is equipped with a block-level read counter for each storage block and a word-line-level read counter for each word line within the storage block.
[0010] The eMMC storage method includes:
[0011] The host interface receives word line read requests, and the word line-level read counter is updated in real time.
[0012] Obtain the P / E cycle, data retention time, and ambient temperature parameters of the memory block corresponding to the target word line, and calculate the dynamic read count threshold of the target word line;
[0013] Read the count value of the word-line level read counter corresponding to the target word line, and determine whether the current read count value has reached 80% of the dynamic threshold;
[0014] If the dynamic threshold is reached at 80% but not 100%, adaptive read voltage training is initiated to find the optimal read voltage and update the lookup table; if the dynamic threshold is reached at 100%, an early warning is issued, and data priority is obtained based on the data's metadata tags or access history, and a hierarchical migration strategy is implemented.
[0015] After the migration is complete, reset the word line read counter corresponding to the original word line.
[0016] Furthermore, the step of obtaining the P / E cycle, data retention time, and ambient temperature parameters of the memory block corresponding to the target word line, and calculating the dynamic read count threshold of the target word line, specifically includes:
[0017] Obtain the current P / E cycle count C, current data retention time T, and current ambient temperature Temp from the flash memory metadata area for the memory block corresponding to the target word line;
[0018] Obtain the maximum tolerated P / E cycle count Cmax, the rated maximum data retention time Tmax, and the maximum allowable operating temperature Tempmax of the memory block corresponding to the target word line from the flash memory metadata area;
[0019] The formula for calculating the dynamic read count threshold of a word line is as follows:
[0020] ;
[0021] Among them, R baseThe base read count threshold is determined by the characteristics of the flash memory; α, β, and γ are the weighting coefficients for the number of P / E cycles, data retention time, and ambient temperature, respectively, which are determined through experimental fitting; n, m, and k are the correction exponents, which are usually greater than or equal to 1 and are used to describe the nonlinear relationship between the parameters and the sensitivity.
[0022] Furthermore, the step of initiating adaptive read voltage training, finding the optimal read voltage, and updating the lookup table specifically includes:
[0023] A series of read voltage reference values Vref were iteratively tested on the target word line and its adjacent word lines with the most severe interference. At the same time, the bit error rate BER was calculated by reading the status page, and soft information provided by the ECC decoder was read.
[0024] By using a binary search method or gradient descent algorithm, the voltage reference value Vref that minimizes the bit error rate (BER) within a preset voltage range is selected as the optimal read voltage. The optimal read voltage is then updated in the voltage lookup table (LUT) of the controller to compensate for the threshold voltage drift that has occurred.
[0025] Furthermore, the hierarchical migration strategy specifically involves: high-priority data being pre-migrated to the idle block immediately when the system is idle; low-priority or cold data being migrated with a delay, or being compensated only by updating the read voltage.
[0026] The beneficial effects of this invention are:
[0027] 1) By dynamically predicting and intervening in advance, the error correction node is moved forward significantly from correcting uncorrectable errors that have already occurred to preventing correctable errors from worsening, which significantly reduces the probability of encountering UEs with uncorrectable errors and improves system reliability.
[0028] 2) Through fine-grained management at the word line level and a hierarchical migration strategy, the wasteful behavior of migrating the entire block due to a single word line problem in the existing technology is completely avoided. This significantly reduces the write amplification factor (WAF) and the number of invalid erase / write cycles of NAND flash memory, thereby directly extending the lifespan of eMMC.
[0029] 3) It avoids high-latency read retries or emergency data recovery operations on the critical path of user reads, resulting in more stable read latency and a better user experience.
[0030] 4) The dynamic threshold mechanism enables the system to adapt to changes in the characteristics of flash memory chips under different health conditions and working environments throughout their entire life cycle, ensuring that management strategies remain accurate and effective. Attached Figure Description
[0031] Figure 1 This is a flowchart illustrating an eMMC storage method for suppressing read interference according to the present invention. Detailed Implementation
[0032] The technical solution of the present invention will be clearly and completely described below with reference to the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0033] See Figure 1 The present invention provides a technical solution:
[0034] An eMMC storage method for suppressing read interference is applied to an eMMC storage system. The eMMC storage system includes an eMMC controller and a NAND flash memory array. The NAND flash memory array includes multiple storage blocks for data storage. The eMMC controller is equipped with a block-level read counter for each storage block and a word-line-level read counter for each word line within the storage block. The hierarchical read counter structure in the controller memory enables ultra-fine monitoring of the access frequency of storage cells.
[0035] See Figure 1 The present invention provides a technical solution:
[0036] An eMMC storage method for suppressing read interference is applied to an eMMC storage system. The eMMC storage system includes an eMMC controller and a NAND flash memory array. The NAND flash memory array includes multiple storage blocks for data storage. The eMMC controller is equipped with a block-level read counter for each storage block and a word-line-level read counter for each word line within the storage block. The hierarchical read counter structure in the controller memory enables ultra-fine monitoring of the access frequency of storage cells.
[0037] like Figure 1 As shown, the eMMC storage method includes:
[0038] S1. Receive word line read requests through the host interface, and update the word line-level read counter in real time.
[0039] S2. Obtain the P / E cycle, data retention time, and ambient temperature parameters of the memory block corresponding to the target word line, and calculate the dynamic read count threshold of the target word line;
[0040] S3. Read the count value of the word-line level read counter corresponding to the target word line, and determine whether the current read count value has reached 80% of the dynamic threshold. If it reaches 80% of the dynamic threshold but not 100%, start adaptive read voltage training to find the optimal read voltage and update the lookup table. If it reaches 100% of the dynamic threshold, issue an early warning and obtain the data priority based on the data's metadata tags or access history, and implement a hierarchical migration strategy. The metadata tags are used to describe the nature of the data, such as "system key data", "hot data", and "cold data".
[0041] The hierarchical migration strategy is as follows: high-priority data is immediately pre-migrated to the idle block when the system is idle; low-priority or cold data is migrated with a delay, or is compensated only by updating the read voltage.
[0042] S4. After the migration is complete, reset the word line read counter corresponding to the original word line.
[0043] Step S2, which involves obtaining the P / E cycle, data retention time, and ambient temperature parameters of the memory block corresponding to the target word line, and calculating the dynamic read count threshold of the target word line, specifically includes:
[0044] Obtain the current P / E cycle count C, current data retention time T, and current ambient temperature Temp from the flash memory metadata area for the memory block corresponding to the target word line;
[0045] Obtain the maximum tolerated P / E cycle count Cmax, the rated maximum data retention time Tmax, and the maximum allowable operating temperature Tempmax of the memory block corresponding to the target word line from the flash memory metadata area;
[0046] The formula for calculating the dynamic read count threshold of a word line is as follows:
[0047] ;
[0048] Among them, R base The base read count threshold is determined by the characteristics of the flash memory; α, β, and γ are the weighting coefficients for the number of P / E cycles, data retention time, and ambient temperature, respectively, which are determined through experimental fitting; n, m, and k are the correction exponents, which are usually greater than or equal to 1 and are used to describe the nonlinear relationship between the parameters and the sensitivity.
[0049] The above calculation formula takes into account multiple dynamic decay factors and quantifies their combined impact on read interference sensitivity in a non-linear superposition manner to calculate the dynamic read count threshold for each word line, so that the threshold can be adaptively adjusted according to the health status of the flash memory and changes in the environment.
[0050] In this embodiment, step S3, which involves initiating adaptive read voltage training, finding the optimal read voltage, and updating the lookup table, specifically includes:
[0051] A series of read voltage reference values Vref were iteratively tested on the target word line and its adjacent word lines with the most severe interference. At the same time, the bit error rate BER was calculated by reading the status page, and soft information provided by the ECC decoder was read.
[0052] Using a binary search or gradient descent algorithm, the voltage reference value Vref that minimizes the bit error rate (BER) within a preset voltage range is selected as the optimal read voltage. This optimal read voltage is then updated in the controller's voltage lookup table (LUT) to compensate for any threshold voltage drift. The ECC codec and the voltage lookup table work together to ensure data reliability.
[0053] The ECC (Error Correction Code) decoder is a core hardware module ensuring the reliability of NAND flash memory data. Its function is to decode data containing redundancy check information during data reading, detecting and correcting a certain number of bit errors. When the number of errors is within its error correction capability, it can silently repair the data; when the errors exceed its capability (i.e., a UE (User Equipment) error occurs, it reports a fault to the controller. Soft information, on the other hand, is a reliability metric generated by the ECC decoder during the decoding process. It not only provides a hard decision that a bit is 0 or 1, but also a soft metric about how reliable that decision is. In adaptive read voltage training, judging voltage quality solely based on "successful decoding" or a rough bit error rate is not accurate enough. Soft information (such as LLR) provides a finer-grained view of data quality, helping the training algorithm to more quickly and accurately locate the optimal read voltage Vref that maximizes overall channel reliability.
[0054] For a received signal or read bit, the LLR (Log-Likelihood Ratio) value is calculated as follows: LLR = log(P(the bit was originally 0) / P(the bit was originally 1)). LLR > 0 indicates that the decoder tends to judge the bit as originally 0; LLR < 0 indicates that it tends to judge it as 1. The larger the absolute value of LLR, the higher the confidence level of this judgment; the smaller the absolute value of LLR (closer to 0), the more unreliable the bit is, falling on the ambiguous boundary between 0 and 1.
[0055] In the voltage training process of this embodiment, when testing different Vrefs, the average or distribution of the absolute values of all relevant bits LLR is calculated. The Vref that maximizes the absolute value of the average LLR is found, which means that the overall data has the highest certainty and the fewest ambiguous bits. This usually directly corresponds to the lowest bit error rate (BER). Therefore, LLR is an extremely effective "compass" for guiding the voltage search algorithm.
[0056] A Voltage Lookup Table (LUT) is a data structure inside the controller, typically stored in SRAM. It stores optimal read voltage reference values (Vref) for different physical memory cell groups (block, word line, page level). Due to factors such as manufacturing process variations, P / E wear, read interference, data retention time, and temperature, the threshold voltage (Vth) distribution of each memory cell group will experience unique drift. The role of the LUT is to "tailor-make" the read voltage for each memory cell group to minimize the raw bit error rate (RBER) during reads.
[0057] The principle behind changing the LUT voltage to compensate for drift: Read interference causes electrons in the interfered cell to be injected into the floating gate, increasing its threshold voltage Vth (drifting in the positive direction). Standard read: A fixed default Vref is used to determine the cell state (0 or 1). When Vth shifts to the right due to interference, some cells that should be judged as "1" (high bit) may have a Vth exceeding Vc, thus being misjudged as "0" (low bit), resulting in an error.
[0058] Optimized Read: Through adaptive read voltage training, a series of Vref values are tried on the target word line and its adjacent word lines. It is found that if Vref is appropriately increased, this new decision voltage can better align with the "valley" of the Vth distribution map after interference, thereby minimizing the probability of misjudgment and significantly reducing the original bit error rate. This optimized Vc' is updated to the entry in the LUT corresponding to this word line, and all subsequent read operations on this word line will use this optimized voltage, thereby compensating for the voltage drift that has occurred.
[0059] In this embodiment, the ECC codec and voltage lookup table (LUT) work together to ensure data reliability during voltage training. When a read operation occurs, the controller first queries the LUT and reads the data using a Vref optimized for that storage location. This minimizes the raw data read from the flash array, reducing the error rate (RBER). The ECC decoder decodes the read data stream, corrects correctable errors, and ensures that the final data returned to the host is 100% correct. During the adaptive read voltage training phase, the system reads soft information provided by the ECC decoder to evaluate data quality under different Vrefs, thereby finding the optimal Vref. This forms a virtuous cycle of "LUT optimization - ECC error correction": the better the LUT is optimized, the lighter the burden on the ECC, and the higher the overall system reliability and performance.
[0060] The invention will now be described in detail through a specific embodiment:
[0061] The host requests to read the data on Word Line X of Block A.
[0062] Request Received and Count Updated: The eMMC controller receives a read request and increments the word line level read counter Cnt_WLX of Word Line X from 117,999 to 118,000.
[0063] Triggering prediction and dynamic threshold calculation: When read interference sensitivity prediction is triggered, the following parameters of Block A are obtained from the flash memory metadata area: P / E cycle count C = 5000 times, C_max = 10000 times, data retention time T = 90 days, T_max = 365 days, current temperature Temp = 55℃, Temp_max = 85℃, and preset parameters: R_base = 150000, α = 0.2, β = 0.1, γ = 0.05, n = m = k = 1.
[0064] Calculations are performed using the formula of this invention:
[0065]
[0066] To allow for a safety margin, the dynamic threshold can be set to 120,000 times.
[0067] Judgment and Decision: The system compares the current count Cnt_WLX = 118,000 with the dynamic threshold of 120,000. Since 98.3% of the threshold has been reached, the system determines it is "close to the threshold" and performs the following parallel operations:
[0068] Step a: Initiate Adaptive Read Voltage Training: The adaptive read voltage training module performs a binary search within a preset voltage range (e.g., Vref0 ± 300mV) for WL-X and its adjacent WL-X-1 and WL-X+1. By reading test patterns or user data and combining it with soft information provided by the ECC decoder, it finds the optimal Vref_new that minimizes the BER. Subsequently, the controller updates the optimal read voltage Vref_new corresponding to (Block A, WL-X) into the LUT.
[0069] Step b: Initiate hierarchical data pre-migration decision: The proactive early warning module queries the metadata tags of the WL-X data and finds that it is "system critical data" with a priority of "high". Therefore, the module schedules a background task to prepare to migrate this data to the idle block B.
[0070] Pre-migration and reset are performed: During system idle periods, the controller completely reads the data from Block A, WL-X (using an optimized Vref_new to ensure accuracy) and writes it to the free word line of Block B. Subsequently, the original WL-X data is marked as invalid, and Cnt_WLX is reset to 0. The metadata table is updated to record the physical location of the new data.
[0071] Request Response: Before or simultaneously with completing any of the necessary background operations described above, the controller has returned the requested data to the host using the currently optimal read voltage. The entire process is transparent to the host, and the read latency is stable.
[0072] Modern eMMC controllers typically employ programmable ARM or RISC-V cores, possessing the computational capabilities to implement the aforementioned algorithms and counter management. Read voltage training (read retry) is existing technology; this invention elevates it from "post-fault recovery" to "pre-fault optimization." The memory overhead required for fine-grained counters is controllable; for example, a 10GB eMMC, assuming 100,000 word lines and 4 bytes per counter, would have a total overhead of approximately 400KB.
[0073] All prediction, training, and migration operations are performed in the background or when the system is idle, without affecting the real-time performance of foreground read and write operations. Proactive voltage training avoids more time-consuming read retry sequences. This invention is primarily implemented through firmware / algorithm, requiring no additional dedicated hardware, resulting in minimal cost increase and easy deployment in existing eMMC products. Simulation results demonstrate that this invention effectively reduces the uncorrectable error rate caused by read interference by more than an order of magnitude, while simultaneously reducing additional write operations due to read interference management by 50%-70%, thereby significantly extending product lifespan.
[0074] The above description is merely a preferred embodiment of the present invention. It should be understood that the present invention is not limited to the forms disclosed herein and should not be construed as excluding other embodiments. It can be used in various other combinations, modifications, and environments, and can be altered within the scope of the concept described herein through the above teachings or related technologies or knowledge. Modifications and variations made by those skilled in the art that do not depart from the spirit and scope of the present invention should be within the protection scope of the appended claims.
Claims
1. A method for suppressing read interference in eMMC storage, applied to an eMMC storage system, characterized in that: The eMMC storage system includes an eMMC controller and a NAND flash memory array. The NAND flash memory array includes multiple storage blocks for data storage. The eMMC controller is equipped with a block-level read counter for each storage block and a word-line-level read counter for each word line within the storage block. The eMMC storage method includes: The host interface receives word line read requests, and the word line-level read counter is updated in real time. Obtain the P / E cycle, data retention time, and ambient temperature parameters of the memory block corresponding to the target word line, and calculate the dynamic read count threshold of the target word line; Read the count value of the word-line level read counter corresponding to the target word line, and determine whether the current read count value has reached 80% of the dynamic threshold; If the dynamic threshold is reached at 80% but not 100%, adaptive read voltage training is initiated to find the optimal read voltage and update the lookup table; if the dynamic threshold is reached at 100%, an early warning is issued, and data priority is obtained based on the data's metadata tags or access history, and a hierarchical migration strategy is implemented. After the migration is complete, reset the word line read counter corresponding to the original word line.
2. The eMMC storage method for suppressing read interference according to claim 1, characterized in that: The process of obtaining the P / E cycle, data retention time, and ambient temperature parameters of the memory block corresponding to the target word line, and calculating the dynamic read count threshold of the target word line, specifically includes: Obtain the current P / E cycle count C, current data retention time T, and current ambient temperature Temp from the flash memory metadata area for the memory block corresponding to the target word line; Obtain the maximum tolerated P / E cycle count Cmax, the rated maximum data retention time Tmax, and the maximum allowable operating temperature Tempmax of the memory block corresponding to the target word line from the flash memory metadata area; The formula for calculating the dynamic read count threshold of a word line is as follows: ； Among them, R base The base read count threshold is determined by the characteristics of the flash memory; α, β, and γ are the weighting coefficients for the number of P / E cycles, data retention time, and ambient temperature, respectively, which are determined through experimental fitting; n, m, and k are the correction exponents, which are usually greater than or equal to 1 and are used to describe the nonlinear relationship between the parameters and the sensitivity.
3. The eMMC storage method for suppressing read interference according to claim 1, characterized in that: The process of initiating adaptive read voltage training, finding the optimal read voltage, and updating the lookup table specifically includes: A series of read voltage reference values Vref were iteratively tested on the target word line and its adjacent word lines with the most severe interference. At the same time, the bit error rate BER was calculated by reading the status page, and soft information provided by the ECC decoder was read. By using a binary search method or gradient descent algorithm, the voltage reference value Vref that minimizes the bit error rate (BER) within a preset voltage range is selected as the optimal read voltage. The optimal read voltage is then updated in the voltage lookup table (LUT) of the controller to compensate for the threshold voltage drift that has occurred.
4. The eMMC storage method for suppressing read interference according to claim 1, characterized in that: The hierarchical migration strategy is as follows: high-priority data is immediately pre-migrated to the idle block when the system is idle; low-priority or cold data is migrated with a delay, or is compensated only by updating the read voltage.