Integrated dc-dc fault handling circuit based on containment feedback

Abstract

This invention belongs to the field of chip integration technology and relates to an integrated DC-DC fault handling circuit based on feedback tolerance. It includes: a DC-DC output terminal connected to the input terminal of an output control unit and a fault modulation-feedback coordination unit; an output terminal of the output control unit connected to the input terminal of the fault modulation-feedback coordination unit; an output terminal of the fault modulation-feedback coordination unit connected to the input terminal of a primary-side latch unit and the input terminal of a power transmission control unit; an output terminal of the primary-side latch unit connected to a PG signal module and the input terminal of the power transmission control unit; an output terminal of the PG signal module connected to the input terminal of a dual unlocking control unit; an output terminal of the dual unlocking control unit connected to the input terminals of the primary-side latch unit and the power transmission control unit; and an output terminal of the power transmission control unit connected to the DC-DC input terminal. The fault handling circuit of this invention provides a complete fault detection-modulation-demodulation-latch-unlocking process path, enabling fault handling.

Description

Technical Field

[0001] This invention belongs to the field of chip integration technology and relates to an integrated DC-DC fault handling circuit based on isolation feedback. Background Technology

[0002] Existing magnetically isolated DC-DC converters rely heavily on a split design of "core chip + external components" for fault handling and feedback (such as the ADI ADUM3070 isolated switching regulator). This requires external Schottky diodes, filter inductors, or capacitors to achieve secondary rectification and voltage regulation. Furthermore, the ADI ADuM347x isolator requires an external power transformer (T1) and rectifier (RECT) to complete energy transfer. This results in large parasitic parameters in the system (e.g., the wiring inductance of the ADUM3070 external inductor is ≥30nH), redundant chip interfaces (occupying an additional 3-5 I / O pins), and increased board area (external components occupy a total board area of ​​≥4mm²).

[0003] Some solutions only integrate a single function of fault detection or feedback, failing to cover the entire chain (such as the DC-DC fault detection method based on incremental iterative correlation coefficients). They can only achieve fault identification through the sudden change in the correlation coefficient between current ripple and PWM signal, requiring an external feedback modulation chip and unlocking controller. Another example is the fault diagnosis device based on the voltage of magnetic components, which only focuses on the filtering and logic comparison of fault signals, lacking tolerance feedback and latching functions, resulting in the need for multiple chips to be cascaded and a delayed fault response.

[0004] Existing multi-functional integrated solutions (such as the ST A6983I automotive isolated power supply) integrate synchronous rectification and overvoltage / overcurrent protection, but the functional units are not optimized around the magnetic isolation core. The fault detection unit and primary latch unit are scattered at both ends of the chip, resulting in the fault + feedback unit accounting for ≥32% of the total chip area. Moreover, the unlocking function only supports a single path through the external ENA pin, relying on the vehicle controller for triggering, which results in insufficient operational flexibility. In addition, industrial 48V to 12V isolated DC-DC solutions, although integrating magnetic components through multi-phase coupled inductors, do not integrate a single-chip fault handling module, requiring external protection circuits and resulting in poor adaptability. Summary of the Invention

[0005] To address the aforementioned problems in the prior art, this invention employs an integrated DC-DC fault handling circuit based on feedback tolerance, comprising: an output control unit, a fault modulation-feedback coordination unit, a primary-side latch unit, a power transmission control unit, a dual unlocking control unit, and a PG signal module; the output terminal of the DC-DC converter is connected to the input terminal of the output control unit and the fault modulation-feedback coordination unit, the output terminal of the output control unit is connected to the input terminal of the fault modulation-feedback coordination unit, the output terminal of the fault modulation-feedback coordination unit is connected to the input terminal of the primary-side latch unit and the input terminal of the power transmission control unit, the output terminal of the primary-side latch unit is connected to the input terminal of the PG signal module and the input terminal of the power transmission control unit, the output terminal of the PG signal module is connected to the input terminal of the dual unlocking control unit, the output terminal of the dual unlocking control unit is connected to the input terminals of the primary-side latch unit and the power transmission control unit, and the output terminal of the power transmission control unit is connected to the input terminal of the DC-DC converter; wherein, the DC-DC converter is a DC-DC converter, and the PG signal module is a power-ready signal module.

[0006] Beneficial effects:

[0007] 1. The fault handling circuit of this invention is a complete fault detection-modulation-demodulation-latch-unlocking process path. This path detects secondary faults through a secondary fault detection unit. If there is no secondary fault, the secondary fault detection unit outputs a normal feedback signal, which is directly transmitted to the power transmission control unit through the modulation transmitter (TX) and demodulation receiver (RX). In the absence of secondary faults and latching, PWM modulation is performed on the power stage of the primary power supply unit. If there is a secondary fault, the normal feedback signal will be shielded by the fault signal. At this time, the secondary fault detection unit outputs a fault signal, which is transmitted to the power transmission control unit through the modulation transmitter (TX) and demodulation receiver (RX). After the receiver demodulates the RX signal, it sends it to the primary-side latch unit. The primary-side latch unit outputs a high-level latch signal LATCH. The LATCH signal then pulls down the power control input of the primary power supply unit, causing the primary power supply unit to stop transmitting power to the secondary power supply unit. At the same time, the dual unlock control unit can clear the latch signal, allowing the system to resume operation, thereby effectively controlling the power transmission from the primary power supply unit to the secondary power supply unit. 2. This invention integrates full-link functions on a single chip, requiring no external auxiliary modules. The chip system occupies more than 40% of the board area, adapting to the miniaturization packaging requirements of magnetically isolated DC-DC chips. Attached Figure Description

[0008] Figure 1 A structural diagram of an integrated DC-DC fault handling circuit based on tolerant feedback provided in an embodiment of the present invention;

[0009] Figure 2 A flowchart illustrating an integrated DC-DC fault handling method based on tolerant feedback, provided for an embodiment of the present invention;

[0010] Figure 3 The diagram shows the structure of a DC-DC converter provided in an embodiment of the present invention.

[0011] Figure 4 This is a structural diagram of the primary-side latch circuit provided in an embodiment of the present invention.

[0012] Figure 5 The circuit diagram of the Watch_Dog And ENA_RESET module provided in the embodiments of the present invention;

[0013] Figure 6 A circuit diagram of a secondary fault detection unit provided in an embodiment of the present invention;

[0014] Figure 7 The circuit diagram of the PG signal module provided in the embodiment of the present invention. Detailed Implementation

[0015] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0016] like Figure 1 As shown, this embodiment of the invention employs an integrated DC-DC fault handling circuit based on feedback tolerance, comprising: an output control unit, a fault modulation-feedback coordination unit, a primary-side latch unit, a power transmission control unit, a dual unlocking control unit, and a PG signal module; the output terminal of the DC-DC converter is connected to the input terminal of the output control unit and the fault modulation-feedback coordination unit, the output terminal of the output control unit is connected to the input terminal of the fault modulation-feedback coordination unit, the output terminal of the fault modulation-feedback coordination unit is connected to the input terminal of the primary-side latch unit and the input terminal of the power transmission control unit, the output terminal of the primary-side latch unit is connected to the input terminal of the PG signal module and the input terminal of the power transmission control unit, the output terminal of the PG signal module is connected to the input terminal of the dual unlocking control unit, the output terminal of the dual unlocking control unit is connected to the input terminals of the primary-side latch unit and the power transmission control unit, and the output terminal of the power transmission control unit is connected to the input terminal of the DC-DC converter; wherein, the DC-DC converter is a DC-DC converter, and the PG signal module is a power-ready signal module.

[0017] The integrated DC-DC fault handling circuit also includes an OSC32K module and a voltage protection module. The OSC32K module outputs a 32kHz clock signal. The input of the voltage protection module is connected to the DC-DC power supply VIN. The output of the voltage protection module outputs an undervoltage lockout signal UVLO and an overvoltage lockout signal OVLO. The undervoltage lockout signal UVLO and the overvoltage lockout signal OVLO are obtained by sampling the DC-DC power supply VIN and comparing it with a reference voltage source through a hysteresis comparator.

[0018] Undervoltage lockout (UVLO): Triggers protection when the monitored power supply voltage is lower than a preset threshold (reference voltage source); Overvoltage lockout (OVLO): Triggers protection immediately when the monitored power supply voltage is higher than a preset threshold (reference voltage source).

[0019] In one embodiment, the reference voltage source for undervoltage lockout is VREF0P8, and the reference voltage source for overvoltage lockout (OVLO) is VREF0P725.

[0020] like Figure 3 As shown, the DC-DC converter includes: a primary power supply unit, a transformer, and a secondary power supply unit; the output of the primary power supply unit is connected to the input of the secondary power supply unit through the transformer, and the output of the secondary power supply unit is connected to the output control unit and the input of the fault modulation-tolerance feedback coordination unit after voltage division.

[0021] The primary power supply unit includes: a power supply, switching circuits (transistors Q1~Q4), a gate-drive logic and level shifting unit, and an Oscillator SSM (spread spectrum modulation oscillator). The positive terminal VIN and negative terminal GNDP of the power supply are connected to the switching circuit. The Oscillator SSM controls the gate-drive logic and level shifting unit to generate dead zones, thereby controlling the conduction of transistors Q1, Q4 and Q2, Q3 respectively. The resulting transient current is transferred to the secondary power supply unit through a transformer. The secondary power supply unit performs full-bridge rectification on the transferred current to generate secondary power to supply power to the load. The entire chip is powered solely by the primary power supply unit; the secondary power supply is supplied by the primary power supply unit through an integrated transformer and does not require a separate power supply.

[0022] The secondary power supply side unit includes: Schottky diodes D1~D4, which generate the secondary power supply (positive power supply VDD, negative power supply VEE).

[0023] Industrial-grade and automotive-grade integrated DC-DC converters incorporate a soft-start unit, which directly outputs the SLOW_START_OK signal. Without any external circuitry, it can output the secondary soft-start ready signal SLOW_START_OK, which signifies that the secondary power supply's soft-start process is complete, the output voltage has steadily risen to the rated value, and it has entered a stable operating state.

[0024] The output control unit includes: resistors R1~R2, capacitors C1~C2, a reference voltage source VREF, and comparator A1. The non-inverting input of comparator A1 is connected to one end of resistor R1 and one end of capacitor C1, with the other end of capacitor C1 grounded. The other end of resistor R1 is connected to voltage FBVDD. Voltage FBVDD is the voltage after voltage division at the output of the DC-DC converter, i.e., the voltage after voltage division of the secondary power supply of the secondary power supply side unit. The inverting input of comparator A1 is connected to one end of resistor R2 and one end of capacitor C2, with the other end of capacitor C2 grounded. The other end of resistor R2 is connected to one end of the reference voltage source VREF, with the other end of reference voltage source VREF grounded. The output of comparator A1 is the output of the output control unit and is connected to the input of the fault modulation-tolerance feedback coordination unit. The reference voltage source VREF is VREF2P5, which is a 2.5V reference voltage source.

[0025] The fault modulation-isolation feedback coordination unit includes: a secondary fault detection unit, an oscillator (OSC100MSSM), a modulation transmitter (TX), an isolation feedback unit, and a demodulation receiver (RX); the oscillator outputs a 500kHz modulation signal and a 100MHz modulation signal; the input of the secondary fault detection unit is connected to the 500kHz modulation signal and the output of the output control unit; the input of the modulation transmitter (TX) is connected to the output of the secondary fault detection unit and the 100MHz modulation signal; the output of the modulation transmitter (TX) is connected to the input of the isolation feedback unit; the output of the isolation feedback unit is connected to the input of the demodulation receiver (RX); the output of the demodulation receiver (RX) is the output of the fault modulation-isolation feedback coordination unit, which is connected to the input of the power transmission control unit and the primary-side latch unit.

[0026] like Figure 6 As shown, the secondary fault detection unit includes: comparators CMP1~CMP3, AND gates AND5~AND8, NAND gate NAND1, OR gate OR3, inverter INV3, temperature sensor, and reference voltage source VREF; the temperature sensor outputs voltage V_TSENSER; the reference voltage source VREF outputs reference voltages VREF0P4, VREF0P5, VREF2P25, and VREF2P75;

[0027] Hysteresis comparator CMP1 has its non-inverting input connected to the voltage V_TSENSER output from the temperature sensor, and its inverting input connected to the reference voltage source VREF (i.e., reference voltages VREF0P4 and VREF0P5). Comparator CMP2 has its non-inverting input connected to the voltage FBVDD, and its inverting input connected to the reference voltage source VREF (i.e., reference voltage VREF2P25). Comparator CMP3 has its inverting input connected to the voltage FBVDD, and its non-inverting input connected to the reference voltage source VREF (i.e., reference voltage VREF2P75). Here, voltage FBVDD is the voltage obtained by dividing the output voltage of the DC-DC converter.

[0028] The outputs of comparators CMP2 and CMP3 are connected to the inputs of AND gate AND5. The outputs of AND gate AND5 and comparator CMP1 are connected to the inputs of NAND gate NAND1. The output of NAND gate NAND1 is connected to one input of AND gate AND6. The other input of AND gate AND6 is connected to the DC-DC soft-start ready signal SLOW_START_OK. The output (FAULT) of AND gate AND6 is connected to one input of AND gate AND7 and the input of inverter INV3. The other input of AND gate AND7 is connected to a 500kHz modulation signal. The output of inverter INV3 is connected to one input of AND gate AND8. The other input of AND gate AND8 is connected to the output of the output control unit (i.e., signal CMP_OUT). The outputs of AND gate AND7 and AND gate AND8 are connected to the inputs of OR gate OR3. The output of OR gate OR3 is the output of the secondary fault detection unit.

[0029] The secondary fault detection unit (Sencondary-side feedback regulation and fault monitoring) receives the signal CMP_OUT output by comparator A1, the 500kHz modulation signal OSC_500K, and the temperature sensor output voltage V_TSENSER, and outputs a fault detection signal. If a fault is detected, the fault detection signal is the fault signal, i.e., the 500kHz modulation signal. If no fault is detected, the fault detection signal is the normal feedback signal, i.e., the signal CMP_OUT output by the output terminal of the output control unit.

[0030] The modulation transmitter TX (located near the secondary side and built into the chip) integrates an OOK modulator using BCD technology. Its carrier frequency is 100MHz, provided by an oscillator (OSC100MSSM). It is used to modulate the signal output from the secondary fault detection unit into a high-frequency differential signal, working in conjunction with the on-chip internal isolation feedback unit.

[0031] The feedback unit (built into the chip) uses BCD-compatible MIM capacitors C3 and C4, namely metal-insulator-metal capacitors; one end of capacitors C3 and C4 is connected to the output of the modulation transmitter TX, and the other end of capacitors C3 and C4 is connected to the input of the demodulation receiver RX.

[0032] The demodulation receiver RX (located near the primary side, built into the chip) integrates a 100MHz bandpass filter (BCD active filter structure) and a demodulation unit to demodulate the differential signal output from the isolation feedback unit and send it to the primary side latch unit.

[0033] like Figure 4 As shown, the primary-side latch unit includes: power supply VDD5, AND gate AND1, AND gate AND2, AND gate AND8, AND gate OR8, SR latch SRFF3, SR latch SRFF4, four cascaded divide-by-two D flip-flops DFF10~DFF13, operational amplifier A2, inverters INV1~INV2, capacitor C5, current source, transistor Q6, and reference voltage source VREF; the four cascaded divide-by-two D flip-flops serve as an octet divide-by-eight circuit;

[0034] The input of inverter INV1 is the reset terminal of the primary-side latch unit, connected to the reset signal RESET output by the dual unlock control unit. The output of inverter INV1 is connected to the gate of transistor Q6. The source of transistor Q6 and one end of capacitor C5 are grounded. The drain of transistor Q6, the other end of capacitor C5, and the inverting input of operational amplifier A2 are connected to the output of current source. The input of current source is connected to power supply VDD5 (i.e., 5V power supply). The non-inverting input of operational amplifier A2 is connected to reference voltage source VREF (i.e., reference voltage VREF2P5). The enable terminal of operational amplifier A2 is connected to the enable signal EN, which is the OK signal reported after BG is established (such as baseband initialization, hardware configuration loading, and successful link connection). The output of operational amplifier A2 outputs signal R and is connected to the input of inverter INV2. The output of inverter INV2 outputs signal RN.

[0035] The input of AND gate AND1 is connected to the output of the OSC32K module and the enable signal EN. The output of AND gate AND1 is connected to the asynchronous reset terminals of four D flip-flops DFF10~DFF13. The D terminals of the four D flip-flops DFF10~DFF13 are respectively connected to their respective... The CLK terminal of D flip-flop DFF10 is connected to the output terminal (RX_OUT) of the fault modulation-tolerance feedback coordination unit; D flip-flops DFF10~DFF13 are cascaded in sequence, with the previous D flip-flop's... The terminal is connected to the CLK terminal of the next D flip-flop (i.e., the CLK terminal of D flip-flop DFF11 is connected to the CLK terminal of D flip-flop DFF10). The CLK terminal of D flip-flop DFF12 is connected to the terminal of D flip-flop DFF11. The CLK terminal of D flip-flop DFF13 is connected to the terminal of D flip-flop DFF12. end);

[0036] The Q terminal of the D flip-flop DFF13 and the output terminal (signal RN) of the inverter INV2 are connected to the input terminal of the AND gate AND2. The output terminal of the AND gate AND2 is connected to the S terminal of the SR latch SRFF3. The enable terminal of the SR latch SRFF3 is connected to the enable signal EN. The R terminal of the SR latch SRFF3 is connected to the output terminal (signal R) of the operational amplifier A2. The Q terminal of the SR latch SRFF3 outputs the latch signal LATCH, which is the error latch status output signal.

[0037] The input of OR gate OR8 is connected to the Q terminal (i.e., the latch signal LATCH) of SR latch SRFF3 and the timing output signal TIMER_OUT. The output is connected to one input of AND gate AND8. The other input of AND gate AND8 is connected to the output (signal RN) of inverter INV2. The output of AND gate AND8 is connected to the S terminal of SR latch SRFF4. The enable terminal of SR latch SRFF4 is connected to the enable signal EN. The R terminal of SR latch SRFF4 is connected to the output (signal R) of operational amplifier A2. The QN terminal of SR latch SRFF4 outputs the feedback signal SENCOND_FEEDBACK. This signal indicates that if there is no latch or the watchdog timer has finished, the signal outputs 1; otherwise, it outputs 0.

[0038] In this SR latch, the S, R, Q, and QN terminals are the set input, reset input, positive output, and inverted output, respectively; the CLK, D, and Q terminals of the D flip-flop are... The terminals are respectively clock input, data input, positive output, and negative output.

[0039] When the input of the primary-side latch unit is a 500kHz fault trigger signal OSC_500K, since 32kHz is less than 500kHz after eight cycles, the D flip-flop of the primary-side latch unit cannot be reset and will input a high level to the SR latch SRFF3 to latch the power transmission control unit.

[0040] The dual unlock control unit includes an AND gate AND3 and a Watch_Dog And ENA_RESET module. The Watch_Dog And ENA_RESET module includes a Watch_Dog module (watchdog module) and an ENA_RESET module (enable and reset module). The inputs of the Watch_Dog And ENA_RESET module are connected to the output of the OSC32K module, the enable signal EA, and the undervoltage lockout signal UVLO, respectively. The outputs are the timing output signal TIMER_OUT and the enable and reset signal ENA_RESET, respectively. The timing output signal TIMER_OUT is connected to the input of the power transmission control unit. The enable and reset signal ENA_RESET is connected to one input of the AND gate AND3, and the other input of the AND gate AND3 is connected to the undervoltage lockout signal UVLO. The output of the AND gate AND3 outputs the reset signal RESET and is connected to the reset terminal of the primary-side latch unit.

[0041] like Figure 5 As shown, the ENA_RESET module includes: AND gates AND9~AND, SR latch SRFF1, inverters INV4~INV8, multiplexer MUX1, and buffers BUF1~BUF2; the Watch_Dog module includes: AND gates AND16~AND21, 10 cascaded D flip-flops DFF0~DFF9, SR latch SRFF2, inverters INV9~INV11, clock gating unit ICG2, and OR gates OR4~OR7;

[0042] The input of inverter INV4 is connected to the enable signal EN, the output is connected to the signal ENN and the input of inverter INV5 is connected to the output of inverter INV5. The output of inverter INV5 is the signal ENP.

[0043] AND gate AND9's input is connected to the output of inverter INV5 (i.e., signal ENP) and undervoltage lockout signal UVLO, and its output is signal ENA. AND gate AND10's input is connected to the output of AND gate AND9 (i.e., signal ENA) and the output of inverter INV11 (i.e., signal TIMER_OUT_B), and its output is connected to one input of AND gate AND11. Inverter INV6's input is connected to the output of the PG signal module (i.e., power good drop signal PG_DOWN), and its output is connected to the other input of AND gate AND11. AND gate AND11 outputs a signal. ;

[0044] The input of AND gate AND12 is connected to the output of inverter INV4 (i.e., signal ENN) and the undervoltage lockout signal UVLO. The output signal ENB is connected to one input of AND gate AND13. The other input of AND gate AND13 is connected to the output of inverter INV7 (i.e., the reset signal ENA_RESET). The output of AND gate AND13 is connected to the input of buffer BUF1. The output of buffer BUF1 is connected to the input of buffer BUF2. The output of buffer BUF2 outputs a signal. ;

[0045] The input terminal A of the multiplexer MUX1 is connected to the output terminal of the OSC32K module (i.e., the clock signal CLK_32K), the input terminal B is grounded to GND, the selection control terminal S is connected to the Q terminal of the SR latch SRFF1 (i.e., the signal SET), the enable terminal is connected to the output terminal of the AND gate AND12 (i.e., the signal ENB), and the output terminal Y outputs the signal CP_1.

[0046] The input of AND gate AND14 is connected to the Q output (i.e., signal Q) of D flip-flops DFF0~DFF2. <0> Q <1> And Q <2> The output terminal is connected to one input terminal of AND gate AND15, the other input terminal of AND gate AND15 is connected to the output terminal of AND gate AND12 (i.e., signal ENB), the output terminal of AND gate AND15 is connected to the S terminal of SR latch SRFF1, the enable terminal of SR latch SRFF1 is connected to the output terminal of AND gate AND12 (i.e., signal ENB), the R terminal of SR latch SRFF1 is connected to the output terminal of inverter INV8 (i.e., signal RESET_1), and the Q terminal of SR latch SRFF1 outputs the signal SET; the input terminal of inverter INV7 is connected to the Q terminal of SR latch SRFF1 (i.e., signal SET), and the output terminal outputs the signal ENA_RESET; the input terminal of inverter INV8 is connected to the output terminal of AND gate AND12 (i.e., signal ENB), and the output terminal outputs the signal RESET_1; wherein, the S terminal, R terminal, and Q terminal of SR latch SRFF1 are the set input port, the reset input port, and the positive output port, respectively.

[0047] The input terminal A of the multiplexer MUX2 is connected to the output terminal of the OSC32K module (i.e., the clock signal CLK_32K), the input terminal B is grounded (GND), the selection control terminal S is connected to the Q terminal of the SR latch SRFF2 (i.e., signal S), the enable terminal is connected to the output terminal of the AND gate AND9 (i.e., signal ENA), and the output terminal Y outputs the signal CP_1. Among them, the input terminal A is the first data input terminal, the input terminal B is the second data input terminal, the selection control terminal S=0 selects port A, S=1 selects port B, and the output terminal Y is the output of this unit. According to the value of S, the signal from input terminal A or input terminal B is transmitted.

[0048] The input of OR gate OR4 is connected to the output Y (signals CP_1 and CP_2) of multiplexers MUX1 and MUX2, and the output of OR gate OR4 is connected to the CLK terminal of D flip-flop DFF0; D flip-flops DFF0 to DFF9 are connected in series, with the D terminal of the previous D flip-flop connected to the CLK terminal of the D flip-flop DFF0. The terminal is connected to the CLK terminal of the next D flip-flop, DFF1; the Q terminals of D flip-flops DFF0 to DFF9 output signals Q respectively. <0> ~ Q <9> The inputs of OR gates OR5~OR7 are connected to the output of AND gate AND11 and the output of buffer BUF2 (i.e., the signal). and signal The output of OR gate OR5 is connected to the asynchronous reset terminal of D flip-flop DFF0. The output of OR gate OR6 is connected to the asynchronous reset terminal of D flip-flop DFF1, and the output of OR gate OR7 is connected to the asynchronous reset terminal of D flip-flop DFF2. ); Asynchronous reset terminals of D flip-flops DFF3~DFF9 ( Connect to the output terminal of AND gate AND11 (i.e., signal) ); where the CLK terminal, D terminal, Q terminal, and D terminal of the D flip-flop. The terminals are respectively clock input, data input, positive output, and negative output.

[0049] The input of AND gate AND16 is connected to the Q output (i.e., signal Q) of D flip-flops DFF0~DFF2. <0> ~ Q <2> The input of AND gate AND17 is connected to the Q output (i.e., signal Q) of D flip-flops DFF3~DFF5. <3> ~ Q <5> The input of AND gate AND18 is connected to the Q output (i.e., signal Q) of D flip-flops DFF6~DFF8. <6> ~ Q <8> The outputs of AND gates AND16, AND17, and AND18 are connected to the input of AND gate AND19. The output of AND gate AND19 is connected to one input of AND gate AND20. The other input of AND gate AND20 is connected to the Q input of D flip-flop DFF9 (i.e., signal Q). <9> The output of AND gate AND20 is connected to one input of AND gate AND21. The other input of AND gate AND21 is connected to the output of inverter INV5 (i.e., signal ENP). The output of AND gate AND21 is connected to the S terminal of SR latch SRFF2. The input of inverter INV10 is connected to the output of inverter INV5 (i.e., signal ENP), and its output outputs a reset signal RESET_2. The enable terminal of SR flip-flop SRFF2 is connected to the output of inverter INV5 (i.e., signal ENP). The R terminal of SR latch SRFF2 is connected to the output of inverter INV10 (reset signal RESET_2). The Q terminal of SR latch SRFF2 outputs signal S and is connected to the input of inverter INV11. The output of inverter INV11 outputs signal TIMER_OUT_B. The input of inverter INV12 is connected to the output of inverter INV11 (i.e., signal TIMER_OUT_B), and its output outputs a timing output signal TIMER_OUT.

[0050] When ENP and UVLO are high, and SECOND_INT (the latch signal for the first high level of RX_OUT, indicating that the secondary side can transmit a signal) is low, the watchdog timer will not reset the 10 D flip-flops, and the watchdog timer will continue timing normally. If all 10 flip-flops output high, i.e., the timing reaches approximately 35ms, TIMER_OUT will output high, controlling the power stage to stop transmitting energy to the secondary side. If the secondary side can transmit a signal within 35ms, SECOND_INT will go high, clearing all the D flip-flops, and the watchdog timer will stop timing.

[0051] The power transmission control unit includes: OR gates OR1~OR2 and transistor Q5; the input of OR gate OR1 is connected to the output of the primary side latch unit (latch signal LATCH) and the output of the dual unlock control unit (i.e., the timing output signal TIMER_OUT); the output of OR gate OR1 is connected to one input of OR gate OR2; the other input of OR gate OR2 is connected to the output of the fault modulation-tolerance feedback coordination unit; the output of OR gate OR2 is connected to the gate of transistor Q5; the drain of transistor Q5 is connected to the input of DC-DC converter (i.e., the input of the gate drive logic-level conversion circuit); and the source of transistor Q5 is grounded.

[0052] The PG signal module outputs a power good drop signal PG_DOWN. Externally, this signal can be used to determine whether the circuit is working properly. A low level indicates that the circuit is normal, and a high level indicates that the circuit is abnormal.

[0053] like Figure 7 As shown, the PG signal module includes: power supply VDD5, AND gate AND4, resistor R3, and transistor Q7; the input of AND gate AND4 is connected to the undervoltage lockout signal UVLO, the overvoltage lockout signal OVLO, and the feedback signal SECOND_FEEDBAKE; the output of AND gate AND4 is connected to the gate of transistor Q7, the drain of transistor Q7 is connected to one end of resistor R3, the other end of resistor R3 is connected to power supply VDD5, and the source of transistor Q7 is grounded; the drain of transistor Q7 outputs the power good drop signal PG_DOWN.

[0054] The feedback signal SECOND_FEEDBAKE is used to determine whether the system is not latched or whether the watchdog timer is not triggered. When UVLO, OVLO, and the SECOND_FEEDBAKE signal are all high, the output is high after passing through the AND gate, which will pull down the power good drop signal PG_DOWN.

[0055] like Figure 2 As shown, the circuit works as follows:

[0056] If no secondary fault occurs, the output level of comparator A1 is transmitted to the power transmission control unit through the modulation transmitter TX and the demodulation receiver RX. In the absence of secondary fault and latching, PWM modulation is performed on the power stage of the primary power supply unit.

[0057] The PWM modulation of the power stage of the primary power supply unit includes: hysteresis threshold comparator A1 compares the voltage FBVDD with the reference voltage source VREF. If the hysteresis threshold comparator A1 outputs a high level, it is considered that the power control duty cycle of the primary power supply unit is too large. The modulation transmitter TX is transmitted through the 100M carrier signal generated by OSC100M. The demodulation receiver RX demodulates a high level RX_OUT. RX_OUT passes through an OR gate to control transistor Q5 (NMOS transistor). If RX_OUT is high, the input of transistor Q5 is high, and its drain is pulled low, i.e., gate driver logic and level shifting. If the output is low, no square wave is supplied to the power stage, energy is no longer transmitted, and the power transmission cycle is reduced. If the hysteresis threshold comparator A1 outputs a low level, it is considered that the power control duty cycle of the primary power supply unit is too small. The modulation transmitter TX transmits through the 100M carrier signal generated by OSC100M. The demodulation receiver RX demodulates a low level RX_OUT, so the input of transistor Q5 is high, and its drain is no longer pulled low, allowing energy to be transmitted and increasing the power transmission cycle.

[0058] If a fault occurs in the secondary side, such as overvoltage, undervoltage, overcurrent, or overtemperature, i.e., the secondary fault signal is triggered, the output signal of the hysteresis threshold comparator A1 will become ineffective. The modulating transmitter TX will no longer transmit the output signal of the hysteresis threshold comparator, but instead transmit a 500kHz fault signal divided from the 100MHz carrier. After being modulated by the modulating transmitter TX and demodulated by the demodulating receiver RX, the fault signal is sent to the primary side latch unit. The primary side latch unit outputs a high-level LATCH signal, which in turn pulls down the power control input of the primary power supply unit, causing the primary power supply unit to stop transmitting power to the secondary power supply unit.

[0059] To disable the LATCH signal, there are two options:

[0060] 1. Reset UVLO by powering down the primary power supply unit;

[0061] 2. After the enable signal EN is pulled low for 250µs, the Watch_Dog And ENA_RESET module will generate an ENA_RESET falling pulse signal. The two signals are input into the primary side latch unit through AND gate AND3 to reset the LATCH signal and thus release the latch.

[0062] If the secondary side fails to power on, no signal will be transmitted to the primary side via TX and RX. After a 35ms wait, the Watch_Dog And ENA_RESET module will pull TIMER_OUT high to stop sending power to the secondary side. The method to release this signal is the same as releasing the LATCH signal.

[0063] The above-described embodiments further illustrate the purpose, technical solution, and advantages of the present invention. It should be understood that the above-described embodiments are merely preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made to the present invention within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. An integrated DC-DC fault handling circuit based on tolerant feedback, characterized in that, include: The system comprises an output control unit, a fault modulation-tolerance feedback coordination unit, a primary-side latch unit, a power transmission control unit, a dual unlocking control unit, and a PG signal module. The output of the DC-DC converter is connected to the input of the output control unit and the fault modulation-tolerance feedback coordination unit. The output of the output control unit is connected to the input of the fault modulation-tolerance feedback coordination unit. The output of the fault modulation-tolerance feedback coordination unit is connected to the input of the primary-side latch unit and the power transmission control unit. The output of the primary-side latch unit is connected to the input of the PG signal module and the power transmission control unit. The output of the PG signal module is connected to the input of the dual unlocking control unit. The output of the dual unlocking control unit is connected to the input of the primary-side latch unit and the power transmission control unit. The output of the power transmission control unit is connected to the input of the DC-DC converter. The DC-DC converter is a DC-DC converter, and the PG signal module is a power-ready signal module.

2. The integrated DC-DC fault handling circuit based on tolerant feedback according to claim 1, characterized in that, The output control unit includes: resistors R1~R2, capacitors C1~C2, a reference voltage source VREF, and comparator A1; The non-inverting input of comparator A1 is connected to one end of resistor R1 and one end of capacitor C1, respectively. The other end of capacitor C1 is grounded, and the other end of resistor R1 is connected to voltage FBVDD; voltage FBVDD is the voltage after voltage division of the output voltage of DC-DC converter. The inverting input of comparator A1 is connected to one end of resistor R2 and one end of capacitor C2, respectively. The other end of capacitor C2 is grounded. The other end of resistor R2 is connected to one end of reference voltage source VREF, and the other end of reference voltage source VREF is grounded. The output of comparator A1 is the output of the output control unit.

3. The integrated DC-DC fault handling circuit based on tolerant feedback according to claim 1, characterized in that, The fault modulation-tolerance feedback coordination unit includes: a secondary fault detection unit, an oscillator, a modulation transmitter (TX), a tolerance feedback unit, and a demodulation receiver (RX); the oscillator outputs a 500kHz modulation signal and a 100MHz modulation signal; the input of the secondary fault detection unit is connected to the 500kHz modulation signal and the output of the output control unit; the input of the modulation transmitter (TX) is connected to the output of the secondary fault detection unit and the 100MHz modulation signal; the output of the modulation transmitter (TX) is connected to the input of the tolerance feedback unit; the output of the tolerance feedback unit is connected to the input of the demodulation receiver (RX); and the output of the demodulation receiver (RX) is the output of the fault modulation-tolerance feedback coordination unit.

4. The integrated DC-DC fault handling circuit based on tolerant feedback according to claim 3, characterized in that, The feedback tolerance unit includes: MIM capacitor C3 and MIM capacitor C4; one end of MIM capacitor C3 and C4 are respectively connected to the output terminal of the modulation transmitter TX, and the other end of MIM capacitor C3 and C4 are respectively connected to the input terminal of the demodulation receiver RX; the MIM capacitor is a metal-insulator-metal capacitor.

5. The integrated DC-DC fault handling circuit based on tolerant feedback according to claim 3, wherein the DC-DC outputs a soft-start ready signal SLOW_START_OK, characterized in that, The secondary fault detection unit includes: comparators CMP1~CMP3, AND gates AND5~AND8, NAND gate NAND1, OR gate OR3, inverter INV3, temperature sensor, and reference voltage source VREF; the temperature sensor output voltage V_TSENSER; The non-inverting input of comparator CMP1 is connected to the voltage V_TSENSER output from the temperature sensor, and the inverting input is connected to the reference voltage source VREF; the non-inverting input of comparator CMP2 is connected to the voltage FBVDD, and the inverting input is connected to the reference voltage source VREF; the inverting input of comparator CMP3 is connected to the voltage FBVDD, and the non-inverting input is connected to the reference voltage source VREF; where voltage FBVDD is the voltage obtained by voltage division at the output of the DC-DC converter. The outputs of comparators CMP2 and CMP3 are connected to the inputs of AND gate AND5. The outputs of AND gate AND5 and comparator CMP1 are connected to the inputs of NAND gate NAND1. The output of NAND gate NAND1 is connected to one input of AND gate AND6. The other input of AND gate AND6 is connected to the DC-DC soft-start ready signal SLOW_START_OK. The output of AND gate AND6 is connected to one input of AND gate AND7 and the input of inverter INV3. The other input of AND gate AND7 is connected to a 500kHz modulation signal. The output of inverter INV3 is connected to one input of AND gate AND8. The other input of AND gate AND8 is connected to the output of the output control unit. The outputs of AND gate AND7 and AND gate AND8 are connected to the inputs of OR gate OR3. The output of OR gate OR3 is the output of the secondary fault detection unit.

6. The integrated DC-DC fault handling circuit based on tolerant feedback according to claim 1, characterized in that, Also includes: OSC32K module; The dual unlock control unit outputs a timing output signal TIMER_OUT and a reset signal RESET. The primary-side latch unit includes: power supply VDD5, AND gate AND1, AND gate AND2, AND gate AND8, AND gate OR8, SR latch SRFF3, SR latch SRFF4, four cascaded D flip-flops DFF10~DFF13, operational amplifier A2, inverters INV1~INV2, capacitor C5, current source, transistor Q6, and reference voltage source VREF; The input of inverter INV1 is the reset terminal of the primary-side latch unit, connected to the reset signal RESET output by the dual unlock control unit. The output of inverter INV1 is connected to the gate of transistor Q6. The source of transistor Q6 and one end of capacitor C5 are grounded. The drain of transistor Q6, the other end of capacitor C5, and the inverting input of operational amplifier A2 are connected to the output of current source. The input of current source is connected to power supply VDD5. The non-inverting input of operational amplifier A2 is connected to reference voltage source VREF. The enable terminal of operational amplifier A2 is connected to enable signal EN. The output of operational amplifier A2 is connected to the input of inverter INV2. The input of AND gate AND1 is connected to the output of the OSC32K module and the enable signal EN. The output of AND gate AND1 is connected to the asynchronous reset terminals of four D flip-flops DFF10~DFF13. The D terminals of the four D flip-flops DFF10~DFF13 are respectively connected to their respective... The CLK terminal of D flip-flop DFF10 is connected to the output of the fault modulation-tolerance feedback coordination unit; D flip-flops DFF10~DFF13 are cascaded sequentially, with the previous D flip-flop's... The terminal is connected to the CLK terminal of the next D flip-flop; The Q terminal of the D flip-flop DFF13 and the output terminal of the inverter INV2 are connected to the input terminal of the AND gate AND2. The output terminal of the AND gate AND2 is connected to the S terminal of the SR latch SRFF3. The enable terminal of the SR latch SRFF3 is connected to the enable signal EN. The R terminal of the SR latch SRFF3 is connected to the output terminal of the operational amplifier A2. The Q terminal of the SR latch SRFF3 outputs the latch signal LATCH. The input of OR gate OR8 is connected to the Q terminal of SR latch SRFF3 and the timing output signal TIMER_OUT. The output is connected to one input of AND gate AND8. The other input of AND gate AND8 is connected to the output of inverter INV2. The output of AND gate AND8 is connected to the S terminal of SR latch SRFF4. The enable terminal of SR latch SRFF4 is connected to the enable signal EN. The R terminal of SR latch SRFF4 is connected to the output of operational amplifier A2. The QN terminal of SR latch SRFF4 outputs the feedback signal SECOND_FEEDBACK. In this SR latch, the S, R, Q, and QN terminals are the set input, reset input, positive output, and inverted output, respectively; the CLK, D, and Q terminals of the D flip-flop are... The terminals are respectively clock input, data input, positive output, and negative output.

7. The integrated DC-DC fault handling circuit based on tolerant feedback according to claim 6, characterized in that, The dual unlock control unit outputs a timing output signal TIMER_OUT; the power transmission control unit includes: OR gates OR1~OR2 and transistor Q5; the input of OR gate OR1 is connected to the latch signal LATCH and the timing output signal TIMER_OUT, the output of OR gate OR1 is connected to one input of OR gate OR2, the other input of OR gate OR2 is connected to the output of the fault modulation-tolerance feedback coordination unit, the output of OR gate OR2 is connected to the gate of transistor Q5, the drain of transistor Q5 is connected to the input of DC-DC converter, and the source of transistor Q5 is grounded.

8. The integrated DC-DC fault handling circuit based on tolerant feedback according to claim 6, characterized in that, It also includes a voltage protection module, whose input is connected to the power supply of the DC-DC converter, and whose output outputs an undervoltage lockout signal UVLO and an overvoltage lockout signal OVLO. The PG signal module includes: power supply VDD5, AND gate AND4, resistor R3, and transistor Q7; the input of AND gate AND4 is connected to the undervoltage lockout signal UVLO, the overvoltage lockout signal OVLO, and the feedback signal SECOND_FEEDBAKE; the output of AND gate AND4 is connected to the gate of transistor Q7, the drain of transistor Q7 is connected to one end of resistor R3, the other end of resistor R3 is connected to power supply VDD5, and the source of transistor Q7 is grounded; the drain of transistor Q7 outputs the power good drop signal PG_DOWN.

9. The integrated DC-DC fault handling circuit based on tolerant feedback according to claim 1, characterized in that, Also includes: The OSC32K module and voltage protection module are connected. The input of the voltage protection module is connected to the power supply of the DC-DC converter, and the output of the voltage protection module outputs an undervoltage lockout signal UVLO. The dual unlock control unit includes an AND gate AND3 and a Watch_Dog AndENA_RESET module. The input of the Watch_Dog And ENA_RESET module is connected to the output of the OSC32K module, the enable signal EA, and the undervoltage lockout signal UVLO. The output of the Watch_Dog And ENA_RESET module outputs a timing output signal TIMER_OUT and an enable / reset signal EAN_RESET. The enable / reset signal EAN_RESET is connected to one input of the AND gate AND3, the other input of the AND gate AND3 is connected to the undervoltage lockout signal UVLO, and the output of the AND gate AND3 outputs a reset signal RESET.

10. The integrated DC-DC fault handling circuit based on tolerant feedback according to claim 9, characterized in that, The Watch_Dog and ENA_RESET modules include: the Watch_Dog module and the ENA_RESET module; the ENA_RESET module includes: AND gates AND9~AND, SR latch SRFF1, inverters INV4~INV8, multiplexer MUX1, and buffers BUF1~BUF2; the Watch_Dog module includes: AND gates AND16~AND21, 10 cascaded D flip-flops DFF0~DFF9, SR latch SRFF2, inverters INV9~INV11, clock gating unit ICG2, and OR gates OR4~OR7; among them, the ENA_RESET module is the enable / reset module, and the Watch_Dog module is the watchdog module. The input of inverter INV4 is connected to the enable signal EN, and its output is connected to the input of inverter INV5; the input of AND gate AND9 is connected to the output of inverter INV5 and the undervoltage lockout signal UVLO; the input of AND gate AND10 is connected to the output of AND gate AND9 and the output of inverter INV11, and its output is connected to one input of AND gate AND11; the input of inverter INV6 is connected to the output of the PG signal module, and its output is connected to the other input of AND gate AND11. The input of AND gate AND12 is connected to the output of inverter INV4 and the undervoltage lockout signal UVLO. The output is connected to one input of AND gate AND13. The other input of AND gate AND13 is connected to the output of inverter INV7. The output of AND gate AND13 is connected to the input of buffer BUF1. The output of buffer BUF1 is connected to the input of buffer BUF2. The input terminal A of the multiplexer MUX1 is connected to the output terminal of the OSC32K module, the input terminal B is grounded (GND), the selection control terminal S is connected to the Q terminal of the SR latch SRFF1, and the enable terminal is connected to the output terminal of the AND gate AND12. The input of AND gate AND14 is connected to the Q terminals of D flip-flops DFF0~DFF2, and its output is connected to one input of AND gate AND15. The other input of AND gate AND15 is connected to the output of AND gate AND12. The output of AND gate AND15 is connected to the S terminal of SR latch SRFF1. The enable terminal of SR latch SRFF1 is connected to the output of AND gate AND12. The R terminal of SR latch SRFF1 is connected to the output of inverter INV8. The input of inverter INV7 is connected to the Q terminal of SR latch SRFF1, and its output is the signal ENA_RESET. The input of inverter INV8 is connected to the output of AND gate AND12. The input terminal A of the multiplexer MUX2 is connected to the output terminal of the OSC32K module, the input terminal B is grounded (GND), the selection control terminal S is connected to the Q terminal of the SR latch SRFF2, and the enable terminal is connected to the output terminal of the AND gate AND9. The input of OR gate OR4 is connected to the outputs of multiplexers MUX1 and MUX2, and the output of OR gate OR4 is connected to the CLK terminal of D flip-flop DFF0; D flip-flops DFF0 to DFF9 are connected in series, with the D terminal of the previous D flip-flop connected to... The inputs of OR gates OR5 to OR7 are connected to the outputs of AND gate AND11 and buffer BUF2; the output of OR gate OR5 is connected to the asynchronous reset terminal of D flip-flop DFF0; the output of OR gate OR6 is connected to the asynchronous reset terminal of D flip-flop DFF1; the output of OR gate OR7 is connected to the asynchronous reset terminal of D flip-flop DFF2; and the asynchronous reset terminals of D flip-flops DFF3 to DFF9 are connected to the output of AND gate AND11. The inputs of AND gate AND16 are connected to the Q terminals of D flip-flops DFF0~DFF2; the inputs of AND gate AND17 are connected to the Q terminals of D flip-flops DFF3~DFF5; the inputs of AND gate AND18 are connected to the Q terminals of D flip-flops DFF6~DFF8; the outputs of AND gates AND16, AND17, and AND18 are connected to the inputs of AND gate AND19; the output of AND gate AND19 is connected to one input of AND gate AND20; the other input of AND gate AND20 is connected to the Q terminal of D flip-flop DFF9; and the output of AND gate AND20 is connected to one input of AND gate AND21. The other input of AND21 is connected to the output of inverter INV5. The output of AND21 is connected to the S terminal of SR latch SRFF2. The input of inverter INV10 is connected to the output of inverter INV5. The enable terminal of SR flip-flop SRFF2 is connected to the output of inverter INV5. The R terminal of SR latch SRFF2 is connected to the output of inverter INV10. The Q terminal of SR latch SRFF2 is connected to the input of inverter INV11. The input of inverter INV12 is connected to the output of inverter INV11. The output terminal outputs the timing output signal TIMER_OUT. In this circuit, the S, R, and Q terminals of the SR latch SRFF1 are the set input, reset input, and positive output, respectively; the CLK, D, and Q terminals of the D flip-flop are... The terminals are respectively clock input, data input, positive output, and negative output.

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