A dual-mode reconfigurable compact CMOS ultra-wideband fourth-order bandpass filter

Abstract

This invention provides a dual-mode reconfigurable compact CMOS ultra-wideband fourth-order bandpass filter, comprising: a first tunable second-order filter for acquiring an external differential RF signal and performing frequency selection processing on the external differential RF signal under the action of a first control signal to obtain a first frequency-selective differential signal; a second tunable second-order filter for acquiring the external differential RF signal and performing frequency selection processing on the external differential RF signal under the action of a second control signal to obtain a second frequency-selective differential signal; and an output stage for receiving the first and second frequency-selective differential signals and performing corresponding subtraction processing according to the polarity of the first and second frequency-selective differential signals to obtain a final output differential signal; the first and second control signals are calculated based on the target center frequency and the target in-band ripple using the parallel fourth-order bandpass filter synthesis principle. This achieves a significant improvement in tuning smoothness and integration.

Description

Technical Field

[0001] This invention relates to the field of radio frequency tunable filter technology, specifically to a dual-mode reconfigurable compact CMOS ultrawideband fourth-order bandpass filter. Background Technology

[0002] With the rapid development of multi-standard RF systems and radar communication fusion technologies, modern RF terminals are evolving towards high integration that supports multiple frequency bands and functions. In this context, systems often need to handle multiple adjacent channels or operating modes with different frequencies, which places higher demands on the frequency band selection and reconfiguration capabilities of the RF front-end. Tunable RF filters, due to their ability to dynamically change their center frequency, select target signals in different modes, and suppress out-of-band interference, are gradually becoming key components for achieving spectrum adaptability and system reconfiguration. Therefore, how to further broaden the tuning range of the filter while ensuring the tuning continuity of its center frequency within a compact chip area, and also considering a certain range of bandwidth adjustability, has become a core technical problem that urgently needs to be solved.

[0003] In the implementation of silicon-based tunable RF filters, LC filters based on Q-value enhancement technology have become an attractive architecture by compensating for the losses of on-chip passive networks with negative resistance. Extensive research has been conducted on their wideband tuning and bandwidth adjustment. To expand the frequency tuning range, one existing approach combines varactor array tuning with a mode-switching transformer to change the inductance value. This transformer typically consists of two sets of symmetrical multi-segment inductors and corresponding switch arrays. By controlling the switch states to switch the inductor connection method, the inductance value variation and frequency tuning range can be further expanded. Another similar approach employs a multi-stage cascaded second-order resonator topology. Each resonator integrates a programmable negative resistance array, a switched capacitor array, and a transconductance array. By adjusting the center frequency and quality factor of each stage of the resonator, the overall bandwidth of the filter can be flexibly configured.

[0004] However, the existing solutions mentioned above still have significant shortcomings. For filters combined with mode-switching transformers, the tuning curve is prone to interruption during inductor switching, resulting in a lack of smooth and continuous frequency coverage between low and high frequency bands and gaps in the tuning range. Furthermore, the filter bandwidth of this solution is usually fixed, lacking a dynamic adjustment mechanism, making it difficult to adapt to the differentiated requirements of narrowband anti-interference or broadband high-speed transmission in different communication scenarios. As for the multi-stage resonant cavity cascaded architecture, the main problem is the large number of resonant cavities required, leading to a significant increase in chip core area, lower integration density, and hindering the miniaturization of the RF front end. In addition, the center frequency tuning range of this solution is relatively limited, making it difficult to meet the requirements of multi-standard wireless systems for continuous wideband adaptation. Summary of the Invention

[0005] To address the aforementioned problems in the prior art, this invention provides a dual-mode reconfigurable compact CMOS ultrawideband fourth-order bandpass filter.

[0006] The technical problem to be solved by this invention is achieved through the following technical solution: This invention provides a dual-mode reconfigurable compact CMOS ultra-wideband fourth-order bandpass filter, comprising: a first tunable second-order filter, a second tunable second-order filter, and an output stage; The first adjustable second-order filter is used to acquire an external differential radio frequency signal and perform frequency selection processing on the external differential radio frequency signal under the action of a first control signal to obtain a first frequency-selective differential signal; The second adjustable second-order filter is used to acquire the external differential radio frequency signal and perform frequency selection processing on the external differential radio frequency signal under the action of the second control signal to obtain the second frequency-selective differential signal; The output stage is used to receive the first frequency-selective differential signal and the second frequency-selective differential signal, and perform corresponding subtraction processing according to the polarity of the first frequency-selective differential signal and the second frequency-selective differential signal to obtain the final output differential signal; The first adjustable second-order filter and the second adjustable second-order filter are connected in parallel and are both connected in series with the output stage; the first adjustable second-order filter and the second adjustable second-order filter have the same structure; the first control signal and the second control signal are calculated based on the target center frequency and the target in-band ripple using the parallel fourth-order bandpass filter synthesis principle.

[0007] Optionally, the first adjustable second-order filter includes: an input stage, an LC resonant filter, a gain control stage, and a negative resistance compensation circuit; The input stage is used to receive the external differential radio frequency signal and perform impedance matching and buffering to obtain a buffered input signal; The LC resonant filter is used to receive the buffered input signal and perform frequency selection processing on the buffered input signal under the control of the first control signal, under the gain adjustment processing of the gain control stage and the loss compensation of the negative resistance compensation circuit, to obtain the first frequency-selective differential signal.

[0008] Optionally, the LC resonant filter includes: a variable capacitor array and a multi-inductor coupled adjustable structure; The first control signal includes: a capacitor control signal and an inductor control signal; The variable capacitor array is used to acquire the capacitor control signal, and under the gain adjustment processing of the gain control stage and the loss compensation of the negative resistance compensation circuit, the capacitor control signal is used to perform initial frequency selection processing on the buffered input signal to obtain a first initial frequency selection differential signal. The multi-inductor coupled adjustable structure is used to acquire the inductor control signal, and under the gain adjustment processing of the gain control stage and the loss compensation of the negative resistance compensation circuit, the inductor control signal is used to perform final frequency selection processing on the first initial frequency-selective differential signal to obtain the first frequency-selective differential signal.

[0009] Optionally, the input terminal of the input stage is connected to the external differential radio frequency signal; the first output terminal of the input stage is connected to the first input terminal of the LC resonant filter, one end of the gain control stage, and one end of the negative resistance compensation circuit, respectively. The second output terminal of the input stage is connected to the second input terminal of the LC resonant filter, the other end of the gain control stage, and the other end of the negative resistance compensation circuit, respectively. The first and second output terminals of the LC resonant filter are both connected to the input terminal of the output stage.

[0010] Optionally, the input stage includes: resistor Ri and NMOS transistors M1-M4; The gate of NMOS transistor M1 and one end of resistor Ri are both connected to the differential input signal Vp; the gate of NMOS transistor M2 and the other end of resistor Ri are both connected to the differential input signal Vn; the drain of NMOS transistor M1, the drain of NMOS transistor M2, and one end of resistor Ri are all connected to power supply VDD2; the drain of NMOS transistor M3, the source of NMOS transistor M1, and the first input terminal of the LC resonant filter are interconnected; the gate of NMOS transistor M3 and the gate of NMOS transistor M4 are both connected to the bias signal Bias. The sources of NMOS transistors M3 and M4 are both connected to ground potential, and the drain of NMOS transistor M4, the source of NMOS transistor M2, and the second input terminal of the LC resonant filter are interconnected.

[0011] Optionally, the LC resonant filter includes: a variable resistor R s1 Variable resistor R s2 Variable capacitor C var1 Variable capacitor C var2 Capacitor C s1 Capacitor C s2 Capacitor C t1 Capacitor C t2 NMOS transistor M s1 NMOS transistor Ms2 NMOS transistor M t1 NMOS transistor M t2 Inductor L1, inductor L2, and NMOS transistor M so ; Variable resistor R s1 One end is connected to the first input terminal of the LC resonant filter; the variable resistor R s1 The other end is connected to one end of the gain control stage, one end of the negative resistance compensation circuit, and the variable capacitor C, respectively. var1 The upper plate and capacitor C s1 The upper plate and capacitor C t1 The upper plate, one end of inductor L1, and the first output terminal of the LC resonant filter are connected; the variable resistor R s2 One end is connected to the second input terminal of the LC resonant filter; the variable resistor R s2 The other end is connected to the other end of the gain control stage, the other end of the negative resistance compensation circuit, and the variable capacitor C, respectively. var2 The lower electrode plate and capacitor C s2 The lower electrode plate and capacitor C t2 The lower electrode plate, the other end of inductor L1, and the second output terminal of the LC resonant filter are connected; Variable capacitor C var1 The lower plate and the variable capacitor C var2 The upper plates are all connected to the external voltage V c0 Connection; Capacitor C s1 The lower electrode and NMOS transistor M s1 Drain connection; NMOS transistor M s1 The gate and NMOS transistor M s2 The gates are interconnected and simultaneously connected to an external voltage V. c1 NMOS transistor M s1 The source and NMOS transistor M s2 The sources of the NMOS transistors are interconnected and simultaneously grounded; NMOS transistor M s2 The drain and capacitor C s2 Upper plate connection; capacitor C t1 The lower electrode and NMOS transistor M t1 Drain connection; NMOS transistor M t1 The gate and NMOS transistor M t2 The gates are interconnected and simultaneously connected to an external voltage V. c2 NMOS transistor M t1 The source and NMOS transistor M t2 The sources of the NMOS transistors are interconnected and simultaneously grounded; NMOS transistor M t2 The drain and capacitor C t2 The upper plate is connected; inductors L1 and L2 are coupled by a coupling coefficient. kMagnetic coupling is performed; one end of inductor L1 is also connected to power supply VDD; one end of inductor L2 is also connected to ground potential; NMOS transistor M so The drain of the NMOS transistor is connected to one end of inductor L2; so The source of the NMOS transistor is connected to the other end of inductor L2; so The gate is connected to an external voltage V. sw .

[0012] Optionally, the gain control stage includes: an NMOS transistor M G1 NMOS transistor M G2 Variable resistor R G1 and variable resistor R G2 ; NMOS transistor M G1 The drain of the NMOS transistor is connected to the first input terminal of the LC resonant filter; G1 The source and variable resistor R G1 One end is connected; NMOS transistor M G1 The gate of the NMOS transistor is connected to the differential input signal Vn; G2 The drain of the NMOS transistor is connected to the second input terminal of the LC resonant filter; G2 The gate of the NMOS transistor is connected to the differential input signal Vp; G1 The source and NMOS transistor M G2 The source poles are all connected to the ground; NMOS transistor M G2 The source and variable resistor R G2 One end is connected; variable resistor R G1 With variable resistor R G2 The other end is grounded.

[0013] Optionally, the output stage includes: NMOS transistors M5-M 10 Resistance R 01 and resistance R 02 ; The drains of NMOS transistors M5, M6, M8, and M9 are all connected to power supply VDD1; the gate of NMOS transistor M5 is connected to the first output terminal of the first adjustable second-order filter; the gate of NMOS transistor M8 is connected to the first output terminal of the second adjustable second-order filter; the gate of NMOS transistor M6 is connected to the second output terminal of the first adjustable second-order filter; the gate of NMOS transistor M9 is connected to the second output terminal of the second adjustable second-order filter; the source of NMOS transistor M6 is connected to resistor R. 01 One end of the resistor is connected to the gate of the NMOS transistor M7; resistor R 01 The other end, the source of NMOS transistor M7, and resistor R02 The other end and NMOS transistor M 10 The sources are connected to each other; resistor R 02 One end, the source of NMOS transistor M9 and NMOS transistor M 10 The gates of NMOS transistors M5, M7, and the positive terminal of the final output differential signal are connected; the source of NMOS transistor M8 and the drain of NMOS transistor M7 are connected. 10 The drain of the signal is connected to the negative terminal of the final output differential signal.

[0014] Optionally, the negative resistance compensation circuit includes: an NMOS transistor M n1 NMOS transistor M n2 Variable resistor R var1 and variable resistor R var2 ; NMOS transistor M n1 The drain of the NMOS transistor M n2 The gate of the NMOS transistor and the first input terminal of the LC resonant filter are interconnected; n2 The drain of the NMOS transistor M n1 The gate of the NMOS transistor and the second input terminal of the LC resonant filter are interconnected; n1 The source and variable resistor R var1 One end is connected to the other; NMOS transistor M n2 The source and variable resistor R var2 One end of the resistor is connected to the other end; variable resistor R var1 The other end and the variable resistor R var2 The other end of each is grounded.

[0015] This invention provides a dual-mode reconfigurable compact CMOS ultra-wideband fourth-order bandpass filter, comprising: a first tunable second-order filter, a second tunable second-order filter, and an output stage; the first tunable second-order filter is used to acquire an external differential RF signal and perform frequency selection processing on the external differential RF signal under the action of a first control signal to obtain a first frequency-selective differential signal; the second tunable second-order filter is used to acquire an external differential RF signal and perform frequency selection processing on the external differential RF signal under the action of a second control signal to obtain a second frequency-selective differential signal; the output stage is used to receive the first frequency-selective differential signal and the second frequency-selective differential signal, and perform corresponding subtraction processing according to the polarity of the first frequency-selective differential signal and the second frequency-selective differential signal to obtain the final output differential signal; the first tunable second-order filter and the second tunable second-order filter are connected in parallel and are both connected in series with the output stage; the first tunable second-order filter and the second tunable second-order filter have the same structure, and the first control signal and the second control signal are calculated based on the target center frequency and the target in-band ripple using the parallel fourth-order bandpass filter synthesis principle. This invention first employs a dual-mode reconfigurable design, utilizing two tunable second-order filters operating in parallel. Based on the synthesis principle, the control signal is dynamically calculated, enabling continuous adjustment of capacitor parameters and avoiding frequency gaps caused by hard switching. Simultaneously, the subtraction processing in the output stage allows for dynamic bandwidth adjustment, thereby improving tuning smoothness and bandwidth adjustability. Next, two identical second-order filters are connected in parallel, targeting a fourth-order filtering response. This reduces the number of resonant cavities and lowers hardware complexity. Combined with the compact characteristics of CMOS technology, this achieves a reduction in chip core area and an increase in integration density. Finally, the control signal is optimized through the reconfigurable mechanism and synthesis principle, allowing the frequency responses of the two second-order filters to synergistically cover a wider frequency band, thus extending the continuous tuning range of the center frequency and meeting the broadband adaptation requirements of multi-standard wireless systems. In summary, this invention, through a dual-mode reconfigurable parallel structure, achieves significant improvements in tuning smoothness, bandwidth adjustability, chip area, and integration density, while simultaneously expanding frequency coverage and reducing tuning gaps and hardware costs.

[0016] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the structure of a dual-mode reconfigurable compact CMOS ultrawideband fourth-order bandpass filter provided in an embodiment of the present invention; Figure 2 The equivalent inductance value of the multi-inductor coupled adjustable structure is illustrated exemplarily when the switch is off and on. Figure 3 The parametric simulation results of a dual-mode reconfigurable compact CMOS ultrawideband fourth-order bandpass filter are shown as an example. Detailed Implementation

[0018] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0019] To achieve significant improvements in tuning smoothness, bandwidth adjustability, chip area, and integration density, this invention provides a dual-mode reconfigurable compact CMOS ultra-wideband fourth-order bandpass filter. Figure 1 This is a schematic diagram of a dual-mode reconfigurable compact CMOS ultrawideband fourth-order bandpass filter provided in an embodiment of the present invention, as shown below. Figure 1 As shown, it includes: a first adjustable second-order filter, a second adjustable second-order filter, and an output stage; The first adjustable second-order filter is used to acquire the external differential radio frequency signal and perform frequency selection processing on the external differential radio frequency signal under the action of the first control signal to obtain the first frequency-selective differential signal. The second adjustable second-order filter is used to acquire the external differential radio frequency signal and perform frequency selection processing on the external differential radio frequency signal under the action of the second control signal to obtain the second frequency-selective differential signal; The output stage receives the first frequency-selective differential signal and the second frequency-selective differential signal, and performs corresponding subtraction processing according to the polarity of the first frequency-selective differential signal and the second frequency-selective differential signal to obtain the final output differential signal. The first adjustable second-order filter and the second adjustable second-order filter are connected in parallel and are both connected in series with the output stage. The first adjustable second-order filter and the second adjustable second-order filter have the same structure. The first control signal and the second control signal are calculated based on the target center frequency and the target in-band ripple using the parallel fourth-order bandpass filter synthesis principle.

[0020] This invention provides a dual-mode reconfigurable compact CMOS ultra-wideband fourth-order bandpass filter. First, it employs a dual-mode reconfigurable design, using two tunable second-order filters operating in parallel. Based on the synthesis principle, the control signal is dynamically calculated, allowing for continuous adjustment of capacitor parameters and avoiding frequency cutoffs caused by hard switching. Simultaneously, the subtraction processing in the output stage allows for dynamic bandwidth adjustment, thereby improving tuning smoothness and bandwidth tunability. Then, two structurally identical second-order filters are connected in parallel, targeting the fourth-order filtering response. This reduces the number of resonant cavities and lowers hardware complexity. Combined with the compact characteristics of CMOS technology, this achieves a reduction in chip core area and an increase in integration density. Finally, by optimizing the control signal through the reconfigurable mechanism and synthesis principle, the frequency responses of the two second-order filters synergistically cover a wider frequency band, thereby extending the continuous tuning range of the center frequency and meeting the broadband adaptation requirements of multi-standard wireless systems. In summary, this invention, through a dual-mode reconfigurable parallel structure, achieves significant improvements in tuning smoothness, bandwidth tunability, chip area, and integration density, while expanding frequency coverage and reducing tuning cutoffs and hardware costs.

[0021] Optionally, the first adjustable second-order filter includes: an input stage, an LC resonant filter, a gain control stage, and a negative resistance compensation circuit; The input stage is used to receive external differential RF signals and perform impedance matching and buffering to obtain a buffered input signal; An LC resonant filter is used to receive a buffered input signal and perform frequency selection processing on the buffered input signal under the control of a first control signal, in addition to the gain adjustment processing of the gain control stage and the loss compensation of the negative resistance compensation circuit, to obtain a first frequency-selective differential signal.

[0022] Optionally, the LC resonant filter includes: a variable capacitor array and a multi-inductor coupled adjustable structure; The first control signal includes: capacitor control signal and inductor control signal; A variable capacitor array is used to acquire the capacitor control signal. Under the gain adjustment processing of the gain control stage and the loss compensation of the negative resistance compensation circuit, the capacitor control signal is used to perform initial frequency selection processing on the buffered input signal to obtain the first initial frequency selection differential signal. A multi-inductor coupled adjustable structure is used to acquire the inductor control signal. Under the gain adjustment processing of the gain control stage and the loss compensation of the negative resistance compensation circuit, the inductor control signal is used to perform final frequency selection processing on the first initial frequency-selective differential signal to obtain the first frequency-selective differential signal.

[0023] Optionally, the input terminal of the input stage is connected to an external differential RF signal; the first output terminal of the input stage is connected to the first input terminal of the LC resonant filter, one end of the gain control stage, and one end of the negative resistance compensation circuit, respectively. The second output terminal of the input stage is connected to the second input terminal of the LC resonant filter, the other end of the gain control stage, and the other end of the negative resistance compensation circuit, respectively. The first and second output terminals of the LC resonant filter are both connected to the input terminal of the output stage.

[0024] Optionally, the input stage includes: resistor Ri and NMOS transistors M1-M4; The gate of NMOS transistor M1 and one end of resistor Ri are both connected to the differential input signal Vp; the gate of NMOS transistor M2 and the other end of resistor Ri are both connected to the differential input signal Vn; the drain of NMOS transistor M1, the drain of NMOS transistor M2, and one end of resistor Ri are all connected to power supply VDD2; the drain of NMOS transistor M3, the source of NMOS transistor M1, and the first input terminal of LC resonant filter are interconnected; the gate of NMOS transistor M3 and the gate of NMOS transistor M4 are both connected to the bias signal Bias. The sources of NMOS transistors M3 and M4 are both connected to ground potential. The drain of NMOS transistor M4, the source of NMOS transistor M2, and the second input terminal of the LC resonant filter are interconnected.

[0025] Optionally, the LC resonant filter includes: a variable resistor R s1 Variable resistor R s2 Variable capacitor C var1 Variable capacitor C var2 Capacitor C s1 Capacitor C s2 Capacitor C t1 Capacitor C t2 NMOS transistor M s1 NMOS transistor M s2 NMOS transistor M t1 NMOS transistor M t2 Inductor L1, inductor L2, and NMOS transistor M so ; Variable resistor R s1 One end is connected to the first input terminal of the LC resonant filter; the variable resistor R s1 The other end is connected to one end of the gain control stage, one end of the negative resistance compensation circuit, and the variable capacitor C, respectively. var1 The upper plate and capacitor C s1 The upper plate and capacitor C t1 The upper plate, one end of inductor L1, and the first output terminal of the LC resonant filter are connected; the variable resistor R s2 One end is connected to the second input terminal of the LC resonant filter; the variable resistor R s2The other end is connected to the other end of the gain control stage, the other end of the negative resistance compensation circuit, and the variable capacitor C, respectively. var2 The lower electrode plate and capacitor C s2 The lower electrode plate and capacitor C t2 The lower electrode plate, the other end of inductor L1, and the second output terminal of the LC resonant filter are connected; Variable capacitor C var1 The lower plate and the variable capacitor C var2 The upper plates are all connected to the external voltage V c0 Connection; Capacitor C s1 The lower electrode and NMOS transistor M s1 Drain connection; NMOS transistor M s1 The gate and NMOS transistor M s2 The gates are interconnected and simultaneously connected to an external voltage V. c1 NMOS transistor M s1 The source and NMOS transistor M s2 The sources of the NMOS transistors are interconnected and simultaneously grounded; NMOS transistor M s2 The drain and capacitor C s2 Upper plate connection; capacitor C t1 The lower electrode and NMOS transistor M t1 Drain connection; NMOS transistor M t1 The gate and NMOS transistor M t2 The gates are interconnected and simultaneously connected to an external voltage V. c2 NMOS transistor M t1 The source and NMOS transistor M t2 The sources of the NMOS transistors are interconnected and simultaneously grounded; NMOS transistor M t2 The drain and capacitor C t2 The upper plate is connected; inductors L1 and L2 are coupled by a coupling coefficient. k Magnetic coupling is performed; one end of inductor L1 is also connected to power supply VDD; one end of inductor L2 is also connected to ground potential; NMOS transistor M so The drain of the NMOS transistor is connected to one end of inductor L2; so The source of the NMOS transistor is connected to the other end of inductor L2; so The gate is connected to an external voltage V. sw .

[0026] The hybrid variable capacitor array in the LC resonant filter consists of a varactor branch C var With two sets of binary weighted switched capacitors (Cs) 1，2 -M S1,2 C t1,2 -M t1,2The capacitors are connected in parallel. The switched capacitor branch provides a discrete capacitance range, while the varactor provides a continuous capacitance variation. The capacitance tuning range provided by the varactor is greater than the unit capacitance of the switched capacitor (C=Cs). 1，2 =0.5C t1,2 When the hybrid variable capacitor array is used, continuous capacitance tuning can be achieved.

[0027] Specifically, the external voltage V c0 V c1 and V c2 Together they serve as the first control signal; external voltage V sw As the second control signal, the determination of the first control signal and the second control signal can be carried out in the following manner.

[0028] First, based on the relationship between the fourth-order filter and the second-order filter, the resonant frequencies of the first and second adjustable second-order filters are determined. .

[0029] ; ; This represents the resonant frequency of the first adjustable second-order filter. This represents the resonant frequency of the second adjustable second-order filter. Indicates the target center frequency. The selected bandwidth of the fourth-order filter is typically 3dB. This indicates the ripple within the target band.

[0030] because: Based on this, in the calculation and In this case, the total capacitance and total inductance values ​​corresponding to the first adjustable second-order filter and the second adjustable second-order filter can be determined respectively.

[0031] And the external voltage V c0 V c1 and V c2 Together, they serve as the first control signal, controlling the total capacitance value of the variable capacitor array. The control principle is as follows: A variable capacitor array (VCA array) controls the voltage V of the varactor branch by changing the voltage V. c0 A single variable capacitance tube can achieve C min To C max The continuous capacitance change. Among them, C min C is the minimum capacitance that the variable capacitance tube can provide. max This is the maximum capacitance that the variable capacitance tube can provide. The total capacitance variation range that the variable capacitance tube branch can achieve is (C). max -C min) / 2, (series capacitor, capacitance value halved).

[0032] The switched capacitor branch controls the voltage V through the control switching transistor. c1 (V) c2 This achieves discrete capacitance value changes. For example, controlling the voltage V... c1 For high, switch M S1 When conducting, capacitor C s1、 C s2 The contribution of the variable capacitor array is C. s1、 C s2 The capacitance value; the control voltage V c1 For low, the switching transistor M S1，2 (M) S1 With M S2 When disconnected, capacitor C s1、 C s2 The capacitance value that contributes zero to the variable capacitor array. Therefore, C s1，2 -M S1,2 Branches can share contributions of 0 or C. S1 / 2 of the total capacity.

[0033] Similarly, control voltage V c2 For high, switch M t1,2 When conducting, C t1，2 The contribution of the varactor branch to the varactor array is C. t1，2 The capacitance value; the control voltage V c2 For low, the switching transistor M t1,2 When disconnected, capacitor C t1，2 The capacitance value that contributes zero to the variable capacitor array. Therefore, C t1,2 -M t1,2 Branches can share contributions of 0 or C. t1,2 / 2 of the total capacity.

[0034] The capacitance tuning range provided by the variable capacitance tube (C) max -C min () is greater than the unit capacitance value of the switched capacitor (C=Cs) 1，2 =0.5C t1,2 When the variable capacitor array is used, continuous capacitance tuning can be achieved. Switched capacitors can only achieve discrete capacitance changes; the minimum interval between discrete capacitance changes is defined here as a unit capacitance C. Clearly, the total capacitance that two switched capacitor branches can provide is 0, C / 2, C, 3C / 2. The capacitance range of the varactor tube (C...) max -C min When ) > C, the total capacity of the corresponding branch satisfies (C) max -C min If C / 2 > C / 2, the capacitance can be continuously tuned.

[0035] The minimum capacitance value achievable by a variable capacitor array, achieved by combining voltage change and switching state control with a varactor tube, is: C. min,tot =C min / 2; Maximum capacity is: C max,tot =(C max +Cs 1，2 +C t1,2 ) / 2=(C max +3C) / 2.

[0036] Within this range, the capacitance value changes continuously.

[0037] It should be noted that the adjustable multi-inductor coupling structure is composed of stacked transformers L1 (primary coil) and L2 (secondary coil), and the coupling coefficient between them is [value missing]. k This structure controls M so Gate voltage V sw Switch working mode. Correspondingly, Figure 2 The equivalent inductance values ​​of a multi-inductor coupled adjustable structure are illustrated exemplarily when the switch is off and on. For example... Figure 2 As shown, the shutdown mode (V) sw =0V), the secondary circuit impedance is approximately open, and the equivalent inductance L of the adjustable multi-inductor coupling structure is 0V. eq,off ≈L1; On-mode (V sw =1V), secondary circuit short circuit, equivalent inductance L of adjustable multi-inductor coupling structure eq,on =L1(1- k ²).

[0038] Optionally, the gain control stage includes: an NMOS transistor M G1 NMOS transistor M G2 Variable resistor R G1 and variable resistor R G2 ; NMOS transistor M G1 The drain of the NMOS transistor is connected to the first input terminal of the LC resonant filter; G1 The source and variable resistor R G1 One end is connected; NMOS transistor M G1 The gate of the NMOS transistor is connected to the differential input signal Vn; G2 The drain of the NMOS transistor is connected to the second input terminal of the LC resonant filter; G2 The gate of the NMOS transistor is connected to the differential input signal Vp; G1 The source and NMOS transistor M G2 The source poles are all connected to the ground; NMOS transistor M G2 The source and variable resistor R G2One end is connected; variable resistor R G1 With variable resistor R G2 The other end is grounded.

[0039] Optionally, the output stage includes: NMOS transistors M5-M 10 Resistance R 01 and resistance R 02 ; The drains of NMOS transistors M5, M6, M8, and M9 are all connected to power supply VDD1; the gate of NMOS transistor M5 is connected to the first output terminal of the first adjustable second-order filter; the gate of NMOS transistor M8 is connected to the first output terminal of the second adjustable second-order filter; the gate of NMOS transistor M6 is connected to the second output terminal of the first adjustable second-order filter; the gate of NMOS transistor M9 is connected to the second output terminal of the second adjustable second-order filter; the source of NMOS transistor M6 is connected to resistor R. 01 One end of the resistor is connected to the gate of the NMOS transistor M7; resistor R 01 The other end, the source of NMOS transistor M7, and resistor R 02 The other end and NMOS transistor M 10 The sources are connected to each other; resistor R 02 One end, the source of NMOS transistor M9 and NMOS transistor M 10 The gates of NMOS transistors M5, M7, and the positive terminal of the final output differential signal are connected; the source of NMOS transistor M8 and the drain of NMOS transistor M7 are connected. 10 The drain of the signal is connected to the negative terminal of the final output differential signal.

[0040] It should be noted that in this embodiment, VDD and VDD1 are both 1V power supply voltages, and VDD2 is a 1.8V power supply voltage.

[0041] The fourth-order bandpass filter proposed in this invention uses source followers (M1, M2) in the input stage to enhance the driving capability, and M3 and M4 as bias transistors to provide a suitable DC bias for the input stage circuit; the gain control stage is controlled by transistor M. G1 M G2 and adjustable resistor R G Composition, by adjusting R G Different resistance values ​​are used to compensate for losses; the two second-order resonators consist of an adjustable multi-inductor coupling structure, a hybrid variable capacitor array, and a negative resistance unit; the output stage consists of source followers (M5, M7) and a common-source amplifier (M8, M...). 10 This forms a differential subtractor, which realizes the subtraction of second-order signals out of phase, and finally outputs a fourth-order bandpass response.

[0042] Optionally, the negative resistance compensation circuit includes: an NMOS transistor Mn1 NMOS transistor M n2 Variable resistor R var1 and variable resistor R var2 ; NMOS transistor M n1 The drain of the NMOS transistor M n2 The gate of the NMOS transistor and the first input terminal of the LC resonant filter are interconnected; n2 The drain of the NMOS transistor M n1 The gate of the NMOS transistor and the second input terminal of the LC resonant filter are interconnected; n1 The source and variable resistor R var1 One end is connected to the other; NMOS transistor M n2 The source and variable resistor R var2 One end of the resistor is connected to the other end; variable resistor R var1 The other end and the variable resistor R var2 The other end of each is grounded.

[0043] In this invention, a negative resistance circuit is used to compensate for the losses introduced by the LC resonant filter, thereby improving the overall performance of the LC resonator. Q value.

[0044] To verify the effectiveness of the dual-mode reconfigurable compact CMOS ultrawideband fourth-order bandpass filter provided by this invention, simulation experiments were also conducted. Figure 3 Exemplary parametric simulation results for a dual-mode reconfigurable compact CMOS ultrawideband fourth-order bandpass filter are shown. Figure 3 Figure (a) exemplarily illustrates a schematic diagram of the absolute bandwidth tuned from 150MHz to 2GHz when the filter has a fixed center frequency of 3.3GHz; as Figure 3 Figure (b) exemplarily illustrates a schematic diagram of the absolute bandwidth tuned from 150MHz to 2GHz when the filter has a fixed center frequency of 6.0GHz; as Figure 3 Figure (c) exemplarily illustrates a schematic diagram of the absolute bandwidth tuned from 150MHz to 2GHz when the filter's center frequency is fixed at 8.3GHz. As shown in Figure 3, the center frequency can be continuously varied from 3.3GHz to 8.3GHz, and the bandwidth can be continuously tuned from 150MHz to 2GHz, covering a wide fractional bandwidth range of 1.5% to 60%. This not only enhances anti-interference capabilities through narrowband mode but also adapts to high-speed data transmission requirements through broadband mode, improving the filter's adaptability to various scenarios. Therefore, the introduction of the adjustable multi-inductor coupling structure effectively widens the frequency tuning range. Its dual-mode inductance value switching, in conjunction with the hybrid variable capacitor array, achieves continuous tuning of the ultra-wide internal frequency. At the same time, the parallel architecture of the dual second-order resonators endows the filter with excellent bandwidth tuning capabilities.

[0045] The fourth-order bandpass filter proposed in this invention solves the problems of narrow tuning range and poor bandwidth flexibility of traditional filters through the synergistic design of an adjustable multi-inductor coupling structure, a hybrid variable capacitor array, and a negative resistance compensation circuit. This fourth-order bandpass filter architecture achieves a fourth-order filtering response through two second-order LC tunable resonators based on an adjustable multi-inductor coupling structure and heterogeneous synthesis technology. This retains the wide tuning flexibility of second-order resonators while imparting excellent out-of-band rejection and selectivity through heterogeneous synthesis, significantly improving filtering performance.

[0046] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art, by reviewing the accompanying drawings and the disclosure, will understand and implement other variations of the disclosed embodiments in carrying out the claimed invention. In this description, the word "comprising" does not exclude other components or steps, "a" or "an" does not exclude a plurality, and "a plurality" means two or more, unless otherwise explicitly specified. Furthermore, while different embodiments may describe certain measures, this does not mean that these measures cannot be combined to produce good results.

[0047] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the inventive concept, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A dual-mode reconfigurable compact CMOS ultrawideband fourth-order bandpass filter, characterized in that, include: The system comprises a first adjustable second-order filter, a second adjustable second-order filter, and an output stage. The first adjustable second-order filter is used to acquire an external differential radio frequency signal and perform frequency selection processing on the external differential radio frequency signal under the action of a first control signal to obtain a first frequency-selective differential signal; The second adjustable second-order filter is used to acquire the external differential radio frequency signal and perform frequency selection processing on the external differential radio frequency signal under the action of the second control signal to obtain the second frequency-selective differential signal; The output stage is used to receive the first frequency-selective differential signal and the second frequency-selective differential signal, and perform corresponding subtraction processing according to the polarity of the first frequency-selective differential signal and the second frequency-selective differential signal to obtain the final output differential signal; The first adjustable second-order filter and the second adjustable second-order filter are connected in parallel and are both connected in series with the output stage; the first adjustable second-order filter and the second adjustable second-order filter have the same structure; the first control signal and the second control signal are calculated based on the target center frequency and the target in-band ripple using the parallel fourth-order bandpass filter synthesis principle.

2. The dual-mode reconfigurable compact CMOS ultrawideband fourth-order bandpass filter according to claim 1, characterized in that, The first adjustable second-order filter includes: an input stage, an LC resonant filter, a gain control stage, and a negative resistance compensation circuit; The input stage is used to receive the external differential radio frequency signal and perform impedance matching and buffering to obtain a buffered input signal; The LC resonant filter is used to receive the buffered input signal and perform frequency selection processing on the buffered input signal under the control of the first control signal, under the gain adjustment processing of the gain control stage and the loss compensation of the negative resistance compensation circuit, to obtain the first frequency-selective differential signal.

3. The dual-mode reconfigurable compact CMOS ultrawideband fourth-order bandpass filter according to claim 2, characterized in that, The LC resonant filter includes: a variable capacitor array and a multi-inductor coupled adjustable structure; The first control signal includes: a capacitor control signal and an inductor control signal; The variable capacitor array is used to acquire the capacitor control signal, and under the gain adjustment processing of the gain control stage and the loss compensation of the negative resistance compensation circuit, the capacitor control signal is used to perform initial frequency selection processing on the buffered input signal to obtain a first initial frequency selection differential signal. The multi-inductor coupled adjustable structure is used to acquire the inductor control signal, and under the gain adjustment processing of the gain control stage and the loss compensation of the negative resistance compensation circuit, the inductor control signal is used to perform final frequency selection processing on the first initial frequency-selective differential signal to obtain the first frequency-selective differential signal.

4. The dual-mode reconfigurable compact CMOS ultrawideband fourth-order bandpass filter according to claim 2, characterized in that, The input terminal of the input stage is connected to the external differential radio frequency signal; the first output terminal of the input stage is connected to the first input terminal of the LC resonant filter, one end of the gain control stage, and one end of the negative resistance compensation circuit, respectively. The second output terminal of the input stage is connected to the second input terminal of the LC resonant filter, the other end of the gain control stage, and the other end of the negative resistance compensation circuit, respectively. The first and second output terminals of the LC resonant filter are both connected to the input terminal of the output stage.

5. The dual-mode reconfigurable compact CMOS ultrawideband fourth-order bandpass filter according to claim 2, characterized in that, The input stage includes: resistor Ri and NMOS transistors M1-M4; The gate of NMOS transistor M1 and one end of resistor Ri are both connected to the differential input signal Vp; the gate of NMOS transistor M2 and the other end of resistor Ri are both connected to the differential input signal Vn; the drain of NMOS transistor M1, the drain of NMOS transistor M2, and one end of resistor Ri are all connected to power supply VDD2; the drain of NMOS transistor M3, the source of NMOS transistor M1, and the first input terminal of the LC resonant filter are interconnected; the gate of NMOS transistor M3 and the gate of NMOS transistor M4 are both connected to the bias signal Bias. The sources of NMOS transistors M3 and M4 are both connected to ground potential, and the drain of NMOS transistor M4, the source of NMOS transistor M2, and the second input terminal of the LC resonant filter are interconnected.

6. The dual-mode reconfigurable compact CMOS ultrawideband fourth-order bandpass filter according to claim 2, characterized in that, The LC resonant filter includes: a variable resistor R s1 Variable resistor R s2 Variable capacitor C var1 Variable capacitor C var2 Capacitor C s1 Capacitor C s2 Capacitor C t1 Capacitor C t2 NMOS transistor M s1 NMOS transistor M s2 NMOS transistor M t1 NMOS transistor M t2 Inductor L1, inductor L2, and NMOS transistor M so ; Variable resistor R s1 One end is connected to the first input terminal of the LC resonant filter; the variable resistor R s1 The other end is connected to one end of the gain control stage, one end of the negative resistance compensation circuit, and the variable capacitor C, respectively. var1 The upper plate and capacitor C s1 The upper plate and capacitor C t1 The upper plate, one end of inductor L1, and the first output terminal of the LC resonant filter are connected; the variable resistor R s2 One end is connected to the second input terminal of the LC resonant filter; the variable resistor R s2 The other end is connected to the other end of the gain control stage, the other end of the negative resistance compensation circuit, and the variable capacitor C, respectively. var2 The lower electrode plate and capacitor C s2 The lower electrode plate and capacitor C t2 The lower electrode plate, the other end of inductor L1, and the second output terminal of the LC resonant filter are connected; Variable capacitor C var1 The lower plate and the variable capacitor C var2 The upper plates are all connected to the external voltage V c0 Connection; Capacitor C s1 The lower electrode and NMOS transistor M s1 Drain connection; NMOS transistor M s1 The gate and NMOS transistor M s2 The gates are interconnected and simultaneously connected to an external voltage V. C1 NMOS transistor M s1 The source and NMOS transistor M s2 The sources of the NMOS transistors are interconnected and simultaneously grounded; NMOS transistor M s2 The drain and capacitor C s2 Upper plate connection; capacitor C t1 The lower electrode and NMOS transistor M t1 Drain connection; NMOS transistor M t1 The gate and NMOS transistor M t2 The gates are interconnected and simultaneously connected to an external voltage V. C2 NMOS transistor M t1 The source and NMOS transistor M t2 The sources of the NMOS transistors are interconnected and simultaneously grounded; NMOS transistor M t2 The drain and capacitor C t2 The upper plate is connected; inductors L1 and L2 are coupled by a coupling coefficient. k Magnetic coupling is performed; one end of inductor L1 is also connected to power supply VDD; one end of inductor L2 is also connected to ground potential; NMOS transistor M so The drain of the NMOS transistor is connected to one end of inductor L2; so The source of the NMOS transistor is connected to the other end of inductor L2; so The gate is connected to an external voltage V. sw ; Wherein, external voltage V c0 External voltage V C1 and external voltage V C2 Together they serve as the first control signal; external voltage V sw As the second control signal.

7. The dual-mode reconfigurable compact CMOS ultrawideband fourth-order bandpass filter according to claim 2, characterized in that, The gain control stage includes: an NMOS transistor M G1 NMOS transistor M G2 Variable resistor R G1 and variable resistor R G2 ; NMOS transistor M G1 The drain of the NMOS transistor is connected to the first input terminal of the LC resonant filter; G1 The source and variable resistor R G1 One end is connected; NMOS transistor M G1 The gate of the NMOS transistor is connected to the differential input signal Vn; G2 The drain of the NMOS transistor is connected to the second input terminal of the LC resonant filter; G2 The gate of the NMOS transistor is connected to the differential input signal Vp; G1 The source and NMOS transistor M G2 The source poles are all connected to the ground; NMOS transistor M G2 The source and variable resistor R G2 One end is connected; variable resistor R G1 With variable resistor R G2 The other end is grounded.

8. The dual-mode reconfigurable compact CMOS ultrawideband fourth-order bandpass filter according to claim 1, characterized in that, The output stage includes: NMOS transistors M5-M 10 Resistance R 01 and resistance R 02 ; The drains of NMOS transistors M5, M6, M8, and M9 are all connected to power supply VDD1; the gate of NMOS transistor M5 is connected to the first output terminal of the first adjustable second-order filter; the gate of NMOS transistor M8 is connected to the first output terminal of the second adjustable second-order filter; the gate of NMOS transistor M6 is connected to the second output terminal of the first adjustable second-order filter; the gate of NMOS transistor M9 is connected to the second output terminal of the second adjustable second-order filter; the source of NMOS transistor M6 is connected to resistor R. 01 One end of the resistor is connected to the gate of the NMOS transistor M7; resistor R 01 The other end, the source of NMOS transistor M7, and resistor R 02 The other end and NMOS transistor M 10 The sources are connected to each other; resistor R 02 One end, the source of NMOS transistor M9 and NMOS transistor M 10 The gates of NMOS transistors M5, M7, and the positive terminal of the final output differential signal are connected; the source of NMOS transistor M8 and the drain of NMOS transistor M7 are connected. 10 The drain of the signal is connected to the negative terminal of the final output differential signal.

9. The dual-mode reconfigurable compact CMOS ultrawideband fourth-order bandpass filter according to claim 2, characterized in that, The negative resistance compensation circuit includes: an NMOS transistor M n1 NMOS transistor M n2 Variable resistor R var1 and variable resistor R var2 ; NMOS transistor M n1 The drain of the NMOS transistor M n2 The gate of the NMOS transistor and the first input terminal of the LC resonant filter are interconnected; n2 The drain of the NMOS transistor M n1 The gate of the NMOS transistor and the second input terminal of the LC resonant filter are interconnected; n1 The source and variable resistor R var1 One end is connected to the other; NMOS transistor M n2 The source and variable resistor R var2 One end of the resistor is connected to the other end; variable resistor R var1 The other end and the variable resistor R var2 The other end of each is grounded.

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