Threshold implementation method and system for a s-box of a block cipher
By mapping intermediate state data to a composite field and reusing guard variables across stages in the threshold implementation of the block cipher S-box, the problem of excessive random number consumption in the prior art is solved, achieving low hardware overhead and high security, and is suitable for resource-constrained cryptographic chips.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- JIANGSU HUAIAN TECHNICIAN COLLEGE
- Filing Date
- 2026-03-06
- Publication Date
- 2026-06-02
Smart Images
Figure CN122137534A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of information security block cipher protection technology, and in particular to a threshold implementation method and system for a block cipher S-box. Background Technology
[0002] In the hardware implementation of block cipher algorithms, the S-box, as the sole nonlinear computation unit, is a crucial element in resisting side-channel attacks (such as differential power analysis). To ensure the security of the S-box in its physical implementation, threshold implementation techniques are often employed. This involves splitting sensitive data into multiple statistically independent shares and performing distributed computation to eliminate the correlation between intermediate variables and physical leaks, thus providing provable first-order security even in environments with circuit glitches. Therefore, researching efficient and low-overhead S-box threshold implementation methods is of great significance for improving the overall security and practicality of cryptographic chips.
[0003] In existing technologies, threshold implementation schemes typically require compliance with three security criteria: correctness, incompleteness, and uniformity. To satisfy uniformity, especially in multi-stage, multi-level S-box computation structures (such as the composite field inversion structure used in AES), traditional schemes often require introducing a large number of fresh random numbers for share refresh at each computation stage, resulting in high random number consumption and significant hardware area and power consumption overhead. For example, while typical 3-share or d+1-share schemes can achieve first-order security, a single S-box computation may consume tens of bits of random numbers, placing a heavy burden on the design and system integration of random number generators. Furthermore, some studies have attempted to reduce random number requirements by optimizing algebraic structures, sharing masks, or reducing the number of refreshes, but these often lead to problems such as uniformity violations, increased logic depth, or longer path delays, making it difficult to achieve a comprehensive performance of low area, low latency, and low random number consumption while ensuring security. Summary of the Invention
[0004] The purpose of this invention is to provide a threshold implementation method for the S-box of a block cipher, which significantly reduces resource consumption while ensuring first-order security by reusing guard variables across stages.
[0005] To address the aforementioned technical problems, embodiments of the present invention provide a threshold implementation method for an S-box in a block cipher, comprising the following steps: The intermediate state data of the multiple secret sharing shares that have been split in the block cipher operation are mapped from the original domain to the composite domain to obtain the mapped data shares represented by multiple subdomain components; the multiple subdomain components are registered separately, and the registered multiple subdomain components are defined as the first guard variable; Based on multiple subdomain components, by introducing a first set of fresh random numbers, the threshold implementation of the composite domain inversion operation of the S-box is performed to obtain the corresponding multiple intermediate operation result shares; and during the threshold implementation calculation process, a set of second guard variables is generated simultaneously, and each variable in the second guard variables is registered separately. Based on multiple intermediate operation result shares, perform at least one subdomain multiplication operation that reuses the first set of guard variables as the input mask, and a low-bit nonlinear operation that is thresholded by injecting a second set of fresh random numbers to obtain the corresponding operation result share. Based on the result share of the operation, the final output mask share of the S-box is synthesized through combinational logic, and the second guard variable is reused to refresh the final output mask share during the synthesis process.
[0006] In some optional embodiments, the step of calculating the composite field inversion operation of the S-box based on multiple subdomain components by introducing a first set of fresh random numbers and performing threshold calculations to obtain corresponding multiple intermediate operation result shares includes the following steps: Based on the inversion algorithm predefined by the S-box on the composite field, we determine the multiple basic operations that need to be performed to calculate the final inversion result and have a sequential dependency relationship. Define the output of each basic operation as a sequentially dependent intermediate variable; For each intermediate variable, based on the security criteria of threshold implementation, a set of component functions is constructed that act on its input secret sharing share, so that the component functions together satisfy the requirements of correctness, incompleteness and uniformity. When executing a component function corresponding to a nonlinear basic operation, one or more random bits from the first set of fresh random numbers are injected into the component function to ensure that the secret share of its output meets the uniform distribution requirement, thereby obtaining multiple intermediate operation result shares.
[0007] In some optional embodiments, the first set of fresh random numbers is 4 bits, used to simultaneously achieve uniformity refresh and the generation of the second guard variable in the threshold implementation calculation of the composite field inversion operation.
[0008] In some optional embodiments, the second set of fresh random numbers is 2 bits, which is dedicated to threshold protection of the output share of low-order nonlinear operations.
[0009] Embodiments of the present invention also provide a threshold implementation system for a block cipher S-box, comprising: The domain mapping and guard preparation module is used to map the intermediate state data of multiple secret sharing shares that have been split in the block cipher operation from the original domain to the composite domain, so as to obtain the mapped data shares represented by multiple subdomain components; the multiple subdomain components are registered separately, and the registered multiple subdomain components are defined as the first guard variable; The composite field inversion and guarded generation module is used to perform threshold implementation calculations of the composite field inversion operation of the S-box based on multiple subdomain components by introducing a first set of fresh random numbers, and obtain the corresponding multiple intermediate operation result shares; and simultaneously generate a set of second guard variables during the threshold implementation calculation process, and register each variable in the second guard variables separately. The guard reuse and nonlinear calculation module is used to perform at least one subdomain multiplication operation that reuses the first set of guard variables as the input mask, and a low-order nonlinear operation with threshold protection by injecting a second set of fresh random numbers, based on multiple intermediate operation result shares, to obtain the corresponding operation result share. The output synthesis and guard refresh module is used to synthesize the final output mask share of the S-box based on the calculation result share through combinational logic, and to refresh the final output mask share by reusing the second guard variable during the synthesis process.
[0010] In some optional embodiments, the output terminals of the domain mapping and guard preparation module, the composite domain inversion and guard generation module, and the guard multiplexing and nonlinear calculation module are all equipped with registers; the subdomain components output by the domain mapping and guard preparation module, the intermediate operation result shares output by the composite domain inversion and guard generation module, and the operation result shares output by the guard multiplexing and nonlinear calculation module all need to be stored in their respective registers before being transmitted to the next module.
[0011] The threshold implementation method for the S-box of the block cipher provided by this invention has at least the following beneficial effects: This invention divides the S-box computation process into multiple logical stages and introduces register isolation and guard variable reuse mechanisms between stages. While ensuring first-order side-channel security, it significantly reduces overall resource overhead. This method not only drastically reduces the demand for fresh random numbers, alleviating the hardware burden on the random number generation module, but also effectively maintains the uniformity of output share across stages through cross-stage reuse of guard variables and fine-grained refresh control, thereby avoiding security risks caused by glitches. Compared with existing technologies, this method achieves synergistic optimization in three key indicators: hardware area, timing delay, and random number consumption. Its structure supports modular and pipelined design, facilitating integration into resource-constrained cryptographic chips, and possesses good scalability and algorithm adaptability, ultimately achieving an effective balance between security, execution efficiency, and engineering feasibility. Attached Figure Description
[0012] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings:
[0013] Figure 1 This is a flowchart of a threshold implementation method for an S-box of a block cipher provided according to an embodiment of the present invention; Figure 2 This is a specific four-stage structural block diagram of an AES S box provided according to an embodiment of the present invention. Detailed Implementation
[0014] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below in conjunction with specific embodiments and corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of this invention, and not all of them. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.
[0015] One embodiment of the present invention relates to a threshold implementation method for a block cipher S-box. The implementation details of the threshold implementation method for the block cipher S-box in this embodiment are described in detail below. The following implementation details are provided for ease of understanding and are not necessary for implementing this solution.
[0016] The specific process of the threshold implementation method of the block cipher S-box in this embodiment can be described as follows: Figure 1 As shown, it includes: Step 101: Map the intermediate state data of the multiple secret sharing shares that have been split in the block cipher operation from the original domain to the composite domain to obtain the mapped data share represented by multiple subdomain components; register the multiple subdomain components respectively, and define the registered multiple subdomain components as the first guard variable; Step 102: Based on multiple subdomain components, by introducing the first set of fresh random numbers, the threshold implementation calculation of the composite domain inversion operation of the S-box is performed to obtain the corresponding multiple intermediate operation result shares; and a set of second guard variables is generated simultaneously during the threshold implementation calculation process, and each variable in the second guard variables is registered separately. Step 103: Based on multiple intermediate operation result shares, perform at least one subdomain multiplication operation that reuses the first set of guard variables as the input mask, and a low-bit nonlinear operation that is thresholded by injecting a second set of fresh random numbers, to obtain the corresponding operation result share. Step 104: Based on the result share of the operation, synthesize the final output mask share of the S-box through combinational logic, and refresh the final output mask share by reusing the second guard variable during the synthesis process.
[0017] By breaking down the nonlinear inversion, finite field multiplication, and linear combination processes within the S-box into stages, introducing register isolation and guard (guard variable) reuse mechanisms, and employing precisely controlled fresh random refresh, the consumption of random numbers is significantly reduced, the hardware area is reduced, and the overall implementation efficiency is improved while ensuring the security of the first-order side channel.
[0018] Based on its algebraic or composite field representation, the overall computation process of the S-box is divided into four sequentially executed stages: isomorphic mapping stage, subfunction generation stage, subfield nonlinear operation stage, and output combination stage. Registers are inserted at the stage boundaries to achieve isolation and eliminate the propagation of glitches between logic levels.
[0019] The embodiments of the present invention also provide a threshold implementation system for a block cipher S-box. The implementation details of the block cipher S-box threshold implementation system of this embodiment are described in detail below. The following content is only for the convenience of understanding the implementation details provided and is not necessary for implementing this solution.
[0020] Specifically, the domain mapping and guard preparation module is used to map the intermediate state data of the multiple secret sharing shares that have been split in the block cipher operation from the original domain to the composite domain, so as to obtain the mapped data shares represented by multiple subdomain components; the multiple subdomain components are registered separately, and the registered multiple subdomain components are defined as the first guard variable; The composite field inversion and guarded generation module is used to perform threshold implementation calculations of the composite field inversion operation of the S-box based on multiple subdomain components by introducing a first set of fresh random numbers, and obtain the corresponding multiple intermediate operation result shares; and simultaneously generate a set of second guard variables during the threshold implementation calculation process, and register each variable in the second guard variables separately. The guard reuse and nonlinear calculation module is used to perform at least one subdomain multiplication operation that reuses the first set of guard variables as the input mask, and a low-order nonlinear operation with threshold protection by injecting a second set of fresh random numbers, based on multiple intermediate operation result shares, to obtain the corresponding operation result share. The output synthesis and guard refresh module is used to synthesize the final output mask share of the S-box based on the calculation result share through combinational logic, and to refresh the final output mask share by reusing the second guard variable during the synthesis process.
[0021] This embodiment uses the AES block cipher algorithm as the target algorithm to be protected. The first-order threshold implementation method of the 8-bit S-box for block ciphers proposed in this invention is applied to the AES encryption process to achieve effective protection against first-order side-channel attacks. This embodiment focuses on the integration method and structural details of the 8-bit S-box AES algorithm of this invention.
[0022] The AES block cipher algorithm has a block length of 128 bits. The round function consists of S-box substitution, row shifting, column mixing, and round key addition. Since the S-box is the only non-linear component in AES and the most sensitive part for side-channel attacks, the threshold protection scheme of this invention only processes the S-box part of AES. Other linear operations (such as ShiftRows and MixColumns) do not require additional thresholding operations because they maintain linearity with respect to share. This embodiment will focus on illustrating the four-stage protection structure for the S-box part.
[0023] To resist first-order side-channel attacks, this embodiment splits the AES plaintext input and round key input into two shares, and maintains independent propagation of each share during the AES encryption process. The AES nonlinear component S-box is processed using the four-stage thresholding structure proposed in this invention, specifically including: isomorphic mapping in stage 1, intermediate subfunction generation in stage 2, subdomain nonlinear operation in stage 3, and output combination in stage 4.
[0024] Phase 1: Isomorphic Mapping. This phase maps the 8-bit input shares to a composite domain structure suitable for S-box hardware implementation, e.g., from GF(2^8) to GF((2^4)^2). Both shares undergo the same linear transformation independently, without introducing fresh random numbers. To prevent glitches, all outputs in this phase are latched through registers, ensuring that the input shares for subsequent phases are completely independent in the time domain. The high 4 bits and low 4 bits of this phase will serve as the source of the guard (i.e., the first guard variable) value for the multiplier in subsequent phases.
[0025] Phase 2: Subfunction Generation and Guard Generation. Combining the algebraic structure of the AES standard S-box, the four intermediate quantities (x, y, z, t) in the composite field inversion process are decomposed using threshold decomposition. Each intermediate quantity is composed of several component functions f0 and f1, which must satisfy: correctness, incompleteness, and uniformity. To ensure uniformity, this embodiment introduces 1 bit of fresh random number for each intermediate quantity, thus consuming a total of 4 bits of fresh random number in this phase. Simultaneously, guard(0) to guard(3) (i.e., the second guard variables) are generated. These guards can be reused in subsequent phases, thereby significantly reducing random refresh overhead.
[0026] Phase 3: Guardian Reuse and Nonlinear Computation. This phase executes two GF(2) operations. 4 The subfield multiplication of ) and the inversion of a GF(2²) are the most concentrated parts of the nonlinearity of the AES S-box. To reduce the randomness of the numbers, this invention adopts the following strategy:
[0027] The multiplier uses the register output of stage 1 (the first guard variable) as a guard, without introducing new random numbers; The inverse of GF(2²) can be represented as two Boolean functions m and n of degree 2, which can maintain uniformity with only 2 bits of random numbers (i.e., the second set of fresh random numbers); All outputs are isolated through registers, improving glitches prevention.
[0028] Therefore, the total amount of fresh randomness in this stage is only 2 bits.
[0029] Phase 4: Output Synthesis and Guardian Refresh. This phase includes four GF(2) 4 The subfield multiplier and the final affine operation are used to generate an 8-bit output of the AES S-box. The key features of this invention are:
[0030] No new random numbers are needed in this phase; All output refreshes reuse guard(0)--guard(3) (the second guard variable) generated in phase 2; The affine transformation of the output is a linear operation, thus naturally preserving safety for both shares.
[0031] The final output share is the AES S-box output implemented through a first-order threshold, which can be directly used in subsequent linear operations of AES.
[0032] In this embodiment, the S-box of the AES algorithm, under the four-stage structure of this invention, requires only 6 bits of fresh random number per S-box (4 bits for stage 2 and 2 bits for stage 3), significantly lower than common threshold implementations (typically requiring 20-40 bits). All linear operations maintain linear superposition of shares, without adding additional overhead. Through register isolation and fine-grained guard multiplexing, the implementation of this invention satisfies the first-order threshold security under the glitch propagation detection model, which can be verified by Prover or TVLA testing.
[0033] The specific four-stage structure diagram applied to the AES S box is as follows: Figure 2 As shown in the figure, a four-stage structural block diagram illustrating the application of this invention to an AES S-box is presented. This figure is based on... Figure 2The overall structure of the AES S-box is further refined, detailing the specific computational modules within the composite domain (GF((2^4)^2)). The diagram illustrates in detail: Stage 1 contains the linear mapping module (L); Stage 2 includes multiple component functions (f_i) for calculating intermediate variables (x, y, z, t) and generating a Guard(0-3); Stage 3 contains two GF(2^4) multipliers (reusing the high / low bits of Stage 1 output as masks) and a GF(2^2) inversion module (injecting 2-bit random numbers); Stage 4 contains multiple GF(2^4) multipliers and an affine transformation, reusing the Guard(0-3) from Stage 2 for output refresh. This diagram is crucial for understanding how the invention is specifically implemented in typical application scenarios.
[0034] To verify the actual hardware performance of the proposed solution, in one specific embodiment, the Advanced Encryption Standard (AES) algorithm was selected as the evaluation object. Using the Synopsys Design Compiler synthesis tool, within the UMC 180nm process standard cell library, logic synthesis and performance evaluation were performed on the first-order secure AES encryption circuit implemented based on the method of this invention.
[0035] In this embodiment, the hardware area of the first-order secure S-cell implementing the method of the present invention is 2.37 kGE. Compared with existing typical technical solutions, the area efficiency of the present invention is significantly improved:
[0036] Compared to the threshold implementation scheme that also uses a composite field decomposition structure but requires storing the output share for each intermediate operation and consumes a single bit of fresh random number, the area is reduced by approximately 18.3%.
[0037] Compared to threshold implementations that employ special algebraic structures to completely eliminate the consumption of fresh random numbers, the area is reduced by approximately 34.4%.
[0038] The S-box of this invention is integrated into a complete AES encryptor, with a total hardware area of 8.12 kGE. It should be noted that there are benchmark differences in gate equivalent (GE) values between different semiconductor process libraries, which should be carefully considered when making cross-process comparisons.
[0039] The scheme shown in this embodiment requires only 6 bits of fresh random numbers to be injected when encrypting a 128-bit plaintext data block, and the encryption operation takes 226 clock cycles.
[0040] Regarding random number consumption: Compared to the optimized threshold implementation scheme that still consumes 28 bits of random numbers despite using the "guard swap" (COTG) strategy, the random number consumption of the present invention is reduced by about 79%, which greatly alleviates the hardware design pressure of the random number generator (PRNG).
[0041] In terms of computing speed: Compared with the compact threshold implementation scheme that requires only 4 bits of random number but has an encryption latency of 236 cycles by deeply optimizing the combinational logic path, the encryption latency of the present invention is further reduced by 10 cycles, achieving a higher throughput with low random number overhead.
[0042] To clearly demonstrate the overall performance differences between this invention and various existing technical approaches, key indicators of representative solutions are compared in Table 1: Table 1 Performance Comparison of First-Order Secure AES Implementation Schemes The experimental data above demonstrates that this invention, through a series of collaborative designs including staged register isolation, cross-stage reuse of guarded variables, and precise random number injection control, effectively resolves the inherent contradiction in existing threshold implementation technologies regarding the difficulty of balancing random number consumption, hardware area, and computational latency. Compared to various existing solutions, this invention achieves competitive optimization results in several key hardware efficiency indicators while ensuring strict first-order side-channel security, realizing a synergistic improvement in security and resource efficiency.
[0043] The steps of the various methods described above are only for clarity. In practice, they can be combined into one step or some steps can be split into multiple steps. As long as they include the same logical relationship, they are all within the protection scope of this invention. Adding insignificant modifications or introducing insignificant designs to the algorithm or process, without changing the core design of the algorithm and process, are also within the protection scope of this invention.
[0044] Another embodiment of the present invention relates to a computer-readable storage medium storing a computer program. When executed by a processor, the computer program implements the method embodiments described above.
[0045] That is, those skilled in the art will understand that all or part of the steps in the methods of the above embodiments can be implemented by a program instructing related hardware. This program is stored in a storage medium and includes several instructions to cause a device (which may be a microcontroller, chip, etc.) or processor to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.
[0046] Those skilled in the art will understand that the above embodiments are specific embodiments for implementing the present invention, and in practical applications, various changes can be made to them in form and detail without departing from the spirit and scope of the present invention.
Claims
1. A threshold implementation method for an S-box block cipher, characterized in that, The method includes: The intermediate state data of the multiple secret sharing shares that have been split in the block cipher operation are mapped from the original domain to the composite domain to obtain the mapped data shares represented by multiple subdomain components; the multiple subdomain components are registered separately, and the registered multiple subdomain components are defined as the first guard variable; Based on multiple subdomain components, by introducing a first set of fresh random numbers, the threshold implementation of the composite domain inversion operation of the S-box is performed to obtain the corresponding multiple intermediate operation result shares; and during the threshold implementation calculation process, a set of second guard variables is generated simultaneously, and each variable in the second guard variables is registered separately. Based on multiple intermediate operation result shares, perform at least one subdomain multiplication operation that reuses the first set of guard variables as the input mask, and a low-bit nonlinear operation that is thresholded by injecting a second set of fresh random numbers to obtain the corresponding operation result share. Based on the result share of the operation, the final output mask share of the S-box is synthesized through combinational logic, and the second guard variable is reused to refresh the final output mask share during the synthesis process.
2. The threshold implementation method for the S-box of the block cipher as described in claim 1, characterized in that, The method, based on multiple subdomain components, involves introducing a first set of fresh random numbers and performing threshold calculations on the composite field inversion of the S-box to obtain corresponding multiple intermediate calculation result shares. This includes the following steps: Based on the inversion algorithm predefined by the S-box on the composite field, we determine the multiple basic operations that need to be performed to calculate the final inversion result and have a sequential dependency relationship. Define the output of each basic operation as a sequentially dependent intermediate variable; For each intermediate variable, based on the security criteria of threshold implementation, a set of component functions is constructed that act on its input secret sharing share, so that the component functions together satisfy the requirements of correctness, incompleteness and uniformity. When executing a component function corresponding to a nonlinear basic operation, one or more random bits from the first set of fresh random numbers are injected into the component function to ensure that the secret share of its output meets the uniform distribution requirement, thereby obtaining multiple intermediate operation result shares.
3. The threshold implementation method for the S-box of a block cipher as described in claim 1, characterized in that, The first set of fresh random numbers is 4 bits, which is used to simultaneously achieve uniformity refresh and the generation of the second guard variable in the threshold implementation calculation of the composite field inversion operation.
4. The threshold implementation method for the S-box of a block cipher as described in claim 1, characterized in that, The second set of fresh random numbers is 2 bits, which is used to threshold and protect the output share of low-order nonlinear operations.
5. A threshold implementation system for an S-box block cipher, characterized in that, The system includes: The domain mapping and guard preparation module is used to map the intermediate state data of multiple secret sharing shares that have been split in the block cipher operation from the original domain to the composite domain, so as to obtain the mapped data shares represented by multiple subdomain components; the multiple subdomain components are registered separately, and the registered multiple subdomain components are defined as the first guard variable; The composite field inversion and guarded generation module is used to perform threshold implementation calculations of the composite field inversion operation of the S-box based on multiple subdomain components by introducing a first set of fresh random numbers, and obtain the corresponding multiple intermediate operation result shares; and simultaneously generate a set of second guard variables during the threshold implementation calculation process, and register each variable in the second guard variables separately. The guard reuse and nonlinear calculation module is used to perform at least one subdomain multiplication operation that reuses the first set of guard variables as the input mask, and a low-order nonlinear operation with threshold protection by injecting a second set of fresh random numbers, based on multiple intermediate operation result shares, to obtain the corresponding operation result share. The output synthesis and guard refresh module is used to synthesize the final output mask share of the S-box based on the calculation result share through combinational logic, and to refresh the final output mask share by reusing the second guard variable during the synthesis process.
6. The threshold implementation system for the S-box of a block cipher as described in claim 5, characterized in that, The output terminals of the domain mapping and guard preparation module, the composite domain inversion and guard generation module, and the guard multiplexing and nonlinear calculation module are all equipped with registers. The subdomain components output by the domain mapping and guard preparation module, the intermediate operation result shares output by the composite domain inversion and guard generation module, and the operation result shares output by the guard multiplexing and nonlinear calculation module all need to be stored in their respective registers before being transmitted to the next module.