Cxl on-chip switch network and cxl switch chip of multi-target port queue architecture

By employing a three-level cross-connect topology with a multi-target port queue architecture and distributed arbitration, the bandwidth bottleneck and arbitration complexity of traditional CXL on-chip switching networks are resolved, enabling efficient CXL message switching and in-order switching to meet the needs of large-scale heterogeneous computing systems.

CN122137812APending Publication Date: 2026-06-02BEIJING SHUDU INFORMATION TECH CO LTD
View PDF 1 Cites 0 Cited by

Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
BEIJING SHUDU INFORMATION TECH CO LTD
Filing Date
2026-03-19
Publication Date
2026-06-02

AI Technical Summary

Technical Problem

Traditional CXL on-chip switching networks suffer from bandwidth bottlenecks and a surge in arbitration complexity as the number of input/output ports increases, and cannot guarantee the in-order switching of CXL packets.

Method used

It adopts a multi-target port queue architecture, including a three-level cross-connection topology of input layer, intermediate layer and output layer. Each CXL basic switching unit contains CXL order preservation module and multi-way arbitration module, and achieves high scalability and in-order switching through multi-level topology and distributed arbitration.

Benefits of technology

It improves the scalability and throughput efficiency of the switching network, reduces chip area and power consumption, ensures the in-order switching of CXL messages, and adapts to the interconnection needs of large-scale heterogeneous computing systems.

✦ Generated by Eureka AI based on patent content.

Smart Images

  • Figure CN122137812A_ABST
    Figure CN122137812A_ABST
Patent Text Reader

Abstract

This invention belongs to the field of switching chips and relates to a CXL on-chip switching network and CXL switching chip with a multi-target port queue architecture. The switching network consists of several structurally identical CXL basic switching units, employing a three-level cross-connection topology of input layer, intermediate layer, and output layer. Each CXL basic switching unit includes m input ports, n output ports, m CXL ordering modules, and n multi-arbitration modules. The CXL ordering modules implement CXL packet parsing, protocol ordering, and buffered forwarding. The multi-arbitration modules use a round-robin algorithm to implement distributed arbitration. This invention achieves traffic isolation based on target ports, with arbitration complexity increasing linearly and scalable to over 256 ports. Protocol-level ordered switching of CXL packets improves throughput and link utilization while reducing chip area, power consumption, and manufacturing costs. It is suitable for heterogeneous device interconnection in data centers and high-performance computing systems.
Need to check novelty before this filing date? Find Prior Art