A method, apparatus, device, and medium for television key solidification and activation verification.

Abstract

This invention relates to the technical field of information security. Specifically, it relates to a method, apparatus, device, and medium for television key solidification and startup verification. The method includes reading key A information from the secure state machine of a chip, reading key B information from a preset secure encryption area of ​​flash memory, performing hash generation processing based on key A and key B information to obtain key C information, writing key C information into a preset independent non-writable area, reading solidified key information from the preset independent non-writable area of ​​flash memory, performing a consistency comparison processing between key C information and solidified key information to obtain startup verification result information, allowing the smart TV to enter the startup process if the startup verification result information is consistent, and prohibiting the smart TV from entering the startup process if the startup verification result information is inconsistent. This invention effectively solves the problem of insufficient verification reliability caused by the easy copying or replacement of verification criteria during television startup verification.

Description

Technical Field

[0001] This invention relates to the field of information security technology, and in particular to a method, apparatus, device, and medium for television key solidification and activation verification. Background Technology

[0002] As a home terminal with network connectivity, smart TVs typically integrate functions such as application installation, content subscription, account login, remote upgrades, and local data caching. During operation, the device stores critical data related to the terminal's identity, access permissions, and application data locally. Furthermore, the startup phase often bears the responsibility of checking the legitimacy of the operating environment and the integrity of critical data. Therefore, the security of the startup link directly affects the reliability of the terminal in mass production deployment, after-sales maintenance, and long-term operation.

[0003] In existing technologies, some terminal security verifications rely on identifiers or verification data from a single source, such as judging based solely on fixed verification information in memory or solely on software layer configuration. In scenarios where memory is copied, replaced, or rewritten without authorization, this type of method is prone to the problem of verification criteria migrating along with the data. As a result, the terminal may still pass the verification process under different hardware combinations or different storage media conditions. In addition, if the verification process is mainly triggered by a general software layer and completed in a general read / write path, the verification data may also be affected by debugging interfaces, privilege escalation, or abnormal flashing behavior during the read / write and comparison process, resulting in insufficient stability of the verification mechanism.

[0004] On the other hand, during the production, burning, factory configuration, upgrade and maintenance of TV terminals, write control and state switching of storage areas are often involved. The writability and protection status requirements of the same storage area are different at different stages. If there is a lack of solidification strategy and state management for key verification data, the verification data may be repeatedly written, rolled back or overwritten, which may lead to problems such as inconsistent startup verification results, unreproducible verification process or increased maintenance costs. Therefore, the reliability and anti-substitution and anti-copying capabilities of the verification mechanism for the terminal startup stage in multiple stages and multiple scenarios still need to be further improved. Summary of the Invention

[0005] To address the problem of insufficient verification reliability caused by the easy copying or replacement of verification criteria during the TV startup verification process, this application provides a TV key solidification and startup verification method, apparatus, device, and medium.

[0006] The above-mentioned objective of this application is achieved through the following technical solution: A method for solidifying and verifying a television key, the method comprising: Obtain the key generation instruction information and send it to the chip; When the chip receives the key generation instruction information, it reads the key A information from the chip's secure state machine and the key B information from the preset secure encryption area of ​​the flash memory; Based on key A and key B, perform hash generation to obtain key C. Determine whether the first power-on completion marker information has been detected; If the first power-on completion marker is not detected, the preset independent non-writable area of ​​the flash memory is unlocked, the key C information is written into the preset independent non-writable area, and the preset independent non-writable area is locked. Upon detecting the completion of the first power-on marker, the hardened key information is read from the preset independent non-writable area of ​​the flash memory. The key C information is compared with the hardened key information to obtain the startup verification result information. If the startup verification results are consistent, the smart TV is allowed to enter the startup process; if the startup verification results are inconsistent, the smart TV is prohibited from entering the startup process.

[0007] By adopting the above technical solution, the key information A output by the chip's secure state machine and the key information B stored in the preset secure encryption area of ​​the flash memory can be introduced simultaneously during the key generation stage. Based on the hash generation process of key information A and key information B, key information C is formed. This ensures that the key data on which the startup verification depends is constrained by both the chip side and the flash memory side, avoiding the situation where the verification basis is synchronously migrated when relying on key data from a single source in the flash memory copying or replacement scenario. Furthermore, when the initial power-on completion marker information is not detected, the preset independent non-writable area of ​​the flash memory is subjected to a solidification process of unlocking, writing, and locking. This ensures that key information C is written into the preset independent non-writable area in the form of solidified key information and remains in a non-writable state, thereby preventing the solidified key information from being repeatedly written or rewritten during subsequent startup processes, which would lead to instability of the verification benchmark. When the initial power-on completion marker information is detected, the solidified key information is read from the preset independent non-writable area and compared with key information C to obtain the startup verification result information. Then, the startup verification result information is used to control whether to allow entry into the startup process, establishing a clear association between the entry into the startup process and the key consistency result, reducing the risk of entering the startup process even in the case of inconsistency.

[0008] In a preferred embodiment, this application can be further configured such that: the hash generation process based on key A information and key B information to obtain key C information includes: Read the key A information as the first key byte sequence, and read the key B information as the second key byte sequence; The first key byte sequence and the second key byte sequence are concatenated according to a preset concatenation order to obtain the byte sequence to be hashed. The hash byte sequence is processed by a preset hash algorithm to obtain the hash output byte sequence; Extract the key field corresponding to the preset byte length from the hash output byte sequence to obtain the key C information.

[0009] By adopting the above technical solution, key A information and key B information can be converted into a first key byte sequence and a second key byte sequence, respectively, so that subsequent processing is performed in a unified byte sequence form. This avoids instability in concatenation and hash input due to inconsistent data representation methods. Furthermore, the first key byte sequence and the second key byte sequence are concatenated according to a preset concatenation order to obtain a byte sequence to be hashed, thus fixing the order of hash input and preventing key C information from becoming unreproducible due to changes in the concatenation order. The byte sequence to be hashed is processed by a preset hash algorithm to obtain a hash output byte sequence, which has a fixed length and fixed generation rules, making it convenient as a unified source for subsequent key derivation. The key field corresponding to the preset byte length is extracted from the hash output byte sequence to obtain key C information, ensuring that the length of key C information meets preset constraints and is easy to write and compare.

[0010] In a preferred embodiment, this application can be further configured as follows: performing an unlocking operation on the preset independent writable area of ​​the flash memory when no first power-on completion marker information is detected includes: Based on the interval address information corresponding to the preset independent non-writable area, locate the preset independent non-writable area in the flash memory; Perform an unlock control operation on the flash memory to switch the preset independent non-writable area from a non-writable state to a writable state; Read the unlock status information returned by the flash memory, and determine whether the unlocking of the preset independent non-writable area is complete based on the unlock status information; If the unlock status information indicates that unlocking is complete, an unlock completion message is generated.

[0011] By adopting the above technical solution, the location of the preset independent writable area in the flash memory can be completed based on the interval address information corresponding to the preset independent writable area. This allows subsequent unlocking control operations to be performed on a specific storage interval, avoiding write protection status changes to non-target intervals. Furthermore, by performing unlocking control operations on the flash memory, the preset independent writable area is switched from a writable state to a writable state, ensuring that the preset independent writable area meets the write conditions during the solidification write phase. By reading the unlocking status information returned by the flash memory and determining whether the unlocking of the preset independent writable area is complete based on the unlocking status information, the execution result of the unlocking control operation has a verifiable status basis, avoiding directly entering the write process when the unlocking is not complete. When the unlocking status information indicates that the unlocking is complete, unlocking completion information is generated, giving subsequent write operations a clear pre-state identifier and facilitating the establishment of a correspondence with the interval address information.

[0012] In a preferred embodiment, this application can be further configured as follows: writing the key C information into a preset independent writable area and performing a locking operation on the preset independent writable area includes: When the preset independent non-writable area is in a writable state, the key C information is written into the preset independent non-writable area according to the interval address information corresponding to the preset independent non-writable area, and the writing completion information is obtained. Based on the write completion information, the interval data of the preset independent non-writable area is read, and the interval data is compared with the key C information to obtain the write verification result information. If the write verification result information is consistent, a locking control operation is performed on the flash memory to switch the preset independent non-writable area from a writable state to a non-writable state. Read the lock status information returned by the flash memory, and generate lock completion information based on the lock status information.

[0013] By adopting the above technical solution, key C information can be written into the preset independent non-writable area according to the interval address information when the preset independent non-writable area is in a writable state. The writing position and writing length are constrained by the interval address information, forming traceable writing completion information. Based on the writing completion information, the interval data of the preset independent non-writable area is read and compared with the key C information to obtain the writing verification result information. This establishes a clear verification relationship between the written content and the target key data, avoiding inconsistencies between the solidified data and the key C information caused by writing anomalies or writing offsets. When the writing verification result information indicates consistency, a locking control operation is performed on the flash memory to switch the preset independent non-writable area from a writable state to a non-writable state. After the key C information completes the writing verification, the corresponding storage interval is restored to a non-writable state while maintaining write protection constraints. The locking status information returned by the flash memory is read and locking completion information is generated based on the locking status information. This ensures that the execution result of the locking control operation has a verifiable status basis and is easy to associate with the interval address information for recording.

[0014] In a preferred embodiment, this application can be further configured to: upon detecting the first power-on completion marker information, read the hardened key information from a preset independent writable area of ​​the flash memory, including: Based on the address information of the preset independent non-writable area in the flash memory, the data of the preset byte length is read from the preset independent non-writable area to obtain the read data; Perform length verification on the read data to obtain the read determination result information; If the verification result indicates that the verification is successful, the read data will be identified as the solidified key information.

[0015] By adopting the above technical solution, it is possible to read interval data of a preset byte length from the preset independent non-writable area based on the interval address information corresponding to the preset independent non-writable area in the flash memory. This ensures that the reading range is constrained by the interval address information and the preset byte length, and maintains the integrity of the byte sequence of the read data. Furthermore, length verification processing is performed on the read data to obtain the read judgment result information. This ensures that the read data meets the preset byte length requirement before entering the subsequent consistency comparison, avoiding incomplete or non-compliant format of the solidified key data due to abnormal read length. When the read judgment result information indicates that the verification has passed, the read data is identified as solidified key information, establishing a correspondence between the source of the solidified key information and the read verification result, and serving as the consistency comparison benchmark data for subsequent verification.

[0016] In a preferred embodiment, this application can be further configured as follows: the step of performing a consistency comparison process between the key C information and the solidified key information to obtain startup verification result information includes: Perform a length consistency check on the key C information and the fixed key information to obtain the length check result information; If the length verification results are consistent, a memory comparison method to prevent timing attacks is adopted. The key C information and the solidified key information are compared byte by byte according to the preset byte order to obtain the comparison result information. Startup verification result information is generated based on the comparison results.

[0017] By adopting the above technical solution, length verification result information can be obtained by performing length consistency verification processing on key C information and solidified key information. This ensures that the consistency comparison process is carried out under the premise that the number of bytes in both is consistent, thereby keeping the comparison range and comparison boundary definite. When the length verification result information indicates consistency, a memory comparison method that prevents timing attacks is adopted, and the key C information and solidified key information are performed byte by byte in a preset byte order for consistency comparison processing. This ensures that the comparison process performs the same traversal process on all byte positions and forms a unified comparison conclusion through difference accumulation rules, avoiding premature termination of the comparison process when inconsistencies occur and thus avoiding the generation of distinguishable comparison timing. Startup verification result information is generated based on the comparison result information, establishing a correspondence between the startup verification result information and the output result of the byte-by-byte consistency comparison processing, and forming result data for subsequent startup process entry control.

[0018] In a preferred embodiment, this application can be further configured as follows: allowing the smart TV to enter the startup process when the startup verification result information is consistent, and prohibiting the smart TV from entering the startup process when the startup verification result information is inconsistent, includes: If the startup verification result information is consistent, a startup permission instruction is generated, and the entry conditions for the startup process are released according to the startup permission instruction information, so that the smart TV can continue to execute the startup process; If the startup verification results are inconsistent, a startup prohibition indication is generated, and the startup process is blocked based on the startup prohibition indication to prevent the smart TV from continuing to execute the startup process.

[0019] By adopting the above technical solution, when the startup verification result information is consistent, a startup permission indication information can be generated. Based on the startup permission indication information, the entry condition of the startup process is processed by state switching, changing the entry condition from restricted entry to allowed entry, thereby allowing the smart TV to continue executing the startup process. Conversely, when the startup verification result information is inconsistent, a startup prohibition indication information can be generated. Based on the startup prohibition indication information, the entry condition of the startup process is processed by state switching, changing the entry condition from allowed entry to restricted entry, thereby blocking the smart TV from continuing to execute the startup process before it enters the startup process.

[0020] The second objective of this invention is achieved through the following technical solution: A television key solidification and activation verification device, the television key solidification and activation verification device comprising: The instruction sending module is used to obtain key generation instruction information and send the key generation instruction information to the chip; The key reading module is used to read key A information from the chip's secure state machine and key B information from the preset secure encryption area of ​​the flash memory when the chip receives key generation instruction information; The hash generation module is used to perform hash generation processing based on key information A and key information B to obtain key information C. The tag detection module is used to determine whether the tagging information for the first power-on completion has been detected; The solidification writing module is used to perform an unlocking operation on the preset independent non-writable area of ​​the flash memory, write the key C information into the preset independent non-writable area, and perform a locking operation on the preset independent non-writable area when the first power-on completion marking information is not detected. The startup verification module is used to read the solidified key information from the preset independent non-writable area of ​​the flash memory when the first power-on completion marking information is detected, and to perform a consistency comparison process between the key C information and the solidified key information to obtain the startup verification result information. The startup control module is used to allow the smart TV to enter the startup process if the startup verification result information is consistent, and to prevent the smart TV from entering the startup process if the startup verification result information is inconsistent.

[0021] By adopting the above technical solution, the key information A output by the chip's secure state machine and the key information B stored in the preset secure encryption area of ​​the flash memory can be introduced simultaneously during the key generation stage. Based on the hash generation process of key information A and key information B, key information C is formed. This ensures that the key data on which the startup verification depends is constrained by both the chip side and the flash memory side, avoiding the situation where the verification basis is synchronously migrated when relying on key data from a single source in the flash memory copying or replacement scenario. Furthermore, when the initial power-on completion marker information is not detected, the preset independent non-writable area of ​​the flash memory is subjected to a solidification process of unlocking, writing, and locking. This ensures that key information C is written into the preset independent non-writable area in the form of solidified key information and remains in a non-writable state, thereby preventing the solidified key information from being repeatedly written or rewritten during subsequent startup processes, which would lead to instability of the verification benchmark. When the initial power-on completion marker information is detected, the solidified key information is read from the preset independent non-writable area and compared with key information C to obtain the startup verification result information. Then, the startup verification result information is used to control whether to allow entry into the startup process, establishing a clear association between the entry into the startup process and the key consistency result, reducing the risk of entering the startup process even in the case of inconsistency.

[0022] The above-mentioned objective three of this application is achieved through the following technical solution: A computer device includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of the above-described television key solidification and startup verification method.

[0023] The fourth objective of this application is achieved through the following technical solution: A computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of the above-described television key solidification and startup verification method.

[0024] In summary, this application includes at least one of the following beneficial technical effects: 1. By adopting the above technical solution, the key information A output by the chip's secure state machine and the key information B stored in the preset secure encryption area of ​​the flash memory can be introduced simultaneously during the key generation stage. Based on the hash generation process of key information A and key information B, key information C is formed. This ensures that the key data on which the startup verification depends is constrained by both the chip side and the flash memory side, avoiding the situation where the verification basis is synchronously migrated when relying on key data from a single source in the flash memory copying or replacement scenario. Furthermore, when the initial power-on completion marker information is not detected, the preset independent non-writable area of ​​the flash memory is subjected to a solidification process of unlocking, writing, and locking. This ensures that key information C is written into the preset independent non-writable area in the form of solidified key information and remains in a non-writable state, thereby preventing the solidified key information from being repeatedly written or rewritten during subsequent startup processes, which would lead to instability of the verification benchmark. When the initial power-on completion marker information is detected, the solidified key information is read from the preset independent non-writable area and compared with key information C to obtain the startup verification result information. Then, the startup verification result information is used to control whether to allow entry into the startup process, establishing a clear association between the entry into the startup process and the key consistency result, reducing the risk of entering the startup process even in the case of inconsistency. Attached Figure Description

[0025] Figure 1 This is a flowchart of a television key solidification and startup verification method according to an embodiment of this application.

[0026] Figure 2 This is a flowchart illustrating the implementation of step S30 in a television key solidification and startup verification method according to an embodiment of this application. Figure 3 This is a flowchart illustrating the implementation of step S50 in a television key solidification and startup verification method according to an embodiment of this application. Figure 4 This is another implementation flowchart of step S50 in a television key solidification and startup verification method according to an embodiment of this application; Figure 5 This is a flowchart illustrating the implementation of step S60 in a television key solidification and startup verification method according to an embodiment of this application. Figure 6 This is another implementation flowchart of step S60 in a television key solidification and startup verification method according to an embodiment of this application; Figure 7 This is a flowchart illustrating the implementation of step S70 in a television key solidification and startup verification method according to an embodiment of this application. Figure 8 This is a schematic diagram of a television key solidification and activation verification device according to one embodiment of this application. Detailed Implementation

[0027] The present application will be further described in detail below with reference to the accompanying drawings.

[0028] In one embodiment, such as Figure 1 As shown, this application discloses a method for television key solidification and startup verification, which specifically includes the following steps: S10: Obtain key generation instruction information and send the key generation instruction information to the chip.

[0029] In this embodiment, the key generation instruction information refers to instruction data organized according to a preset instruction format for triggering the chip to perform key generation actions. The preset instruction format refers to the conventions made for the byte position, byte length, and byte order of each field in the instruction data. The key generation instruction information includes at least an instruction type field and an instruction parameter field. The instruction type field is used to characterize the instruction as a key generation trigger instruction, and the instruction parameter field is used to characterize the parameter values ​​corresponding to the key generation trigger instruction. The application processor refers to the processing unit inside the chip used to execute the startup process and instruction issuance processing. The secure area refers to the functional area inside the chip used to perform protected security operations. The instruction receiving location refers to the preset write address or preset write register location within the secure area used to receive the key generation instruction information.

[0030] Specifically, when generating key generation instruction information, the byte position and byte length of the instruction type field are first determined according to the preset instruction format. Then, the preset key generation trigger identifier value is written into the instruction type field in byte order to form instruction type field data. Subsequently, the byte position and byte length of the instruction parameter field are determined according to the preset instruction format, and the parameter value corresponding to the key generation trigger instruction is written into the instruction parameter field to form instruction parameter field data. Then, the instruction type field data and the instruction parameter field data are concatenated according to the byte order of the preset instruction format to form key generation instruction information. When sending the key generation instruction information to the chip, the key generation instruction information is written into the instruction receiving position of the secure area in byte order according to the instruction receiving rules of the chip. The instruction visibility is switched according to the instruction gating rules of the secure area to make the secure area enter the key generation trigger state. The sending completion confirmation process includes performing a readback verification on the instruction receiving position or performing a status read on the instruction receiving status register position to indicate that the key generation instruction information has been written.

[0031] S20: When the chip receives the key generation instruction information, it reads the key A information from the chip's secure state machine and the key B information from the preset secure encryption area of ​​the flash memory.

[0032] In this embodiment, the secure state machine refers to a protected logic unit located inside the chip and used to store and output key A information. The preset secure encryption area refers to a preset storage partition located in the flash memory and used to store key B information. Key A information is a unique identifier key built into the chip at the factory and cannot be modified externally. Key B information is exclusive data that corresponds one-to-one with a single device. The main I2C refers to the master control interface inside the chip used to initiate I2C access transactions. The I2C PAD refers to the interface unit inside the chip used to connect the main I2C and the peripheral I2C lines. The read buffer refers to the buffer area on the secure state machine side used to temporarily store the byte sequence of key A information. The write buffer refers to the buffer area on the secure state machine side used to temporarily store the byte sequence of key generation instruction information trigger parameters. The flash memory control interface unit refers to the interface unit inside the chip used to organize read and write transfers between the eMMC or NAND medium and the memory-side cache. The memory-side cache refers to the memory-side read buffer area used to temporarily store the byte sequence of key B information.

[0033] Specifically, after the chip receives the key generation instruction information, it enters the key reading stage according to the read trigger rule corresponding to the key generation instruction information. When reading key A information from the security state machine mapped inside the chip, the reading range is first determined based on the preset reading address and preset reading length of the security state machine. Then, a read channel is established through the on-chip connection from the main I2C to the I2C PAD, and the I2C... The PAD and the secure state machine's register access interface complete read transaction arbitration. Then, it performs a byte-order read operation on the read range to obtain key A information and write it to the read buffer. It then performs a length consistency check on the byte sequence output from the read buffer to confirm that key A information meets the preset length requirement. When reading key B information, it first locates the preset secure encryption area according to the preset partition identifier corresponding to the preset secure encryption area. Then, the flash memory control interface unit reads the data corresponding to key B information from the eMMC or NAND medium side according to the preset start offset and preset read length and writes it to the memory-side cache. Then, it outputs the key B information byte sequence from the memory-side cache in the preset byte order and performs a length consistency check on the key B information byte sequence to confirm that key B information meets the preset length requirement. The key A information reading process can be organized into a DMA read mode and includes a start stage, a read identifier stage, a data stage, and a stop stage in sequence. During the data stage, the key A information byte sequence is continuously output according to the preset read length.

[0034] S30: Perform hash generation processing based on key information A and key information B to obtain key information C.

[0035] In this embodiment, hash generation processing refers to the operation of mapping the input byte sequence to a fixed-length output byte sequence. Key C information refers to the key data obtained by performing hash generation processing based on key A information and key B information, which is used for subsequent solidification and verification. The encryption algorithm engine refers to the cryptographic operation unit inside the chip used to generate the key stream. The key stream refers to the byte stream output by the encryption algorithm engine and subjected to a byte-by-byte XOR operation with the data to be written. The XOR operation unit refers to the operation unit used to perform the byte-by-byte XOR operation. DRAM refers to the dynamic random access memory outside the chip that stores cached data and is used to store the cached byte sequence to be hashed and the cached hash output byte sequence.

[0036] Specifically, during hash generation, key A and key B are input as byte sequences, and the byte sequences corresponding to key A and key B are concatenated according to a preset concatenation order to form a byte sequence to be hashed. Then, a preset hash algorithm is applied to the byte sequence to be hashed to obtain a hash output byte sequence. The preset hash algorithm uses the SHA-256 hash algorithm and performs block compression on the byte sequence to be hashed to output a 256-bit hash output byte sequence. Then, a key field of a preset byte length is extracted from the hash output byte sequence according to a preset truncation rule as key C information. The preset truncation rule is used to limit the starting byte position and truncation byte length of the key field in the hash output byte sequence. When the hash byte sequence is written to DRAM to form a cache, the encryption algorithm engine outputs a key stream, and the XOR operation unit performs byte-by-byte XOR processing on the byte sequence to be written and writes it to the corresponding cache address in DRAM. When reading into hash generation, the byte sequence participating in hash generation is output from the DRAM cache according to the corresponding reading rule.

[0037] S40: Determine whether the first power-on completion marker information has been detected.

[0038] In this embodiment, the first power-on completion marker information refers to the marker data used to characterize that the TV has completed the first power-on initialization process. The first power-on initialization process refers to the process of executing the key solidification writing process and establishing the marker after the writing is completed when the first power-on completion marker information does not exist. The marker storage location refers to the preset storage entry location used to store the first power-on completion marker information and is limited by the storage path or storage file name.

[0039] Specifically, when determining whether the first power-on completion marker information has been detected, the marker storage location is first located according to the preset marker storage location rules. The preset marker storage location rules refer to the conventions made for the storage path or file name of the first power-on completion marker information. Then, an existence detection operation is performed on the marker storage location to determine whether the first power-on completion marker information exists. The existence detection operation refers to the operation of performing an access judgment on the storage entry corresponding to the marker storage location and outputting the existence judgment result. When the existence detection operation indicates that the marker storage location has a corresponding storage entry, the existence judgment result is associated with the marker storage location to form the first power-on completion marker information. When the existence detection operation indicates that the marker storage location does not have a corresponding storage entry, the non-existence judgment result is associated with the marker storage location to form the first power-on completion marker information.

[0040] S50: If the first power-on completion marker information is not detected, the preset independent non-writable area of ​​the flash memory is unlocked, the key C information is written into the preset independent non-writable area, and the preset independent non-writable area is locked.

[0041] In this embodiment, the preset independent non-writable area refers to an independent storage area in the flash memory that is pre-defined for storing key C information. The independent storage area is in a non-writable state by default and is independent of the storage partition corresponding to the preset security encryption area. The interval address information refers to the address data used to characterize the starting address and interval length of the preset independent non-writable area in the flash memory. The unlock operation refers to the control operation that switches the preset independent non-writable area from a non-writable state to a writable state. The lock operation refers to the control operation that switches the preset independent non-writable area from a writable state to a non-writable state. The write protection state refers to the state value that characterizes whether the preset independent non-writable area is allowed to be written to. WP# refers to the write protection pin of the flash memory and is used to control the write protection state. The busy / idle indicator pin refers to the pin state of the flash memory used to characterize the internal write or erase busy state.

[0042] Specifically, if the initial power-on completion marker is not detected, the preset independent non-writable area is first located based on the interval address information corresponding to the preset independent non-writable area, and the write start address and write length are parsed to obtain them. A consistency check is then performed on the write length and the preset byte length corresponding to the key C information to confirm that the write length meets the write requirements. Subsequently, an unlocking operation is performed on the preset independent non-writable area to make it writable. The unlocking operation includes changing the write protection status according to the write protection control rules, submitting a status setting request, and reading the unlocking status information. The unlocking status information is the write protection status data returned by the flash memory and is used to characterize the writable or non-writable state. Finally, a comparison is performed between the unlocking status information and the preset writable status value to determine if unlocking is complete. Upon successful unlocking, the key C information is written byte-wise to a preset independent writable area according to the write start address corresponding to the interval address information, forming a write completion message. The writing process is organized according to the command latch and address latch timing sequence. In the address stage, the column address and row address are latched byte-wise by the preset secure encryption area, and the key C information byte sequence is output in the data stage. After writing, the interval data of the preset independent writable area is read, and a byte-by-byte consistency comparison is performed between the interval data and the key C information to obtain the write verification result information. Here, the interval data refers to the continuous byte sequence data read from the preset independent writable area based on the read start address and read length determined by the interval address information. The read start address is consistent with the write start address, and the read length is consistent with the write length. If the write verification result information indicates consistency, a locking operation is performed to restore the preset independent writable area to a writable state. The locking operation includes setting the write protection state to a writable state, submitting a state setting request, reading the locking state information, and generating locking completion information based on the locking state information. The locking state information is the write protection state data returned by the flash memory and is used to characterize the writable or writable state.

[0043] S60: Upon detecting the first power-on completion marker information, read the solidified key information from the preset independent non-writable area of ​​the flash memory, perform a consistency comparison process between the key C information and the solidified key information, and obtain the startup verification result information.

[0044] In this embodiment, the solidified key information refers to the key data stored in a preset independent non-writable area and used as a startup verification benchmark. The startup verification result information refers to the result data generated based on the consistency comparison result between the key C information and the solidified key information, which is used to characterize whether the startup process is allowed. The page cache refers to the cache area inside the flash memory used to temporarily store page read and write data. The error correction logic refers to the logic unit inside the flash memory that performs verification and error correction on the read path. The I / O buffer refers to the buffer unit inside the flash memory used to output the interval data byte sequence.

[0045] Specifically, upon detecting the completion of the initial power-on marking information, the preset independent non-writable area is located based on the interval address information corresponding to the preset independent non-writable area. Interval data of a preset byte length is read from the preset independent non-writable area according to the read start position and read length corresponding to the interval address information to form solidified key information. The reading process is organized into command, address, and data output stages. In the address stage, the column address and row address are latched in byte order by the preset secure encryption area, and in the data output stage, the interval data byte sequence is output in the preset byte order. The read path can form the interval data byte sequence through page buffering and error correction logic, and be output by the I / O buffer and written to the read buffer. Subsequently, a length consistency check is performed on the key C information and the solidified key information to confirm that their lengths meet the preset length requirements. If the length consistency check indicates consistency, a byte-by-byte consistency comparison is performed on the key C information and the solidified key information according to the preset byte order to obtain the comparison result. The comparison result is then mapped to the start-up verification result information according to the preset result mapping rules. The preset result mapping rules are used to map the comparison result indicating that all bytes are consistent to a consistency marker and to map the comparison result with any inconsistent byte to an inconsistency marker.

[0046] S70: If the startup verification results are consistent, allow the smart TV to enter the startup process; if the startup verification results are inconsistent, prohibit the smart TV from entering the startup process.

[0047] In this embodiment, the startup process refers to the startup execution sequence that the smart TV continues to execute after completing key verification. The startup execution sequence includes the execution process of loading startup components and entering the running state. Allowing the smart TV to enter the startup process means that when the startup verification result information is consistent, the entry restriction on the startup process is lifted so that the startup process can continue to execute. Prohibiting the smart TV from entering the startup process means that when the startup verification result information is inconsistent, the entry restriction on the startup process is maintained to block the startup process from continuing to execute. The preset startup control position refers to the startup control record area used to store the startup allowance state or startup prohibition state. The entry condition refers to the gating condition used to limit whether the startup process is allowed to continue to execute.

[0048] Specifically, after the startup verification result information is generated, the startup verification result information is read and parsed as the basis for startup release judgment, and startup control branch processing is executed according to the value of the startup verification result information. When the startup verification result information is consistent, the startup release status is written to the preset startup control position and the entry condition is processed to remove the entry restriction at the startup entry point, so that the startup process continues to execute according to the predetermined startup execution sequence. When the startup verification result information is inconsistent, the startup prohibition status is written to the preset startup control position and the entry condition is processed to maintain the entry restriction at the startup entry point, so that the startup process is blocked before entering the running state.

[0049] In one embodiment, such as Figure 2 As shown, in step S30, a hash generation process is performed based on key A and key B to obtain key C, including: S301: Read the key A information as the first key byte sequence and read the key B information as the second key byte sequence.

[0050] In this embodiment, the first key byte sequence refers to a continuous byte array obtained by converting key A information according to a preset byte order, and the second key byte sequence refers to a continuous byte array obtained by converting key B information according to a preset byte order. The preset byte order refers to the convention made for the arrangement order of each byte in the byte sequence. The read buffer refers to a buffer area used to temporarily store the read output byte array. The memory-side buffer refers to a buffer area written by the flash memory control interface unit and used to temporarily store the flash memory read data. The DMA read mode refers to a read mode in which the read path control unit organizes continuous read transactions and continuously moves the data stages to the buffer area.

[0051] Specifically, when key A information is read as the first key byte sequence, the reading range is determined according to the preset reading address and preset reading length of the security state machine, and a read transaction path is established through the main I2C and I2C PAD. Then, the read buffer of the security state machine outputs the byte data of key A information in byte order, and writes the output bytes sequentially to the cache address corresponding to the first key byte sequence. After reading, the number of bytes in the first key byte sequence is checked for consistency according to the preset reading length. When key B information is read as the second key byte sequence, the preset security encryption area is located according to the partition positioning rules corresponding to the preset security encryption area of ​​the flash memory, and a partition read transaction is initiated on the eMMC or NAND medium through the flash memory control interface unit to move the key B information to the memory-side cache. Then, bytes are retrieved from the memory-side cache in preset byte order and written to the cache address corresponding to the second key byte sequence. The read transaction can be organized in DMA read mode and includes a start stage, a read identifier stage, a data stage, and a stop stage in sequence. During the data stage, byte data is continuously output according to the preset reading length until the preset reading length is met.

[0052] S302: Perform concatenation processing on the first key byte sequence and the second key byte sequence according to the preset concatenation order to obtain the byte sequence to be hashed.

[0053] In this embodiment, the preset splicing order refers to the convention made on the order of the first key byte sequence and the second key byte sequence in the byte sequence to be hashed. The byte sequence to be hashed refers to a continuous byte array used to input the preset hash algorithm for processing. The splicing process refers to the process of copying the two byte arrays in order to a continuous target array.

[0054] Specifically, during the concatenation process, the correspondence between the first and second concatenation segments is first determined according to the preset concatenation order, and a continuous buffer of preset length is allocated for the byte sequence to be hashed. Then, the first key byte sequence is copied byte-by-byte in order to the starting position corresponding to the first concatenation segment of the byte sequence to be hashed, and the second key byte sequence is copied byte-by-byte in order to the starting position corresponding to the second concatenation segment of the byte sequence to be hashed. During the copying process, the target write offset is calculated based on the index position of each byte in the source byte sequence, and byte-by-byte writing is performed to form the byte sequence to be hashed.

[0055] S303: Perform a preset hash algorithm on the byte sequence to be hashed to obtain a hash output byte sequence.

[0056] In this embodiment, the preset hash algorithm refers to the algorithm rule that maps the input byte sequence to a fixed-length output byte sequence, the hash output byte sequence refers to the fixed-length byte array output by the preset hash algorithm, the block compression operation refers to the operation process of dividing the input according to the preset block length and performing round function updates on each block, DRAM refers to the dynamic random access memory used to store the cache of the byte sequence to be hashed and the cache of the hash output byte sequence, the encryption algorithm engine refers to the cryptographic operation unit used to generate the key stream, the key stream refers to the byte stream output by the encryption algorithm engine, and the XOR operation unit refers to the operation unit used to perform byte-by-byte XOR operation on the byte data and the key stream.

[0057] Specifically, when performing the preset hash algorithm, the byte sequence to be hashed is grouped according to the preset group length and padded and length encoded according to the algorithm rules to form a group data sequence for calculation. Then, the group compression operation is performed on each group in turn to update the intermediate state. After processing the last group, a fixed-length hash output byte sequence is output and written into the output buffer in DRAM according to the preset byte order. When the hash byte sequence is written into DRAM to form a buffer, the encryption algorithm engine can output a key stream and the XOR operation unit can perform byte XOR processing on the byte data to be written and write it into the corresponding buffer address in DRAM. Thus, the byte sequence to be hashed is stored in DRAM as byte data after XOR processing and is output as byte data for hash operation according to the corresponding reading rules when it is read into the preset hash algorithm.

[0058] S304: Extract the key field corresponding to the preset byte length from the hash output byte sequence to obtain the key C information.

[0059] In this embodiment, the preset byte length refers to the convention for the number of bytes of key C information, the preset truncation rule refers to the convention for the starting byte position and the truncation byte length in the hash output byte sequence, the key field refers to the continuous byte segment truncated from the hash output byte sequence, and the key C information refers to the key data corresponding to the key field.

[0060] Specifically, during the extraction process, the starting truncation offset and truncation byte length of the hash output byte sequence are determined according to the preset truncation rules. The preset byte length bytes are then read continuously from the starting truncation offset in the DRAM output buffer according to the preset byte order to form the key field. The key field is then written into the buffer corresponding to the key C information according to the preset byte order and the length consistency confirmation process is completed, thereby obtaining the key C information.

[0061] In one embodiment, such as Figure 3As shown, in step S50, i.e., when no first power-on completion marker information is detected, an unlocking operation is performed on the preset independent writable area of ​​the flash memory, including: S501: Based on the address information of the interval corresponding to the preset independent non-writable area, locate the preset independent non-writable area in the flash memory.

[0062] In this embodiment, positioning refers to the process of determining the column address and row address required for flash memory access based on the interval address information and forming an address register value that can be used for access. The column address refers to the address field corresponding to the page offset, and the row address refers to the address field corresponding to the page number or block page positioning. The address latch enable preset security encryption area refers to the enable signal used to latch the address field during the address phase.

[0063] Specifically, during the location processing, the interval address information is first parsed to obtain the read or write start address, and the start address is split into column address field and row address field according to the flash memory address mapping rules. Then, in the flash memory address stage, the preset security encryption area is made valid and the column address field and row address field are written into the address latch path in the preset byte order to form the located state. The located state includes a combination of column address register value, row address register value and interval length information.

[0064] S502: Perform an unlock control operation on the flash memory to switch the preset independent writable area from a writable state to a writable state.

[0065] In this embodiment, the unlock control operation refers to the control operation that changes the state of the write-protected state to allow writing. WP# refers to the write-protected pin of the flash memory and is used to control the write-protected state. The write enable signal WE# is the control signal used to trigger the write pulse. The chip select signal CE# is the control signal used to enable the flash memory to respond to the access cycle.

[0066] Specifically, when performing the unlock control operation, the chip select signal CE# is made active, and the write protection state corresponding to WP# is changed according to the write protection control rules to enable the writable state. Then, within the control cycle limited by WE#, an unlock control request is submitted to switch the write protection constraint corresponding to the preset independent writable area to a writable constraint. After the control request is submitted, the unlock state confirmation stage is entered.

[0067] S503: Read the unlock status information returned by the flash memory, and determine whether the unlocking of the preset independent writable area is complete based on the unlock status information.

[0068] In this embodiment, the unlock status information refers to the status data returned by the flash memory to indicate whether the write protection state has been switched. The busy / idle indicator pin R / B# is a status pin used to indicate whether the internal operation is busy or idle. Determining whether the unlock is complete refers to the process of comparing the unlock status information with the preset writable status value and outputting a determination conclusion.

[0069] Specifically, when performing the unlock status read, the chip select signal CE# is made valid and a status read transaction is initiated. When R / B# indicates an idle state, the unlock status information is read. Then, the unlock status information is compared with the preset writable status value. When the comparison result indicates that they are consistent, the unlock completion judgment result is output. When the comparison result indicates that they are inconsistent, the unlock failure judgment result is output. The judgment result is then associated with the interval address information and recorded.

[0070] S504: If the unlock status information indicates that unlocking is complete, generate unlock completion information.

[0071] In this embodiment, the unlock completion information refers to the confirmation data used to indicate that the preset independent writable area has been switched to a writable state. The confirmation data is used to record the unlock confirmation mark and the interval address information corresponding to the preset independent writable area.

[0072] In this embodiment, unlock completion information refers to the marker data used to indicate that the preset independent writable area has entered the writable state. Generating unlock completion information refers to the process of writing the unlock completion marker into the preset control record position and establishing a correspondence with the interval address information.

[0073] Specifically, when the unlock status information indicates that unlocking is complete, unlock completion information containing range address information and writable status flag is generated, and the unlock completion information is written to a preset control record location or to a buffer as a prerequisite for subsequent writing of key C information.

[0074] In one embodiment, such as Figure 4 As shown, in step S50, the key C information is written into a preset independent writable area, and a locking operation is performed on the preset independent writable area, including: S505: When the preset independent non-writable area is in a writable state, write the key C information into the preset independent non-writable area according to the interval address information corresponding to the preset independent non-writable area, and obtain the writing completion information.

[0075] In this embodiment, write completion information refers to marker data indicating that the key C information has been written to disk according to the interval address information; command latch enable (CLE) refers to the enable signal used to latch access commands during the command phase; address latch enable preset security encryption zone refers to the enable signal used to latch column addresses and row addresses during the address phase; page programming refers to the write process of writing input data into the page cache and programming it into the storage array; and FCIE refers to the flash memory control interface unit used to organize write operations.

[0076] Specifically, when the preset independent non-writable area is in a writable state, the interval address information is parsed to obtain the write start address and write length, and the FCIE submits the write transaction parameters to start the write process. In the command phase, the write process enables CLE and latches the page programming command. In the address phase, the preset secure encryption area is enabled and the column address and row address are latched in byte order. In the data phase, the key C information is driven to the data line in the preset byte order and written to the page cache. Then, the page cache programs the data to the storage array to complete the write operation. After the write is completed, write completion information containing interval address information, write length and completion mark is generated.

[0077] S506: Based on the write completion information, read the interval data of the preset independent non-writable area, and perform a consistency comparison process between the interval data and the key C information to obtain the write verification result information.

[0078] In this embodiment, the written verification result information refers to the result data used to characterize whether the readback interval data is consistent with the key C information. The consistency comparison processing refers to the process of performing a comparison byte by byte on two equal-length byte sequences according to a preset byte order and outputting the comparison conclusion. The page cache and error correction logic are used to form the interval data byte sequence for readback.

[0079] Specifically, based on the write completion information, the interval address information and readback length are extracted, and an interval data readback transaction is initiated to read the interval data from the preset independent non-writable area. The interval data byte sequence is formed through page caching and error correction logic. The interval data byte sequence and the key C information byte sequence are then compared byte by byte in the preset byte order. The comparison results of each byte are collected to form the write verification result information. When all byte comparison results indicate that they are consistent, a consistency mark is written in the write verification result information. When any byte comparison result indicates that they are inconsistent, an inconsistency mark is written in the write verification result information.

[0080] S507: When the write verification result information is consistent, perform a locking control operation on the flash memory to switch the preset independent non-writable area from a writable state to a non-writable state.

[0081] In this embodiment, the lock control operation refers to the control operation of changing the state of the write-protected state to prevent writing. WP# refers to the flash write protection pin used to control the write protection state, and R / B# refers to the status pin used to indicate the internal busy / idle status.

[0082] Specifically, when the written verification result information is consistent, the chip select signal is made valid, and the write protection state corresponding to WP# is set to non-writable state according to the write protection control rules. Then, a lock control request is submitted within the control cycle to switch the write protection constraint corresponding to the preset independent non-writable area to a non-writable constraint. After submitting the request, the lock state confirmation stage is entered according to the R / B# state switch.

[0083] S508: Reads the lock status information returned by the flash memory and generates lock completion information based on the lock status information.

[0084] In this embodiment, the lock status information refers to the status data returned by the flash memory that indicates whether the write protection state has been switched to the writable state, and the lock completion information refers to the marker data that indicates that the preset independent writable area has entered the writable state.

[0085] Specifically, a status read transaction is initiated, and the lock status information is read when R / B# indicates an idle state. Then, the lock status information is compared with the preset non-writable status value. When the comparison result indicates that they are consistent, lock completion information containing range address information and non-writable status flag is generated. The lock completion information is written to the preset control record position or written to the buffer as the status basis for subsequent start verification and reading of solidified key information.

[0086] In one embodiment, such as Figure 5 As shown, in step S60, i.e., upon detecting the first power-on completion marker information, the hardened key information is read from the preset independent non-writable area of ​​the flash memory, including: S601: Based on the address information of the preset independent non-writable area in the flash memory, read the interval data of the preset byte length from the preset independent non-writable area to obtain the read data.

[0087] In this embodiment, the interval address information refers to the address data used to characterize the starting address and interval length of the preset independent non-writable area; the interval data refers to the byte data read continuously within the address range defined by the interval address information; the page cache refers to the cache area inside the flash memory used to temporarily store page read and write data; the error correction logic refers to the logic unit inside the flash memory used to perform verification and error correction on the read data; the I / O buffer refers to the buffer unit used to output the interval data byte sequence; FCIE refers to the flash memory control interface unit used to organize read and write transfer between the eMMC or NAND medium and the memory-side cache; and the DMA read timing refers to the continuous read timing including the start phase, read flag phase, data phase, and stop phase.

[0088] Specifically, when reading data from a preset independent non-writable area, the starting address and length of the read are first parsed based on the area address information, and then submitted to the FCIE to initiate the read transaction. The read transaction is organized on the NAND media side according to the command phase, address phase, and data phase. In the command phase, the read command is latched through the command latching mechanism. In the address phase, the preset security encryption area is enabled by address latching to latch the column address and row address in byte order and complete the address decoding. Then, the storage array data is read into the page cache, and the error correction logic performs verification and error correction on the output data of the page cache. Then, the I / O buffer outputs the byte sequence of the area data in the preset byte order and the FCIE writes it into the memory-side cache. The read process can be organized according to the DMA read timing and the area data corresponding to the preset byte length is continuously moved in the data phase. After the movement is completed, the byte data is output from the memory-side cache in the preset byte order to form the read data.

[0089] S602: Perform length verification on the read data to obtain the read judgment result information.

[0090] In this embodiment, the length verification process refers to the process of comparing the number of bytes of the read data with the preset byte length and outputting the verification conclusion. The reading judgment result information refers to the result data used to characterize whether the length verification has passed.

[0091] Specifically, when performing length verification, the target byte count is first determined based on the preset byte length, then the actual byte count of the read data is counted, and the actual byte count is compared with the target byte count. When the comparison result is equal, a length verification pass flag is generated and written into the read judgment result information. When the comparison result is not equal, a length verification fail flag is generated and written into the read judgment result information.

[0092] S603: If the reading result information indicates that the verification has passed, the read data will be identified as the solidified key information.

[0093] In this embodiment, the solidified key information refers to the key data stored in a preset independent non-writable area and used as the starting verification benchmark. Determining it as solidified key information means binding the read data to the data object corresponding to the solidified key information and entering the state of subsequent consistency comparison processing.

[0094] Specifically, when the reading result information indicates that the length verification has passed, the read data is written to the cache area or parameter register location corresponding to the solidified key information, and an association record is established between the source identifier of the solidified key information and the interval address information to indicate that the solidified key information comes from the read interval corresponding to the preset independent non-writable area. Then, the solidified key information is used as input data for subsequent consistency comparison processing to participate in the process of starting the verification result information generation.

[0095] In one embodiment, such as Figure 6 As shown, in step S60, a consistency comparison process is performed between the key C information and the solidified key information to obtain the startup verification result information, including: S604: Perform length consistency verification on the key C information and the fixed key information to obtain the length verification result information.

[0096] In this embodiment, the length verification result information refers to the result data used to characterize whether the number of bytes of the key C information is consistent with the number of bytes of the fixed key information.

[0097] Specifically, the number of bytes in the key C information and the number of bytes in the solidified key information are counted, and an equality comparison is performed on the two byte counts. When the comparison results are equal, a consistency flag is written into the length verification result information; when the comparison results are not equal, an inconsistency flag is written into the length verification result information.

[0098] S605: When the length verification result information is consistent, a memory comparison method to prevent timing attacks is adopted. The key C information and the solidified key information are compared byte by byte according to the preset byte order to obtain the comparison result information.

[0099] In this embodiment, the memory comparison method to prevent timing attacks refers to a comparison method that performs the same traversal process on all byte positions during the comparison process and avoids premature termination when the first inconsistent byte is found. The comparison accumulation value refers to the cumulative variable used to collect the differences between each byte.

[0100] Specifically, when the length verification result information indicates that the comparison accumulation value is consistent, the comparison accumulation value is initialized to a preset initial value, and the key C information byte and the solidified key information byte are read sequentially from the start byte position to the end byte position according to the preset byte order. A bitwise XOR operation is performed on each pair of bytes to obtain the difference byte. Then, a bitwise OR operation is performed between the difference byte and the comparison accumulation value to update the comparison accumulation value. After the traversal is completed, the comparison accumulation value is compared with the preset zero value. When the comparison result indicates that it is equal to the zero value, a consistent comparison result is generated and the comparison result information is written. When the comparison result indicates that it is not equal to the zero value, an inconsistent comparison result is generated and the comparison result information is written.

[0101] S606: Generate startup verification result information based on the comparison result information.

[0102] In this embodiment, the startup verification result information refers to the result data used to characterize whether entry into the startup process is allowed, and the preset result mapping rule refers to the rule convention that maps the comparison result information to a consistent mark or an inconsistent mark.

[0103] Specifically, the comparison result information is read and the result mapping process is performed according to the preset result mapping rules. When the comparison result information indicates that the results are consistent, a consistent startup verification result is generated and written into the startup verification result information. When the comparison result information indicates that the results are inconsistent, an inconsistent startup verification result is generated and written into the startup verification result information. The startup verification result information is then written into the result record area corresponding to the preset startup control position.

[0104] In one embodiment, such as Figure 7 As shown, in step S70, if the startup verification result information is consistent, the smart TV is allowed to enter the startup process; if the startup verification result information is inconsistent, the smart TV is prohibited from entering the startup process, including: S701: If the startup verification result information is consistent, a startup permission instruction is generated, and the entry conditions of the startup process are released according to the startup permission instruction information so that the smart TV can continue to execute the startup process.

[0105] In this embodiment, the start-up permission indication information refers to the marker data used to characterize that the start-up entry gate condition is in the allowed entry state, the entry condition refers to the gate condition used to limit whether the start-up process is allowed to continue to be executed, the preset start-up control position refers to the control record position used to store the start-up permission indication information or the start-up prohibition indication information, and the application processor refers to the processing unit used to execute the start-up process and gate judgment processing.

[0106] Specifically, when the startup verification result information is consistent, startup permission indication information containing permission flags and verification result source identifiers is generated, and the startup permission indication information is written to a preset startup control position to form a readable gating basis. Then, the preset startup control position is read and permission flags are parsed at the startup entry point, and the entry condition is processed to switch the entry condition to the allowed entry state, so that the startup process continues to execute according to the startup execution sequence.

[0107] S702: If the startup verification result information is inconsistent, a startup prohibition indication is generated, and the startup process entry condition is blocked according to the startup prohibition indication information to prevent the smart TV from continuing to execute the startup process.

[0108] In this embodiment, the start prohibition indication information refers to the marker data used to characterize that the start entry gate control condition is in a prohibited entry state, and the blocking entry condition refers to the process of switching the entry condition to a prohibited entry state and keeping the start entry in a restricted state.

[0109] Specifically, when the startup verification result information is inconsistent, a startup prohibition indication information containing a prohibition mark and a verification result source identifier is generated, and the startup prohibition indication information is written into a preset startup control position to form a readable gating basis. Then, the preset startup control position is read and the prohibition mark is parsed at the startup entry point, and the entry condition is processed to switch the entry condition to a prohibited entry state, so that the startup process remains blocked and stops continuing to execute before entering the running state.

[0110] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0111] In one embodiment, a television key solidification and startup verification device is provided, which corresponds one-to-one with the television key solidification and startup verification method described in the above embodiment. This television key solidification and startup verification device includes an instruction sending module, a key reading module, a hash generation module, a tag detection module, a solidification writing module, a startup verification module, and a startup control module. Detailed descriptions of each functional module are as follows: Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is used as an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above.

[0112] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A method for solidifying and verifying a television key, characterized in that, The television key solidification and startup verification method includes: Obtain the key generation instruction information and send it to the chip; When the chip receives the key generation instruction information, it reads the key A information from the chip's secure state machine and the key B information from the preset secure encryption area of ​​the flash memory; Based on key A and key B, perform hash generation to obtain key C. Determine whether the first power-on completion marker information has been detected; If the first power-on completion marker is not detected, the preset independent non-writable area of ​​the flash memory is unlocked, the key C information is written into the preset independent non-writable area, and the preset independent non-writable area is locked. Upon detecting the completion of the first power-on marker, the hardened key information is read from the preset independent non-writable area of ​​the flash memory. The key C information is compared with the hardened key information to obtain the startup verification result information. If the startup verification results are consistent, the smart TV is allowed to enter the startup process; if the startup verification results are inconsistent, the smart TV is prohibited from entering the startup process.

2. The television key solidification and startup verification method according to claim 1, characterized in that, The hash generation process based on key A and key B to obtain key C includes: Read the key A information as the first key byte sequence, and read the key B information as the second key byte sequence; The first key byte sequence and the second key byte sequence are concatenated according to a preset concatenation order to obtain the byte sequence to be hashed. The hash byte sequence is processed by a preset hash algorithm to obtain the hash output byte sequence; Extract the key field corresponding to the preset byte length from the hash output byte sequence to obtain the key C information.

3. The television key solidification and startup verification method according to claim 1, characterized in that, The step of unlocking the preset independent writable area of ​​the flash memory when no first power-on completion marker information is detected includes: Based on the interval address information corresponding to the preset independent non-writable area, locate the preset independent non-writable area in the flash memory; Perform an unlock control operation on the flash memory to switch the preset independent non-writable area from a non-writable state to a writable state; Read the unlock status information returned by the flash memory, and determine whether the unlocking of the preset independent non-writable area is complete based on the unlock status information; If the unlock status information indicates that unlocking is complete, an unlock completion message is generated.

4. The television key solidification and startup verification method according to claim 1, characterized in that, The step of writing the key C information into a preset independent non-writable area and performing a locking operation on the preset independent non-writable area includes: When the preset independent non-writable area is in a writable state, the key C information is written into the preset independent non-writable area according to the interval address information corresponding to the preset independent non-writable area, and the writing completion information is obtained. Based on the write completion information, the interval data of the preset independent non-writable area is read, and the interval data is compared with the key C information to obtain the write verification result information. If the write verification result information is consistent, a locking control operation is performed on the flash memory to switch the preset independent non-writable area from a writable state to a non-writable state. Read the lock status information returned by the flash memory, and generate lock completion information based on the lock status information.

5. The television key solidification and startup verification method according to claim 1, characterized in that, The step of reading the hardened key information from a preset independent non-writable area of ​​the flash memory upon detecting the initial power-on completion marker information includes: Based on the address information of the preset independent non-writable area in the flash memory, the data of the preset byte length is read from the preset independent non-writable area to obtain the read data; Perform length verification on the read data to obtain the read determination result information; If the verification result indicates that the verification is successful, the read data will be identified as the solidified key information.

6. The television key solidification and startup verification method according to claim 1, characterized in that, The process of performing a consistency comparison between the key C information and the solidified key information to obtain the startup verification result information includes: Perform a length consistency check on the key C information and the fixed key information to obtain the length check result information; If the length verification results are consistent, a memory comparison method to prevent timing attacks is adopted. The key C information and the solidified key information are compared byte by byte according to the preset byte order to obtain the comparison result information. Startup verification result information is generated based on the comparison results.

7. The television key solidification and startup verification method according to claim 1, characterized in that, The provision that if the startup verification results are consistent, the smart TV is allowed to enter the startup process; if the startup verification results are inconsistent, the smart TV is prohibited from entering the startup process includes: If the startup verification result information is consistent, a startup permission instruction is generated, and the entry conditions for the startup process are released according to the startup permission instruction information, so that the smart TV can continue to execute the startup process; If the startup verification results are inconsistent, a startup prohibition indication is generated, and the startup process is blocked based on the startup prohibition indication to prevent the smart TV from continuing to execute the startup process.

8. A television key solidification and activation verification device, characterized in that, The television key solidification and activation verification device includes: The instruction sending module is used to obtain key generation instruction information and send the key generation instruction information to the chip; The key reading module is used to read key A information from the chip's secure state machine and key B information from the preset secure encryption area of ​​the flash memory when the chip receives key generation instruction information; The hash generation module is used to perform hash generation processing based on key information A and key information B to obtain key information C. The tag detection module is used to determine whether the tagging information for the first power-on completion has been detected; The solidification writing module is used to perform an unlocking operation on the preset independent non-writable area of ​​the flash memory, write the key C information into the preset independent non-writable area, and perform a locking operation on the preset independent non-writable area when the first power-on completion marking information is not detected. The startup verification module is used to read the solidified key information from the preset independent non-writable area of ​​the flash memory when the first power-on completion marking information is detected, and to perform a consistency comparison process between the key C information and the solidified key information to obtain the startup verification result information. The startup control module is used to allow the smart TV to enter the startup process if the startup verification result information is consistent, and to prevent the smart TV from entering the startup process if the startup verification result information is inconsistent.

9. A computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the television key solidification and startup verification method as described in any one of claims 1 to 7.

10. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, it implements the steps of the television key solidification and startup verification method as described in any one of claims 1 to 7.

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