Methods for manufacturing semiconductor devices

Abstract

A method of manufacturing a semiconductor device, the semiconductor device comprising: a first molding structure, the first molding structure including a first insulating layer and a third insulating layer alternately disposed on a substrate; a first channel hole penetrating the first molding structure; and a first sacrificial layer formed in the first channel hole. A second sacrificial layer filling the first channel hole is formed on the first sacrificial layer; a second molding structure including a second insulating layer and a fourth insulating layer alternately disposed on the first molding structure is formed; and a second channel hole penetrating the second molding structure is formed. The first sacrificial layer and the second sacrificial layer in the first channel hole are removed through the second channel hole, and a vertical structure is formed in the first channel hole and the second channel hole. The first sacrificial layer includes a carbon nitride layer, and the second sacrificial layer includes a carbon layer.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices and methods for manufacturing semiconductor devices. Background Technology

[0002] In electronic systems that require data storage, semiconductor devices capable of storing large amounts of data are needed. Therefore, research is underway aimed at increasing the data storage capacity of semiconductor devices. For example, as one method to increase the data storage capacity of semiconductor devices, semiconductor devices incorporating three-dimensionally arranged memory cells rather than two-dimensionally arranged memory cells are being proposed. Summary of the Invention

[0003] In general, this disclosure relates to semiconductor devices with improved yield and reliability, and methods for manufacturing such semiconductor devices.

[0004] According to some embodiments, this disclosure relates to a method of manufacturing a semiconductor device, the method comprising: forming a first molding structure, the first molding structure including a first insulating layer and a third insulating layer alternately disposed on a substrate; forming a first channel hole penetrating the first molding structure; forming a first sacrificial layer in the first channel hole; forming a second sacrificial layer on the first sacrificial layer filling the first channel hole; forming a second molding structure, the second molding structure including a second insulating layer and a fourth insulating layer alternately disposed on the first molding structure; forming a second channel hole penetrating the second molding structure; removing the first sacrificial layer and the second sacrificial layer from the first channel hole through the second channel hole; and forming a vertical structure in the first channel hole and the second channel hole, wherein the first sacrificial layer includes a carbon nitride layer and the second sacrificial layer includes a carbon layer.

[0005] According to some embodiments, this disclosure relates to a method of manufacturing a semiconductor device, the method comprising: forming a first molding structure, the first molding structure including a first insulating layer and a third insulating layer alternately disposed on a substrate; forming a first channel hole penetrating the first molding structure; forming a sacrificial pattern in the first channel hole; forming a second molding structure, the second molding structure including a second insulating layer and a fourth insulating layer alternately disposed on the first molding structure; forming a second channel hole penetrating the second molding structure; removing the sacrificial pattern in the first channel hole through the second channel hole; and forming a vertical structure in the first channel hole and the second channel hole, wherein forming the sacrificial pattern includes a first deposition process supplying a nitrogen source and a carbon source, and a second deposition process supplying the carbon source without supplying the nitrogen source.

[0006] According to some embodiments, this disclosure relates to a semiconductor device, the semiconductor device comprising: a first gate stack structure and a second gate stack structure sequentially disposed on a substrate, the first gate stack structure and the second gate stack structure each comprising alternately stacked electrodes and insulating layers; a vertical structure penetrating the first gate stack structure and the second gate stack structure, the vertical structure each comprising a vertical channel pattern and an information storage layer; and a residual sacrificial layer disposed between the uppermost insulating layer of the vertical structure and the insulating layer of the first gate stack structure, wherein the residual sacrificial layer comprises a carbon nitride layer.

[0007] According to some embodiments, the residual sacrificial layer involved in this disclosure may appear as an annular or partially annular ring around the outer surface of the vertical structure in a top view.

[0008] According to some embodiments, the vertical structure involved in this disclosure may include a stepped portion whose diameter changes discontinuously between the first gate stack structure and the second gate stack structure, and the residual sacrificial layer may be configured to be adjacent to the stepped portion.

[0009] According to some embodiments, the carbon content of the residual sacrificial layer involved in this disclosure can be from about 30 at% to about 70 at, and the nitrogen content of the residual sacrificial layer can be from about 30 at% to about 70 at.

[0010] According to some embodiments, the residual sacrificial layer involved in this disclosure can be an amorphous layer. Attached Figure Description

[0011] The exemplary embodiments can be more clearly understood through the following detailed description taken in conjunction with the accompanying drawings.

[0012] Figure 1 This is a schematic diagram illustrating an example of an electronic system including a semiconductor memory element according to some embodiments.

[0013] Figure 2 This is a perspective view schematically illustrating an example of an electronic system including a semiconductor memory element according to some embodiments.

[0014] Figure 3 and Figure 4 It is along Figure 2 The cross-sectional views taken along line I-I' and line II-II' schematically illustrate examples of semiconductor packages according to some embodiments.

[0015] Figure 5 This is a top view showing an example of a semiconductor memory element according to some embodiments.

[0016] Figure 6It is based on some implementation methods along Figure 5 A cross-sectional view taken from line A-A'.

[0017] Figure 7 It is based on some implementation methods Figure 6 A magnified view of region S.

[0018] Figure 8 This is a process flow diagram illustrating an example of a method for manufacturing a semiconductor device according to some embodiments.

[0019] Figures 9 to 13 , Figure 15 , Figure 16 , Figure 18 and Figure 19 It is along Figure 5 The cross-sectional view taken by line A-A' is used to illustrate an example of a method for manufacturing a semiconductor device according to some embodiments.

[0020] Figure 14 It is based on some implementation methods Figure 13 A magnified view of region Q.

[0021] Figure 17 It is based on some implementation methods Figure 16 A magnified view of region R. Detailed Implementation

[0022] Hereinafter, a three-dimensional semiconductor memory device, a method of manufacturing the same, and an electronic system including the same, according to some embodiments, will be described in detail with reference to the accompanying drawings.

[0023] Figure 1 This is a schematic diagram illustrating examples of electronic systems including three-dimensional semiconductor memory devices according to some embodiments. Figure 1 In this system, electronic system 1000 may include a three-dimensional semiconductor storage device 1100 and a controller 1200 electrically connected to the three-dimensional semiconductor storage device 1100. Electronic system 1000 may be a storage device including one or more three-dimensional semiconductor storage devices 1100, or an electronic device including such a storage device. For example, electronic system 1000 may be a solid-state drive (SSD) device including one or more three-dimensional semiconductor storage devices 1100, a universal serial bus (USB), a computing system, a medical device, or a communication device.

[0024] The three-dimensional semiconductor memory device 1100 may be a non-volatile memory device, and for example, may be a three-dimensional NAND flash memory device, which will be described later. The three-dimensional semiconductor memory device 1100 may include a first region 1100F and a second region 1100S located on the first region 1100F. However, in some embodiments, the first region 1100F may be located adjacent to the second region 1100S. The first region 1100F may be a peripheral circuit region including decoder circuitry 1110, page buffer 1120, and logic circuitry 1130. The second region 1100S may be a memory cell region including bit line BL, common source line CSL, word line WL, first lines LL1 and LL2, second lines UL1 and UL2, and a memory cell string CSTR between bit line BL and common source line CSL.

[0025] In the second region 1100S, each memory cell string CSTR may include first transistors LT1 and LT2 adjacent to the common source line CSL, second transistors UT1 and UT2 adjacent to the bit line BL, and a plurality of memory cell transistors MCTs disposed between the first transistors LT1 and LT2 and the second transistors UT1 and UT2. The number of first transistors LT1 and LT2 and the number of second transistors UT1 and UT2 may vary according to some implementations. The memory cell string CSTR may be located between the common source line CSL and the first region 1100F.

[0026] For example, the second transistors UT1 and UT2 may include string select transistors, and the first transistors LT1 and LT2 may include ground select transistors. First lines LL1 and LL2 may be the gate electrodes of the first transistors LT1 and LT2. Word line WL may be the gate electrode of the memory cell transistor MCT, and second lines UL1 and UL2 may be the gate electrodes of the second transistors UT1 and UT2.

[0027] The common source line CSL, first lines LL1 and LL2, word line WL, and second lines UL1 and UL2 can be electrically connected to the decoder circuit 1110 via a first connection line 1115 extending from the first region 1100F to the second region 1100S. The bit line BL can be electrically connected to the page buffer 1120 via a second connection line 1125 extending from the first region 1100F to the second region 1100S.

[0028] In the first region 1100F, decoder circuit 1110 and page buffer 1120 can perform control operations on at least one selected memory cell transistor among a plurality of memory cell transistors (MCTs). Decoder circuit 1110 and page buffer 1120 can be controlled by logic circuit 1130. The three-dimensional semiconductor memory device 1100 can communicate with controller 1200 via input / output pads 1101 electrically connected to logic circuit 1130. Input / output pads 1101 can be electrically connected to logic circuit 1130 via input / output connection lines 1135 extending from the first region 1100F to the second region 1100S.

[0029] The controller 1200 may include a processor 1210, a NAND controller 1220, and a host interface 1230. According to some embodiments, the electronic system 1000 may include a plurality of three-dimensional semiconductor memory devices 1100, and in this case, the controller 1200 may control the plurality of three-dimensional semiconductor memory devices 1100.

[0030] Processor 1210 can control the overall operation of electronic system 1000, including controller 1200. Processor 1210 can operate according to predetermined firmware and control NAND controller 1220 to access three-dimensional semiconductor memory device 1100. NAND controller 1220 may include NAND interface 1221, which handles communication with three-dimensional semiconductor memory device 1100. Control commands for controlling three-dimensional semiconductor memory device 1100, data to be written to memory cell transistors (MCTs) of three-dimensional semiconductor memory device 1100, data to be read from memory cell transistors (MCTs) of three-dimensional semiconductor memory device 1100, etc., can be transmitted through NAND interface 1221. Host interface 1230 provides communication functionality between electronic system 1000 and external host. When control commands are received from external host through host interface 1230, processor 1210 can control three-dimensional semiconductor memory device 1100 in response to the control commands.

[0031] Figure 2 This is a perspective view schematically illustrating an example of an electronic system including a three-dimensional semiconductor memory device according to some embodiments. Figure 2 In this system, electronic system 2000 may include motherboard 2001, controller 2002 mounted on motherboard 2001, one or more semiconductor packages 2003, and DRAM 2004. Semiconductor packages 2003 and DRAM 2004 may be connected to controller 2002 via wiring pattern 2005 configured to motherboard 2001.

[0032] The motherboard 2001 may include a connector 2006, which includes multiple pins for connection to an external host. The number and arrangement of the multiple pins in the connector 2006 may vary depending on the communication interface between the electronic system 2000 and the external host. For example, the electronic system 2000 may communicate with the external host via any interface such as Universal Serial Bus (USB), Peripheral Component Interconnect High Speed ​​(PCI-express), Serial Advanced Technology Attachment (SATA), and M-Phy for Universal Flash Storage (UFS). For example, the electronic system 2000 may be operated by power supplied from the external host via the connector 2006. The electronic system 2000 may also include a power management integrated circuit (PMIC) that distributes power supplied from the external host to the controller 2002 and the semiconductor package 2003.

[0033] The controller 2002 can write data to or read data from the semiconductor package 2003 and can improve the operating speed of the electronic system 2000.

[0034] DRAM 2004 can be a buffer memory used to mitigate speed differences between an external host and the semiconductor package 2003, which serves as data storage space. DRAM 2004 included in the electronic system 2000 can also function as a cache memory and provide space for temporary data storage during control operations of the semiconductor package 2003. When DRAM 2004 is included in the electronic system 2000, the controller 2002 may include a DRAM controller for controlling DRAM 2004, in addition to a NAND controller for controlling the semiconductor package 2003.

[0035] Semiconductor package 2003 may include a first semiconductor package 2003a and a second semiconductor package 2003b spaced apart from each other. Both the first semiconductor package 2003a and the second semiconductor package 2003b may be semiconductor packages including a plurality of semiconductor chips 2200. Both the first semiconductor package 2003a and the second semiconductor package 2003b may include a package substrate 2100, semiconductor chips 2200 located on the package substrate 2100, adhesive layers 2300 respectively disposed on the lower surface of the semiconductor chips 2200, connection structures 2400 electrically connecting the semiconductor chips 2200 and the package substrate 2100, and a molding layer 2500 located on the package substrate 2100 and covering the semiconductor chips 2200 and the connection structures 2400.

[0036] The package substrate 2100 may be a printed circuit board including package pads 2130. Each semiconductor chip 2200 may include input / output pads 2210. The input / output pads 2210 may each correspond to... Figure 1 The input / output pads 1101. Semiconductor chip 2200 may each include a gate stack structure 3210 and a memory channel structure 3220. Semiconductor chip 2200 may each include a three-dimensional semiconductor memory device, which will be described later.

[0037] The connection structure 2400 may be, for example, a bonding wire that electrically connects the input / output pads 2210 and the on-package pads 2130. Therefore, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other via wire bonding and may be electrically connected to the on-package pads 2130 of the package substrate 2100. According to some embodiments, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other via silicon vias instead of the connection structure 2400 in the wire bonding method.

[0038] In some implementations, the controller 2002 and the semiconductor chip 2200 may be included in a single package. The controller 2002 and the semiconductor chip 2200 may be mounted on a separate interposer substrate, different from the motherboard 2001, and may be interconnected by lines provided to the interposer substrate.

[0039] Figure 3 and Figure 4 It is along Figure 2 The cross-sectional views taken by lines I-I' and II-II' schematically illustrate examples of semiconductor packages according to some embodiments. Figure 3 and Figure 4 In the semiconductor package 2003, the package substrate 2100 may include a package substrate 2100, a plurality of semiconductor chips 2200 located on the package substrate 2100, and a molding layer 2500 covering the package substrate 2100 and the semiconductor chips 2200.

[0040] The packaging substrate 2100 may include a packaging substrate body portion 2120, an upper pad 2130 disposed on or exposed through the upper surface of the packaging substrate body portion 2120, a lower pad 2125 disposed on or exposed through the lower surface of the packaging substrate body portion 2120, and an internal line 2135 electrically connecting the upper pad 2130 and the lower pad 2125 within the packaging substrate body portion 2120. The upper pad 2130 may be electrically connected to the connection structure 2400. The lower pad 2125 may be connected to via a conductive connection portion 2800. Figure 2Wiring pattern 2005 of motherboard 2001 of electronic system 2000 shown.

[0041] exist Figure 2 and Figure 3 In this configuration, one sidewall of each semiconductor chip 2200 may not be aligned with each other, and the other sidewall of each semiconductor chip 2200 may be aligned with each other. The semiconductor chips 2200 may be electrically connected to each other via a connection structure 2400 in the form of bonding leads. Each semiconductor chip 2200 may include substantially the same components.

[0042] Semiconductor chip 2200 may include semiconductor substrate 4010, a first structure 4100 located on semiconductor substrate 4010, and a second structure 4200 located on first structure 4100. The second structure 4200 can be connected to the first structure 4100 by wafer bonding.

[0043] The first structure 4100 may include peripheral circuit lines 4110 and a first bonding pad 4150. The second structure 4200 may include a common source line 4205, a gate stack structure 4210 between the common source line 4205 and the first structure 4100, a memory channel structure 4220 penetrating the gate stack structure 4210, a separator structure 4230, and a word line WL electrically connected to the memory channel structure 4220 and the gate stack structure 4210 (see [link]). Figure 1 The second bonding pad 4250 can be electrically connected to the bit line 4240 of the memory channel structure 4220 and electrically connected to the word line WL (see [link to memory channel structure 4220]). Figure 1 The gate connection line 4235 is electrically connected to the memory channel structure 4220 and the word line WL (see [link]). Figure 1 The first bonding pad 4150 of the first structure 4100 and the second bonding pad 4250 of the second structure 4200 can contact each other and can be connected to each other. The connection portion of the first bonding pad 4150 and the second bonding pad 4250 may, for example, include copper (Cu).

[0044] Each semiconductor chip 2200 may also include input / output pads 2210 and input / output connection lines 4265 located below the input / output pads 2210. The input / output connection lines 4265 may be electrically connected to some second bonding pads 4250 and some peripheral circuit lines 4110.

[0045] Figure 5 This is a top view showing an example of a semiconductor memory element according to some embodiments. Figure 6 It is based on some implementation methods along Figure 5 A cross-sectional view taken from line A-A'. Figure 7 It is based on some implementation methods Figure 6 A magnified view of region S.

[0046] exist Figures 5 to 7 In this design, a peripheral circuit structure PS, including a peripheral transistor PTR, can be disposed on the first substrate 10. A cell array structure CS, including a gate stack structure ST, can be disposed on the peripheral circuit structure PS. The first substrate 10 can be a silicon substrate, a silicon-germanium substrate, a germanium substrate, or a single-crystal epitaxial layer grown on a single-crystal silicon substrate. The first substrate 10 can include an active region defined by a device isolation layer DIL. The peripheral transistor PTR can constitute a decoder circuit, page buffer, logic circuit, etc., as described above.

[0047] The peripheral circuit structure PS may include a lower line INL disposed on the peripheral transistor PTR, and a first interlayer insulating layer 50 covering the peripheral transistor PTR and the lower line INL. A peripheral contact PCNT electrically connecting the lower line INL and the peripheral transistor PTR may be disposed between the lower line INL and the peripheral transistor PTR. The first interlayer insulating layer 50 may include multiple layers of insulating layers stacked together. For example, the first interlayer insulating layer 50 may include a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and / or a low-k layer.

[0048] A cell array structure CS can be provided on the first interlayer insulating layer 50 of the peripheral circuit structure PS. The cell array structure CS will be described in more detail below. A second substrate SL can be provided on the first interlayer insulating layer 50. The second substrate SL can support a gate stack structure ST disposed thereon.

[0049] The second substrate SL may include a lower semiconductor layer LSL, a source semiconductor layer SSL, and a top semiconductor layer USL stacked sequentially. The lower semiconductor layer LSL, the source semiconductor layer SSL, and the top semiconductor layer USL may all comprise a semiconductor material (e.g., at least one of silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), aluminum gallium arsenide (AlGaAs), or mixtures thereof). The lower semiconductor layer LSL, the source semiconductor layer SSL, and the top semiconductor layer USL may all be single-crystal, amorphous, and / or polycrystalline. For example, the lower semiconductor layer LSL, the source semiconductor layer SSL, and the top semiconductor layer USL may all comprise an n-type polycrystalline silicon layer doped with impurities. The lower semiconductor layer LSL, the source semiconductor layer SSL, and the top semiconductor layer USL may have different impurity concentrations than each other. For example, the impurity concentration of the source semiconductor layer SSL may be higher than the impurity concentration of each of the lower semiconductor layer LSL and the top semiconductor layer USL.

[0050] like Figure 5As shown, the second substrate SL may include a cell array region CAR and a connection region CNR. The cell array region CAR may be located at the center of the second substrate SL. The connection region CNR may be located on at least one side of the cell array region CAR. The lower semiconductor layer LSL and the upper semiconductor layer USL may be connected to each other through the source semiconductor layer SSL.

[0051] The gate stack structure ST may include electrodes EL stacked in a direction perpendicular to the second substrate SL (i.e., the third direction D3). For example, the gate stack structure ST may include a first gate stack structure ST1 and a second gate stack structure ST2 located on the first gate stack structure ST1. The following description is based on two gate stack structures, but alternatively, three or more gate stack structures may be provided. The first gate stack structure ST1 may include a first insulating layer IL1, and the stacked first electrodes EL1 are spaced apart from each other by the first insulating layer IL1. The second gate stack structure ST2 may include alternately stacked second insulating layers IL2 and second electrodes EL2. The first insulating layer IL1 and the first electrode EL1 of the first gate stack structure ST1 may be alternately stacked in the third direction D3. The second insulating layer IL2 and the second electrode EL2 of the second gate stack structure ST2 may be alternately stacked in the third direction D3. The first insulating layer IL1 at the uppermost portion of the first gate stack structure ST1 may be thicker than the first insulating layer IL1 below it. The second insulating layer IL2 at the uppermost portion of the second gate stack structure ST2 may be thicker than the second insulating layer IL2 below it. The uppermost first insulating layer IL1 of the first gate stack structure ST1 can contact the lowermost second insulating layer IL2 of the second gate stack structure ST2.

[0052] The gate stack structure ST can extend from the cell array region CAR to the connection region CNR. For example... Figures 2 to 5 As shown, the gate stack structure ST can be in a stepped structure on the connection region CNR. The height of the stepped structure of the gate stack structure ST can decrease as it moves away from the cell array region CAR. In other words, the height of the stepped structure of the gate stack structure ST can decrease from the cell array region CAR along the second direction D2. Due to the stepped structure, the end of each electrode EL can be exposed, and the cell contact plug CC can be connected to the end of each electrode EL.

[0053] In the electrodes EL of the gate stack structure ST, the paired bottom electrode EL can be a reference. Figure 1 The gate electrodes of the first transistors LT1 and LT2 are described, and the paired uppermost electrodes EL can be referenced. Figure 1The gate electrodes of the second transistors UT1 and UT2 are described. Other electrodes EL besides those corresponding to the first transistors LT1 and LT2 and the second transistors UT1 and UT2 can be word lines.

[0054] Electrodes EL may each comprise at least one of a doped semiconductor (e.g., doped silicon), a metal (e.g., tungsten, copper, or aluminum), a conductive metal nitride (e.g., titanium nitride or tantalum nitride), or a transition metal (e.g., titanium or tantalum). The first insulating layer IL1 and the second insulating layer IL2 may both comprise a silicon oxide layer.

[0055] Multiple vertical structures VS with a through-gate stack structure ST can be disposed on the cell array region CAR. For example, reference Figure 5 Four vertical structures VS can be arranged in the first direction D1 to form a first column C1, and five vertical structures VS can be arranged in the first direction D1 to form a second column C2. The first column C1 and the second column C2 can be arranged alternately along the second direction D2. The diameter of each vertical structure VS can gradually decrease as it gets closer to the second substrate SL. In some embodiments, the vertical structure VS may include a stepped portion at the boundary between the first gate stack structure ST1 and the second gate stack structure ST2, where its diameter changes discontinuously.

[0056] A dummy structure DS that penetrates the gate stack structure ST can be provided on the connection region CNR. The dummy structure DS can penetrate the stepped structure of the gate stack structure ST. In a top view, the size (e.g., the maximum diameter) of each dummy structure DS can be larger than the size (e.g., the maximum diameter) of each vertical structure VS.

[0057] Vertical structures VS can be respectively disposed in the channel vias CH of the through-gate stack structure ST. Each vertical structure VS may include an information storage layer FM, a vertical channel pattern SP, and a buried insulating pattern VI. The vertical channel pattern SP can be inserted between the information storage layer FM and the buried insulating pattern VI. A conductive pad PAD can be provided on the upper part of each vertical structure VS. The vertical channel pattern SP can be spaced apart from the electrode EL by the information storage layer FM located therebetween.

[0058] The information storage layer FM may include a barrier insulating layer, a charge storage layer, and a tunneling insulating layer sequentially stacked on the sidewalls of the channel via CH. The barrier insulating layer may be adjacent to the stacked structure or the second substrate SL, and the tunneling insulating layer may be adjacent to the vertical channel pattern SP. The charge storage layer may be inserted between the barrier insulating layer and the tunneling insulating layer. The barrier insulating layer, the charge storage layer, and the tunneling insulating layer may extend in a third direction D3 between the stacked structure ST and the vertical channel pattern SP. Due to the Fowler-Nordheim tunneling phenomenon caused by the voltage difference between the electrode EL and the vertical channel pattern SP, the data storage pattern may store and / or modify data. For example, the barrier insulating layer and the tunneling insulating layer may include silicon oxide, and the charge storage layer may include silicon nitride or silicon oxynitride.

[0059] Vertical channel patterns (SPs) can include semiconductor materials such as silicon (Si), germanium (Ge), or mixtures thereof. Furthermore, vertical channel patterns (SPs) can be doped semiconductors or intrinsic semiconductors without doping. For example, vertical channel patterns (SPs) can include polycrystalline silicon. In some embodiments, vertical channel patterns (SPs) can include oxide semiconductors such as IGZO. Vertical channel patterns (SPs) comprising semiconductor materials can be used as channels for transistors constituting NAND cell strings.

[0060] The conductive pad PAD can cover the upper surface of the vertical channel pattern SP and the upper surface of the buried insulating pattern VI. The conductive pad PAD can include doped semiconductor material and / or metallic material. The first contact plug CT1 can be electrically connected to the vertical channel pattern SP through the conductive pad PAD.

[0061] The source semiconductor layer SSL can directly contact the lower part of each vertical channel pattern SP. The source semiconductor layer SSL can electrically connect multiple vertical channel patterns SP located on the cell array region CAR to each other. In other words, the vertical channel patterns SP of the vertical structure VS can be electrically connected to the source semiconductor layer SSL. A common source voltage can be applied to the source semiconductor layer SSL. The source semiconductor layer SSL can extend horizontally and penetrate the lower part of the information storage layer FM to contact the vertical channel patterns SP. That is, the lower part of the information storage layer FM can be separated from the upper part by the source semiconductor layer SSL located therebetween. The buried insulating pattern VI can include silicon oxide and / or silicon oxynitride.

[0062] The dummy structure DS may include an information storage layer FM, a vertical channel pattern SP, and a buried insulating pattern VI, as previously described for the vertical structure VS. Unlike the vertical structure VS, the dummy structure DS may not serve as a channel for the memory cell. The dummy structure DS may not be electrically connected to the bit line BL, which will be described later. That is, the dummy structure DS can be dummy and has no function in the circuit. The dummy structure DS can serve as a pillar (i.e., a support) for the stepped structure of the physical support gate stack structure ST.

[0063] Multiple partition structures SS can be provided, penetrating the gate stack structure ST. The partition structures SS can be disposed in trenches TR penetrating the gate stack structure ST. The trenches TR can expose the upper surface of the underlying semiconductor layer LSL. The partition structures SS can extend parallel to each other in a second direction D2. In a top view, the partition structures SS can all be stripes or lines extending in the second direction D2. For example, the first partition structure SS1 can all extend from the cell array region CAR to the connection region CNR, and one electrode EL can be horizontally divided into multiple electrodes EL. The first partition structure SS1 can extend between the gate stack structures ST and define the gate stack structure ST. For example, as... Figure 5 As shown, the first separation structure SS1 can extend between the gate stack structures ST.

[0064] For example, a second separator structure SS2 can be disposed in the connection region CNR and can be in the form of strips separated from each other in the second direction D2. The second separator structure SS2 can be disposed in each gate stack structure ST. The separator structure SS can include an insulating material such as silicon oxide.

[0065] A second interlayer insulating layer 161, a third interlayer insulating layer 162, and a bit line BL can be sequentially disposed on the gate stack structure ST. A first contact plug CT1 and a second contact plug CT2 connecting to the vertical structure VS can be disposed in the second interlayer insulating layer 161. A passage VA connecting the first contact plug CT1 and the bit line BL can be disposed in the third interlayer insulating layer 162. The second interlayer insulating layer 161 and the third interlayer insulating layer 162 may include silicon oxide. The bit line BL can extend parallel to each other in a first direction D1. Multiple upper lines can be disposed on the cell contact plug CC. In some embodiments, the bit line BL and the upper lines can be electrically connected to the lower line INL of the peripheral circuit structure PS through through-contacts.

[0066] A residual sacrificial layer SC1r may be disposed between the uppermost insulating layer of the first insulating layer IL1 in the vertical structure VS and the first gate stack structure ST1. The residual sacrificial layer SC1r may be disposed adjacent to the interface between the gate stack structures. For example, the residual sacrificial layer SC1r may be disposed on the uppermost first insulating layer IL1 defining the inner wall of the first channel hole CH1 at the location where the uppermost first insulating layer IL1 of the first gate stack structure ST1 connects with the lowermost second insulating layer IL2 of the second gate stack structure ST2. When the second gate stack structure ST2 is the highest gate stack structure, the residual sacrificial layer SC1r may not be disposed in the second gate stack structure ST2.

[0067] When a third gate stack structure is provided on the second gate stack structure ST2, the residual sacrificial layer SC1r may be additionally provided between the second gate stack structure ST2 and the third gate stack structure and adjacent to both the second gate stack structure ST2 and the third gate stack structure. In this case, the residual sacrificial layer may not be provided in the third gate stack structure, which is the highest structure, and the residual sacrificial layer SC1r may be provided only in the second gate stack structure ST2 and the first gate stack structure ST1.

[0068] The interface between the uppermost first insulating layer IL1 of the first gate stack structure ST1 and the lowermost second insulating layer IL2 of the second gate stack structure ST2 can be observed, but alternatively, it may not be observed.

[0069] The location of the residual sacrificial layer SC1r can be described based on the cross-sectional shape of the vertical structure VS. The vertical structure VS may include stepped portions adjacent to the interface between the gate stack structure and whose diameters change discontinuously, and as... Figure 7 As shown, the residual sacrificial layer SC1r can be disposed on the outer wall of the stepped portion. In the top view, the residual sacrificial layer SC1r can be annular or partially annular along the outer surface of the vertical structure VS.

[0070] exist Figure 6 In this configuration, the gate stack structure ST is disposed between the bit line BL and the peripheral circuit structure PS. However, in some embodiments, the bit line BL and the top line can be disposed between the gate stack structure ST and the peripheral circuit structure PS. In this case, the connection between the peripheral circuit structure PS and the cell array structure CS can have a reference... Figure 3 and Figure 4 The form of the description.

[0071] Figure 8 This is a process flow diagram illustrating an example of a method for manufacturing a semiconductor device according to some embodiments. Figures 9 to 13 , Figure 15 , Figure 16 , Figure 18 and Figure 19 It is along Figure 5 The cross-sectional view taken by line A-A' is used to illustrate an example of a method for manufacturing a semiconductor device according to some embodiments. Figure 14 It is based on some implementation methods Figure 13 A magnified view of region Q. Figure 17 It is based on some implementation methods Figure 16 A magnified view of region R.

[0072] exist Figure 8 and Figure 9 In this process, a peripheral circuit structure PS can be formed on the first substrate 10. Forming the peripheral circuit structure PS may include forming a peripheral transistor PTR on the first substrate 10 and forming a lower line INL on the peripheral transistor PTR. For example, forming the peripheral transistor PTR may include forming a device isolation layer DIL defining an active region on the first substrate 10, forming a gate insulating layer and a gate electrode on the active region, and forming a source / drain region by implanting impurities into the active region. A first interlayer insulating layer 50 covering the peripheral transistor PTR and the lower line INL may be formed.

[0073] A lower semiconductor layer LSL may be formed on the first interlayer insulating layer 50. For example, the lower semiconductor layer LSL may include a semiconductor material such as polysilicon. An insulating structure LIL may be formed on the lower semiconductor layer LSL. Forming the insulating structure LIL may include sequentially forming a lower insulating layer IL3, a lower sacrificial layer LHL, and an upper insulating layer IL4 on the lower semiconductor layer LSL. The lower insulating layer IL3 and the upper insulating layer IL4 may include silicon oxide layers, and the lower sacrificial layer LHL may include a silicon nitride layer or a silicon oxynitride layer.

[0074] An upper semiconductor layer (USL) can be conformally formed on the insulating structure (LIL). For example, the upper semiconductor layer (USL) may include a semiconductor material such as polycrystalline silicon.

[0075] A first molded structure MO1 (S1) can be formed on the upper semiconductor layer USL. Specifically, the first molded structure MO1 can be formed by alternately stacking a first insulating layer IL1 and a third insulating layer HL1 on the upper semiconductor layer USL. The first insulating layer IL1 can be formed on the uppermost portion of the first molded structure MO1. The first insulating layer IL1 and the third insulating layer HL1 can be deposited using a thermal chemical vapor deposition (thermal CVD) process, a plasma-enhanced chemical vapor deposition (plasma-enhanced CVD) process, a physical chemical vapor deposition (physical CVD) process, or an atomic layer deposition (ALD) process. The first insulating layer IL1 may include a silicon oxide layer, and the third insulating layer HL1 may include a silicon nitride layer or a silicon oxynitride layer.

[0076] exist Figure 8 and Figure 10 In this process, a first channel hole CH1 (S2) penetrating the first molding structure MO1 can be formed. In an embodiment, a first channel hole CH1 extending into the first molding structure MO1 can be formed. The lower portion of the first channel hole CH1 can penetrate the insulating structure LIL. The first channel hole CH1 can be formed by an anisotropic etching process. The anisotropic etching process can include plasma etching, reactive ion etching (RIE), inductively coupled plasma reactive ion etching (ICP-RIE), or ion beam etching (IBE). The lower portion of the first channel hole CH1 can be formed in the lower semiconductor layer LSL.

[0077] exist Figure 8 and Figure 11 In the process, a first sacrificial layer SC1 (S3) can be formed in the first channel hole CH1. The first sacrificial layer SC1 can be formed conformally along the inner sidewall of the first channel hole CH1 and the upper surface of the uppermost first insulating layer IL1. The first sacrificial layer SC1 can be formed by chemical vapor deposition (e.g., plasma-enhanced chemical vapor deposition (PECVD)). The first deposition process for forming the first sacrificial layer SC1 can include supplying a carbon source and a nitrogen source. The carbon source used to form the first sacrificial layer SC1 can include acetylene (C2H2) gas. The nitrogen source used to form the first sacrificial layer SC1 can include ammonia (NH3) gas and / or nitrogen (N2) gas. The first deposition process for forming the first sacrificial layer SC1 can include supplying an inert gas such as argon (Ar).

[0078] The first sacrificial layer SC1 may include a carbon nitride layer. The first sacrificial layer SC1 may include a CxNy layer (x and y are constants). The atomic ratio of nitrogen to carbon in the first sacrificial layer SC1 (based on the atomic percentage (at%) of the constituent components) may be from about 0.7 to about 1.3. The carbon content of the first sacrificial layer SC1 may be from about 30 at% to about 70 at%. The nitrogen content of the first sacrificial layer SC1 may be from about 30 at% to about 70 at%. If diffusion or impurities in adjacent layers are excluded, the first sacrificial layer SC1 may not include silicon.

[0079] exist Figure 8 and Figure 12In this process, a second sacrificial layer SC2 (S4) can be formed on the first sacrificial layer SC1 to fill the first channel hole CH1. The second sacrificial layer SC2 can fill the remaining space of the first channel hole CH1 on which the first sacrificial layer SC1 is formed. The second sacrificial layer SC2 can be formed by chemical vapor deposition (e.g., plasma-enhanced chemical vapor deposition (PECVD)). The second deposition process for forming the second sacrificial layer SC2 and the first deposition process for forming the first sacrificial layer SC1 can be performed continuously in the same process chamber. The second deposition process may include supplying a carbon source, but may not include supplying a nitrogen source. The carbon source for forming the second sacrificial layer SC2 may include acetylene (C2H2) gas. The second deposition process for forming the second sacrificial layer SC2 may include supplying hydrogen (H2) gas. The second deposition process for forming the second sacrificial layer SC2 may include supplying an inert gas such as argon (Ar).

[0080] The second sacrificial layer SC2 may include a carbon layer. The carbon content of the second sacrificial layer SC2 may be about 90 at% or more. The nitrogen content of the second sacrificial layer SC2 may be less than about 5 at%. If diffusion or impurities in adjacent layers are excluded, the second sacrificial layer SC2 may not include silicon.

[0081] The first deposition process for forming the first sacrificial layer SC1 can be performed at a first pressure, and the second deposition process for forming the second sacrificial layer SC2 can be performed at a second pressure higher than the first pressure. The first deposition process for forming the first sacrificial layer SC1 can be performed at a first RF power, and the second deposition process for forming the second sacrificial layer SC2 can be performed at a second RF power greater than the first RF power. The first deposition process and the second deposition process can be performed at substantially the same temperature.

[0082] exist Figure 13 and Figure 14 In this process, a planarization process can be performed until the upper surface of the uppermost first insulating layer IL1 is exposed. As a result, the first sacrificial layer SC1 and the second sacrificial layer SC2 can become independent sacrificial patterns SC within the first channel hole CH1. The planarization process may include chemical mechanical polishing. Both the first sacrificial layer SC1 and the second sacrificial layer SC2 constituting the sacrificial pattern SC can be amorphous layers. The thickness d2 of the second sacrificial layer SC2 can be approximately five to approximately fifteen times the thickness d1 of the first sacrificial layer SC1. For example, the first thickness d1 can be approximately 3 nm to approximately 15 nm. The second thickness d2 can be approximately 15 nm to approximately 150 nm.

[0083] Compared to the second sacrificial layer SC2, the first sacrificial layer SC1 exhibits superior adhesion to the first molded structure MO1 (particularly the first insulating layer IL1 constituting the first molded structure MO1). This can be attributed to the relatively high nitrogen concentration of the first sacrificial layer SC1. Furthermore, due to the relatively high nitrogen concentration, the first sacrificial layer SC1 also exhibits excellent adhesion to the second sacrificial layer SC2.

[0084] Before forming the second molded structure, which will be described later, a wet etching process can be performed on the first molded structure MO1, on which the sacrificial pattern SC is formed. For example, the wet etching process can be part of a planarization process or a process for forming alignment marks. Buffered oxide etch (BOE) solution or phosphoric acid solution can be used in the wet etching process. This etching material of the wet etching process can penetrate into the first molded structure MO1 through the upper part (more specifically, through the interface between the first molded structure MO1 and the sacrificial pattern SC). Therefore, due to the wet etching material, partial loss of the third insulating layer HL1 may occur.

[0085] According to some embodiments, since the sacrificial pattern SC includes a first sacrificial layer SC1 that has excellent adhesion to the first insulating layer IL1, the loss of the third insulating layer HL1 can be prevented, thereby improving the yield and reliability of the semiconductor device.

[0086] exist Figure 8 and Figure 15 In this process, a second molding structure MO2 can be formed on the first molding structure MO1 (S5). The second molding structure MO2 can be formed by alternately depositing a second insulating layer IL2 and a fourth insulating layer HL2. The second insulating layer IL2 may include the same material as the first insulating layer IL1. The fourth insulating layer HL2 may include the same material as the third insulating layer HL1. The uppermost second insulating layer IL2 may be formed to be thicker than the second insulating layer IL2 below it.

[0087] A second channel hole CH2 (S6) can be formed that penetrates the second molding structure MO2. In an embodiment, a second channel hole CH2 extending to the second molding structure MO2 can be formed. The second channel hole CH2 can expose the upper surface of the sacrificial pattern SC. Hereinafter, the structure in which the first channel hole CH1 and the second channel hole CH2 are connected is referred to as the channel hole CH.

[0088] exist Figure 8 , Figure 16 and Figure 17In this process, the sacrificial pattern SC can be selectively removed via the second channel hole CH2 (S7). The selective removal of the sacrificial pattern SC can be performed using an etchant including hydrofluoric acid. When the sacrificial pattern SC is selectively removed, a portion of the first sacrificial layer SC1 may not be removed and may remain above the first channel hole CH1. That is, a residual sacrificial layer SC1r can be formed at a portion of the channel hole CH. The residual sacrificial layer SC1r can be positioned adjacent to the interface between the first molding structure MO1 and the second molding structure MO2. For example... Figure 17 As shown, the residual sacrificial layer SC1r can remain in a part of the stepped portion, which is the part where the first channel hole CH1 and the second channel hole CH2 are connected, that is, the stepped portion where the diameter of the channel hole CH changes discontinuously.

[0089] exist Figure 8 and Figure 18 In this process, a vertical structure VS (S8) can be formed in the channel hole CH. Forming the vertical structure VS may include forming an information storage layer FM, a vertical channel pattern SP, and a buried insulation pattern VI that sequentially cover the inner wall of the channel hole CH, and forming a conductive pad PAD thereon.

[0090] exist Figure 19 In this process, a groove TR can be formed that penetrates both the second molding structure MO2 and the first molding structure MO1. The groove TR can extend along the second direction D2 to correspond to the reference... Figure 5 The shape of the partition structure SS is described. The lower part of the trench TR may expose the lower sacrificial layer LHL. Forming the trench TR may include anisotropic etching processes.

[0091] The lower sacrificial layer LHL exposed by the trench TR can be replaced by the source semiconductor layer SSL. Specifically, the lower sacrificial layer LHL can be selectively removed due to the trench TR. As the lower sacrificial layer LHL is removed, the lower portion of the information storage layer FM can be exposed. An undercut region can be formed by removing the exposed lower portion of the information storage layer FM. The undercut region can expose the lower portion of the vertical channel pattern SP. During the removal of the lower portion of the information storage layer FM, the lower insulating layer IL3 and the upper insulating layer IL4 can be removed together. The source semiconductor layer SSL can be formed in the space where the insulating structure LIL is removed. The source semiconductor layer SSL can contact the vertical channel pattern SP.

[0092] A gate stack structure ST can be formed by replacing the third insulating layer HL1 and the fourth insulating layer HL2 exposed by the trench TR with electrodes EL, respectively. Specifically, the third insulating layer HL1 and the fourth insulating layer HL2 exposed by the trench TR can be selectively removed. Electrodes EL can be formed in the spaces where the third insulating layer HL1 and the fourth insulating layer HL2 are removed. That is, the third insulating layer HL1 can be replaced with a first electrode EL1, and the fourth insulating layer HL2 can be replaced with a second electrode EL2. A separator structure SS can be formed in the trench TR by filling the trench TR with an insulating material. The separator structure SS may include silicon oxide.

[0093] exist Figures 5 to 7 In this process, a second interlayer insulating layer 161 and a first contact plug CT1 and a second contact plug CT2 penetrating the second interlayer insulating layer 161 can be formed on the separator structure SS. A third interlayer insulating layer 162 and a passage VA penetrating the third interlayer insulating layer 162 can be formed on the second interlayer insulating layer 161. Subsequently, a bit line BL can be formed on the third interlayer insulating layer 162. A wiring layer can be formed on the bit line BL.

[0094] According to some implementations, the sacrificial pattern of the first sacrificial layer, which has relatively high adhesion to the molded structure, can prevent partial loss of the molded structure due to the wet etching process.

[0095] According to some implementation methods, semiconductor devices with improved yield and reliability can be provided.

[0096] While this disclosure contains numerous specific implementation details, these details should not be construed as limiting the scope of protection that may be claimed, or its equivalents, or the claims described later. Certain features described in the context of individual embodiments in this disclosure may also be implemented in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually in multiple embodiments or in any suitable sub-combination. Furthermore, although features may be described above as functioning in certain combinations, one or more features from a combination may be removed from the combination in certain circumstances, and combinations may involve sub-combinations or variations thereof.

Claims

1. A method for manufacturing a semiconductor device, the method comprising: A first molding structure is formed, the first molding structure including a plurality of first insulating layers and a plurality of third insulating layers, wherein the plurality of first insulating layers and the plurality of third insulating layers are alternately disposed on a substrate; Forming a plurality of first channel holes extending into the first molded structure; A first sacrificial layer is formed in the plurality of first channel holes; A second sacrificial layer is formed on the first sacrificial layer to fill the plurality of first channel holes; A second molding structure is formed, the second molding structure including a plurality of second insulating layers and a plurality of fourth insulating layers, wherein the plurality of second insulating layers and the plurality of fourth insulating layers are alternately disposed on the first molding structure; Forming a plurality of second channel holes extending into the second molded structure; The first sacrificial layer and the second sacrificial layer in the plurality of first trench holes are removed through the plurality of second trench holes; and A vertical structure is formed in the plurality of first channel holes and the plurality of second channel holes. Wherein, the first sacrificial layer includes a carbon nitride layer, and The second sacrificial layer includes a carbon layer.

2. The method according to claim 1, wherein, The atomic ratio of nitrogen to carbon in the first sacrificial layer is 0.7 to 1.

3.

3. The method according to claim 1, wherein, The carbon content of the second sacrificial layer is 90 at% or more.

4. The method according to claim 1, in, The carbon content of the first sacrificial layer is 30 at% to 70 at%. The nitrogen content of the first sacrificial layer is 30 at% to 70 at%, and Wherein, the sum of the carbon content and the nitrogen content is 100 at% or less.

5. The method according to claim 1, wherein, The first sacrificial layer and the second sacrificial layer comprise amorphous layers.

6. The method according to claim 1, wherein, The thickness of the second sacrificial layer is five to fifteen times the thickness of the first sacrificial layer.

7. The method according to claim 1, wherein, The first sacrificial layer and the second sacrificial layer are formed continuously in the same process chamber.

8. The method according to claim 1, wherein, The first sacrificial layer and the second sacrificial layer are formed in a plasma-enhanced chemical vapor deposition process.

9. The method according to claim 1, wherein, Forming the first sacrificial layer and forming the second sacrificial layer includes supplying a carbon source comprising C2H2 to the process chamber.

10. The method according to claim 9, wherein, Forming the first sacrificial layer includes supplying the process chamber with a nitrogen source comprising NH3 and / or N2, while forming the second sacrificial layer does not include supplying the process chamber with the nitrogen source comprising NH3 and / or N2.

11. The method according to claim 1, in, Forming the first sacrificial layer includes performing a first deposition process under a first pressure, and The formation of the second sacrificial layer includes performing a second deposition process at a second pressure higher than the first pressure.

12. The method according to claim 1, in, Forming the first sacrificial layer includes performing a first deposition process at a first RF power, and The formation of the second sacrificial layer includes performing a second deposition process at a second RF power greater than the first RF power.

13. The method of claim 1, further comprising performing a planarization process after forming the second sacrificial layer and before forming the second molded structure.

14. A method for manufacturing a semiconductor device, the method comprising: A first molding structure is formed, the first molding structure including a plurality of first insulating layers and a plurality of third insulating layers, wherein the plurality of first insulating layers and the plurality of third insulating layers are alternately disposed on a substrate; Forming a plurality of first channel holes extending into the first molded structure; Multiple sacrificial patterns are formed in the plurality of first channel holes respectively; A second molding structure is formed, the second molding structure including a plurality of second insulating layers and a plurality of fourth insulating layers, wherein the plurality of second insulating layers and the plurality of fourth insulating layers are alternately disposed on the first molding structure; Forming a plurality of second channel holes extending into the second molded structure; The plurality of sacrificial patterns in the plurality of first channels are removed through the plurality of second channel holes; and A vertical structure is formed in the plurality of first channel holes and the plurality of second channel holes. The formation of the plurality of sacrificial patterns includes: performing a first deposition process, the first deposition process including supplying a nitrogen source and a carbon source; and performing a second deposition process, the second deposition process including supplying the carbon source but not the nitrogen source.

15. The method according to claim 14, in, Performing the first deposition process includes forming a first sacrificial layer. The second deposition process includes forming a second sacrificial layer, and The second sacrificial layer is thicker than the first sacrificial layer.

16. The method according to claim 15, wherein, The atomic ratio of nitrogen to carbon in the first sacrificial layer is 0.7 to 1.

3.

17. The method according to claim 15, wherein, The carbon content of the second sacrificial layer is 90 at% or more.

18. The method according to claim 15, in, The carbon content of the first sacrificial layer is 30 at% to 70 at%. The nitrogen content of the first sacrificial layer is 30 at% to 70 at%, and Wherein, the sum of the carbon content and the nitrogen content is 100 at% or less.

19. The method according to claim 15, wherein, The first sacrificial layer and the second sacrificial layer are formed continuously in the same process chamber.

20. The method of claim 15, wherein, The first sacrificial layer and the second sacrificial layer comprise amorphous layers.

Images