Semiconductor device

Abstract

This invention relates to a semiconductor device. According to one embodiment, the semiconductor device includes a multilayer film comprising a plurality of electrode layers and a plurality of insulating layers alternately deposited along a first direction. Furthermore, the device includes a charge storage layer and a columnar portion of a first semiconductor layer extending along the first direction within the multilayer film. Furthermore, the device includes a second semiconductor layer or a first insulating film disposed on the multilayer film and the columnar portion, containing impurity atoms identical to those contained in the first semiconductor layer, and having a concentration slope of the impurity atoms in the first direction.

Description

[0001] Information related to divisional application

[0002] This case is a divisional application. The parent application of this divisional application is the invention patent application filed on January 22, 2021, with application number 202110086742.0 and title "Semiconductor Device and Method of Manufacturing Thereof".

[0003] Citation of relevant applications

[0004] This application is based on and seeks the priority interest of prior Japanese Patent Application No. 2020-117284, filed on July 7, 2020, the entire contents of which are incorporated herein by reference. Technical Field

[0005] Embodiments of the present invention relate to a semiconductor device and a method for manufacturing the same. Background Technology

[0006] In the case of semiconductor devices containing impurity atoms, it is desirable to optimize the impact of impurity atoms on the performance of the semiconductor device. Summary of the Invention

[0007] According to one embodiment, a semiconductor device includes a multilayer film comprising a plurality of electrode layers and a plurality of insulating layers alternately deposited along a first direction. Furthermore, the device includes a charge storage layer and a columnar portion of a first semiconductor layer extending along the first direction within the multilayer film. Furthermore, the device includes a second semiconductor layer or a first insulating film disposed on the multilayer film and the columnar portion, the second semiconductor layer or the first insulating film containing the same impurity atoms as those contained in the first semiconductor layer, and having a concentration slope of the impurity atoms in the first direction. Attached Figure Description

[0008] Figure 1 This is a cross-sectional view showing the structure of the semiconductor device according to the first embodiment.

[0009] Figure 2 This is an enlarged cross-sectional view showing the structure of the semiconductor device according to the first embodiment.

[0010] Figure 3 (a), (b) Figure 4 (a), (b) Figure 5 (a), (b) Figure 6 (a), (b) Figure 7 (a) and (b) are cross-sectional views showing the manufacturing method of the semiconductor device according to the first embodiment.

[0011] Figure 8(a) to (c) are cross-sectional views showing details of the manufacturing method of the semiconductor device according to the first embodiment.

[0012] Figure 9 (a) and (b) are graphs illustrating the phosphorus atom concentration in the semiconductor device of the first embodiment.

[0013] Figure 10 (a) and (b) are cross-sectional views showing a method for manufacturing a semiconductor device according to a variation of the first embodiment.

[0014] Figure 11 This is a cross-sectional view showing the structure of the semiconductor device according to the second embodiment.

[0015] Figure 12 This is an enlarged cross-sectional view showing the structure of the semiconductor device according to the second embodiment.

[0016] Figure 13 (a), (b) Figure 14 (a), (b) Figure 15 (a), (b) Figure 16 (a), (b) Figure 17 (a), (b) Figure 18 (a), (b) Figure 19 (a), (b) Figure 20 (a), (b) Figure 21 (a) and (b) are cross-sectional views showing the manufacturing method of the semiconductor device according to the second embodiment.

[0017] Figure 22 It is a graph used to illustrate the concentration of phosphorus atoms contained in the semiconductor layer of the second embodiment.

[0018] Figure 23 This is a cross-sectional view showing the structure of the semiconductor device according to the third embodiment.

[0019] Figure 24 (a) and (b) are cross-sectional views showing the manufacturing method of the semiconductor device according to the third embodiment.

[0020] Figure 25 This is a cross-sectional view showing the structure of a semiconductor device according to a variation of the first embodiment. Detailed Implementation

[0021] The embodiments will now be described with reference to the accompanying drawings. Figures 1 to 25 In the text, identical components are marked with the same symbol, and repeated descriptions are omitted.

[0022] (First Embodiment)

[0023] Figure 1This is a cross-sectional view showing the structure of the semiconductor device according to the first embodiment. Figure 1 Semiconductor devices, for example, are three-dimensional flash memory.

[0024] Figure 1 The semiconductor device includes a circuit region 1 containing CMOS (Complementary Metal Oxide Semiconductor) circuitry and an array region 2 containing a memory cell array. The memory cell array has multiple memory cells for storing data, and the CMOS circuitry includes peripheral circuitry for controlling the operation of the memory cell array. For example, as described below, Figure 1 The semiconductor device is manufactured by bonding a circuit wafer containing circuit region 1 to an array wafer containing array region 2. The symbol S represents the bonding surface between circuit region 1 and array region 2.

[0025] Figure 1 The X, Y, and Z directions are drawn perpendicularly. In this specification, the +Z direction is considered the upward direction, and the -Z direction is considered the downward direction. For example, CMOS region 1 is drawn along the -Z direction of array region 2, and therefore is located below array region 2. Furthermore, the -Z direction may or may not align with the direction of gravity. The Z direction is an example of the first direction.

[0026] like Figure 1 As shown, circuit region 1 includes a substrate 11, a transistor 12, an interlayer insulating film 13, multiple contact plugs 14, a wiring layer 15 containing multiple wires, a dielectric plug 16, and a metal pad 17. Figure 1 The diagram shows three of the multiple wirings within wiring layer 15, and three contact plugs 14 disposed on these wirings. Substrate 11 is an example of a first substrate. Metal pad 17 is an example of a first pad.

[0027] like Figure 1 As shown, the array region 2 includes an interlayer insulating film 21, a metal pad 22, a dielectric plug 23, a wiring layer 24 containing multiple wirings, multiple contact plugs 25, a laminated film 26, multiple columnar portions 27, a source layer 28, and an insulating film 29. Figure 1 The diagram shows one of the multiple wires within the wiring layer 24, along with three contact plugs 25 and three columnar portions 27 disposed on that wire. The metal pad 22 is an example of the second pad.

[0028] Furthermore, the multilayer film 26 includes multiple electrode layers 31 and multiple insulating layers 32. Each pillar 27 includes a memory insulating film 33, a channel semiconductor layer 34, a core insulating film 35, and a core semiconductor layer 36. The source layer 28 includes a semiconductor layer 37 and a metal layer 38. The channel semiconductor layer 34 is an example of a first semiconductor layer. The semiconductor layer 37 is an example of a second semiconductor layer.

[0029] Below, refer to Figure 1 The structure of the semiconductor device in this embodiment will be described.

[0030] The substrate 11 is, for example, a semiconductor substrate such as a Si (silicon) substrate. A transistor 12 is disposed on the substrate 11 and includes a gate insulating film and a gate electrode. The transistor 12, for example, constitutes the CMOS circuit. An interlayer insulating film 13 is formed on the substrate 11 covering the transistor 12. The interlayer insulating film 13 is, for example, a SiO2 film (silicon oxide film), or a laminated film containing a SiO2 film and other insulating films.

[0031] Contact plug 14, wiring layer 15, dielectric plug 16, and metal pad 17 are formed within interlayer insulating film 13. Specifically, contact plug 14 is disposed on substrate 11 or on gate electrode of transistor 12. Figure 1 As shown, contact plugs 14 on substrate 11 are disposed on the source and drain regions (not shown) of transistor 12. Wiring layer 15 is disposed on contact plugs 14. Interlayer plugs 16 are disposed on wiring layer 15. Metal pad 17 is disposed on interlayer plug 16 above substrate 11. Metal pad 17 is, for example, a Cu (copper) layer.

[0032] Interlayer insulating film 21 is formed on interlayer insulating film 13. Interlayer insulating film 21 is, for example, a SiO2 film, or a laminated film containing a SiO2 film and other insulating films.

[0033] Metal pad 22, interlayer plug 23, wiring layer 24, and contact plug 25 are formed within interlayer insulating film 21. Specifically, metal pad 22 is disposed on metal pad 17 above substrate 11. Metal pad 22 is, for example, a Cu layer. Interlayer plug 23 is disposed on metal pad 22. Wiring layer 24 is disposed on interlayer plug 23. Figure 1 The diagram shows one of the multiple wires within wiring layer 24, which functions, for example, as a bit line. A contact plug 25 is disposed on wiring layer 24.

[0034] A laminated film 26 is disposed on an interlayer insulating film 21, comprising a plurality of electrode layers 31 and a plurality of insulating layers 32 alternately laminated along the Z direction. The electrode layers 31 are, for example, metal layers containing a W (tungsten) layer, and function as word lines. The insulating layers 32 are, for example, SiO2 films. In this embodiment, the plurality of electrode layers 31 have the same thickness as each other, and the plurality of insulating layers 32 also have the same thickness as each other. However, as described below, the thickness of the uppermost insulating layer 32 may be greater than the thickness of the other insulating layers 32.

[0035] Each columnar portion 27 is disposed within the stacked film 26 and includes a memory insulating film 33, a channel semiconductor layer 34, a core insulating film 35, and a core semiconductor layer 36. The memory insulating film 33 is formed on the side of the stacked film 26 and has a tubular shape extending in the Z direction. The channel semiconductor layer 34 is formed on the side of the memory insulating film 33 and has a tubular shape extending in the Z direction. The core insulating film 35 and the core semiconductor layer 36 are formed on the side of the channel semiconductor layer 34 and have a rod-like shape extending in the Z direction. Specifically, the core semiconductor layer 36 is disposed on the contact plug 25, and the core insulating film 35 is disposed on the core semiconductor layer 36.

[0036] The memory insulating film 33, as described below, sequentially comprises, for example, a barrier insulating film, a charge storage layer, and a tunnel insulating film. The barrier insulating film is, for example, a SiO2 film. The charge storage layer is, for example, a SiN film (silicon nitride film). The tunnel insulating film is, for example, a SiO2 film or a SiON film (silicon oxynitride film). The channel semiconductor layer 34 is, for example, a polycrystalline silicon layer. The core insulating film 35 is, for example, a SiO2 film. The core semiconductor layer 36 is, for example, a polycrystalline silicon layer. Each memory cell within the memory cell array is composed of the channel semiconductor layer 34, the charge storage layer, the electrode layer 31, etc.

[0037] The channel semiconductor layer 34 within each columnar portion 27 is positioned higher than the metal pad 22 and is electrically connected to the metal pad 22 via the core semiconductor layer 36, contact plug 25, wiring layer 24, and interlayer plug 23. Thus, the memory cell array within the array region 2 is electrically connected to the peripheral circuitry within the circuit region 1 via the metal pad 22 or metal pad 17. Therefore, the operation of the memory cell array can be controlled via the peripheral circuitry.

[0038] The source layer 28 includes a semiconductor layer 37 and a metal layer 38 sequentially formed on the multilayer film 26 and the pillars 27, serving as a source line. In this embodiment, the channel semiconductor layer 34 of each pillar 27 is exposed from the memory insulating film 33, and the semiconductor layer 37 is formed directly on the channel semiconductor layer 34. Furthermore, the metal layer 38 is formed directly on the semiconductor layer 37. Thus, the source layer 28 is electrically connected to the channel semiconductor layer 34 of each pillar 27. The semiconductor layer 37 is, for example, a polysilicon layer. The metal layer 38 includes, for example, a W layer, a Cu layer, or an Al (aluminum) layer.

[0039] An insulating film 29 is formed on the source layer 28. The insulating film 29 is, for example, a SiO2 film.

[0040] Here, the impurity atoms included in the semiconductor device of this embodiment will be explained.

[0041] The semiconductor layer 37 of this embodiment contains specified impurity atoms. These impurity atoms are, for example, P (phosphorus) atoms. In this embodiment, the impurity atoms are further contained within the channel semiconductor layer 34 and at least the uppermost insulating layer 32 of the plurality of insulating layers 32. The reason why the semiconductor layer 37, the channel semiconductor layer 34, and the insulating layer 32 of this embodiment contain the same impurity atoms will be explained below.

[0042] Figure 2 This is an enlarged cross-sectional view showing the structure of the semiconductor device according to the first embodiment.

[0043] Figure 2 The diagram illustrates the three electrode layers 31 and three insulating layers 32 contained within the multilayer film 26, as well as a columnar portion 27 disposed within the multilayer film 26. The memory insulating film 33 within this columnar portion 27, as described above, includes a barrier insulating film 33a, a charge storage layer 33b, and a tunnel insulating film 33c sequentially formed on the side of the multilayer film 26. The barrier insulating film 33a is, for example, a SiO2 film. The charge storage layer 33b is, for example, a SiN film. The tunnel insulating film 33c is, for example, a SiO2 film or a SiON film.

[0044] On the other hand, each electrode layer 31 includes a barrier metal layer 31a and an electrode material layer 31b. The barrier metal layer 31a is, for example, a TiN film (titanium nitride film). The electrode material layer 31b is, for example, a W layer. Each electrode layer 31 in this embodiment is as follows... Figure 2As shown, a barrier insulating film 39 is formed on the lower surface of the upper insulating layer 32, the upper surface of the lower insulating layer 32, and the side surface of the barrier insulating film 33a. The barrier insulating film 39 is, for example, an Al2O3 film (alumina film), and together with the barrier insulating film 33a, it functions as a barrier insulating film for each memory cell. Therefore, in this embodiment, the multilayer film 26 includes a barrier insulating film 39 in addition to the electrode layer 31 and the insulating layer 32. The barrier insulating film 39, the barrier metal layer 31a, and the electrode material layer 31b are sequentially formed on the lower surface of the upper insulating layer 32, the upper surface of the lower insulating layer 32, and the side surface of the barrier insulating film 33a.

[0045] Figure 25 This is a cross-sectional view showing the structure of a semiconductor device according to a variation of the first embodiment.

[0046] Array region 2 includes a memory cell array 111 containing multiple memory cells, a semiconductor layer 112 on the memory cell array 111, a back gate insulating film 113 on the semiconductor layer 112, and a back gate electrode 114 on the back gate insulating film 113. The back gate electrode 114, similar to the select gate SG described below, is used to control the electric field of the semiconductor layer 12. Array region 2 further includes an interlayer insulating film 21a under the memory cell array 111 and an insulating film 21b under the interlayer insulating film 21a as the interlayer insulating film 21. The insulating film 21b is, for example, a silicon oxide film.

[0047] Circuit region 1 is disposed under array region 2. Circuit region 1 has an insulating film 13a under insulating film 21b and an interlayer insulating film 13b under insulating film 13a as interlayer insulating film 13, and has a substrate 11 under interlayer insulating film 13b. Insulating film 13a is, for example, a silicon oxide film. Substrate 11 is, for example, a semiconductor substrate such as a silicon substrate.

[0048] Array region 2 has multiple word lines WL and select gate SG to serve as electrode layers within the memory cell array 111. Figure 25 The stepped structure 121 of the memory cell array 111 is shown in the diagram. The array region 2 further includes the back gate electrode 114 as an electrode layer outside the memory cell array 111. Figure 25 As shown, each word line WL is electrically connected to the word line wiring layer 123 via contact plug 122, the back gate electrode 114 is electrically connected to the back gate wiring layer 125 via contact plug 124, and the select gate SG is electrically connected to the select gate wiring layer 127 via contact plug 126. The pillar-shaped portion 27 passing through the word line WL and the select gate SG is electrically connected to the bit line BL within the wiring layer 24 via contact plug 25, and is also electrically connected to the semiconductor layer 112. Furthermore, the word line WL corresponds to a specific example of the electrode layer 31.

[0049] Circuit region 1 includes a plurality of transistors 12. Each transistor 12 includes a gate electrode 12a disposed on a substrate 11 separated by a gate insulating film, and a source diffusion layer and a drain diffusion layer (not shown) disposed within the substrate 11. Circuit region 1 further includes a plurality of contact plugs 14 disposed on the source diffusion layers or drain diffusion layers of these transistors 12, a wiring layer 15a disposed on these contact plugs 14 and including multiple wires, and a wiring layer 15b disposed on the wiring layer 15a and including multiple wires. Circuit region 1 further includes a plurality of dielectric plugs 16 disposed on the wiring layer 15b, and a plurality of metal pads 17 disposed on these dielectric plugs 16 within an insulating film 13a. Circuit region 1 functions as the control circuit (logic circuit) of the control array region 2. Furthermore, wiring layers 15a and 15b are specific examples of the wiring layer 15.

[0050] Array region 2 includes a plurality of metal pads 22 disposed on metal pads 37 within an insulating film 21b, a plurality of dielectric plugs 23 disposed on the metal pads 22, and a wiring layer 131 disposed on these dielectric plugs 23 and including multiple wirings. Each word line WL and each bit line BL is electrically connected to the corresponding wiring in the wiring layer 131. Array region 2 further includes a wiring layer 132 disposed on the wiring layer 131 and including multiple wirings, a wiring layer 133 disposed on the wiring layer 132 and including multiple wirings, and dielectric plugs 134 disposed on the wiring 133. Array region 2 further includes a metal pad 135 disposed on the dielectric plug 134, and a passivation film 136 covering the metal pad 135 and the back gate electrode 114. The passivation film 136 is, for example, a silicon oxide film, having an opening P that exposes the upper surface of the metal pad 136. The metal pad 136 is... Figure 25 External connection pads of semiconductor devices can be connected to mounting substrates or other devices via solder balls, metal bumps, bonding wires, etc.

[0051] Figures 3 to 7 This is a cross-sectional view showing the manufacturing method of the semiconductor device according to the first embodiment.

[0052] Figure 3 (a) shows the array wafer W2 used to fabricate array region 2. When fabricating array region 2, firstly, an insulating film 42 is formed on substrate 41, and multiple sacrificial layers 31' and multiple insulating layers 32 are alternately formed on the insulating film 42. Figure 3 (a)). As a result, a multilayer film 26' is formed on the insulating film 42. The multilayer film 26' comprises a plurality of sacrificial layers 31' and a plurality of insulating layers 32 alternately deposited along the Z direction. The substrate 41 is, for example, a semiconductor substrate such as a Si substrate. The substrate 41 is an example of a second substrate. The insulating film 42 is, for example, a SiN film. The sacrificial layers 31' are, for example, SiN.

[0053] Next, a plurality of memory holes H1 are formed through the stacked film 26' and the insulating film 42, and a memory insulating film 33, a channel semiconductor layer 34 and a core insulating film 35 are sequentially formed in each memory hole H1. Figure 3 (a)). As a result, multiple columnar portions 27 extending in the Z direction are formed within these memory holes H1. The memory insulating film 33 is formed by sequentially forming a barrier insulating film 33a, a charge storage layer 33b, and a tunnel insulating film 33c within each memory hole H1 (see reference). Figure 2 ).

[0054] Next, an insulating film 43 is formed on the laminated film 26' and the columnar portion 27. Figure 3 (a)). The insulating film 43 is, for example, a SiO2 film.

[0055] Next, a slit (not shown) is formed penetrating the insulating film 43 and the multilayer film 26', and the sacrificial layer 31' is removed by wet etching using the slit. Figure 3 (b)). As a result, multiple voids H2 are formed between the insulating layers 32 within the laminated film 26'.

[0056] Next, multiple electrode layers 31 are formed within these cavities H2 via slits. Figure 4 (a)). As a result, a laminated film 26 is formed between the insulating film 42 and the insulating film 43, comprising a plurality of electrode layers 31 and a plurality of insulating layers 32 alternately laminated along the Z direction. Furthermore, a structure is formed above the substrate 41 where the plurality of columnar portions 27 penetrate the laminated film 26. In addition, when forming the electrode layer 31 in each cavity H2, a barrier insulating film 39, a barrier metal layer 31a, and an electrode material layer 31b are sequentially formed in each cavity H2 (see reference). Figure 2 ).

[0057] Next, the insulating film 43 is removed, and a portion of the core insulating film 35 within each columnar portion 27 is removed. Then, a core semiconductor layer 36 is embedded in the area of ​​the core insulating film 35 where the portion has been removed. Figure 4 (b)). As a result, each columnar portion 27 is processed into a structure comprising a memory insulating film 33, a channel semiconductor layer 34, a core insulating film 35, and a core semiconductor layer 36.

[0058] Next, an interlayer insulating film 21, a metal pad 22, a dielectric plug 23, a wiring layer 24, and a plurality of contact plugs 25 are formed on the laminated film 26 and the columnar portion 27. Figure 4 (b)). At this time, these contact plugs 25 are formed on the core semiconductor layer 36 of their respective pillar portions 27, and the wiring layer 24, the interlayer plug 23 and the metal pad 22 are formed sequentially on these contact plugs 25.

[0059] Figure 5(a) shows the circuit wafer W1 used to manufacture circuit region 1. Figure 5 (a) The circuit wafer W1 shown is manufactured by forming transistors 12, interlayer insulating film 13, multiple contact plugs 14, wiring layer 15, interlayer plugs 16 and metal pads 17 on substrate 11 (see reference). Figure 1 At this point, transistor 12 is formed on substrate 1, and contact plugs 14 are formed on substrate 1 or on transistor 12. Furthermore, wiring layer 15, dielectric plugs 16, and metal pads 17 are sequentially formed on these contact plugs 14. Substrate 11 is an example of a first substrate.

[0060] Next, the array wafer W2 is reversed, and the circuit wafer W1 is bonded to the array wafer W2 using mechanical pressure. Figure 5 (a)). As a result, interlayer insulating film 13 and interlayer insulating film 21 are bonded. Next, the circuit wafer W1 and the array wafer W2 are annealed. Figure 5 (a)). As a result, metal pad 17 is bonded to metal pad 22. In this way, metal pad 22 on substrate 41 is bonded to metal pad 17 on substrate 11, interlayer insulating film 21 on substrate 41 is bonded to interlayer insulating film 13 on substrate 11, and substrate 41 is deposited on top of substrate 11.

[0061] Next, substrate 41 is removed. Figure 5 (b)). As a result, the insulating film 42 and each columnar portion 27 are exposed above the substrate 11. The substrate 41 is removed, for example, by CMP (Chemical Mechanical Polishing). Figure 5 In step (b), substrate 41 can be removed by CMP and substrate 11 can also be thinned by CMP.

[0062] Next, a portion of the insulating film 42 and the memory insulating film 33 of each columnar portion 27 are removed by etching. Figure 6 (a)). The portion of the memory insulating film 33 that is removed is, for example, the portion exposed from the stacked film 26. As a result, a portion of the channel semiconductor layer 34 of each columnar portion 27 is exposed from the memory insulating film 33 at a position higher than the stacked film 26.

[0063] Next, a semiconductor layer 37 of the source layer 28 is formed on the multilayer film 26 and the columnar portion 27. Figure 6 (b)). As a result, a semiconductor layer 37 is formed on the channel semiconductor layer 34 of each columnar portion 27, and thus the semiconductor layer 37 is electrically connected to the channel semiconductor layer 34 of each columnar portion 27.

[0064] exist Figure 6In step (b), the semiconductor layer 37 is formed as an amorphous semiconductor layer. This amorphous semiconductor layer is, for example, an a-Si (amorphous silicon) layer. In this embodiment, for example, a source gas containing Si (silicon) and H (hydrogen) elements is used to form the a-Si semiconductor layer 37. Therefore, Figure 6 The semiconductor layer 37 formed in step (b) contains H atoms as impurity atoms. Ideally, these H atoms should be removed from the semiconductor layer 37.

[0065] Next, phosphorus ions are used to perform ion implantation into the semiconductor layer 37. Figure 7 (a) As a result, P atoms are introduced into the semiconductor layer 37 as impurity atoms. As described below, these P atoms have the effect of promoting the detachment of H atoms from the semiconductor layer 37.

[0066] Next, semiconductor layer 37 is annealed to allow H atoms to detach from semiconductor layer 37. Figure 7 (a)). As a result, at least some of the H atoms in the semiconductor layer 37 detach from the semiconductor layer 37, and the H atom concentration in the semiconductor layer 37 decreases. Figure 7 The annealing step in (a) is an example of the first annealing.

[0067] In this embodiment, to remove H atoms, which are impurity atoms, from the semiconductor layer 37, other impurity atoms, namely P atoms, are introduced into the semiconductor layer 37. In this embodiment, the P atoms will remain in the final semiconductor layer 37, that is, in the semiconductor layer 37 of the (finished) semiconductor device after manufacturing. Additionally, during ion implantation, P ions may also be implanted into the channel semiconductor layer 34 of each pillar 27, or into at least the uppermost insulating layer 32 of the plurality of insulating layers 32. In this case, the P atoms will ultimately remain in the channel semiconductor layer 34 or the insulating layer 32. Furthermore, P atoms may also be introduced into other insulating layers 32 of the stacked film 26 and ultimately remain in those insulating layers 32. Regarding... Figure 7 More details about step (a) will be provided below.

[0068] Next, the semiconductor layer 37 is annealed by laser annealing. Figure 7 (b)). As a result, semiconductor layer 37 crystallizes, changing from an amorphous semiconductor layer to a polycrystalline semiconductor layer. The crystallized semiconductor layer 37 is, for example, a polycrystalline silicon layer. Figure 7 (b) is an example of the second annealing step.

[0069] Next, a metal layer 38 of the source layer 28 is formed on the semiconductor layer 37, and an insulating film 29 is formed on the metal layer 38. Figure 7 (b)).

[0070] Then, the circuit wafer W1 and the array wafer W2 are diced into multiple chips. These chips are diced such that each chip contains both circuit region 1 and array region 2. This process manufactures... Figure 1 Semiconductor devices.

[0071] Figure 8 This is a cross-sectional view showing details of the manufacturing method of the semiconductor device according to the first embodiment. Figure 8 (a) to Figure 8 (c) shows the drawing Figure 7 (a) Details of the steps.

[0072] Figure 8 (a) shows the semiconductor layer 37 before ion implantation. Therefore, Figure 8 (a) Semiconductor layer 37 is an a-Si layer containing H atoms as impurity atoms.

[0073] Figure 8 (b) illustrates the implantation of ions into semiconductor layer 37. Figure 8 (b) involves introducing P atoms as impurity atoms into semiconductor layer 37. Figure 8 (b) schematically illustrates the Si and H atoms contained within the semiconductor layer 37. The Si and H atoms form Si-Si or Si-H bonds. According to this embodiment, by introducing P atoms into the semiconductor layer 37, the Si-H bonds can be broken using the P atoms. Therefore, it is possible to promote the detachment of H atoms from the semiconductor layer 37.

[0074] From the perspective of breaking Si-H bonds, the impurity atoms introduced into semiconductor layer 37 can be any impurity atom other than P atoms, which are capable of breaking Si-H bonds. However, if P atoms are introduced into semiconductor layer 37, then semiconductor layer 37 can be an n-type semiconductor layer, thereby improving the performance of semiconductor layer 37. Therefore, P atoms are the most ideal impurity atoms to be introduced into semiconductor layer 37.

[0075] In this embodiment, P atoms are further introduced into the channel semiconductor layer 34 of each columnar portion 27 and into the uppermost insulating layer 32. According to this embodiment, by introducing P atoms into the channel semiconductor layer 34, the channel semiconductor layer 34 can be made into an n-type semiconductor layer, thereby improving the performance of the channel semiconductor layer 34.

[0076] In this embodiment, the concentration of P atoms within the channel semiconductor layer 34 decreases with increasing depth from the upper end of the channel semiconductor layer 34. The upper end of the channel semiconductor layer 34 is the leading edge of the channel semiconductor layer 34 in the +Z direction, such as... Figure 8(b) shows the location within semiconductor layer 37. Ideally, the ion implantation in this embodiment should achieve, for example, a P atom concentration of 1 × 10⁻⁶ at a depth of 200 nm from the upper end of channel semiconductor layer 34. 19 cm -3 Under the above conditions, the P atom concentration within the channel semiconductor layer 34 reaches 1 × 10⁻⁶ across the entire region between the location at the top and a location 200 nm deep from the top. 19 cm -3 The above. These conditions can be set, for example, by adjusting the accelerating voltage and dose of ion implantation.

[0077] According to this embodiment, the concentration of P atoms in the channel semiconductor layer 34 can be set relatively high near the upper end, thereby improving the performance of the channel semiconductor layer 34. For example, by setting the concentration of P atoms in the channel semiconductor layer 34 relatively high near the upper end, sufficient deletion current of the memory cell, i.e., GIDL (Gate Induced Drain Leakage) current, can be generated.

[0078] Furthermore, the P atoms contained in semiconductor layer 37 can be... Figure 8 (b) is followed by annealing for diffusion. Therefore, in this embodiment, P atoms can also diffuse from semiconductor layer 37 to channel semiconductor layer 34 through such annealing. Accordingly, the P atoms in the channel semiconductor layer 34 of the finished semiconductor device can originate from P ions implanted in the channel semiconductor layer 34 during ion implantation, or from P atoms diffused through subsequent annealing. The same applies to the P atoms in the uppermost insulating layer 32. However, compared to diffusion, ion implantation makes it easier to control the P atom concentration. Therefore, if it is desired to control the P atom concentration in the channel semiconductor layer 34 to a desired concentration, it is preferable to adjust the P atom concentration in the channel semiconductor layer 34 by ion implantation.

[0079] In addition, the P atoms contained in the channel semiconductor layer 34 can also be... Figure 8 (b) Step 2 involves annealing followed by diffusion. In this case, 1×10 19 cm -3 The concentrations described above are also ideally applicable in the channel semiconductor layer 34 of the finished semiconductor device. That is, in the finished semiconductor device, the P atom concentration in the channel semiconductor layer 34 ideally reaches 1 × 10⁻⁶ at a depth of 200 nm from the upper end of the channel semiconductor layer 34. 19 cm -3The above. This concentration can be achieved, for example, by taking into account subsequent diffusion, thereby adjusting the concentration of P atoms within the channel semiconductor layer 34 during ion implantation.

[0080] Figure 8 (c) shows the annealing (dehydrogenation annealing) process of semiconductor layer 37. Through Figure 8 In step (c), H atoms detach from semiconductor layer 37, and the H atom concentration within semiconductor layer 37 decreases. At this point, H atoms that have broken away from Si atoms can easily detach from semiconductor layer 37.

[0081] Dehydrogenation annealing is performed, for example, by reducing the H atom concentration within the semiconductor layer 37 to 10% or less (preferably 5% or less) at a temperature below 400°C. Dehydrogenation annealing can be performed using an annealing furnace or by low-intensity laser annealing to a degree that does not dissolve the semiconductor layer 37. On the other hand, Figure 7 (b) The laser annealing step is performed at a high intensity to the extent that some or all of the semiconductor layer 37 is dissolved, thereby changing the semiconductor layer 37 from an a-Si layer to a polycrystalline silicon layer.

[0082] If a high concentration of H atoms remains within the semiconductor layer 37, these H atoms may form H2 molecules, potentially creating pores or causing ablation during laser annealing. Alternatively, H atoms within the semiconductor layer 37 may detach through high-temperature annealing at temperatures above 400°C. However, such high-temperature annealing could adversely affect the metal pads 17 and 22, which are Cu layers.

[0083] In this embodiment, P atoms are first introduced into the semiconductor layer 37, and then H atoms are detached from the semiconductor layer 37 through subsequent annealing. Therefore, according to this embodiment, H atoms can be detached from the semiconductor layer 37 by low-temperature annealing at less than 400°C. This suppresses both the adverse effects on the metal pads 17 and 22 and the ablation of pores within the semiconductor layer 37 or during laser annealing.

[0084] Furthermore, in this embodiment, p atoms are used as impurity atoms to promote the removal of hydrogen atoms. These p atoms also contribute to improving the performance of the semiconductor layer 37 and the channel semiconductor layer 34. Therefore, according to this embodiment, by implanting ions, both promoting removal and improving performance can be achieved simultaneously. This eliminates the need for separate ion implantation for improving the performance of the semiconductor layer 37 and the channel semiconductor layer 34, and separate ion implantation for promoting hydrogen atom removal. Consequently, the time required to manufacture the semiconductor device can be shortened.

[0085] Figure 9It is a graph used to illustrate the concentration of P (phosphorus) atoms in the semiconductor device of the first embodiment.

[0086] Figure 9 (a) The vertical axis represents Figure 1 The concentration of P atoms at various locations within the channel semiconductor layer 34. Figure 9 (a) The horizontal axis represents Figure 1 The depth of each point within the channel semiconductor layer 34 from the top end of the channel semiconductor layer 34. The direction of this depth is parallel to the Z direction. Hereinafter, the P atom concentration will be referred to as "P concentration".

[0087] Figure 9 (a) Curves A1 to A5 represent five examples of P concentration distribution within the channel semiconductor layer 34. The P concentration distribution within the channel semiconductor layer 34 can be set to any shape, for example, it can be set to the shape of any of the curves A1 to A5.

[0088] Curve A1 is a sloping straight line, with the P concentration decreasing linearly. Curve A2 is a convex curve, with the P concentration decreasing non-linearly. Curve A3 is a concave curve, with the P concentration decreasing non-linearly. Curve A4 successively includes a horizontal straight section and a sloping straight section, where the P concentration initially remains constant and then decreases from a specified depth. Curve A5 successively includes a sloping straight section and a horizontal straight section, where the P concentration initially decreases and then remains constant after reaching a specified depth. Curves A1 to A5 are decreasing functions of P concentration with depth. Furthermore, curves A1 to A3 are monotonically decreasing functions of P concentration with depth. In this way, the P atoms within the channel semiconductor layer 34 will have a concentration slope in the Z direction.

[0089] As described above, the ideal P concentration within the channel semiconductor layer 34 is 1 × 10⁻⁶ at a depth of 300 nm from the top of the channel semiconductor layer 34. 18 cm -3 Ideally, a depth of 200 nm from the top of the channel semiconductor layer 34 should be achieved to reach 1×10⁻⁶. 19 cm -3 Therefore, to achieve the desired P concentration distribution within the channel semiconductor layer 34 as shown in curve A1, the ideal P concentration at a depth of 300 nm in curve A1 is set to 1 × 10⁻⁶. 18 cm -3 The same applies when the P concentration distribution within the channel semiconductor layer 34 is set as shown by any of the curves A2 to A5. In this embodiment, the P concentration distribution within the channel semiconductor layer 34 is set according to a Gaussian distribution, for example.

[0090] exist Figure 9In (a), the P concentration at a depth of 0 nm in curves A1–A5 was set to 1 × 10⁻⁶. 20 cm -3 However, it can also be set to other values.

[0091] Figure 9 (b) The vertical axis represents Figure 1 The concentration of P atoms (P concentration) at various locations within the semiconductor layer 37 and the top insulating layer 32. Figure 9 (b) The horizontal axis represents Figure 1 The depth of each point within the semiconductor layer 37 and the uppermost insulating layer 32 from the upper surface of the semiconductor layer 37. The direction of this depth is also parallel to the Z-direction. Furthermore, Figure 9 The assumption in the graph in (b) is that, as described above, the thickness of the uppermost insulating layer 32 is set to be greater than the thickness of the other insulating layers 32.

[0092] Figure 9 (b) Curve B1 represents an example of the P concentration distribution within the semiconductor layer 37 and the top insulating layer 32. The P concentration distribution within the semiconductor layer 37 and the top insulating layer 32 can be set to any shape, for example, it can be set to the shape of curve B1.

[0093] As shown in curve B1, the P concentration within semiconductor layer 37 is 1 × 10⁻⁶ at any location. 19 cm -3 The above-mentioned high concentration of P can be achieved, for example, by setting a higher accelerating voltage for ion implantation. In this case, not only will the P concentration in the semiconductor layer 37 increase, but the P concentration in the uppermost insulating layer 32 will also increase. If the accelerating voltage for ion implantation is set higher, then in the finished semiconductor device, the uppermost insulating layer 32 (and consequently, other insulating layers 32) will contain P atoms. As shown in curve B1, the P concentration in the uppermost insulating layer 32 decreases with depth. The P concentration distribution in the semiconductor layer 37 and the uppermost insulating layer 32 in this embodiment is, for example, set according to a Gaussian distribution. In this way, the P atoms in the semiconductor layer 37 and the uppermost insulating layer 32 will have a concentration slope in the Z direction.

[0094] Figure 10 This is a cross-sectional view showing a method for manufacturing a semiconductor device according to a variation of the first embodiment.

[0095] Figure 10 (a) and Figure 10 Step (b) corresponds to respectively Figure 7 (a) and Figure 7 (b) steps. Figure 6(b) The semiconductor layer 37 shown can also be formed to have an upper surface with unevenness due to the protrusion of the columnar portion 27. Figure 10 (a) illustrates the semiconductor layer 37 formed in this manner. In this case, the semiconductor layer 37 is subjected to ion implantation and annealing. Figure 10 (a)), and then laser annealing is performed on the semiconductor layer 37. Figure 10 (b) Then, a metal layer 38 is formed on the semiconductor layer 37, an insulating film 29 is formed on the metal layer 38, and the upper surface of the insulating film 29 is planarized by CMP. Alternatively, the CMP can be omitted.

[0096] As described above, in this embodiment, a semiconductor layer 38 is formed first, then P atoms are introduced into the semiconductor layer 38, and then the semiconductor layer 38 is annealed. Therefore, according to this embodiment, H atoms can be detached from the semiconductor layer 38 through low-temperature annealing. Furthermore, according to this embodiment, by introducing P atoms to detach H atoms, P atoms can be introduced into the semiconductor layer 38 and the channel semiconductor layer 34, thereby improving the performance of the semiconductor layer 38 and the channel semiconductor layer 34.

[0097] In this way, according to this embodiment, the impact of impurity atoms (P atoms and H atoms) on the performance of semiconductor devices can be optimized. For example, the advantages of P atoms can be enjoyed while the problems caused by H atoms can be suppressed. Furthermore, the method of this embodiment can also be applied to impurity atoms other than P atoms and H atoms.

[0098] (Second Implementation)

[0099] Figure 11 This is a cross-sectional view showing the structure of the semiconductor device according to the second embodiment. The semiconductor device of this embodiment is, for example, a three-dimensional flash memory, having the same characteristics as the semiconductor device of the first embodiment (…). Figure 1 Different structures. Hereinafter, the structure of the semiconductor device of this embodiment will be described, focusing on the differences from the structure of the semiconductor device of the first embodiment.

[0100] The semiconductor device in this embodiment is as follows: Figure 11 As shown, the device includes a substrate 51, an interlayer insulating film 52, a laminated film 53, an interlayer insulating film 54, multiple pillar-shaped portions 55, an interlayer insulating film 56, multiple sets of insulating films 57, a wiring layer 58, and multiple contact plugs 59. The interlayer insulating film 56 is an example of the first insulating film.

[0101] Furthermore, the multilayer film 53 includes multiple electrode layers 61 and multiple insulating layers 62. Each pillar 55 includes a semiconductor layer 63, a memory insulating film 64, a channel semiconductor layer 65, a core insulating film 66, and a core semiconductor layer 67. The channel semiconductor layer 65 is an example of the first semiconductor layer.

[0102] The substrate 51 is, for example, a semiconductor substrate such as a Si substrate. An interlayer insulating film 52 is formed on the substrate 51. The interlayer insulating film 52 is, for example, a SiO2 film.

[0103] A multilayer film 53 is disposed on an interlayer insulating film 52, comprising a plurality of electrode layers 61 and a plurality of insulating layers 62 alternately deposited along the Z direction. The electrode layers 61 are, for example, metal layers containing W layers, and function as word lines. The insulating layers 62 are, for example, SiO2 films. An interlayer insulating film 54 is formed on the multilayer film 53. The interlayer insulating film 54 is, for example, a SiO2 film.

[0104] Each columnar portion 55 is disposed within the interlayer insulating film 52, the stacked film 53 and the interlayer insulating film 54, and includes a semiconductor layer 63, a memory insulating film 64, a channel semiconductor layer 65, a core insulating film 66 and a core semiconductor layer 67.

[0105] A semiconductor layer 63 is disposed on a substrate 51 within the interlayer insulating film 52 and the stacked film 53, and is electrically connected to the substrate 51. The semiconductor layer 63 forms the bottom of each pillar 55 and has a rod-like shape extending along the Z-direction. A memory insulating film 64 is formed on the side of the stacked film 53 and the interlayer insulating film 54, and has a tubular shape extending along the Z-direction. A channel semiconductor layer 65 is formed on the side of the memory insulating film 64 or on the upper surface of the semiconductor layer 63, and has a tubular shape extending along the Z-direction. The channel semiconductor layer 65 is electrically connected to the semiconductor layer 63. A core insulating film 66 is formed on the side or upper surface of the channel semiconductor layer 65, and has a rod-like shape extending along the Z-direction. A core semiconductor layer 67 is formed on the side of the channel semiconductor layer 65 or on the upper surface of the core insulating film 66, and has a rod-like shape extending along the Z-direction. The core semiconductor layer 67 is electrically connected to the channel semiconductor layer 65.

[0106] Semiconductor layer 63 is, for example, a single-crystal silicon layer formed by epitaxial growth from substrate 61. Memory insulating film 64, as described below, sequentially includes, for example, a barrier insulating film, a charge storage layer, and a tunnel insulating film. The barrier insulating film is, for example, a SiO2 film. The charge storage layer is, for example, a SiN film. The tunnel insulating film is, for example, a SiO2 film or a SiON film. Channel semiconductor layer 65 is, for example, a polycrystalline silicon layer. Core insulating film 66 is, for example, a SiO2 film. Core semiconductor layer 66 is, for example, a polycrystalline silicon layer. Each memory cell of the three-dimensional flash memory of this embodiment is composed of channel semiconductor layer 65, charge storage layer, electrode layer 61, etc.

[0107] An interlayer insulating film 56 is formed on the interlayer insulating film 54 and the columnar portion 55. The interlayer insulating film 56 is, for example, a silicon oxide film. Each set of insulating films 57 and the wiring layer 58 are sequentially formed within the interlayer insulating film 52, the laminated film 53, the interlayer insulating film 54, and the interlayer insulating film 56, extending along the Z direction. The wiring layer 58 is electrically connected to the substrate.

[0108] Contact plugs 59 are disposed within the interlayer insulating film 56 and positioned on the pillar-shaped portion 55. Each contact plug 59 is formed on the core semiconductor layer 67 corresponding to the pillar-shaped portion 55, thereby being electrically connected to the core semiconductor layer 67, the channel semiconductor layer 65, the semiconductor layer 63, and the substrate 51. The contact plug 59 is an example of a plug.

[0109] Here, the impurity atoms included in the semiconductor device of this embodiment will be explained.

[0110] The interlayer insulating film 56 of this embodiment contains specified impurity atoms. These impurity atoms are, for example, H (hydrogen) atoms. In this embodiment, these impurity atoms are further contained in the channel semiconductor layer 65. The reason why the interlayer insulating film 56 and the channel semiconductor layer 65 of this embodiment contain the same impurity atoms will be explained below.

[0111] Figure 12 This is an enlarged cross-sectional view showing the structure of the semiconductor device according to the second embodiment.

[0112] Figure 12 The diagram illustrates the three electrode layers 61 and three insulating layers 62 contained within the multilayer film 53, as well as a columnar portion 55 disposed within the multilayer film 53. The memory insulating film 64 within this columnar portion 55, as described above, includes a barrier insulating film 64a, a charge storage layer 64b, and a tunnel insulating film 64c sequentially formed on the side of the multilayer film 53. The barrier insulating film 64a is, for example, a SiO2 film. The charge storage layer 64b is, for example, a SiN film. The tunnel insulating film 64c is, for example, a SiO2 film or a SiON film.

[0113] On the other hand, each electrode layer 61 includes a barrier metal layer 61a and an electrode material layer 61b. The barrier metal layer 61a is, for example, a TiN film. The electrode material layer 61b is, for example, a W layer. Each electrode layer 61 in this embodiment is as follows... Figure 12As shown, a barrier insulating film 68 is formed on the lower surface of the upper insulating layer 62, the upper surface of the lower insulating layer 62, and the side surface of the barrier insulating film 64a. The barrier insulating film 68 is, for example, an Al2O3 film, and together with the barrier insulating film 64a, it functions as a barrier insulating film for each memory cell. Therefore, in addition to the electrode layer 61 and the insulating layer 62, the laminated film 53 of this embodiment also includes the barrier insulating film 68. The barrier insulating film 68, the barrier metal layer 61a, and the electrode material layer 61b are sequentially formed on the lower surface of the upper insulating layer 62, the upper surface of the lower insulating layer 62, and the side surface of the barrier insulating film 64a.

[0114] Figures 13 to 21 This is a cross-sectional view showing the manufacturing method of the semiconductor device according to the second embodiment.

[0115] First, an interlayer insulating film 52 is formed on a substrate 51, and multiple sacrificial layers 61' and multiple insulating layers 62 are alternately formed on the interlayer insulating film 52. Figure 13 (a)). As a result, a laminated film 53' is formed on the interlayer insulating film 52. The laminated film 53' comprises a plurality of sacrificial layers 61' and a plurality of insulating layers 62 alternately laminated along the Z direction. The sacrificial layers 61' are, for example, SiN. Next, an interlayer insulating film 54 is formed on the laminated film 53'. Figure 13 (a)).

[0116] Next, multiple memory holes H3 are formed that penetrate the interlayer insulating film 52, the laminated film 53', and the interlayer insulating film 54. Figure 13 (b)). As a result, the surface of the substrate 51 is exposed within these memory holes H3. Then, a semiconductor layer 63 is formed on the substrate 51 within each memory hole H3 by epitaxial growth from the substrate 51. Figure 14 (a)).

[0117] Next, a memory insulating film 64 is formed on the entire surface of the substrate 51. Figure 14 (b) As a result, a memory insulating film 64 is formed inside and outside the memory hole H3, specifically, on the upper surface of the semiconductor layer 63, the sides of the stacked film 53' and the interlayer insulating film 54, and the upper surface of the interlayer insulating film 54. The memory insulating film 64 is formed by sequentially forming a barrier insulating film 64a, a charge storage layer 64b, and a tunnel insulating film 64c on the entire surface of the substrate 51 (see reference). Figure 12 ).

[0118] Next, the memory insulating film 64 is removed from the upper surface of the semiconductor layer 63 and the upper surface of the interlayer insulating film 54. Figure 15 (a)). As a result, the upper surface of the semiconductor layer 63 is exposed in each memory hole H3.

[0119] Next, a channel semiconductor layer 65 is formed on the entire surface of the substrate 51. Figure 15 (b) As a result, the channel semiconductor layer 65 is formed inside and outside the memory hole H3, specifically on the upper surface of the semiconductor layer 63, the side surface of the memory insulating film 64, and the upper surface of the interlayer insulating film 54.

[0120] Next, a core insulating film 66 is embedded in each memory hole H3. Figure 16 (a)). As a result, the core insulating film 66 is formed in each memory hole H3 on the upper surface or side surface of the channel semiconductor layer 65.

[0121] Next, a portion of the core insulating film 66 within each memory hole H3 is removed by etch-back. Figure 16 (b)). As a result, a recess H4 is formed on the core insulating film 66 within each memory hole H3.

[0122] Next, a core semiconductor layer 67 is formed on the entire surface of the substrate 51. Figure 17 (a)). As a result, a portion of the core semiconductor layer 67 is formed within each recess H4. Figure 17 In step (a), the core semiconductor layer 67 is formed as an amorphous semiconductor layer and crystallizes into a polycrystalline semiconductor layer in a subsequent step. This amorphous semiconductor layer is, for example, an a-Si (amorphous silicon) layer.

[0123] Next, the core semiconductor layer 67 outside the recess H4 is removed by RIE (Reactive Ion Etching). Figure 17 (b) As a result, a plurality of columnar portions 55 extending in the Z direction are formed within the plurality of memory holes H3. Each columnar portion 55 is formed to include a semiconductor layer 63, a memory insulating film 64, a channel semiconductor layer 65, a core insulating film 66, and a core semiconductor layer 67.

[0124] Next, an interlayer insulating film 56 is formed on the interlayer insulating film 54 and the columnar portion 55. Figure 18 (a) Next, multiple slits H5 are formed through the RIE (Reaching Interlayer) to penetrate the interlayer insulating film 52, the laminated film 53', the interlayer insulating film 54, and the interlayer insulating film 56. Figure 18 (b)).

[0125] Next, the sacrificial layer 61' is removed by wet etching using these slits H5. Figure 19 (a)). As a result, multiple voids H6 are formed between the insulating layers 62 within the laminated film 53'.

[0126] Next, multiple electrode layers 61 are formed within these cavities H6 via these slits H5. Figure 19(b) As a result, a laminated film 53 is formed between the interlayer insulating film 52 and the interlayer insulating film 54, comprising a plurality of electrode layers 61 and a plurality of insulating layers 62 alternately deposited along the Z direction. Furthermore, on the substrate 51, a structure is formed in which the plurality of pillar-shaped portions 55 penetrate the interlayer insulating film 52, the laminated film 53, and the interlayer insulating film 54. Figure 19 As shown in (b), an interlayer insulating film 56 is disposed on these columnar portions 55, and is disposed on the laminated film 53 with an interlayer insulating film 54 in between. Furthermore, when forming the electrode layer 61 within each cavity H6, a barrier insulating film 68, a barrier metal layer 61a, and an electrode material layer 61b are sequentially formed within each cavity H6 (see reference). Figure 12 ).

[0127] Next, an insulating film 57 is formed within each slit H5, and then the insulating film 57 is removed from the bottom of each slit H5. Finally, a wiring layer 58 is formed within each slit H5. Figure 20 (a)). As a result, multiple sets of insulating films 57 and wiring layers 58 are formed within the plurality of slits H5. The wiring layer 58 within each slit H5 is electrically connected to the substrate 51.

[0128] Next, a semiconductor layer 71 is formed on the interlayer insulating film 56, the insulating film 57, and the wiring layer 58. Figure 20 (b)). In Figure 20 In step (b), the semiconductor layer 71 is formed as an amorphous semiconductor layer. This amorphous semiconductor layer is, for example, an a-Si layer. In this embodiment, for example, a source gas containing Si and H elements is used to form the semiconductor layer 71, which is an a-Si layer. Therefore, Figure 20 The semiconductor layer 71 formed in step (b) contains H atoms as impurity atoms. Semiconductor layer 71 is an example of the first film.

[0129] Next, phosphorus ions are used to perform ion implantation into the semiconductor layer 71. Figure 21 (a) As a result, P atoms are introduced into the semiconductor layer 71 as impurity atoms. As explained with respect to semiconductor layer 37 in the first embodiment, the P atoms have the effect of promoting the detachment of H atoms from semiconductor layer 71. As described below, in this embodiment, the H atoms detached from semiconductor layer 71 are effectively used to terminate dangling bonds.

[0130] Semiconductor layer 71 can be formed for any purpose. For example, semiconductor layer 71 can be formed for the purpose of serving as a wiring layer on substrate 51, or it can be formed for the purpose of serving as a hard mask layer in the manufacturing process of a semiconductor device. In the former case, semiconductor layer 71 will remain in the finished semiconductor device, but in the latter case, semiconductor layer 71 will not remain in the finished semiconductor device. In this embodiment, semiconductor layer 71 is formed as a hard mask layer for processing layers (not shown) on substrate 51, and therefore, as described below, it will not remain in the finished semiconductor device. Therefore, in this embodiment, a metal layer, an insulating film, or a multilayer film can also be formed as the hard mask layer instead of semiconductor layer 71.

[0131] Alternatively, the ions used in ion implantation can be other ions capable of promoting the detachment of H atoms from the semiconductor layer 71. Such ions include, for example, boron (B) ions, arsenic (As) ions, silicon (Si) ions, or oxygen (O) ions. For instance, when using the semiconductor layer 71 as a wiring layer, Si ions can be implanted into the Si-based semiconductor layer 71. In this case, both the semiconductor layer 71 and the ions are composed of Si, thus suppressing the adverse effects of the ions on the semiconductor layer 71. On the other hand, when using the semiconductor layer 71 as a wiring layer, P ions, B ions, or As ions can be implanted into the semiconductor layer 71 to make it a p-type or n-type semiconductor layer.

[0132] In this embodiment, ion implantation is performed using a high-energy ion implanter at an implantation energy of approximately 60 keV or less. Furthermore, the ion implantation dose in this embodiment is set to, for example, 1 × 10⁻⁶. 15 cm -2 above.

[0133] Next, the semiconductor layer 71 is annealed to allow the H atoms to detach from the semiconductor layer 71. Figure 21 (a)). As a result, at least some of the H atoms in the semiconductor layer 71 detach from the semiconductor layer 71, and the H atom concentration in the semiconductor layer 71 decreases.

[0134] In this embodiment, H atoms detached from semiconductor layer 71 are introduced into channel semiconductor layer 65. The channel semiconductor layer 65 in this embodiment is a polycrystalline silicon layer containing dangling bonds of Si atoms. According to this embodiment, the dangling bonds within the channel semiconductor layer 65 can be terminated by the H atoms detached from semiconductor layer 71. This improves the reliability of the channel semiconductor layer 65 and the memory cell. As a result, in the finished semiconductor device, the channel semiconductor layer 65 of this embodiment contains H atoms as impurity atoms.

[0135] The dangling bond then forms between the channel semiconductor layer 65 and the tunnel insulating film 64c (see reference). Figure 12 H atoms also exist in high density at the interface between the semiconductor layer 71 and the tunnel insulating film 64c. In this embodiment, H atoms detached from the semiconductor layer 71 also reach the interface between the channel semiconductor layer 65 and the tunnel insulating film 64c. According to this embodiment, the dangling bonds at the interface between the channel semiconductor layer 65 and the tunnel insulating film 64c can be terminated by the H atoms detached from the semiconductor layer 71. As a result, in the finished semiconductor device, H atoms are also contained at the interface between the channel semiconductor layer 65 and the tunnel insulating film 64c, and within the tunnel insulating film 64c.

[0136] In this embodiment, H atoms detached from semiconductor layer 71 reach channel semiconductor layer 65 and tunnel insulating film 64c via interlayer insulating film 56. Therefore, in the finished semiconductor device of this embodiment, H atoms detached from semiconductor layer 71 are also present in interlayer insulating film 56. In this embodiment, the lower surface of semiconductor layer 71 is in contact with the upper surface of interlayer insulating film 56 over a large area, so H atoms detached from semiconductor layer 71 are easily introduced into interlayer insulating film 56. In the finished semiconductor device of this embodiment, H atoms detached from semiconductor layer 71 may also be present in interlayer insulating film 54 and at least in the uppermost insulating layer 62 of the plurality of insulating layers 62. Furthermore, the H atoms in semiconductor layer 71, interlayer insulating film 56, channel semiconductor layer 65 and tunnel insulating film 64c of this embodiment have a concentration slope in the Z direction for the same reason as the P atoms in semiconductor layer 37, uppermost insulating layer 32 and channel semiconductor layer 34 of the first embodiment.

[0137] The annealing temperature of the semiconductor layer 71 can be any temperature. Ideally, the annealing temperature should be set relatively high to facilitate efficient removal of H atoms from the semiconductor layer 71. However, if the annealing temperature is too high, there is a risk that the annealing will adversely affect the metal layer within the semiconductor device. Therefore, it is ideal to set the annealing temperature to a high temperature that will not adversely affect the metal layer. In this embodiment, the annealing temperature of the semiconductor layer 71 is set, for example, to 400°C to 500°C.

[0138] In this embodiment, where the semiconductor layer 71 is formed as a hard mask layer used to process a layer (not shown) on the substrate 51, the processing is completed, and... Figure 21 After step (a) is completed, the semiconductor layer 71 will be removed. Figure 21 (b) Furthermore, an opening is formed on the columnar portion 55 within the interlayer insulating film 56, and a contact plug 59 is formed within the opening. Figure 21 (b) As a result, each contact plug 59 is formed on the core semiconductor layer 67 of the corresponding columnar portion 55 and is electrically connected to the core semiconductor layer 67.

[0139] Then, various wiring layers, plugs, interlayer insulating films, etc., are formed on the substrate 51. This completes the fabrication of... Figure 11 Semiconductor devices.

[0140] Here, a more detailed description of the semiconductor layer 71 in this embodiment will be provided.

[0141] In this embodiment, dangling bonds are terminated using H atoms detached from semiconductor layer 71. This improves the reliability of the channel semiconductor layer 65 and tunnel insulating film 64c, as well as the reliability of the memory cell containing the channel semiconductor layer 65 and tunnel insulating film 64c.

[0142] Furthermore, in this embodiment, the semiconductor layer 71, which is used as a hard mask, is also used to terminate dangling bonds. Therefore, according to this embodiment, the semiconductor layer 71 can be effectively utilized for these two purposes. That is, the semiconductor layer 71 can be used not only as a hard mask and then removed, but also to terminate dangling bonds before removal. However, in this embodiment, the semiconductor layer 71 may also be used solely to terminate dangling bonds.

[0143] Furthermore, in this embodiment, the semiconductor layer 71 contains H atoms from the point in time of its formation. However, it is also possible to introduce H atoms into the semiconductor layer 71 after its formation through heat treatment or plasma treatment. In this case, after introducing H atoms into the semiconductor layer 71, further processing is required. Figure 21 Ion implantation and annealing in step (a).

[0144] In addition, in this embodiment, it is also possible to... Figure 21 Between ion implantation and annealing in step (a), an insulating film is formed on the semiconductor layer 71. This suppresses the release of H atoms from the upper surface of the semiconductor layer 71 during annealing, allowing them to easily escape from the lower surface. In other words, the insulating film suppresses upward diffusion of H atoms. As a result, dangling bonds can be terminated more efficiently. Ideally, the insulating film should block the diffusion of H atoms. Examples of such insulating films include SiN films or Al2O3 films. Alternatively, in this embodiment, a semiconductor layer or metal layer that blocks the diffusion of H atoms can be formed on the semiconductor layer 71 instead of the insulating film. Furthermore, an example using a barrier layer 99 that blocks the diffusion of H atoms will be described in the third embodiment below.

[0145] Alternatively, the semiconductor layer 71 in this embodiment may also contain atoms other than H atoms capable of terminating dangling bonds. Examples of such atoms include F (fluorine) atoms or Cl (chlorine) atoms. Furthermore, the H atoms within the semiconductor layer 71 can be ordinary...1 H atom (light hydrogen atom), can also be 2 H atoms (deuterium atoms: D atoms). Regardless of which type of impurity atom is used, it can be included in the semiconductor layer 71 either from the point of formation of the semiconductor layer 71 or introduced into the semiconductor layer 71 after its formation. For example, if the semiconductor layer 71 contains F atoms, F atoms detached from the semiconductor layer 71 can be introduced into the channel semiconductor layer 65, etc., terminating dangling bonds, and included in the channel semiconductor layer 65, etc., of the finished semiconductor device.

[0146] Furthermore, the P atom in this embodiment is obtained through... Figure 21 In step (a), ion implantation is performed to introduce ions into the semiconductor layer 71. At this time, P atoms may also be introduced into layers other than the semiconductor layer 71. In the ion implantation of this embodiment, P atoms may, for example, also be introduced into the interlayer insulating film 56, interlayer insulating film 54, channel semiconductor layer 65, core semiconductor layer 67, and at least the uppermost insulating layer 62 of the plurality of insulating layers 62. In this case, the P atoms will be contained within the interlayer insulating film 56 of the finished semiconductor device. For example, by introducing P atoms into the channel semiconductor layer 65 and the core semiconductor layer 67, the performance of the channel semiconductor layer 65 and the core semiconductor layer 67 can be improved. (See reference...) Figure 22 This will further explain the P atom.

[0147] Figure 22 It is a graph used to illustrate the concentration of P (phosphorus) atoms contained in the semiconductor layer 71 of the second embodiment.

[0148] Figure 22 The vertical axis represents Figure 21 (a) P atom concentration (P concentration) at various locations within the semiconductor layer 71 and the interlayer insulating film 56. Figure 22 The horizontal axis represents Figure 21 (a) The depth of each point within the semiconductor layer 71 and the interlayer insulating film 56 from the upper surface of the semiconductor layer 71. The symbol T represents the thickness of the semiconductor layer 71. Figure 22 The direction of the depth is parallel to the Z direction.

[0149] Figure 22 The curve represents an example of the P concentration distribution within semiconductor layer 71 and interlayer insulating film 56. This P concentration distribution has the characteristics of... Figure 9 (b) The curve B1 has the same shape as the P concentration distribution. Specifically, the P concentration within the interlayer insulating film 56 decreases with depth. In the finished semiconductor device of this embodiment, as a process of... Figure 21 (a) traces, the interlayer insulating film 56 will contain having Figure 22The P concentration distribution shown represents the P atoms. The same applies when P atoms are present in layers other than the interlayer insulating film 56. Thus, the P atoms within the semiconductor layer 71 and the interlayer insulating film 56 will have a concentration slope in the Z direction.

[0150] In addition, if in Figure 21 After step (a), the P atoms in the interlayer insulating film 56 diffuse significantly, so the P concentration distribution in the interlayer insulating film 56 in the finished semiconductor device may be... Figure 22 The P concentration distribution shown varies significantly. On the other hand, if... Figure 21 After step (a), the P atoms in the interlayer insulating film 56 do not diffuse much, so the P concentration distribution in the interlayer insulating film 56 in the finished semiconductor device will be similar to... Figure 22 The P concentration distributions shown are the same.

[0151] As described above, in this embodiment, a semiconductor layer 71 is formed first, then P atoms are introduced into the semiconductor layer 71, and then the semiconductor layer 71 is annealed. Therefore, according to this embodiment, H atoms detached from the semiconductor layer 71 can be introduced into the channel semiconductor layer 65, thereby terminating dangling bonds within the channel semiconductor layer 65. This improves the reliability of the channel semiconductor layer 65.

[0152] In this way, according to this embodiment, the impact of impurity atoms (P atoms and H atoms) on the performance of the semiconductor device can be optimized. For example, H atoms can be generated using P atoms to terminate dangling bonds, and the dangling bonds can be terminated by the H atoms generated in this way. Furthermore, the method of this embodiment, as described above, can also be applied to impurity atoms other than P atoms and H atoms. In addition, the atoms introduced into the semiconductor layer 71 can also be atoms other than impurity atoms, like the Si atoms described above.

[0153] (Third Implementation)

[0154] Figure 23 This is a cross-sectional view showing the structure of the semiconductor device according to the third embodiment. The semiconductor device of this embodiment includes a plurality of planar transistors. Hereinafter, the structure of the semiconductor device of this embodiment will be described, focusing on the differences in structure from the semiconductor devices of the first and second embodiments.

[0155] Figure 23The semiconductor device includes a substrate 81, multiple element separation regions 82, gate insulating films 83 and gate electrodes 84 for each transistor, multiple sidewall insulating films 85, multiple extension regions 86 and source / drain regions 87, interlayer insulating films 88, multiple contact plugs 89, a wiring layer 90 containing multiple wires, an interlayer insulating film 91, a dielectric plug 92, a wiring layer 93 containing multiple wires, an interlayer insulating film 94, a dielectric plug 95, a wiring layer 96 containing multiple wires, and a passivation film 97.

[0156] The substrate 81 is, for example, a semiconductor substrate such as a Si substrate. The substrate 81 can also be a semiconductor substrate other than Si, or it can be an SOI (Silicon on Insulator) substrate. Component separation regions 82 are formed within the substrate 81 to separate the transistors from each other. Component separation regions 82 are also referred to as STI (Shallow Trench Isolation).

[0157] Each transistor includes a gate insulating film 83 and a gate electrode 84 sequentially formed on a substrate 81. The gate insulating film 83 is, for example, a SiO2 film or a high dielectric constant film (high-k film). The gate electrode 84 is, for example, a polysilicon layer, a metal layer, or a multilayer film comprising a polysilicon layer and a metal layer. A sidewall insulating film 85 is formed on the substrate 81 on the side of the gate electrode 84. An extension region 86 is formed in the substrate 81 across the gate electrode 84. A source / drain region 87 is also formed in the substrate 81 across the gate electrode 84. However, the extension region 86 is sandwiched between the source / drain regions 87. Furthermore, the transistor formed on the substrate 81 can be a finned FET (Field Effect Transistor) or a nanowire FET.

[0158] An interlayer insulating film 88 is formed on the substrate 81, covering the transistor. The interlayer insulating film 88 is, for example, a SiO2 film, or a multilayer film containing a SiO2 film and other insulating films. Contact plugs 89 are formed within the interlayer insulating film 88 and disposed on the gate electrode 84 and the source / drain region 87.

[0159] A wiring layer 90 is formed on the interlayer insulating film 88 and on the contact plug 89. The wiring layer 90 is, for example, a metal layer. An interlayer insulating film 91 is formed on the interlayer insulating film 88, covering the wiring layer 90. The interlayer insulating film 91 is, for example, a SiO2 film, or a laminated film comprising a SiO2 film and other insulating films. A dielectric plug 92 is formed on the wiring layer 90 within the interlayer insulating film 91.

[0160] A wiring layer 93 is formed on the interlayer insulating film 91 and on the dielectric plug 92. The wiring layer 93 is, for example, a metal layer. An interlayer insulating film 94 is formed on the interlayer insulating film 91, covering the wiring layer 93. The interlayer insulating film 94 is, for example, a SiO2 film, or a laminated film comprising a SiO2 film and other insulating films. A dielectric plug 95 is formed on the wiring layer 93 within the interlayer insulating film 94.

[0161] A wiring layer 96 is formed on the interlayer insulating film 94 and on the dielectric plug 95. The wiring layer 96 is, for example, a metal layer and contains wiring that functions as bonding pads. A passivation film 97 covers the wiring layer 96 and is formed on the interlayer insulating film 94. However, the bonding pads within the wiring layer 96 are exposed from the passivation film 97. The passivation film 97 is, for example, an insulating film such as a SiO2 film.

[0162] Furthermore, the semiconductor device of this embodiment has three wiring layers 90, 93, and 96, but it may also have four or more wiring layers. The number of wiring layers in the semiconductor device of this embodiment is arbitrary.

[0163] Here, the impurity atoms included in the semiconductor device of this embodiment will be explained.

[0164] The interlayer insulating film 94 of this embodiment contains specified impurity atoms. These impurity atoms are, for example, H (hydrogen) atoms. In this embodiment, these impurity atoms are further contained in the substrate 81. The reason why the interlayer insulating film 94 and the substrate 81 of this embodiment contain the same impurity atoms will be explained below.

[0165] Figure 24 This is a cross-sectional view showing the manufacturing method of the semiconductor device according to the third embodiment.

[0166] First, a component separation region 82 is formed within the substrate 81, and then a gate insulating film 83 and a gate electrode 84 of each transistor are sequentially formed on the substrate 81. Figure 24 (a)). The component separation region 82 is formed, for example, by forming trenches in the substrate 81 through dry etching and embedding a SiO2 film in the trenches.

[0167] Next, an extended region 86 is formed within the substrate 81, a sidewall insulating film 85 is formed on the side of the gate electrode 84 by etching back, and a source / drain region 87 is formed within the substrate 81. Figure 24 (a)). The extended region 86 and the source / drain region 87 are formed, for example, by introducing impurity atoms such as P (phosphorus), B (boron), and As (arsenic) into the substrate 81.

[0168] Next, an interlayer insulating film 88 is formed on the substrate 81, and a contact plug 89 is formed within the interlayer insulating film 88. Figure 24(a)). Next, a wiring layer 90 is formed on the interlayer insulating film 88 and the contact plug 89, an interlayer insulating film 91 is formed on the interlayer insulating film 88 and the wiring layer 90, and a via plug 92 is formed in the interlayer insulating film 91( Figure 24 (a)). Next, a wiring layer 93 is formed on the interlayer insulating film 91 and the via plug 92, an interlayer insulating film 94 is formed on the interlayer insulating film 91 and the wiring layer 93, and a via plug 95 is formed in the interlayer insulating film 94( Figure 24 (a)).

[0169] Next, a semiconductor layer 98 is formed on the interlayer insulating film 94 and the via plug 95( Figure 24 (a)). In Figure 24 (a), the semiconductor layer 98 is formed as an amorphous semiconductor layer. This amorphous semiconductor layer is, for example, an a-Si layer. In the present embodiment, for example, a source gas containing Si element and H element is used to form the semiconductor layer 98 which is an a-Si layer. Therefore, Figure 24 (a), the semiconductor layer 98 formed contains H atoms as impurity atoms. The semiconductor layer 98 is an example of the first film.

[0170] Next, ion implantation into the semiconductor layer 98 is performed using P (phosphorus) ions( Figure 24 (a)). As a result, P atoms are introduced into the semiconductor layer 98 as impurity atoms. As described for the semiconductor layers 37 and 71 in the first and second embodiments, these P atoms have the effect of promoting the detachment of H atoms from the semiconductor layer 98. As described below, in the present embodiment, the H atoms detached from the semiconductor layer 98 are effectively used to terminate dangling bonds.

[0171] The semiconductor layer 98 can be formed for any purpose. For example, the semiconductor layer 98 can be formed for the purpose of serving as a wiring layer on the substrate 51, or can be formed for the purpose of serving as a hard mask layer in the manufacturing process of a semiconductor device. In the former case, the semiconductor layer 98 remains in the finished semiconductor device, but in the latter case, the semiconductor layer 98 does not remain in the finished semiconductor device. The semiconductor layer 98 of the present embodiment is formed as a hard mask layer for processing an unillustrated layer on the substrate 51, and thus, as described below, does not remain in the finished semiconductor device. Therefore, in the present embodiment, a metal layer, an insulating film, or a stacked film can also be formed as the hard mask layer to replace the semiconductor layer 98.

[0172] In addition, the ions used in the ion implantation can also be other ions that can promote the detachment of H atoms from the semiconductor layer 98. Such ions are, for example, B (boron) ions, As (arsenic) ions, Si (silicon) ions, or O (oxygen) ions.

[0173] In this embodiment, ion implantation is performed using a high-energy ion implanter at an implantation energy of approximately 60 keV or less. Furthermore, the ion implantation dose in this embodiment is set to, for example, 1 × 10⁻⁶. 15 cm -2 above.

[0174] Next, after forming an insulating film 99 on the semiconductor layer 98, the semiconductor layer 98 is annealed to allow H atoms to detach from the semiconductor layer 98. Figure 24 (b)). As a result, at least some of the H atoms in semiconductor layer 98 detach from semiconductor layer 98, and the H atom concentration in semiconductor layer 98 decreases. The annealing temperature of semiconductor layer 98 (annealing temperature) can be any temperature, for example, set to 400°C to 500°C. Insulating film 99 is an example of the second film.

[0175] In this embodiment, H atoms detached from the semiconductor layer 98 are introduced into the substrate 81. The substrate 81 in this embodiment is a Si substrate, containing dangling bonds of Si atoms in the channel region of the transistor, etc. According to this embodiment, the dangling bonds in the substrate 81 can be terminated by the H atoms detached from the semiconductor layer 98. This improves the reliability of the channel region and the transistor. As a result, in the finished semiconductor device, the substrate 81 of this embodiment contains H atoms as impurity atoms.

[0176] Dangling bonds also exist at a high density at the interface between the substrate 81 and the gate insulating film 82. In this embodiment, H atoms detached from the semiconductor layer 98 also reach the interface between the substrate 81 and the gate insulating film 82. According to this embodiment, the dangling bonds at the interface between the substrate 81 and the gate insulating film 82 can be terminated by the H atoms detached from the semiconductor layer 98. As a result, in the finished semiconductor device, H atoms are also contained at the interface between the substrate 81 and the gate insulating film 82, and within the gate insulating film 82.

[0177] In this embodiment, H atoms detached from semiconductor layer 98 reach substrate 81 and gate insulating film 82 via interlayer insulating film 94. Therefore, in the finished semiconductor device of this embodiment, H atoms detached from semiconductor layer 98 also exist within interlayer insulating film 94. In this embodiment, the lower surface of semiconductor layer 98 and the upper surface of interlayer insulating film 94 are in contact over a large area, thus H atoms detached from semiconductor layer 98 are easily introduced into interlayer insulating film 94. In the finished semiconductor device of this embodiment, H atoms detached from semiconductor layer 98 may further exist within interlayer insulating film 91 and interlayer insulating film 88.

[0178] In this embodiment, Figure 24In step (b), an insulating film 99 is formed on the semiconductor layer 98 before annealing. This suppresses the release of H atoms from the upper surface of the semiconductor layer 98 during annealing, allowing them to easily escape from the lower surface. In other words, the insulating film 99 suppresses the upward diffusion of H atoms. As a result, dangling bonds can be terminated more efficiently. The insulating film 99 in this embodiment has a barrier effect on the diffusion of H atoms. Examples of such an insulating film 99 include SiN films or Al2O3 films. Alternatively, in this embodiment, a semiconductor layer or metal layer that has a barrier effect on the diffusion of H atoms may be formed on the semiconductor layer 98 instead of the insulating film 99.

[0179] In this embodiment, where the semiconductor layer 98 is formed as a hard mask layer used to process a layer (not shown) on the substrate 81, the processing is completed, and... Figure 24 (a) and Figure 24 (b) After the semiconductor layer 98 is removed, the insulating film 99 is also removed before the semiconductor layer 98 is removed.

[0180] Then, a wiring layer 96 is formed on the interlayer insulating film 94 and the interlayer plug 95, a passivation film 97 is formed on the wiring layer 96, and the passivation film 97 is processed to expose the bonding pad from the passivation film 97 (see reference). Figure 21 This is how it was created. Figure 21 Semiconductor devices.

[0181] Here, a more detailed description of the semiconductor layer 98 in this embodiment will be provided.

[0182] In this embodiment, dangling bonds are terminated using H atoms detached from semiconductor layer 98. This improves the reliability of the channel region (substrate 81) and gate insulating film 82, as well as the reliability of the transistor containing the channel region and gate insulating film 82.

[0183] Furthermore, in this embodiment, the semiconductor layer 98, which serves as a hard mask, is also used to terminate dangling bonds. Therefore, according to this embodiment, the semiconductor layer 98 can be effectively utilized for these two purposes. That is, the semiconductor layer 98 can be used not only as a hard mask and then removed, but also to terminate dangling bonds before removal. However, in this embodiment, the semiconductor layer 98 may also be used solely to terminate dangling bonds.

[0184] Furthermore, in this embodiment, the semiconductor layer 98 contains H atoms from the point of formation. However, it is also possible to introduce H atoms into the semiconductor layer 98 after its formation through heat treatment or plasma treatment. In this case, after introducing H atoms into the semiconductor layer 98, further processing is required. Figure 24(a) ion implantation in step (a), and Figure 24 Annealing in step (b).

[0185] Furthermore, the semiconductor layer 98 in this embodiment may also contain atoms other than H atoms capable of terminating dangling bonds. Examples of such atoms include F atoms or Cl atoms. Additionally, the H atoms within the semiconductor layer 71 can be ordinary... 1 The H (light hydrogen) atom can also be... 2 H (deuterium: D) atoms. Regardless of which type of impurity atom is used, it can be included in the semiconductor layer 98 either from the point of formation of the semiconductor layer 98 or introduced into the semiconductor layer 98 after its formation. For example, if the semiconductor layer 98 contains F atoms, F atoms detached from the semiconductor layer 98 can be introduced into the substrate 81, terminating dangling bonds, and included in the substrate 81 of the finished semiconductor device, etc.

[0186] Furthermore, the P atom in this embodiment is obtained through... Figure 24 In step (a), ion implantation is performed to introduce ions into the semiconductor layer 98. At this time, P atoms may also be introduced into layers other than the semiconductor layer 98. In the ion implantation of this embodiment, P atoms may also be introduced into, for example, the interlayer insulating film 94, interlayer insulating film 91, interlayer insulating film 88, gate electrode 84, substrate 81, etc. In this case, the P atoms will be contained within the interlayer insulating film 94, etc., of the finished semiconductor device.

[0187] As described above, in this embodiment, a semiconductor layer 98 is formed first, then P atoms are introduced into the semiconductor layer 98, and then the semiconductor layer 98 is annealed. Therefore, according to this embodiment, H atoms detached from the semiconductor layer 98 can be introduced into the substrate 81 (channel region), thereby terminating dangling bonds in the substrate 81. This improves the reliability of the substrate 81.

[0188] In this way, according to this embodiment, the impact of impurity atoms (P atoms and H atoms) on the performance of the semiconductor device can be optimized. For example, H atoms can be generated using P atoms to terminate dangling bonds, and the dangling bonds can be terminated by the H atoms generated in this way. Furthermore, the method of this embodiment, as described above, can also be applied to impurity atoms other than P atoms and H atoms. In addition, the atoms introduced into the semiconductor layer 98 can also be atoms other than impurity atoms, like the Si atoms described above.

[0189] Furthermore, in embodiments 1 to 3, the atoms used in ion implantation are atoms of a different type than the atoms being detached. For example, by using P atoms in ion implantation, H atoms can be detached. However, the atoms used in ion implantation can also be atoms of the same type as the atoms being detached. For example, by implanting H ions into the semiconductor layer 71 of embodiment 2, H atoms can also be detached from the semiconductor layer 71.

[0190] When applied to the semiconductor layer 37 of the first embodiment, if H ions are implanted into the semiconductor layer 37, although it is desirable to reduce the H atom concentration within the semiconductor layer 37, it is conceivable that the H atom concentration within the semiconductor layer 37 will increase. However, one implanted H ion typically breaks multiple Si-H bonds. Therefore, the number of H atoms detaching from the semiconductor layer 71 is greater than the number of H ions implanted into it. As a result, the H atom concentration within the semiconductor layer 37 can be reduced.

[0191] When using H ions in ion implantation, their light weight makes it easy to implant them into deeper locations. For example, H ions are ideal for implanting ions into the interior of any of the stacked films 26', 26', 53', and 53'. In this case, the H ions can be ordinary... 1 H (light hydrogen) ions can also be 2 H (deuterium:D) ions.

[0192] Furthermore, to facilitate the removal of H atoms from the semiconductor layer 71, recesses such as holes or trenches can be formed within the semiconductor layer 71 before annealing, which is used to remove H atoms. The same applies to layers other than the semiconductor layer 71.

[0193] Alternatively, to detach H atoms from thick films such as stacked films 26, 26', 53, and 53', the thick film can be formed in multiple parts. In this case, the steps of forming a portion of the thick film, implanting ions into that portion, and annealing that portion can be repeated sequentially. In this case, the thickness of that portion is thinner than the overall thickness of the thick film, making ion implantation easier.

[0194] Several embodiments have been described above, but these embodiments are merely examples and are not intended to limit the scope of the invention. These embodiments can be implemented according to other different embodiments, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, and are also included in the scope of the invention as described in the claims and its equivalents.

Claims

1. A semiconductor device comprising: A multilayer film comprising a plurality of electrode layers and a plurality of insulating layers alternately deposited along a first direction; The columnar portion includes a charge storage layer and a first semiconductor layer extending along the first direction within the multilayer film; and A second semiconductor layer, disposed on the multilayer film and the columnar portion, contains phosphorus atoms and has a concentration slope of the phosphorus atoms in the first direction; wherein The first concentration of phosphorus atoms at the first position of the second semiconductor layer is higher than the second concentration of phosphorus atoms at the second position between the stacked film and the first position. The second concentration is higher than the third concentration of phosphorus atoms at the third position between the stacked film and the second position.

2. The semiconductor device according to claim 1, further comprising: Substrate; Bit lines are disposed between the substrate and the laminated film.

3. The semiconductor device according to claim 1, wherein The first concentration, the second concentration, and the third concentration are 1×10⁻⁶. 19 cm -3 above.

4. The semiconductor device according to claim 1, wherein The concentration distribution of phosphorus atoms in the second semiconductor layer follows a Gaussian distribution.

5. The semiconductor device according to claim 1, wherein The plurality of insulating layers have a first insulating layer disposed on the uppermost layer of the laminated film, and The first insulating layer contains phosphorus atoms.

6. The semiconductor device according to claim 5, wherein The first insulating layer has the concentration slope of the phosphorus atoms in the first direction.

7. The semiconductor device according to claim 6, wherein The concentration distribution of phosphorus atoms in the first insulating layer follows a Gaussian distribution.

8. The semiconductor device according to claim 5, wherein The concentration of phosphorus atoms in the first insulating layer is below the third concentration.

9. The semiconductor device according to claim 5, wherein The thickness of the first insulating layer in the first direction is greater than the thickness of the plurality of insulating layers other than the first insulating layer in the first direction.

10. The semiconductor device of claim 1, wherein The first semiconductor layer contains phosphorus atoms and has a concentration slope of the phosphorus atoms in the first direction.

11. The semiconductor device of claim 10, wherein In the first semiconductor layer, the concentration of phosphorus atoms decreases linearly from the top end of the first semiconductor layer.

12. The semiconductor device of claim 10, wherein In the first semiconductor layer, the concentration of phosphorus atoms decreases nonlinearly starting from the top end of the first semiconductor layer.

13. The semiconductor device of claim 12, wherein In the first semiconductor layer, starting from the top end of the first semiconductor layer, the concentration of phosphorus atoms decreases in a manner that depicts an upward-convex curve.

14. The semiconductor device of claim 12, wherein In the first semiconductor layer, starting from the top end of the first semiconductor layer, the concentration of phosphorus atoms decreases in a manner that depicts a downward-convex curve.

15. The semiconductor device of claim 10, wherein In the first semiconductor layer, starting from the top of the first semiconductor layer, the concentration of phosphorus atoms is initially kept constant and then decreases from a specified depth.

16. The semiconductor device of claim 10, wherein In the first semiconductor layer, starting from the top of the first semiconductor layer, the concentration of phosphorus atoms is first reduced to a specified depth and then kept constant.

17. The semiconductor device of claim 10, wherein In the first semiconductor layer, the concentration of phosphorus atoms decreases according to the depth from the top end of the first semiconductor layer.

18. The semiconductor device of claim 10, wherein In the first semiconductor layer, the concentration of phosphorus atoms decreases monotonically with respect to the depth from the top of the first semiconductor layer.

19. The semiconductor device of claim 1, wherein The fourth concentration of phosphorus atoms at the fourth position of the first semiconductor layer is lower than the fifth concentration of phosphorus atoms at the fifth position between the second semiconductor layer and the fourth position.

20. The semiconductor device of claim 19, wherein The fourth concentration is 1×10 18 cm -3 above, The fifth concentration is 1×10 19 cm -3 above.

21. The semiconductor device of claim 20, wherein The fourth position is located 300 nm from the upper surface of the second semiconductor layer. The fifth position is located 200 nm from the upper surface of the second semiconductor layer.

22. The semiconductor device of claim 1, wherein The concentration of phosphorus atoms at the sixth position of the second semiconductor layer is lower than the first concentration. The first position is located between the sixth position and the second position.

23. The semiconductor device according to claim 1, wherein The second semiconductor layer has an upper surface with irregularities.

24. The semiconductor device of claim 23, wherein The second semiconductor layer includes: a first upper surface disposed in the first direction of the stacked film; and a second upper surface disposed in the first direction of the columnar portion and above the first upper surface.

25. The semiconductor device according to claim 1, further comprising: A layer containing a metal disposed on the second semiconductor layer.

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