Semiconductor device, power module, and electronic device

Abstract

The application discloses a semiconductor device, a power module and electronic equipment, and relates to the technical field of semiconductors, wherein the semiconductor device comprises a first gate material, a gate and a virtual gate; the first gate material is connected with a first contact hole; the first gate material has at least two convex parts, and the two convex parts are spaced apart to form a recessed part; the gate is partially formed on the convex part of the first gate material and is electrically connected with a metal electrode through the first contact hole; the virtual gate is at least partially formed on the recessed part and is spaced apart from the gate and the first gate material; the virtual gate is connected with a second contact hole and is electrically connected with the metal electrode through the second contact hole. The application aims to realize the miniaturized design of the semiconductor device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor device, power module, and electronic device. Background Technology

[0002] In the design of high-power-density semiconductor devices, it is usually necessary to set up a normal gate and a dummy gate, and the connection method of the dummy gate can affect the final performance of the semiconductor device. For the traditional dummy gate connection, the dummy gate is usually made by covering the polysilicon with a contact, and the polysilicon is connected to the metal electrode through a contact hole to achieve the electrical connection of the dummy gate.

[0003] However, due to the minimum design size between polysilicon, the normal gate and the virtual gate cannot be too close together. Therefore, the above-mentioned traditional virtual gate connection increases the size of semiconductor devices and is not conducive to the miniaturization design of semiconductor devices. Summary of the Invention

[0004] The main objective of this invention is to provide a semiconductor device, power module, and electronic device that aims to achieve miniaturized design of the semiconductor device.

[0005] To achieve the above objectives, the present invention provides a semiconductor device comprising: A first gate material, the first gate material being connected to a first contact hole, the first gate material having at least two protrusions, the two protrusions being spaced apart to form a clearance recess; A gate, wherein the gate portion is formed on the protrusion of the first gate material, and the gate is electrically connected to a metal electrode through the first contact hole; A virtual gate, at least partially formed in the relief recess and spaced apart from the gate and the first gate material, is connected to a second contact hole and is electrically connected to a metal electrode through the second contact hole.

[0006] In one embodiment, the first gate material has a first portion and a second portion, the first portion and the second portion of the first gate material are spaced apart along a first direction, and the first portion and the second portion are provided with a plurality of protrusions facing each other, and the protrusions of the first portion and the protrusions of the second portion are aligned one by one. A gate forming region is provided between two mutually aligned protrusions in the first part, and a virtual gate forming region is provided between two mutually aligned recesses in the two first gate materials; the gate is arranged along the length direction of the gate forming region, and the virtual gate is arranged along the length direction of the virtual gate forming region.

[0007] In one embodiment, the difference in length between the gate and the virtual gate is less than a first preset difference.

[0008] In one embodiment, the number of gates is multiple, and among the multiple gates, adjacent gates form a group of gate components; At least one virtual gate is provided between every two groups of the gate components.

[0009] In one embodiment, the number of virtual gates is multiple, and the adjacent virtual gates form a group of virtual gate components; Each of the virtual gate components is connected to at least one of the second contact holes.

[0010] In one embodiment, the two ends of the virtual gate assembly are respectively connected to the two second contact holes.

[0011] In one embodiment, the virtual gate is connected to at least one second contact hole, and the second contact hole is disposed along the length direction of the virtual gate.

[0012] In one embodiment, the shape of the second contact hole is adapted to the shape of the virtual gate; And / or, the size of the second contact hole is adapted to the size of the virtual gate.

[0013] In one embodiment, the semiconductor device further includes a second gate material, the second gate material being connected to the second contact hole, the second gate material being disposed in the virtual gate forming region, and the second gate material and the first gate material being disposed at a first preset distance apart; the virtual gate assembly and the second gate material are connected. The virtual gate is formed in the second gate material.

[0014] In one embodiment, the number of virtual gates is multiple, and the adjacent virtual gates form a group of virtual gate components; The virtual gate assembly is connected to at least one of the second gate materials.

[0015] In one embodiment, a second gate material is connected to each end of the virtual gate assembly, and the second gate material is disposed in the virtual gate forming region at a position other than the avoidance recess.

[0016] In one embodiment, the first gate material is square in shape, and the protrusions of the first gate material are square, and the plurality of protrusions form a plurality of square gate forming regions and square virtual gate forming regions.

[0017] The present invention also provides a power module comprising at least one semiconductor device as described in any of the preceding claims.

[0018] The present invention also provides an electronic device, the electronic device comprising: Semiconductor devices as described in any of the above; and / or, The power module as described above.

[0019] In summary, the semiconductor device proposed in this invention enables miniaturized design. The semiconductor device includes a first gate material, a gate, and a dummy gate. The first gate material is connected to a first contact hole and has a protrusion and a recess. The protrusion is used to connect to the gate, and the recess is used to set the dummy gate. After the gate is connected to the first gate material, it is connected to a metal electrode through the first contact hole. The dummy gate can be directly connected to a second contact hole instead of the gate material, thus avoiding the negative impact caused by the size requirements between the gate material of the dummy gate and the gate material of the gate in the prior art. Therefore, the semiconductor device proposed in this invention facilitates miniaturized design. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0021] Figure 1 A schematic diagram of the structure of the first embodiment of the semiconductor device provided by the present invention; Figure 2 A schematic diagram of the structure of a second embodiment of the semiconductor device provided by the present invention; Figure 3 A schematic diagram of the structure of the third embodiment of the semiconductor device provided by the present invention; Figure 4 This is a schematic diagram of the structure of the fourth embodiment of the semiconductor device provided by the present invention; Figure 5 This is a schematic diagram of the fifth embodiment of the semiconductor device provided by the present invention.

[0022] Explanation of icon numbers: First gate material 100, protrusion 110, avoidance recess 120, first portion 131, second portion 132, gate forming region 141, virtual gate forming region 142, gate 200, gate assembly 210, virtual gate 300, virtual gate assembly 310, first contact hole 400, second contact hole 500, second gate material 600, transition region 700.

[0023] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0024] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0025] It should be noted that if the embodiments of the present invention involve directional indicators (such as up, down, left, right, front, back, etc.), the directional indicators are only used to explain the relative positional relationship and movement of the components in a specific posture. If the specific posture changes, the directional indicators will also change accordingly.

[0026] Furthermore, if the embodiments of this invention involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the use of "and / or" or "and / or" throughout the text includes three parallel solutions. For example, "A and / or B" includes solution A, solution B, or a solution where both A and B are satisfied simultaneously. Furthermore, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed by this invention.

[0027] In existing semiconductor devices, it is usually necessary to set a normal gate and a virtual gate. Traditional semiconductor devices face challenges such as short-channel effect and increased leakage current. The virtual gate enhances the gate's control over the channel region by introducing additional control mechanisms, such as sidewall gate or back gate, thereby improving switching characteristics and reducing power consumption.

[0028] The traditional virtual gate connection method involves covering the virtual gate with polysilicon, and then connecting the polysilicon to the metal electrode through a contact hole to achieve the electrical connection of the virtual gate.

[0029] However, since the normal gate also needs to be in contact with the polysilicon cover, and the normal gate and the dummy gate need to be connected to different potentials through two independent polysilicon layers, these two polysilicon layers must maintain sufficient spacing to prevent them from short-circuiting during manufacturing. This means that the normal gate and the dummy gate cannot be too close together, increasing the size of the semiconductor device and hindering its miniaturization design.

[0030] Therefore, in order to solve the above problems, such as Figure 1 As shown, the present invention proposes a semiconductor device comprising: a first gate material 100, a gate 200, and a dummy gate 300. The first gate material 100 is connected to a first contact hole 400 and has at least two protrusions 110, with a clearance recess 120 formed between the two protrusions 110. The gate 200 is formed on the protrusions 110 of the first gate material 100 and is electrically connected to a metal electrode through the first contact hole 400. The dummy gate 300 is at least partially formed in the clearance recess 120 and is spaced apart from the gate 200 and the first gate material 100. The dummy gate 300 is connected to a second contact hole 500 and is electrically connected to a metal electrode through the second contact hole 500.

[0031] Understandably, unlike existing technologies, the virtual gate 300 in this semiconductor device may not have a gate material, thus avoiding the negative impact caused by the size requirements between the gate material of the virtual gate 300 and the gate material of the gate 200 in existing technologies, thereby achieving miniaturization design.

[0032] On the other hand, in this invention, due to the presence of the two protrusions 110 of the first gate material 100, an avoidance recess 120 is formed, which can be used to etch the gate material of the virtual gate 300. That is to say, even if the virtual gate 300 is connected to the gate material, the negative impact caused by the size requirements between the gate material of the virtual gate 300 and the gate material of the gate 200 in the prior art can be avoided, and a miniaturized design can be achieved. A layout example will be given later.

[0033] In this embodiment, the first gate material 100 can be one of silicon, silicide, nitride, polycrystalline silicon, etc. In this embodiment, the first gate material 100 is polycrystalline silicon, which has good conductivity and stability, ensuring good contact between the gate 200 and the first gate material 100. It is understood that, in order to achieve electrical connection between the gate 200 and the metal electrode, a first contact hole 400 is etched on the insulating material on the first gate material 100. Thus, after the gate 200 contacts the first gate material 100, it can be electrically connected to the metal electrode through the first contact hole 400. In addition, the first gate material 100, the gate 200, and the dummy gate 300 are all formed on a substrate, which can be a silicon substrate, a silicon carbide substrate, a silicon-germanium substrate, a gallium arsenide substrate, or other commonly used substrates. The first gate material 100 can be formed by common deposition methods such as chemical vapor deposition and atomic layer deposition, and the corresponding shape is etched by etching after deposition.

[0034] Furthermore, the first gate material 100 includes at least two protrusions 110. When the first gate material 100 includes two protrusions 110, a clearance recess 120 can be formed. When the first gate material 100 includes two protrusions 110, a clearance recess 120 can be formed between two adjacent protrusions 110, resulting in a total of two clearance recesses 120, and so on, designed according to the actual application. It can be understood that in this embodiment, the protrusions 110 are used to connect the gate 200, while the clearance recesses 120 can be used to set the dummy gate 300. It should be explained that in some prior art, in order to solve size requirements, gates 200 and dummy gates 300 of different lengths are designed. Although this can solve the size requirements to a certain extent, both may have insufficient performance in terms of withstand voltage or other properties. Therefore, in this embodiment, through the design of the protrusions 110 and clearance recesses 120, the negative impact caused by size requirements can be solved while ensuring that the gate 200 and dummy gate 300 have the same length. Of course, if required by the design, the gate 200 and the virtual gate 300 in this embodiment can also be designed to have different lengths, and no length limitation is made here.

[0035] In this embodiment, firstly, the gate 200 can be formed directly by etching the first gate material 100, meaning the gate 200 and the first gate material 100 are integrally formed without the need for additional materials or steps, simplifying the manufacturing process. Secondly, the gate 200 and the first gate material 100 can also be in a cover contact, meaning that first, another gate material (which can be the same material as the first gate material 100) is etched to form the gate 200, and then the first gate material 100 is re-etched on this gate 200 to form the first gate material 100 of the corresponding shape. Regardless of whether it is the first or the second, the connection between the gate 200 and the first gate material 100 will be used to describe this in the preceding and subsequent descriptions.

[0036] It is understood that the first gate material 100 is connected to a first contact hole 400. Since an insulating material, such as silicon dioxide, needs to be deposited between the first gate material 100 and the metal electrode to isolate the gate 200 and the subsequent metal electrode, contact holes are required in the insulating material to achieve electrical connection between the gate oxide layer and the metal electrode. These include the first contact hole 400 and the second contact hole 500. After the first gate material 100 contacts the first contact hole 400, the gate 200 connects to the first gate material 100, thus achieving electrical connection with the metal electrode through the first contact hole 400. Optionally, a contact hole (not shown in the figure) is also provided at the interval between each corresponding gate 200 and dummy gate 300.

[0037] In this embodiment, the virtual gate 300 can be etched by another gate material (or the same as the first gate material 100). It should be noted that the virtual gate 300 needs to be spaced apart from the gate 200 and from the first gate material 100. The distance between the virtual gate 300, the gate 200, and the gate material should not be too close, because the virtual gate 300 and the gate 200 need to be connected to different potentials and cannot be in direct contact. Therefore, these two parts must be spaced sufficiently, otherwise failure may occur. If the two parts are connected together, it will cause the semiconductor device to fail.

[0038] In this embodiment, the virtual gate 300 is not connected to a gate material. In the prior art, the virtual gate 300 is also connected to a gate material (polysilicon), which is not conducive to the miniaturization design of the device. However, in this embodiment, the virtual gate 300 may not be connected to a gate material. Instead, the second contact hole 500 is deposited directly in the insulating material at the location corresponding to the virtual gate 300. In this way, the electrical connection between the virtual gate 300 and the metal electrode can be directly achieved. In addition, in some examples, the second contact hole 500 may be etched only on the insulating material, or it may be etched through the insulating material into the virtual gate 300. However, the contact method and contact area between the second contact hole 500 and the virtual gate 300 are not limited here.

[0039] It should be noted that the effective cells and virtual gate cells in the semiconductor device provided by this invention can be set according to application requirements, and miniaturization can be achieved for different settings. Specifically, the effective cell contains the actual working circuit part, which is responsible for performing the main functions, such as signal amplification and logic operations; while the virtual gate cell contains a virtual gate 300, which is used to help control the electric field distribution in the channel region and improve the short-channel effect and leakage current problem.

[0040] It is understandable that semiconductor devices can refer to MOSFETs or IGBTs. They can be N-type or P-type.

[0041] In summary, the semiconductor device proposed in this invention enables miniaturized design. The semiconductor device includes a first gate material 100, a gate 200, and a dummy gate 300. The first gate material 100 is connected to a first contact hole 400 and has a protrusion 110 and a recess 120. The protrusion 110 is used to connect to the gate 200, and the recess 120 is used to set the dummy gate 300. After the gate 200 is connected to the first gate material 100, it is connected to a metal electrode through the first contact hole 400. The dummy gate 300 can be directly connected to a second contact hole 500 instead of a gate material, thus avoiding the negative impact caused by the size requirements between the gate materials of the dummy gate 300 and the gate material of the gate 200 in the prior art. Therefore, the semiconductor device proposed in this invention facilitates miniaturized design.

[0042] In one embodiment, the first gate material 100 has two protrusions 110 to form a clearance groove, and the number of protrusions 110 can also be multiple to form multiple clearance recesses 120. It is understood that the number of protrusions 110 depends on the process and application of the device, so the number is not limited here. What is important is the protrusions 110 and the clearance recesses 120 themselves.

[0043] In one embodiment, the difference in length between the gate 200 and the dummy gate 300 is less than a first preset difference. Optionally, the first preset difference can be set very small, close to or equal to 0, which means that the gate 200 and the dummy gate 300 have the same length. It is understood that in some exemplary embodiments, in order to make the polysilicon corresponding to the gate 200 and the dummy gate 300 spaced a certain distance apart, the gate 200 and the dummy gate 300 are designed to be of different lengths, which will also lead to a certain difference in electric field distribution, affecting the current distribution and withstand voltage performance of the device. Therefore, in this embodiment, by the cooperation of the protrusion 110 and the avoidance recess 120, the lengths of the gate 200 and the dummy gate 300 can be set to be the same without affecting the layout of the semiconductor device or increasing the size of the semiconductor device.

[0044] In one embodiment, such as Figure 1 As shown, the first gate material 100 has a first portion 131 and a second portion 132. The first portion 131 and the second portion 132 of the first gate material 100 are spaced apart along a first direction. The first portion 131 and the second portion 132 are provided with a plurality of protrusions 110 facing each other. The protrusions 110 of the first portion 131 and the protrusions 110 of the second portion 131 are aligned one-to-one. A gate forming region 141 is provided between two mutually aligned protrusions in the first portion 131. A virtual gate forming region 142 is provided between two mutually aligned clearance recesses 120 in the two first gate materials 100. The gate 200 is provided along the length direction of the gate forming region 141, and the virtual gate 300 is provided along the length direction of the virtual gate forming region 142.

[0045] It is important to note that Figure 1 The diagram shows a partial cross-sectional view of a semiconductor device. The first gate material 100 is shown in the figure with a first portion 131 and a second portion 132. While the first portion 131 and the second portion 132 are clearly marked, they can be integrally formed or independently. Furthermore, the first portion 131 and the second portion 132 have multiple protrusions 110 facing each other. The protrusions 110 of the first portion 131 and the second portion 132 are aligned one-to-one. This allows the gate 200 and the dummy gate 300 to be more evenly arranged when positioned in corresponding locations, thus better maximizing the device's functionality.

[0046] In one embodiment, such as Figure 1As shown, a gate forming region 141 and a virtual gate forming region 142 are formed between the first portion 131 and the second portion 132. This region is provided with a gate 200 and a virtual gate 300. The gate 200 is disposed in the gate forming region 141, with one end of the gate 200 disposed on a corresponding protrusion 110 in the first portion 131 of the first gate material 100, and the other end of the gate 200 disposed on a corresponding protrusion 110 in the second portion 132 of the first gate material 100. The virtual gate 300 is disposed in the virtual gate forming region 142, spaced apart from the first portion 131 and the second portion 132 of the first gate material 100. That is, the virtual gate 300 is located within the virtual gate forming region 142 but does not directly contact the first portion 131 or the second portion 132. This ensures sufficient spacing between the virtual gate 300 and the normal gate 200, preventing short circuits.

[0047] Understandably, in existing technologies, the contact holes of the virtual gate 300 are often located on one side of the virtual gate 300, i.e., the outward-facing side. However, due to the need to maintain the spacing between polysilicon wafers, the contact holes of the normal gate 200 can only be located on the side further away from the gate material than the contact holes of the virtual gate 300, i.e., in a more outward-facing position, which leads to an increase in the overall chip area. Therefore, in this invention, the virtual gate 300 is directly located between the first portion 131 and the second portion 132. Simultaneously, the second contact hole 500 is directly etched onto the insulating material on the virtual gate 300, because the second contact hole 500 does not need to be located further away from the gate material to maintain the polysilicon spacing. Instead, it can be located directly above or near the virtual gate 300, thereby making the layout of the entire semiconductor device more compact, saving space, and facilitating miniaturization design.

[0048] In this embodiment, the first portion 131 and the second portion 132 of the first gate material 100 are both connected to the first contact hole 400. Through these contact holes, the polysilicon layer and the metal electrode are electrically connected to ensure the normal operation of the gate 200.

[0049] In one embodiment, such as Figure 1As shown, there are multiple gates 200. Adjacent gates 200 form a group of gate components 210. At least one dummy gate 300 is provided between every two groups of gate components 210. It is understood that the semiconductor device also includes at least one gate component 210, which may include multiple parallel gates 200. Optionally, each gate component 210 includes two gates 200, thus forming a gate-virtual gate-gate-gate-virtual gate-gate… structure. Each gate-virtual gate-gate can be considered a gate unit. Each device may have one or more gate units, depending on the specific requirements. It should be explained that the gate 200, as a core control component, is responsible for controlling the opening and closing of the channel. However, at the nanoscale, short-channel effects and leakage current problems become particularly severe, and relying solely on the main gate 200 is insufficient to completely solve these problems. The introduction of the dummy gate 300, by providing an additional control point in the channel region, allows for more precise adjustment of the electric field distribution in the channel region. Specifically, multiple virtual gates 300 can form a denser electric field control network, ensuring more uniform conduction in the channel region during the on-state and less leakage current during the off-state, thereby improving the switching characteristics and overall performance of the device.

[0050] In this embodiment, each gate assembly 210 includes multiple gates 200 arranged in parallel with each other, and the gate assembly 210 and the dummy gate 300 are arranged in parallel. This ensures the reliability and uniformity of the electrical connection, while also reducing interference between the gates 200 and the dummy gate 300, thus improving device performance. Furthermore, more gates 200 and dummy gates 300 can be integrated within a limited chip area, significantly improving the device's integration density.

[0051] In one embodiment, one end of the gate assembly 210 is disposed on a protrusion 110 in one of the first gate materials 100, and the other end of the gate assembly 210 is disposed on a correspondingly aligned protrusion 110 in another of the first gate materials 100. It is understood that if both ends of each gate 200 in the gate assembly 210 are respectively connected to the first portion 110 and the second portion 120, then it is equivalent to both ends of the gate assembly 210 being respectively connected to the first portion 110 and the second portion 120. It is understood that in this embodiment, the length of each gate 200 is greater than that of each virtual gate 300. Thus, it is possible to achieve the following: when both ends of the gate assembly 210 are respectively in contact with the first portion 110 and the second portion 120 of the first gate assembly 210, the two ends of the virtual gate 300 are spaced apart from the first portion 110 and the second portion 120 of the first gate assembly 210.

[0052] It should be noted that there is no limit to the number of gate components 210 or gates 200 in gate components 210. There can be one or more gate components 210, and there can be two gates 200 in each gate component 210. There is also no limit to the number of virtual gate components 310 or virtual gates 300 in virtual gate components 310. There can be one or more virtual gate components 310, and there can also be one or more virtual gates 300 in each virtual gate component 310.

[0053] In one embodiment, such as Figure 1 As shown, there are multiple virtual gates, and adjacent virtual gates form a group of virtual gate assemblies; each virtual gate assembly is connected to at least one second contact hole.

[0054] It is understood that each virtual gate assembly 310 may include multiple virtual gates 300. When multiple virtual gates 300 are included, in order to cover the entire width direction of the virtual gate assembly 310, the area of ​​the two second contact holes 500 needs to be increased to cover the entire width direction of the virtual gate assembly 310. It is understood that the area of ​​the second contact hole 500 in this embodiment can be relatively large, that is, the area of ​​the second contact hole 500 can be designed according to the width of the virtual gate 300. In this case, the width design of the virtual gate 300 is no longer restricted, and the virtual gate 300 can be designed arbitrarily to enhance the function of the virtual gate 300. However, it should be noted that when the area of ​​the second contact hole 500 is too large, it may have a different etching rate than other contact holes in the process (such as the contact hole between the virtual gate 300 and the gate 200), which may affect the performance of the semiconductor device.

[0055] In one embodiment, such as Figure 1 As shown, the two ends of the virtual gate assembly 310 are respectively connected to the two second contact holes 500. After the two second contact holes 500 are connected to the virtual gate assembly 310, they are respectively disposed in the two relief recesses 120. In one embodiment, as... Figure 2 As shown, the virtual gate 300 is connected to a second contact hole 500, which can be adapted to the shape and size of the virtual gate assembly 310.

[0056] Optionally, the virtual gate component 310 has multiple virtual gates 300, and the gate component 210 has multiple gates 200. It should be explained that a single gate 200 and virtual gate 300 design has limitations in high-density integration, especially at the nanoscale, where short-channel effects and leakage current problems become more severe. Therefore, by forming gate components 210 and 310 with multiple parallel gates 200 and virtual gates 300 respectively, these problems can be effectively solved. The parallelism of the gates 200 and virtual gates 300 within each gate component 210 and virtual gate component 310 ensures the reliability and uniformity of the electrical connection, while also reducing interference between gates 200 and virtual gates 300, thus improving device performance. Furthermore, by forming corresponding components with multiple gates 200 and virtual gates 300, more gates 200 and virtual gates 300 can be integrated within a limited chip area, significantly improving the device's integration density.

[0057] In one embodiment, such as Figure 3 and Figure 4 As shown, the virtual gate 300 is connected to at least one second contact hole 500, and the second contact hole 500 is disposed along the length direction of the virtual gate 300. It should be explained that, unlike the previous embodiment, in this embodiment each virtual gate 200 is connected to at least one second contact hole 500, while in the previous embodiment, one virtual gate assembly 310 was connected to at least one second contact hole 500.

[0058] In one embodiment, such as Figure 3 As shown, each virtual gate 300 is connected to at least two second contact holes 500, and both ends of the virtual gate 300 are respectively connected to the two second contact holes 500. It is understood that in this embodiment, each virtual gate 300 is connected to two second contact holes 500. Even in a virtual gate assembly 310 composed of multiple virtual gates 300, each virtual gate 300 in the virtual gate assembly 310 is also connected to two second contact holes. This ensures the electrical connection between each virtual gate 300 and the metal electrode without polysilicon. The spacing between the two second contact holes 500 needs to meet the minimum size requirements of the manufacturing process to prevent short circuits and increased parasitic effects. By reasonably setting the distance between the contact holes, the electrical connection of each contact hole can be ensured to be independent and reliable, reducing contact resistance and improving signal transmission efficiency.

[0059] In one embodiment, such as Figure 4As shown, the shape of the second contact hole 500 is adapted to the shape of the virtual gate 300; and / or, the size of the second contact hole 500 is adapted to the size of the virtual gate 300. It is understood that in some examples, the shape of the second contact hole 500 may be the same as the shape of the virtual gate 300, and the size of the second contact hole 500 may be the same as the size of the virtual gate 300. In other examples, the shape of the second contact hole 500 may be the same as the shape of the virtual gate 300, but the size of the second contact hole 500 is slightly smaller than, equal to, or smaller than the virtual gate 300. However, in this embodiment, the second contact hole 500 extends from one end of the virtual gate 300 to the other, that is, the size of the second contact hole 500 is slightly smaller than the virtual gate 300, and the shape of the second contact hole 500 is the same as the virtual gate 300. This ensures that the potential is uniformly distributed across the entire virtual gate 300, avoiding performance fluctuations caused by localized potential unevenness. Furthermore, the uniform potential distribution reduces the impact of external noise on the virtual gate 300, improves the device's anti-interference capability, and ensures its stable operation in complex environments. However, it should be noted that since there are also minimum size limitations between contact holes, if the second contact hole 500 covers the entire virtual gate 300, it may have a negative impact on the contact hole between the virtual gate 300 and the gate 200, affecting the performance of the semiconductor device.

[0060] In one embodiment, such as Figure 5 As shown, the semiconductor device further includes a second gate material 600, which is connected to a second contact hole 500. The second gate material 600 is disposed in the virtual gate forming region 142, and the second gate material 600 and the first gate material 100 are separated by a first preset distance. The virtual gate 300 is connected to the second gate material 600 and is formed on the second gate material. It can be understood that in this embodiment, the virtual gate forming region 142 contains the second gate material 600, and the insulating material corresponding to the position of the second gate material 600 is etched with a second contact hole 500. The second gate material 600 is connected to the second contact hole 500, and subsequently, the virtual gate 200 is connected to the second gate material 600, thus achieving electrical connection with the metal electrode through the second contact hole 500. In this embodiment, the second gate material 600 can be the same as or different from the first gate material 100; the specific choice depends on the device's performance requirements and manufacturing process compatibility.

[0061] Furthermore, the second gate material 600 and the first gate material 100 are spaced apart by a first preset distance. This first preset distance can be determined according to the actual application. Exceeding this first preset distance can avoid mutual interference between the first gate material 100 and the second gate material 600, thus ensuring sufficient electrical isolation between the virtual gate 300 and the normal gate 200 and avoiding the risk of short circuits. The second gate material 600 can be located in the virtual gate forming region 142 outside the corresponding avoidance recess 120, thereby achieving a first preset distance between it and the first gate material 100, reducing the overall size of the device and achieving a more compact layout design. Thus, the present invention provides a solution for the application requirement that the virtual gate 300 needs to be connected to the second gate material 600, achieving miniaturization while connecting the second gate material 600.

[0062] Furthermore, by placing the dummy gate 300 and the second gate assembly 210 within the dummy gate formation region 142, it is ensured that the dummy gate 300 and the second gate material 600 are kept away from the transition region 700, thereby avoiding the influence of electric field fluctuations in the transition region 700 on the dummy gate 300 and the second gate material 600. This improves the stability and reliability of the device, reduces leakage current caused by electric field fluctuations, and further optimizes the switching characteristics and overall performance of this semiconductor device.

[0063] In one embodiment, such as Figure 5 As shown, each virtual gate assembly 310 has a second gate material 600 connected to both ends, thus each virtual gate assembly 310 has two second gate materials 600 connected. The size of the second gate material 600 can be determined according to the width of the virtual gate assembly 310. It is necessary to ensure that the second gate material 600 completely covers one end of the virtual gate assembly 310. In this way, effective electrical connection in the semiconductor device can be guaranteed, thereby ensuring the performance of the semiconductor device.

[0064] In this embodiment, as Figure 5As shown, the virtual gate assembly 310 has a second gate material 600 connected to each of its two ends. The second gate material 600 is located in the virtual gate forming region 142 outside the avoidance recess 120. The virtual gate assembly 310 is connected to two second contact holes 500, which are spaced apart. This ensures a reliable electrical connection between the virtual gate assembly 310 and the metal electrode. Furthermore, the two second contact holes 500 are located at opposite ends of the virtual gate assembly 310, ensuring the stability of the electrical connection. In addition, the two spaced-apart second contact holes 500 provide better current distribution, reduce contact resistance, thereby reducing power consumption and improving device performance. This design also ensures that each virtual gate assembly 310 has sufficient electrical connection points in high-density integration, avoiding performance degradation due to poor contact.

[0065] It should be noted that the specific location of the second contact hole 500 is not limited, as long as it can ensure that each virtual gate assembly 310 and the virtual components in each virtual gate assembly 310 can achieve good electrical connection with the metal electrode.

[0066] In this embodiment, the virtual gate assembly 310 is connected to the second contact hole 500 at both ends. The virtual gate assembly 310 is disposed after the virtual gate forming region 142, and the two second contact holes 500 are respectively disposed in the two corresponding avoidance recesses 120 in the virtual gate forming region 142.

[0067] In one embodiment, such as Figure 1 As shown, the first gate material 100 is square in shape, and the protrusions 110 of the first gate material 100 are also square. Multiple protrusions 110 form multiple square gate forming regions 141 and square dummy gate forming regions 142. It is understood that the square shape of the first gate material 100 and the protrusions 110 makes the shapes of the gate forming regions 141 and dummy gate forming regions 142 more regular, facilitating precise etching and control. The square protrusions 110 can provide a larger contact area, ensuring good contact between the gate 200 and the first gate material 100, thereby improving the reliability of the electrical connection. Furthermore, the square forming region design makes the layout of the dummy gate 300 and the gate 200 more regular, reducing errors in the manufacturing process and improving the yield.

[0068] In the above embodiments, by combining the square gate forming region 141 and the square virtual gate forming region 142 with the above-mentioned gate 200 and virtual gate 300, the limited chip area can be fully utilized, achieving higher integration and a more compact layout.

[0069] In the above embodiments, such as Figure 1 As shown, the gate assembly 210 includes two parallel gates 200, and the virtual gate assembly 310 includes three parallel virtual gates 300. It can be understood that the virtual gate assembly 310 is provided at the adjacent positions of each gate 200, and the sequence of gate 200-virtual gate 300-virtual gate 300-virtual gate 300-gate 200 is defined as a gate unit.

[0070] The present invention also provides a power module, which includes at least one semiconductor device. The specific structure of the semiconductor device is as described in the above embodiments. Since the present electronic device adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought about by the technical solutions of the above embodiments, which will not be described in detail here.

[0071] In this embodiment, the number of semiconductor devices in the power module can be one, four, six, or more; the specific number is not limited. It is understood that when there is one semiconductor device, it can be used as a switching transistor; when there are four, the four semiconductor devices can be used as an H-bridge and a unidirectional inverter, for bidirectional driving of DC motors, stepper motor control, etc.; when there are six, the six semiconductor devices can be used as a three-phase rectifier circuit or a three-phase inverter. Of course, the application and function of the semiconductor device in the power module are not limited. Importantly, after applying the semiconductor device proposed in this invention, the power module can also achieve a miniaturized design because the semiconductor device facilitates miniaturization. Moreover, because the semiconductor device allows for miniaturization, more semiconductor devices can be integrated without changing the size of the power module.

[0072] The present invention also proposes an electronic device, which includes a semiconductor device or a power module. The specific structure of the semiconductor device and the power module is as described in the above embodiments. Since the electronic device adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought about by the technical solutions of the above embodiments, which will not be described in detail here.

[0073] Optionally, the electronic device includes a circuit board on which the semiconductor device is integrated. Integrating the semiconductor device onto the circuit board enables high integration and miniaturization, improving the overall performance and reliability of the electronic device. This allows the electronic device to process signals more efficiently, reduce power consumption, and improve response speed, making it suitable for high-performance computing, communications, and consumer electronics. Alternatively, the circuit board may integrate a power module on which the semiconductor device is integrated. Integrating the semiconductor device into the power module allows for a higher level of integration and optimization. This allows the power module to provide higher performance and lower power consumption in a smaller size, suitable for applications such as motor drives, power management, and industrial automation.

[0074] Optionally, the electronic device may include household appliances, such as water heaters, air conditioners, washing machines, refrigerators, and cleaning machines; the electronic device may also be a smartphone, laptop, or smart wearable device. Specific application scenarios are not limited; the focus is on this semiconductor device, which facilitates miniaturization design.

[0075] The above description is merely an exemplary embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structural transformations made using the contents of the present invention specification and drawings under the technical concept of the present invention, or direct / indirect applications in other related technical fields, are included within the patent protection scope of the present invention.

Claims

1. A semiconductor device, characterized in that, The semiconductor device includes: A first gate material, the first gate material being connected to a first contact hole, the first gate material having at least two protrusions, and the two protrusions being spaced apart to form a clearance recess; A gate, wherein the gate portion is formed on the protrusion of the first gate material, and the gate is electrically connected to a metal electrode through the first contact hole; A virtual gate, at least partially formed in the relief recess and spaced apart from the gate and the first gate material, is connected to a second contact hole and is electrically connected to a metal electrode through the second contact hole.

2. The semiconductor device as claimed in claim 1, characterized in that, The first gate material has a first part and a second part, the first part and the second part of the first gate material are spaced apart along a first direction, and the first part and the second part are provided with a plurality of protrusions facing each other, and the protrusions of the first part and the protrusions of the second part are aligned one by one. A gate forming region is provided between two mutually aligned protrusions in the first part, and a virtual gate forming region is provided between two mutually aligned recesses in the two first gate materials; the gate is arranged along the length direction of the gate forming region, and the virtual gate is arranged along the length direction of the virtual gate forming region.

3. The semiconductor device as described in claim 2, characterized in that, The difference between the lengths of the gate and the virtual gate is less than a first preset difference.

4. The semiconductor device as claimed in claim 1, characterized in that, The number of gates is multiple, and among the multiple gates, adjacent gates form a group of gate components; At least one virtual gate is provided between every two groups of the gate components.

5. The semiconductor device according to any one of claims 1 to 4, characterized in that, The number of virtual gates is multiple, and adjacent virtual gates form a group of virtual gate components; Each of the virtual gate components is connected to at least one of the second contact holes.

6. The semiconductor device as claimed in claim 5, characterized in that, The two ends of the virtual gate assembly are respectively connected to the two second contact holes, and the two contact holes are respectively located in the two avoidance recesses after being connected to the virtual gate assembly.

7. The semiconductor device according to any one of claims 1 to 4, characterized in that, The virtual gate is connected to at least one second contact hole, and the second contact hole is disposed along the length direction of the virtual gate.

8. The semiconductor device as claimed in claim 7, characterized in that, The shape of the second contact hole is adapted to the shape of the virtual gate; And / or, the size of the second contact hole is adapted to the size of the virtual gate.

9. The semiconductor device as claimed in claim 3, characterized in that, The semiconductor device further includes a second gate material, the second gate material being connected to the second contact hole, the second gate material being disposed in the virtual gate forming region, and the second gate material and the first gate material being disposed at a first preset distance apart; the virtual gate and the second gate material are connected. The virtual gate is formed in the second gate material.

10. The semiconductor device as claimed in claim 9, characterized in that, The number of virtual gates is multiple, and adjacent virtual gates form a group of virtual gate components; The virtual gate assembly is connected to at least one of the second gate materials.

11. The semiconductor device as claimed in claim 10, characterized in that, The virtual gate assembly is connected to a second gate material at each end, and the second gate material is disposed in the virtual gate forming region at a position other than the avoidance recess.

12. The semiconductor device as claimed in claim 3, characterized in that, The first gate material is square in shape, and the protrusions of the first gate material are square. The protrusions form a plurality of square gate forming regions and square virtual gate forming regions.

13. A power module, characterized in that, The power module integrates at least one semiconductor device as described in any one of claims 1 to 12.

14. An electronic device, characterized in that, The electronic device includes: The semiconductor device as described in any one of claims 1 to 12; and / or, The power module as described in claim 13.

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