Semiconductor devices and manufacturing methods thereof

Abstract

This invention relates to a semiconductor device and a method for manufacturing a semiconductor device. The objective is to suppress the reduction of field-effect mobility in a semiconductor device comprising an oxide semiconductor layer. The semiconductor device includes: a first gate electrode; a first insulating layer above the first gate electrode; a first oxide semiconductor layer above the first insulating layer; a second oxide semiconductor layer above and in contact with the first oxide semiconductor layer; a source electrode and a drain electrode in contact with end faces of the first and second oxide semiconductor layers, respectively; and a second insulating layer covering the source and drain electrodes. The second oxide semiconductor layer includes a first region having a first film thickness and a second region having a second film thickness less than the first film thickness. The upper surface of the first region is in contact with one of the source and drain electrodes.

Description

Technical Field

[0001] One embodiment of the present invention relates to a semiconductor device using oxide semiconductors. Another embodiment of the present invention relates to a method for manufacturing a semiconductor device using oxide semiconductors. Background Technology

[0002] In recent years, the development of semiconductor devices using oxide semiconductor films has been continuously advancing, replacing silicon semiconductor films such as amorphous silicon, low-temperature polycrystalline silicon, and monocrystalline silicon (see, for example, Patent Documents 1 to 6). Semiconductor devices containing oxide semiconductor films have a similarly simple structure as semiconductor devices containing amorphous silicon films and can be manufactured using low-temperature processes. Furthermore, semiconductor devices containing oxide semiconductor films are known to have higher field-effect mobility than semiconductor devices containing amorphous silicon films.

[0003] Existing technical documents Patent documents Patent Document 1: Japanese Patent Application Publication No. 2021-141338 Patent Document 2: Japanese Patent Application Publication No. 2014-099601 Patent Document 3: Japanese Patent Application Publication No. 2021-153196 Patent Document 4: Japanese Patent Application Publication No. 2018-006730 Patent Document 5: Japanese Patent Application Publication No. 2016-184771 Patent Document 6: Japanese Patent Application Publication No. 2021-108405 Summary of the Invention

[0004] The problem that the invention aims to solve In the formation of source and drain electrodes, in semiconductor devices with so-called channel etch structures where an oxide semiconductor layer is etched, the desired electrical characteristics are sometimes not obtained due to the influence of the etched back channel. Therefore, it is desirable to suppress the reduction of field-effect mobility in semiconductor devices containing an oxide semiconductor layer and having a channel etch structure.

[0005] In view of the above problems, an embodiment of the present invention aims to suppress the reduction of field-effect mobility in a semiconductor device comprising an oxide semiconductor layer and having a channel etch structure.

[0006] Methods for solving problems An embodiment of the present invention relates to a semiconductor device comprising: a first gate electrode; a first insulating layer above the first gate electrode; a first oxide semiconductor layer above the first insulating layer; a second oxide semiconductor layer above the first oxide semiconductor layer and in contact with the first oxide semiconductor layer; a source electrode and a drain electrode in contact with the respective end faces of the first oxide semiconductor layer and the second oxide semiconductor layer; and a second insulating layer covering the source electrode and the drain electrode, the second oxide semiconductor layer comprising a first region having a first film thickness and a second region having a second film thickness less than the first film thickness, the upper surface of the first region being in contact with one of the source electrode and the drain electrode, and the upper surface of the second region being in contact with the second insulating layer.

[0007] An embodiment of the present invention relates to a method for manufacturing a semiconductor device, comprising: forming a first gate electrode on a substrate; forming a first insulating layer on the first gate electrode; forming a first oxide semiconductor layer on the first insulating layer; forming a second oxide semiconductor layer in contact with the first oxide semiconductor layer; patterning the first oxide semiconductor layer and the second oxide semiconductor layer together such that the first oxide semiconductor layer and the second oxide semiconductor layer have island shapes of substantially the same size; performing heat treatment on the first oxide semiconductor layer and the second oxide semiconductor layer; forming a source electrode and a drain electrode in contact with the respective end faces of the first oxide semiconductor layer and the second oxide semiconductor layer, thereby forming a first region having a first film thickness and a second region having a second film thickness less than the first film thickness in the second oxide semiconductor layer; forming a second insulating layer in a manner that covers the source electrode and the drain electrode, wherein the upper surface of the first region is in contact with one of the source electrode and the drain electrode, and the upper surface of the second region is in contact with the second insulating layer. Attached Figure Description

[0008] [ Figure 1 [Illustrated view] is a schematic cross-sectional view showing the configuration of a semiconductor device according to an embodiment of the present invention.

[0009] [ Figure 2 [This is a schematic enlarged cross-sectional view illustrating the configuration of a semiconductor device according to an embodiment of the present invention.]

[0010] [ Figure 3 [Illustrated view] is a schematic top view showing the configuration of a semiconductor device according to an embodiment of the present invention.

[0011] [ Figure 4 [Illustrated view] is a schematic top view showing the configuration of a semiconductor device according to an embodiment of the present invention.

[0012] [ Figure 5 [Illustrated view] is a schematic top view showing the configuration of a semiconductor device according to an embodiment of the present invention.

[0013] [ Figure 6 [ ] is a flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0014] [ Figure 7 [ ] is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0015] [ Figure 8 [ ] is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0016] [ Figure 9 [ ] is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0017] [ Figure 10 [ ] is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0018] [ Figure 11 [ ] is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0019] [ Figure 12 [ ] is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0020] [ Figure 13 [ ] is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0021] [ Figure 14 [ ] is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0022] Explanation of reference numerals in the attached figures 100: Substrate 110: Gate electrode 1 120: First Insulation Layer 122: Nitride insulating film 124: Oxide insulating film 130: First oxide semiconductor layer 140: Second oxide semiconductor layer 142: Area 1 144: Area 2 150: Source electrode 160: Drain electrode 170: Second Insulation Layer 172: Oxide insulating film 174: Nitride insulating film 180: Second gate electrode Detailed Implementation

[0023] The following description, with reference to the accompanying drawings, outlines various embodiments of the present invention. The following disclosure is merely illustrative. Configurations readily conceived by those skilled in the art, while maintaining the spirit of the invention, through appropriate modifications to the embodiments, are naturally included within the scope of the present invention. Regarding the drawings, to make the description clearer, the width, thickness, and shape of the constituent elements are sometimes schematically shown compared to the actual embodiment. However, the shapes illustrated are merely examples and do not limit the interpretation of the present invention. In this specification and the accompanying drawings, for constituent elements identical to those described with respect to previously presented drawings, there are instances where the same reference numerals are used and detailed descriptions are appropriately omitted.

[0024] In this specification, the direction from the substrate toward the oxide semiconductor layer is referred to as "up" or "above." Conversely, the direction from the oxide semiconductor layer toward the substrate is referred to as "down" or "below." For ease of explanation, the terms "up" or "below" are used, but the vertical relationship between the substrate and the oxide semiconductor layer can also be configured as the opposite of the illustration. Furthermore, the phrase "oxide semiconductor layer on the substrate" simply describes the vertical relationship between the substrate and the oxide semiconductor layer; other components may be arranged between the substrate and the oxide semiconductor layer. "Up" or "below" refers to the stacking order in a structure composed of multiple layers. When described as "pixel electrode above the semiconductor device," it can also refer to the non-overlapping position of the semiconductor device and the pixel electrode when viewed from above. On the other hand, when described as "pixel electrode vertically above the semiconductor device," it refers to the overlapping position of the semiconductor device and the pixel electrode when viewed from above. It should be noted that "viewing from above" refers to viewing from a direction perpendicular to the surface of the substrate.

[0025] In this specification and other documents, unless otherwise specified, statements such as "α includes A, B, or C", "α includes any one of A, B, and C", and "α includes one of the groups selected from A, B, and C" do not exclude the possibility that α includes multiple combinations of A to C. Furthermore, these statements do not exclude the possibility that α includes other constituent elements.

[0026] In this specification and the like, the term "semiconductor device" refers to any device capable of functioning by utilizing the characteristics of semiconductors. Transistors and semiconductor circuits are included in one type of semiconductor device. The semiconductor device in the embodiments shown below may also be, for example, a transistor that can be used in integrated circuits (ICs) such as display devices, microprocessors (MPUs), or memory circuits.

[0027] In this specification and the like, the term "display device" refers to a structure that displays images using an electro-optical layer. For example, the term "display device" sometimes refers to a display panel that includes an electro-optical layer, or sometimes refers to a structure on which other optical components (e.g., polarizing components, backlights, touch panels, etc.) are mounted. The term "electro-optical layer" can include liquid crystal layers, electroluminescent (EL) layers, electrochromic (EC) layers, and electrophoretic layers, provided there is no technical contradiction. Therefore, in this embodiment, a liquid crystal display device including a liquid crystal layer and an organic EL display device including an organic EL layer are described as examples of display devices. However, the structure described in the embodiment can be applied to display devices that include the other electro-optical layers mentioned above.

[0028] In this specification and other materials, the term "membrane" and the term "layer" may be used interchangeably as appropriate.

[0029] Regarding the source and drain electrodes of a transistor, their functions are sometimes interchangeable depending on the voltage supplied to each electrode. Therefore, in this specification and the like, the terms "source electrode" and "drain electrode" can be used interchangeably depending on the situation. Similarly, in this specification and the like, the terms "source region" and "drain region" can be used interchangeably depending on the situation.

[0030] It should be noted that the following implementation methods can be combined with each other as long as there is no technical contradiction.

[0031] [1. Configuration of semiconductor device 10] Figure 1 This is a schematic cross-sectional view illustrating the configuration of a semiconductor device 10 according to an embodiment of the present invention.

[0032] like Figure 1As shown, the semiconductor device 10 includes a substrate 100, a first gate electrode 110, a first insulating layer 120, a first oxide semiconductor layer 130, a second oxide semiconductor layer 140, a source electrode 150, a drain electrode 160, a second insulating layer 170, and a second gate electrode 180. The first gate electrode 110 is disposed on the substrate 100. The first insulating layer 120 covers the first gate electrode 110 and is disposed on the substrate 100. The first oxide semiconductor layer 130 overlaps with the first gate electrode 110 and is disposed on the first insulating layer 120. The second oxide semiconductor layer 140 overlaps with the first gate electrode 110 and is disposed on the first oxide semiconductor layer 130. The source electrode 150 and the drain electrode 160 are connected to the first oxide semiconductor layer 130 and the second oxide semiconductor layer 140 and are disposed on the first insulating layer 120. The second insulating layer 170 covers the first oxide semiconductor layer 130, the second oxide semiconductor layer 140, the source electrode 150, and the drain electrode 160 and is disposed on the first insulating layer 120. The second gate electrode 180 overlaps with the first gate electrode 110, the first oxide semiconductor layer 130, and the second oxide semiconductor layer 140 and is disposed on the second insulating layer 170.

[0033] The first insulating layer 120 and the second insulating layer 170 function as gate insulating layers. In the semiconductor device 10, the first gate electrode 110 is located below the first oxide semiconductor layer 130 and the second oxide semiconductor layer 140, separated by the first insulating layer 120, and the second gate electrode 180 is located above the first oxide semiconductor layer 130 and the second oxide semiconductor layer 140, separated by the second insulating layer 170. That is, the semiconductor device 10 is a so-called dual-gate transistor. Different voltages can be applied to the first gate electrode 110 and the second gate electrode 180, or the first gate electrode 110 and the second gate electrode 180 can be electrically connected and the same voltage can be applied.

[0034] Figure 1 The semiconductor device 10 shown is a dual-gate transistor, but in this embodiment, a so-called bottom-gate transistor, in which only the first gate electrode 110 is located below the first oxide semiconductor layer 130 and the second oxide semiconductor layer 140 through the first insulating layer 120, can also be used as the semiconductor device 10.

[0035] [2. Components of the Semiconductor Device 10] [2-1.Substrate 100] As substrate 100, a rigid substrate with light transmittance, such as a glass substrate, quartz substrate, or sapphire substrate, can be used. Alternatively, a rigid substrate without light transmittance, such as a silicon substrate, can also be used as substrate 100. Furthermore, a flexible substrate with light transmittance, such as a polyimide resin substrate, acrylic resin substrate, siloxane resin substrate, or fluororesin substrate, can be used as substrate 100. To improve the heat resistance of substrate 100, impurities can be introduced into the aforementioned flexible substrate. It should be noted that a substrate on which an oxide insulating film or a nitride insulating film is formed on the aforementioned rigid or flexible substrate can also be used as substrate 100. As an oxide insulating film, silicon oxide (SiO₂) can be used. x ) or silicon nitride (SiO) x N y Additionally, silicon nitride (SiN) can be used as a nitride insulating film. x ) or silicon nitride (SiN) x O y ), etc. Here, SiO x N y SiN is a silicon compound containing nitrogen (N) in a ratio less than that of oxygen (O) (x>y). x O y It is a silicon compound containing oxygen in a ratio less than that of nitrogen (x>y).

[0036] [2-2. First gate electrode 110 and second gate electrode 180] Each of the first gate electrode 110 and the second gate electrode 180 may be made of metallic materials such as aluminum (Al), copper (Cu), titanium (Ti), molybdenum (Mo), or tungsten (W), or alloys thereof. An alloy may be, for example, molybdenum-tungsten (MoW), but is not limited thereto. The first gate electrode 110 and the second gate electrode 180 may have a single-layer structure or a multilayer structure.

[0037] The first gate electrode 110 or the second gate electrode 180 can also function as a light-shielding film. In this case, it is preferable that the first gate electrode 110 or the second gate electrode 180 overlaps entirely with the first oxide semiconductor layer 130 and the second oxide semiconductor layer 140 when viewed from above.

[0038] [2-3. First insulating layer 120 and second insulating layer 170] The first insulating layer 120 and the second insulating layer 170 may each have a single-layer structure, but are preferably stacked structures. The first insulating layer 120 preferably has a stacked structure in which an oxide insulating film 124 is stacked on top of a nitride insulating film 122. In this case, the nitride insulating film 122 is connected to the first gate electrode 110, and the oxide insulating film 124 is connected to the first oxide semiconductor layer 130. Furthermore, the second insulating layer 170 preferably has a stacked structure in which a nitride insulating film 174 is stacked on top of an oxide insulating film 172. In this case, the oxide insulating film 172 is connected to the end face of the first oxide semiconductor layer 130, and the end face and upper surface of the second oxide semiconductor layer 140, and the nitride insulating film 174 is connected to the second gate electrode 180. Silicon oxide (SiO2) can be used as the oxide insulating films 124 and 172. x ) or silicon nitride (SiO) x N y Furthermore, silicon nitride (SiN) can be used as nitride insulating films 122 and 174. x ) or silicon nitride (SiN) x O y For example, the thickness of the first insulating layer 120 is 100 nm or more and 900 nm or less, preferably 200 nm or more and 600 nm or less. When the first insulating layer 120 has such a large thickness, the carrier concentration induced in the first oxide semiconductor layer 130 by the gate voltage of the first gate electrode 110 becomes smaller.

[0039] [2-4. Source electrode 150 and drain electrode 160] The source electrode 150 and drain electrode 160 can be made of the same metal material as the first gate electrode 110 and the second gate electrode 180. The source electrode 150 and drain electrode 160 can have a single-layer structure or a multilayer structure. The source electrode 150 and drain electrode 160 are connected not only to the first oxide semiconductor layer 130, but also to the second oxide semiconductor layer 140.

[0040] [2-5. First oxide semiconductor layer 130 and second oxide semiconductor layer 140] The semiconductor device 10 includes a stacked structure on which a second oxide semiconductor layer 140 is stacked on top of a first oxide semiconductor layer 130. (Refer to...) Figure 2 Provide details about the layered structure.

[0041] Figure 2 This is a schematic enlarged cross-sectional view illustrating the configuration of a semiconductor device 10 according to an embodiment of the present invention. Specifically, Figure 2 It is Figure 1 A magnified cross-sectional view of the semiconductor device 10 in region A.

[0042] At least a portion of the end faces of the first oxide semiconductor layer 130 and the second oxide semiconductor layer 140 are covered by the source electrode 150 or the drain electrode 160. A recess is formed on the upper surface of the second oxide semiconductor layer 140, which includes a first region 142 and a second region 144 with different film thicknesses. The first region 142 and the second region 144 have a first film thickness t1 and a second film thickness t2, respectively. The second film thickness t2 is less than the first film thickness t1. The upper surface of the first region 142 is in contact with and covered by the source electrode 150 or the drain electrode 160. The upper surface of the second region 144 is in contact with and covered by the second insulating layer 170 (more specifically, an oxide insulating film 172). In other words, the first region 142 overlaps with the source electrode 150 or the drain electrode 160, while the second region 144 does not overlap with the source electrode 150 or the drain electrode 160.

[0043] As detailed later, during the patterning of the source electrode 150 and drain electrode 160, the upper surface of the second oxide semiconductor layer 140 is etched to form a recess. Thus, the second region 144 has a second film thickness t2 that is smaller than the first film thickness t1. For example, the first film thickness t1 corresponds to the film thickness during the formation of the second oxide semiconductor layer 140. The first film thickness t1 is 20 nm to 200 nm, preferably 20 nm to 150 nm, and more preferably 20 nm to 100 nm. If the first film thickness t1 is too small, the second region 144 will disappear during the patterning of the source electrode 150 and drain electrode 160, exposing the first oxide semiconductor layer 130. If the first film thickness t1 is too large, not only the formation of the second oxide semiconductor layer 140 but also the patterning of the second oxide semiconductor layer 140 will take longer. The second film thickness t2 can be controlled by the over-etching time during the patterning of the source electrode 150 and drain electrode 160. The second film thickness t2 only needs to be sufficient to cover the upper surface of the first oxide semiconductor layer 130. For example, the second film thickness t2 is greater than 0 nm and less than 100 nm, preferably more than 5 nm and less than 70 nm, and more preferably more than 5 nm and less than 50 nm. If the second film thickness t2 is too large, the oxygen defects in the second region 144 cannot be sufficiently repaired, and the conductivity of the second region 144 becomes high.

[0044] Figures 3-5 This is a schematic top view illustrating the configuration of a semiconductor device according to an embodiment of the present invention. Specifically, Figures 3-5 The diagram shows a second oxide semiconductor layer 140, and a source electrode 150 and a drain electrode 160 that overlap with the second oxide semiconductor layer 140.

[0045] The source electrode 150 and the drain electrode 160 can each be formed in such a way that they completely cover one side of the second oxide semiconductor layer 140 (see [reference]). Figure 3 In this case, the second region 144 is formed between the source electrode 150 and the drain electrode 160 (i.e., between the two first regions 142). Additionally, the source electrode 150 and the drain electrode 160 can each be formed in such a way that they cover a portion of one side of the second oxide semiconductor layer 140 (see [reference]). Figure 4 In this case, the second region 144 is formed not only between the source electrode 150 and the drain electrode 160 (i.e., between the two first regions 142), but also around the source electrode 150 and the drain electrode 160. Alternatively, the source electrode 150 and the drain electrode 160 can be formed by forming multiple second regions 144-1 and 144-2 (see [link to documentation]). Figure 5 In this case, a second region 144-1 is formed between the source electrode 150 and the drain electrode 160 (i.e., between the two first regions 142), and a second region 144-2 is formed on the outer side of the source electrode 150 and the drain electrode, respectively.

[0046] The first oxide semiconductor layer 130 contains indium (In).

[0047] Preferably, the second oxide semiconductor layer 140 also contains indium. The proportion of indium relative to all metal elements in the second oxide semiconductor layer 140 is less than the proportion of indium relative to all metal elements in the first oxide semiconductor layer 130. Furthermore, it is preferable that the second oxide semiconductor layer 140 contains metal elements not present in the first oxide semiconductor layer.

[0048] The third film thickness t3 of the first oxide semiconductor layer 130 is not particularly limited. For example, the third film thickness t3 is 15 nm to 150 nm, preferably 15 nm to 125 nm, and more preferably 15 nm to 100 nm. If the third film thickness t3 is too large, oxygen defects in the first oxide semiconductor layer 130 may not be reduced, and the desired electrical characteristics may not be obtained.

[0049] Preferably, the third film thickness t3 is greater than the second film thickness t2. If the third film thickness t3 is greater than the second film thickness t2, the main channel is formed in the first oxide semiconductor layer 130, thus increasing the field-effect mobility. Alternatively, the third film thickness t3 can be less than the first film thickness t1. Or, the third film thickness t3 can be greater than the thickness difference between the first film thickness t1 and the second film thickness t2. In this case, the number of electrons injected into the first region 142 from the source electrode 150 increases and flows through the first oxide semiconductor layer 130, thus improving the field-effect mobility.

[0050] A transistor whose upper surface (sometimes called the back channel) of the oxide semiconductor layer is etched is called a channel-etched transistor. That is, in the case of semiconductor device 10, by providing a second oxide semiconductor layer 140 with a lower indium content than the first oxide semiconductor layer 130 on the back channel side of the first oxide semiconductor layer 130, the influence of the back channel can be reduced and the decrease in field-effect mobility can be suppressed.

[0051] [3. Method for manufacturing semiconductor device 10] Figure 6 This is a flowchart illustrating a method for manufacturing a semiconductor device 10 according to an embodiment of the present invention. Figures 7-14 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device 10 according to an embodiment of the present invention. The following description will proceed sequentially. Figure 6 The flowchart shown illustrates each step.

[0052] In step S100, a first gate electrode 110 is formed on the substrate 100 (see...). Figure 7 The first gate electrode 110 is formed by sputtering a conductive film and then patterning it into a specified shape using photolithography.

[0053] In step S110, a first insulating layer 120 is formed on the first gate electrode 110 (see...). Figure 8 In the case where the first insulating layer 120 has a laminated structure, the first insulating layer 120 is formed by forming a nitride insulating film 122 and an oxide insulating film 124 using CVD.

[0054] In step S120, a first oxide semiconductor layer 130 is formed on the first insulating layer 120 (see...). Figure 9 The first oxide semiconductor layer 130 is formed by sputtering.

[0055] When sputtering is used to form a film on a target object, the temperature of the target object rises as the film forming process occurs due to collisions between ions generated in the plasma and atoms ejected from the sputtering target.

[0056] In the sputtering process, a first oxide semiconductor layer 130 with an amorphous structure is formed under conditions where the oxygen partial pressure is below 10%.

[0057] In step S130, a second oxide semiconductor layer 140 is formed on the first oxide semiconductor layer 130 (see [link]). Figure 10 The second oxide semiconductor layer 140 is formed by sputtering.

[0058] In step S140, the first oxide semiconductor layer 130 and the second oxide semiconductor layer 140 are patterned together (see...). Figure 11 The first oxide semiconductor layer 130 and the second oxide semiconductor layer 140 are formed using photolithography in a stacked structure having an island shape. For example, a resist mask (not shown) is formed on the second oxide semiconductor layer 140, and the second oxide semiconductor layer 140 and the first oxide semiconductor layer 130 are etched sequentially using the resist mask. Thus, the first oxide semiconductor layer 130 and the second oxide semiconductor layer 140 have island shapes of approximately the same size. The etching of the first oxide semiconductor layer 130 and the second oxide semiconductor layer 140 can be performed using wet etching or dry etching. As wet etching, an acidic etchant can be used. Examples of etchants include oxalic acid, PAN, sulfuric acid, hydrogen peroxide, or hydrofluoric acid.

[0059] In step S150, the first oxide semiconductor layer 130 and the second oxide semiconductor layer 140 are subjected to heat treatment (OS annealing) (see...). Figure 12 In OS annealing, the first oxide semiconductor layer 130 and the second oxide semiconductor layer 140 are held at a predetermined arrival temperature for a predetermined time. The predetermined arrival temperature is 300°C to 500°C, preferably 350°C to 450°C. Furthermore, the holding time at the arrival temperature is 15 minutes to 120 minutes, preferably 30 minutes to 60 minutes.

[0060] The proportion of indium relative to all metal elements in the second oxide semiconductor layer 140 is less than the proportion of indium relative to all metal elements in the first oxide semiconductor layer 130.

[0061] In step S160, a source electrode 150 and a drain electrode 160 are formed in connection with the first oxide semiconductor layer 130 and the second oxide semiconductor layer 140 (see [link]). Figure 13 The source electrode 150 and drain electrode 160 are formed by sputtering a conductive film and then patterning it into a predetermined shape using photolithography. Etching of the source electrode 150 and drain electrode 160 can be performed using either wet etching or dry etching. During etching of the source electrode 150 and drain electrode 160, the upper surface of the second oxide semiconductor layer 140 is also etched, forming a recess. Specifically, a first region 142 overlapping with the source electrode 150 or drain electrode 160 and a second region 144 not overlapping with the source electrode 150 and drain electrode 160 are formed in the second oxide semiconductor layer 140. The second region 144 corresponds to the region where the recess is formed; therefore, the second film thickness t2 of the second region 144 is less than the first film thickness t1 of the first region 142 (see [reference]). Figure 2 ).

[0062] On the upper surface of the second region 144, numerous defects are generated due to the etching of the source electrode 150 and the drain electrode 160. This is more pronounced when dry etching is used. The resist mask formed during the patterning of the source electrode 150 and the drain electrode 160 is removed using a stripping solution. At this time, the upper surface of the second region 144 is exposed to the stripping solution. As for the oxide semiconductor contained in the second oxide semiconductor layer 140, the area near the surface can be etched using the stripping solution. Therefore, in step S160, even if numerous defects are generated on the upper surface of the second region 144, the area near the surface containing numerous defects can be etched using the stripping solution. Therefore, in the semiconductor device 10, defects on the upper surface of the second region 144, i.e., the back channel, can be reduced.

[0063] In step S170, a second insulating layer 170 is formed on the source electrode 150 and the drain electrode 160 (see...). Figure 14 In the case where the second insulating layer 170 has a laminated structure, the second insulating layer 170 is formed by forming an oxide insulating film 172 and a nitride insulating film 174 using CVD.

[0064] It should be noted that in step S170, heat treatment (oxidative annealing) is preferably performed while the second insulating layer 170 covers the first oxide semiconductor layer 130 and the second oxide semiconductor layer 140. Oxidative annealing can repair oxygen defects in the first oxide semiconductor layer 130 and the second oxide semiconductor layer 140. In particular, during oxidative annealing, if the oxide insulating film 172 is in contact with the second region 144 of the second oxide semiconductor layer 140, oxygen is supplied from the oxide insulating film 172 to the second region 144, which can efficiently repair oxygen defects in the back channel. In step S170, oxidative annealing can also be performed after the oxide insulating film 172 is formed, and then the nitride insulating film 174 is formed.

[0065] Oxidative annealing can also be performed while a metal oxide film has been formed on the oxide insulating film 172. By forming a metal oxide film, the release of oxygen from the oxide insulating film 172 to the outside can be suppressed. The metal oxide film is removed after oxidative annealing. Alumina (Al₂O₃) can be used as the metal oxide film. x Indium tin oxide (ITO), indium zinc oxide (IZO), or indium gallium zinc oxide (IGZO), etc. For example, the thickness of the metal oxide film is 1 nm to 50 nm, preferably 1 nm to 30 nm.

[0066] In step S180, a second gate electrode 180 is formed on the second insulating layer 170. The second gate electrode 180 is formed by sputtering a conductive film and then patterning it into a predetermined shape using photolithography.

[0067] Through the above steps, it is possible to manufacture Figure 1 The semiconductor device 10 shown.

[0068] According to this embodiment, the decrease in field-effect mobility of the semiconductor device 10, which includes an oxide semiconductor layer and has a channel etch structure, can be suppressed. Furthermore, deviations in the electrical characteristics of the semiconductor device 10 can be reduced, thereby improving the manufacturing yield of the semiconductor device 10.

[0069] The embodiments described above as embodiments of the present invention can be appropriately combined and implemented as long as they do not contradict each other. In addition, solutions obtained by adding, deleting or designing constituent elements or adding, omitting or changing conditions based on the various embodiments by those skilled in the art are also included in the scope of the present invention as long as they possess the spirit of the present invention.

[0070] Even if other effects are different from those achieved through the above-described embodiments, if they are clearly known from the description in this specification or can be easily predicted by those skilled in the art, they shall of course be understood as effects achieved through the present invention.

Claims

1. A semiconductor device, comprising: First gate electrode; The first insulating layer above the first gate electrode; The first oxide semiconductor layer above the first insulating layer; A second oxide semiconductor layer is connected to the first oxide semiconductor layer above the first oxide semiconductor layer; The source electrode and drain electrode are connected to the respective end faces of the first oxide semiconductor layer and the second oxide semiconductor layer; and A second insulating layer covering the source electrode and the drain electrode. The second oxide semiconductor layer includes a first region having a first film thickness and a second region having a second film thickness smaller than the first film thickness. The upper surface of the first region is in contact with one of the source electrode and the drain electrode. The upper surface of the second region is in contact with the second insulating layer.

2. The semiconductor device of claim 1, wherein, The second oxide semiconductor layer has an amorphous structure.

3. The semiconductor device as claimed in claim 1, wherein, The first oxide semiconductor layer has a third film thickness. The third film thickness is greater than the second film thickness.

4. The semiconductor device of claim 3, wherein, The third film thickness is less than the first film thickness.

5. The semiconductor device as claimed in claim 3, wherein, The third film thickness is greater than or equal to the difference between the first film thickness and the second film thickness.

6. The semiconductor device of claim 1, wherein, The first oxide semiconductor layer and the second oxide semiconductor layer each contain indium. The proportion of indium relative to all metal elements in the second oxide semiconductor layer is less than the proportion of indium relative to all metal elements in the first oxide semiconductor layer.

7. The semiconductor device of claim 1, further comprising a second gate electrode above the second insulating layer.

8. The semiconductor device of claim 7, wherein, The second insulating layer has a laminated structure consisting of an oxide insulating film and a nitride insulating film. The oxide insulating film is in contact with the second oxide semiconductor layer. The nitride insulating film is connected to the second gate electrode.

9. A method for manufacturing a semiconductor device, comprising: A first gate electrode is formed on the substrate; A first insulating layer is formed on the first gate electrode; A first oxide semiconductor layer is formed on the first insulating layer; The second oxide semiconductor layer is formed in a manner that it is in contact with the first oxide semiconductor layer; The first oxide semiconductor layer and the second oxide semiconductor layer are patterned together in such a way that the first oxide semiconductor layer and the second oxide semiconductor layer have island shapes of approximately the same size; The first oxide semiconductor layer and the second oxide semiconductor layer are subjected to heat treatment; A source electrode and a drain electrode are formed in contact with the end faces of the first oxide semiconductor layer and the second oxide semiconductor layer, thereby forming a first region having a first film thickness and a second region having a second film thickness less than the first film thickness in the second oxide semiconductor layer. A second insulating layer is formed in such a way that it covers the source electrode and the drain electrode. The upper surface of the first region is in contact with one of the source electrode and the drain electrode. The upper surface of the second region is in contact with the second insulating layer.

10. The method of manufacturing a semiconductor device as claimed in claim 9, wherein, The second oxide semiconductor layer has an amorphous structure.

11. The method of manufacturing a semiconductor device as claimed in claim 9, wherein, The first oxide semiconductor layer has a third film thickness. The third film thickness is greater than the second film thickness.

12. The method of manufacturing a semiconductor device as claimed in claim 11, wherein, The third film thickness is less than the first film thickness.

13. The method of manufacturing a semiconductor device as claimed in claim 11, wherein, The third film thickness is greater than or equal to the difference between the first film thickness and the second film thickness.

14. The method of manufacturing a semiconductor device as claimed in claim 9, wherein, The first oxide semiconductor layer and the second oxide semiconductor layer each contain indium. The proportion of indium relative to all metal elements in the second oxide semiconductor layer is less than the proportion of indium relative to all metal elements in the first oxide semiconductor layer.

15. The method of manufacturing a semiconductor device as claimed in claim 10, wherein, A second gate electrode is further formed on the second insulating layer.

16. The method of manufacturing a semiconductor device as claimed in claim 15, wherein, The second insulating layer has a laminated structure consisting of an oxide insulating film and a nitride insulating film. The oxide insulating film is in contact with the second oxide semiconductor layer. The nitride insulating film is connected to the second gate electrode.

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