Semiconductor device and display device including the same

Abstract

This disclosure relates to a semiconductor device and a display device including the semiconductor device. In a transistor including an oxide semiconductor, variations in electrical characteristics are suppressed and reliability is improved. The semiconductor device includes a transistor. The transistor includes a first gate electrode, a first insulating film above the first gate electrode, an oxide semiconductor film above the first insulating film, a second insulating film above the oxide semiconductor film, a second gate electrode above the second insulating film, and a third insulating film above the oxide semiconductor film and the second gate electrode. The oxide semiconductor film includes a channel region overlapping the second gate electrode, a source region contacting the third insulating film, and a drain region contacting the third insulating film. The first gate electrode and the second gate electrode are electrically connected. When measuring the field-effect mobility in the saturation region of the transistor, the difference between the minimum and maximum field-effect mobility is 15 cm. 2 / Vs and below.

Description

[0001] This divisional application is a divisional application of Chinese patent application No. 201780023312.6, filed on February 2, 2017, entitled "Semiconductor Device and Display Device Including the Semiconductor Device". More specifically, this divisional application is a further divisional application of Chinese patent application No. 202111645114.8, filed on February 2, 2017, entitled "Semiconductor Device and Display Device Including the Semiconductor Device". Technical Field

[0002] One embodiment of the present invention relates to a semiconductor device comprising an oxide semiconductor film and a display device comprising the semiconductor device.

[0003] Note that one embodiment of the present invention is not limited to the above-described technical field. The technical field of one embodiment of the invention disclosed in this specification relates to an object, method, or manufacturing method. The present invention relates to a process, machine, manufacture, or composition of matter. Embodiments of the present invention particularly relate to a semiconductor device, display device, light-emitting device, energy storage device, storage device, driving method thereof, or manufacturing method thereof.

[0004] In this specification and other materials, a semiconductor device generally refers to a device that can operate by utilizing the properties of semiconductors. Semiconductor elements such as transistors, semiconductor circuits, arithmetic processing devices, and storage devices are all embodiments of semiconductor devices. Imaging devices, display devices, liquid crystal display devices, light-emitting devices, electro-optical devices, power generation devices (including thin-film solar cells or organic thin-film solar cells, etc.), and electronic devices sometimes include semiconductor devices. Background Technology

[0005] The technology of forming transistors (also known as field-effect transistors (FETs) or thin-film transistors (TFTs)) using semiconductor thin films formed on substrates with insulating surfaces has attracted attention. These transistors are widely used in electronic devices such as integrated circuits (ICs) and image display devices (display devices). Silicon is a well-known semiconductor material that can be used for transistors. Among other materials, oxide semiconductors have also garnered attention.

[0006] For example, a technique is disclosed in which a self-aligned top-gate transistor is formed using an oxide thin film (see Patent Document 1).

[0007] Furthermore, a semiconductor device that achieves high field-effect mobility (sometimes simply referred to as mobility or μFE) has the following structure: wherein a plurality of oxide semiconductor layers are stacked, wherein the oxide semiconductor layer used as a channel in the plurality of oxide semiconductor layers contains indium and gallium, and the ratio of indium is higher than the ratio of gallium (see Patent Document 2).

[0008] [References]

[0009] [Patent Literature]

[0010] [Patent Document 1] Japanese Patent Application Publication No. 2009-278115

[0011] [Patent Document 2] Japanese Patent Application Publication No. 2014-007399 Summary of the Invention

[0012] Examples of transistor structures that include oxide semiconductor films include bottom-gate structures and top-gate structures. When transistors including oxide semiconductor films are used in display devices, bottom-gate transistors are used more often than top-gate transistors because their manufacturing process is simpler and their manufacturing cost is lower.

[0013] However, bottom-gate transistors have the following drawbacks: as display screens become larger or the images displayed become more high-resolution—typical examples being high-resolution displays with 4k×2k pixels (3840 pixels horizontally and 2160 pixels vertically) or 8k×4k pixels (7680 pixels horizontally and 4320 pixels vertically)—signal delay and other issues caused by parasitic capacitance between the transistor's gate, source, and drain electrodes increase, leading to a decrease in display quality. Therefore, the development of top-gate transistors, which include oxide semiconductor films, is anticipated to offer stable semiconductor characteristics and high reliability.

[0014] In view of the above problems, one objective of one embodiment of the present invention is to suppress variations in electrical characteristics and improve reliability in a transistor comprising oxide semiconductor. Another objective of one embodiment of the present invention is to provide a top-gate transistor comprising oxide semiconductor. Another objective of one embodiment of the present invention is to provide a transistor comprising oxide semiconductor with a large on-state current. Another objective of one embodiment of the present invention is to provide a transistor comprising oxide semiconductor with a small off-state current. Another objective of one embodiment of the present invention is to provide a semiconductor device with low power consumption. Another objective of one embodiment of the present invention is to provide a novel semiconductor device.

[0015] Note that the description of the above objectives does not preclude the existence of other objectives. One embodiment of the present invention does not need to achieve all of the above objectives. Objectives other than those described above are obvious from the description in the specification, etc., and objectives other than those described above can be extracted from the specification, etc.

[0016] One embodiment of the present invention is a semiconductor device including a transistor. The transistor includes a first gate electrode, a first insulating film on the first gate electrode, an oxide semiconductor film on the first insulating film, a second insulating film on the oxide semiconductor film, a second gate electrode on the second insulating film, and a third insulating film on the oxide semiconductor film and the second gate electrode. The oxide semiconductor film includes a channel region overlapping the second gate electrode, a source region contacting the third insulating film, and a drain region contacting the third insulating film. The first gate electrode and the second gate electrode are electrically connected. When measuring the field-effect mobility in the saturation region of the transistor, the difference between the minimum and maximum values ​​of the field-effect mobility is 15 cm⁻¹. 2 / Vs and below.

[0017] In the above embodiments, it is preferable to measure the field-effect mobility when the voltage applied to the first gate electrode and the second gate electrode is in the range of 3V to 10V and the voltage applied to the drain region is in the range of 10V to 20V.

[0018] In the above embodiments, the oxide semiconductor film preferably contains In, M (M is Al, Ga, Y or Sn) and Zn.

[0019] In the above embodiments, it is preferred that the atomic ratio of In, M and Zn is around 4:2:3, and when the proportion of In is 4, the proportion of M is 1.5 or more and 2.5 or less, and the proportion of Zn is 2 or more and 4 or less.

[0020] Another embodiment of the present invention is a display device, which includes a semiconductor device and a display element as described in any of the above embodiments. Another embodiment of the present invention is a display module, which includes the display device and a touch sensor. Another embodiment of the present invention is an electronic device, which includes a semiconductor device, a display device or display module, and operation keys or a battery as described in any of the above embodiments.

[0021] According to one embodiment of the present invention, in a transistor comprising oxide semiconductor, variations in electrical characteristics can be suppressed and reliability improved. According to one embodiment of the present invention, a top-gate transistor comprising oxide semiconductor can be provided. According to one embodiment of the present invention, a transistor comprising oxide semiconductor with a large on-state current can be provided. According to one embodiment of the present invention, a transistor comprising oxide semiconductor with a small off-state current can be provided. According to one embodiment of the present invention, a semiconductor device with low power consumption can be provided. According to one embodiment of the present invention, a novel semiconductor device can be provided.

[0022] Note that the description of these effects does not preclude the existence of other effects. One embodiment of the invention does not require all of the above-described effects to be achieved. Effects other than those described above are obvious from the description in the specification, drawings, claims, etc., and can be extracted from said description. Attached Figure Description

[0023] In the attached diagram:

[0024] Figures 1A to 1C Each transistor's Id-Vg characteristics are shown;

[0025] Figure 2A and Figure 2B The Id-Vg and Id-Vd characteristics of the transistor are shown.

[0026] Figure 3 The Id-Vg characteristics, linear mobility, and saturation mobility curves calculated based on GCA are shown.

[0027] Figures 4A to 4C These are the top view and cross-sectional view of a transistor;

[0028] Figure 5 This is a schematic diagram illustrating the concept of the effective channel length of a transistor;

[0029] Figures 6A to 6C These are schematic diagrams illustrating the donor density, respectively.

[0030] Figure 7 The Id-Vg characteristics are shown;

[0031] Figure 8 The Id-Vg characteristics are shown;

[0032] Figure 9 The calculation results of the interface state density are shown;

[0033] Figure 10A and Figure 10B The Id-Vg characteristics are shown;

[0034] Figure 11This shows the shape of the mobility curve;

[0035] Figure 12 The calculated mobility curves are shown.

[0036] Figure 13 Show the results of sDOS;

[0037] Figure 14A and Figure 14B This is a cross-sectional diagram illustrating a semiconductor device;

[0038] Figure 15A and Figure 15B This is a cross-sectional diagram illustrating a semiconductor device;

[0039] Figure 16A and Figure 16B This is a cross-sectional diagram illustrating a semiconductor device;

[0040] Figure 17A and Figure 17B This is a cross-sectional diagram illustrating a semiconductor device;

[0041] Figure 18A and Figure 18B This is a cross-sectional diagram illustrating a semiconductor device;

[0042] Figure 19A and Figure 19B This is a cross-sectional diagram illustrating a semiconductor device;

[0043] Figure 20A and Figure 20B This is a cross-sectional diagram illustrating a semiconductor device;

[0044] Figure 21A and Figure 21B This is a cross-sectional diagram illustrating a semiconductor device;

[0045] Figures 22A to 22C Each shows the strip structure of a transistor;

[0046] Figures 23A to 23C Each shows a range of the atomic number ratio for oxide semiconductors;

[0047] Figure 24 The crystals of InMZnO4 are shown.

[0048] Figure 25 It is the energy band diagram of a transistor that includes oxide semiconductor in the channel region;

[0049] Figures 26A to 26C These are cross-sectional TEM images and cross-sectional HR-TEM images of oxide semiconductor films;

[0050] Figures 27A to 27C These are cross-sectional TEM images and cross-sectional HR-TEM images of oxide semiconductor films;

[0051] Figures 28A to 28C These are cross-sectional TEM images and cross-sectional HR-TEM images of oxide semiconductor films;

[0052] Figures 29A to 29C The XRD measurement results and electron diffraction pattern of the oxide semiconductor film are shown.

[0053] Figures 30A to 30C The XRD measurement results and electron diffraction pattern of the oxide semiconductor film are shown.

[0054] Figures 31A to 31C The XRD measurement results and electron diffraction pattern of the oxide semiconductor film are shown.

[0055] Figure 32A and Figure 32B The electron diffraction pattern is shown;

[0056] Figure 33 The line outline of the electron diffraction pattern is shown;

[0057] Figure 34 A conceptual diagram illustrating the line profile of an electron diffraction pattern, the relative brightness R of the line profile, and the full width at half maximum (FWHM) of the line profile is shown.

[0058] Figure 35A1 , Figure 35A2 , Figure 35B1 , Figure 35B2 , Figure 35C1 and Figure 35C2 The electron diffraction pattern and line outline are shown.

[0059] Figure 36 The relative brightness is shown as estimated from the electron diffraction pattern of the oxide semiconductor film;

[0060] Figure 37A1 , Figure 37A2 , Figure 37B1 , Figure 37B2 , Figure 37C1 and Figure 37C2 The image shows a cross-sectional TEM image of an oxide semiconductor film and a cross-sectional TEM image obtained through analysis of that image.

[0061] Figures 38A to 38C The SIMS measurement results for the oxide semiconductor film are shown.

[0062] Figure 39 This is a top view showing one embodiment of the display device;

[0063] Figure 40 This is a cross-sectional view illustrating one embodiment of the display device;

[0064] Figure 41This is a cross-sectional view illustrating one embodiment of the display device;

[0065] Figure 42 This is a cross-sectional view illustrating one embodiment of the display device;

[0066] Figures 43A to 43D This is a cross-sectional view illustrating the method for forming the EL layer;

[0067] Figure 44 This is a conceptual diagram illustrating a droplet ejection device;

[0068] Figure 45 This is a cross-sectional view illustrating one embodiment of the display device;

[0069] Figure 46 This is a cross-sectional view illustrating one embodiment of the display device;

[0070] Figures 47A to 47C A cross-section of a semiconductor device is shown;

[0071] Figure 48 A cross-section of a semiconductor device is shown;

[0072] Figures 49A to 49C These are block diagrams and circuit diagrams illustrating the display device;

[0073] Figures 50A to 50C This is a circuit diagram and timing diagram illustrating one embodiment of the present invention;

[0074] Figures 51A to 51C These are diagrams and circuit diagrams illustrating one embodiment of the present invention;

[0075] Figure 52A and Figure 52B This is a circuit diagram and timing diagram illustrating one embodiment of the present invention;

[0076] Figure 53A and Figure 53B This is a circuit diagram and timing diagram illustrating one embodiment of the present invention;

[0077] Figures 54A to 54E These are block diagrams, circuit diagrams, and waveform diagrams illustrating one embodiment of the present invention;

[0078] Figure 55A and Figure 55B This is a circuit diagram and timing diagram illustrating one embodiment of the present invention;

[0079] Figure 56A and Figure 56B Each of these is a circuit diagram illustrating one embodiment of the present invention;

[0080] Figures 57A to 57C Each of these is a circuit diagram illustrating one embodiment of the present invention;

[0081] Figure 58 The display module is shown;

[0082] Figures 59A to 59E Showing electronic devices;

[0083] Figures 60A to 60G Showing electronic devices;

[0084] Figure 61A and Figure 61B This is a perspective view illustrating the display device;

[0085] Figure 62 The Id-Vg characteristics of the transistor in the embodiment are shown;

[0086] Figure 63 The Id-Vg characteristics of the transistor in the embodiment are shown;

[0087] Figure 64 The Id-Vg characteristics of the transistor in the embodiment are shown;

[0088] Figure 65 The Id-Vg characteristics of the transistor in the embodiment are shown;

[0089] Figure 66 The Id-Vg characteristics of the transistor in the embodiment are shown;

[0090] Figure 67 The Id-Vg characteristics of the transistors in the embodiments are shown; and

[0091] Figure 68 The threshold voltage of the transistor in the embodiment is shown. Detailed Implementation

[0092] The embodiments will now be described with reference to the accompanying drawings. Note that the embodiments can be implemented in many different forms. Those skilled in the art will readily understand that the methods and details can be varied in many ways without departing from the spirit and scope of the invention. Therefore, the invention should not be construed as being limited to the contents described in the following embodiments.

[0093] In the accompanying drawings, sizes, layer thicknesses, or areas are sometimes exaggerated for clarity. Therefore, one embodiment of the invention is not necessarily limited to these dimensions. Furthermore, the drawings schematically illustrate ideal examples, and one embodiment of the invention is not limited to the shapes or values ​​shown in the drawings.

[0094] The ordinal numbers “first,” “second,” “third,” etc., used in this specification are included to avoid confusion among the constituent elements, not to limit the quantity.

[0095] In this specification, for convenience, terms such as "upper" and "lower" are used to indicate the arrangement and to illustrate the positional relationship of the constituent elements with reference to the accompanying drawings. The positional relationship of the constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the terminology used is not limited to that described in the specification and may be replaced as appropriate.

[0096] In this specification and the like, a transistor refers to a device that includes at least three terminals: a gate, a drain, and a source. A transistor has a channel region between its drain (drain terminal, drain region, or drain electrode) and its source (source terminal, source region, or source electrode), through which current can flow between the drain and the source. Note that in this specification and the like, the channel region refers to the region through which current primarily flows.

[0097] In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source" and "drain" are sometimes interchanged. Therefore, in this specification, the "source" and "drain" can be interchanged.

[0098] In this specification, etc., "electrical connection" includes the situation where constituent elements are connected together by a component having a certain electrical function. There are no particular limitations on the "component having a certain electrical function," as long as it enables the transmission and reception of electrical signals between the connected constituent elements. Examples of "components having a certain electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0099] In this specification, "parallel" refers to a state in which two straight lines form an angle of -10° or more and less than 10°, and therefore also includes a state in which the angle is -5° or more and less than 5°. Similarly, "perpendicular" refers to a state in which two straight lines form an angle of 80° or more and less than 100°, and therefore also includes a state in which the angle is 85° or more and less than 95°.

[0100] In this specification and other materials, the terms "film" and "layer" may be used interchangeably. For example, "conductive layer" may sometimes be referred to as "conductive film." Similarly, "insulating film" may sometimes be referred to as "insulating layer."

[0101] In this specification, unless otherwise specified, the off-state current refers to the drain current when the transistor is in the off state (also known as the non-conducting state or the blocked state). Unless otherwise specified, the off state of an n-channel transistor refers to the voltage between the gate and source (Vo). gs Gate-source voltage (V) is below the threshold voltage. th The off state of a p-channel transistor refers to the voltage V between the gate and source.gs Above the threshold voltage V th The state of an n-channel transistor. For example, the off-state current of an n-channel transistor sometimes refers to the gate-source voltage Vo. gs Below the threshold voltage V th The drain current at that time.

[0102] The off-state current of a transistor sometimes depends on V. gs Therefore, "the off-state current of a transistor is less than I" sometimes refers to the existence of a V such that the off-state current of the transistor is less than I. gs The off-state current of a transistor sometimes refers to a predetermined V. gs The closed state in the middle, V within the predetermined range gs The off state or V that can obtain a sufficiently small off-state current. gs The off-state current is equal to the off-state current in the closed state.

[0103] As an example, consider an n-channel transistor with a threshold voltage V. th 0.5V, V gs The drain current at 0.5V is 1×10 -9 A, V gs The drain current at 0.1V is 1×10 -13 A, V gs The drain current at -0.5V is 1×10⁻⁶. -19 A, V gs The drain current at -0.8V is 1×10 -22 A. In V gs When it is -0.5V or V gs When the voltage is in the range of -0.5V to -0.8V, the drain current of this transistor is 1×10⁻⁶. -19 The current is below A, so the off-state current of this transistor is sometimes referred to as 1 × 10⁻⁶. -19 Below A. This is because the drain current of this transistor is 1 × 10⁻⁶. -22 V below A gs Therefore, the off-state current of this transistor is sometimes referred to as 1 × 10⁻⁶. -22 Below A.

[0104] In this specification and the like, the off-state current of a transistor having a channel width W is sometimes expressed as a current value per channel width W, or as a current value per predetermined channel width (e.g., 1 μm). In the latter case, the off-state current is sometimes expressed as current / length (e.g., A / μm).

[0105] The off-state current of a transistor sometimes depends on temperature. In this specification, unless otherwise specified, the off-state current may refer to the off-state current at room temperature, 60°C, 85°C, 95°C, or 125°C. Alternatively, the off-state current may refer to the off-state current at a temperature that ensures the reliability of the semiconductor device including the transistor, or at a temperature in which the semiconductor device including the transistor is used (e.g., a temperature range of 5°C to 35°C). A transistor's off-state current of I or less sometimes refers to a situation where, at room temperature, 60°C, 85°C, 95°C, 125°C, a temperature that ensures the reliability of the semiconductor device including the transistor, or at a temperature in which the semiconductor device is used (e.g., a temperature range of 5°C to 35°C), there exists a V that causes the transistor's off-state current to be I or less. gs .

[0106] The off-state current of a transistor sometimes depends on the voltage V between the drain and source. ds In this specification, unless otherwise specified, the off-state current is sometimes V. ds The off-state current is 0.1V, 0.8V, 1V, 1.2V, 1.8V, 2.5V, 3V, 3.3V, 10V, 12V, 16V, or 20V. Alternatively, the off-state current is sometimes a V that ensures the reliability of semiconductor devices, including the transistor. ds Or the V used in the semiconductor device, etc. ds The off-state current below I. The case where the transistor's off-state current is below I sometimes refers to: at V... ds The voltage ratings are 0.1V, 0.8V, 1V, 1.2V, 1.8V, 2.5V, 3V, 3.3V, 10V, 12V, 16V, and 20V, ensuring the reliability of semiconductor devices including this transistor. ds Or the V used in the semiconductor device, etc. ds Below, there exists a V such that the off-state current of the transistor is less than or equal to I. gs .

[0107] In the above explanation of off-state current, the drain can be referred to as the source. That is to say, off-state current sometimes refers to the current flowing through the source when the transistor is in the off state.

[0108] In this specification, etc., "leakage current" is sometimes used to mean the same thing as off-state current. In this specification, off-state current sometimes refers to the current flowing between the source and drain when the transistor is in the off state.

[0109] In this specification, the threshold voltage of a transistor refers to the gate voltage (V) at which a channel is formed in the transistor. gSpecifically, in a graph where the gate voltage (Vg) is represented on the horizontal axis and the square root of the drain current (Id) is represented on the vertical axis, the threshold voltage of a transistor is sometimes referred to as the straight line extrapolated from the tangent with the maximum slope in the plotted curve (Vg-Id characteristic) to the drain current (Id). d The gate voltage (V) at the crossover point where the square root of ) is 0 (Id is 0A) g Alternatively, the threshold voltage of a transistor sometimes refers to the voltage at which the channel length L is equal to the channel width W, and the voltage I... d The value of [A]×L[μm] / W[μm] is 1×10 -9 Gate voltage (V) at [A] g ).

[0110] In this specification, for example, when the conductivity is sufficiently low, a "semiconductor" sometimes exhibits the characteristics of an "insulator." Furthermore, the boundary between a "semiconductor" and an "insulator" is not always clear, so it is sometimes impossible to precisely distinguish between them. Therefore, "semiconductor" in this specification may sometimes be replaced with "insulator." Similarly, "insulator" in this specification may sometimes be replaced with "semiconductor." Additionally, "insulator" in this specification may sometimes be replaced with "semi-insulator."

[0111] In this specification, for example, when the conductivity is sufficiently high, a "semiconductor" sometimes exhibits the characteristics of a "conductor". Furthermore, the boundary between a "semiconductor" and a "conductor" is not always clear, and therefore, it is sometimes impossible to precisely distinguish between them. Therefore, in this specification, "semiconductor" may sometimes be replaced with "conductor". Similarly, in this specification, "conductor" may sometimes be replaced with "semiconductor".

[0112] In this specification, impurities in a semiconductor refer to elements other than the main components of the semiconductor. For example, elements with a concentration below 0.1 atomic > are considered impurities. If a semiconductor contains impurities, a density of states (DOS) may form in the semiconductor, carrier mobility may decrease, or crystallinity may decrease. When the semiconductor contains oxide semiconductors, examples of impurities that alter semiconductor properties include Group 1 elements, Group 2 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components. Typical examples include hydrogen (also found in water), lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. In oxide semiconductors, oxygen vacancies are sometimes created due to the incorporation of impurities such as hydrogen. Furthermore, when the semiconductor contains silicon, examples of impurities that alter semiconductor properties include oxygen, Group 1 elements (excluding hydrogen), Group 2 elements, Group 13 elements, and Group 15 elements.

[0113] In this specification and other materials, metal oxide refers to oxides of metals in a broad sense. Metal oxides are classified as oxide insulators, oxide conductors (including transparent oxide conductors), and oxide semiconductors (also simply referred to as OS). For example, the metal oxide used in the active layer of a transistor is sometimes called an oxide semiconductor. In other words, an OS FET is a transistor that contains either a metal oxide or an oxide semiconductor.

[0114] In this specification and other materials, nitrogen-containing metal oxides are sometimes referred to as metal oxides. Furthermore, nitrogen-containing metal oxides may also be referred to as metal oxynitrides.

[0115] In this specification and other materials, CAAC (c-axis aligned crystal) or CAC (cloud-aligned composite) is sometimes referred to. CAAC refers to an example of a crystalline structure, while CAC refers to an example of a function or material composition.

[0116] An example of the crystal structure of an oxide semiconductor or metal oxide will be illustrated. Note that an oxide semiconductor deposited by sputtering using an In-Ga-Zn oxide target (In:Ga:Zn = 4:2:4.1 [atomic ratio]) will be used as an example. An oxide semiconductor formed by sputtering using the above target at a substrate temperature above 100°C and below 130°C is called sIGZO, and an oxide semiconductor formed by sputtering using the above target at a substrate temperature of room temperature (RT) is called tIGZO. For example, sIGZO has a crystal structure of either nc (nano crystal) or CAAC. Furthermore, tIGZO has an nc crystal structure. Note that room temperature (RT) here refers to the temperature at which the substrate is not intentionally heated.

[0117] In this specification, CAC-OS or CAC-metal oxide functions as a conductor in one part of the material and as a dielectric (or insulator) in another part, thus possessing overall semiconductor functionality. When CAC-OS or CAC-metal oxide is used as the active layer of a transistor, the conductor allows electrons (or holes) used as charge carriers to flow through, while the dielectric prevents electrons from flowing through. Through the complementary effects of the conductor and dielectric functions, CAC-OS or CAC-metal oxide can possess switching functionality (on / off function). In CAC-OS or CAC-metal oxide, each function can be maximized by separating them.

[0118] In this specification, CAC-OS or CAC-metal oxide includes conductive regions and dielectric regions. The conductive regions have the functions of conductors, and the dielectric regions have the functions of dielectrics. In the material, the conductive and dielectric regions are sometimes separated at the nanoparticle level. The conductive and dielectric regions are sometimes unevenly distributed in the material. When observed, the conductive regions sometimes appear connected in a cloud-like manner with blurred edges.

[0119] In other words, CAC-OS or CAC-metal oxide can also be referred to as matrix composite or metal matrix composite.

[0120] Furthermore, in CAC-OS or CAC-metal oxide, the conductive region and the dielectric region sometimes each have a size of 0.5 nm or more and 10 nm or less, preferably 0.5 nm or more and 3 nm or less, and are dispersed in the material.

[0121] (Implementation Method 1)

[0122] In this embodiment, refer to Figures 1A to 1C , Figure 2A and Figure 2B , Figure 3 , Figures 4A to 4C , Figure 5 , Figures 6A to 6C , Figure 7 , Figure 8 , Figure 9 , Figure 10A and Figure 10B , Figure 11 , Figure 12 , Figure 13 , Figure 14A and Figure 14B , Figure 15A and Figure 15B , Figure 16A and Figure 16B , Figure 17A and Figure 17B , Figure 18A and Figure 18B , Figure 19A and Figure 19B , Figure 20A and Figure 20B , Figure 21A and Figure 21B as well as Figures 22A to 22C A semiconductor device according to one embodiment of the present invention is described.

[0123] One embodiment of the present invention is a semiconductor device including a transistor. The transistor includes a first gate electrode, a first insulating film on the first gate electrode, an oxide semiconductor film on the first insulating film, a second insulating film on the oxide semiconductor film, a second gate electrode on the second insulating film, and a third insulating film on the oxide semiconductor film and the second gate electrode. The oxide semiconductor film includes a channel region overlapping the second gate electrode, a source region contacting the third insulating film, and a drain region contacting the third insulating film. The first gate electrode and the second gate electrode are electrically connected.

[0124] In the saturation region of the aforementioned transistor, the difference between the minimum and maximum field-effect mobility is 15 cm⁻¹. 2 / Vs and below.

[0125] In other words, one embodiment of the semiconductor device of the present invention is a transistor comprising an oxide semiconductor film in the channel region, wherein the variation in field-effect mobility in the saturation region of the transistor is minimal. High reliability can be obtained when such a semiconductor device is used, for example, as a transistor for a pixel in an organic EL display.

[0126] 1-1. Characteristics of a Transistor

[0127] First, refer to Figure 2A , Figure 2B and Figure 3 Explain the general characteristics of a transistor.

[0128] [Id-Vg characteristics of a transistor]

[0129] First, the drain current-gate voltage characteristics (Id-Vg characteristics) of a transistor will be explained. Figure 2A An example of the Id-Vg characteristics of a transistor is shown. In Figure 2A For clarity, the example shown illustrates the use of polysilicon as the active layer in a transistor. Figure 2A In the diagram, the vertical axis represents Id, and the horizontal axis represents Vg.

[0130] like Figure 2A As shown, the Id-Vg characteristic can be roughly divided into three regions. The first region is called the off region (OFF region), the second region is called the subthreshold region, and the third region is called the on region (ON region). The gate voltage at the boundary between the subthreshold region and the on region is called the threshold voltage (Vth).

[0131] To obtain good transistor characteristics, it is preferable to have a small drain current (also known as off-state current or Ioff) in the cutoff region and a large drain current (also known as on-state current or Ion) in the conduction region. Field-effect mobility is often used as an indicator of the on-state current of a transistor. Details regarding field-effect mobility will be explained later.

[0132] Furthermore, in order to drive the transistor at a low voltage, it is preferable that the Id-Vg characteristic in the subthreshold region has a steep slope. The index of the degree of change of the Id-Vg characteristic in the subthreshold region is called the subthreshold swing (SS) or S-value. The S-value is expressed by the following formula (1).

[0133] [Formula 1]

[0134]

[0135] The S-value is the minimum change in gate voltage required for a change in drain current by one digit in the subthreshold region. The smaller the S-value, the more abrupt the switching operation can be.

[0136] [Id-Vd characteristics of a transistor]

[0137] Next, the drain current-drain voltage characteristics (Id-Vd characteristics) of the transistor will be explained. Figure 2B An example of the Id-Vd characteristics of a transistor is shown. In Figure 2B In the diagram, the vertical axis represents Id, and the horizontal axis represents Vd.

[0138] like Figure 2B As shown, the conduction region is further divided into two regions. The first region is called the linear region, and the second region is called the saturation region. In the linear region, the drain current increases parabolically with the increase of the drain voltage. On the other hand, in the saturation region, even if the drain voltage changes, the change in drain current is not significant. Depending on the vacuum tube, the linear region is sometimes called the triode region, and the saturation region is called the pentoode region.

[0139] Sometimes the linear region refers to the state where Vg is greater than Vd (Vd < Vg). Sometimes the saturation region refers to the state where Vd is greater than Vg (Vg < Vd). However, in practice, the transistor's threshold voltage must be considered. Therefore, sometimes the state where the value obtained by subtracting the transistor's threshold voltage from the gate voltage is greater than the drain voltage (Vd < Vg - Vth) is called the linear region. Similarly, sometimes the state where the value obtained by subtracting the transistor's threshold voltage from the gate voltage is less than the drain voltage (Vg - Vth < Vd) is called the saturation region.

[0140] Sometimes, the Id-Vd characteristic of a transistor with a constant current in the saturation region is described as "good saturation." Good saturation is particularly important when transistors are used in organic EL displays. For example, by using a transistor with good saturation as the pixel transistor in an organic EL display, variations in pixel brightness can be suppressed even with changes in drain voltage.

[0141] [Analysis Model of Drain Current]

[0142] Next, the analytical model for drain current will be explained. As the analytical model for drain current, the analytical formula for drain current based on the Gradually Varying Channel Approximation (GCA) is known. Based on GCA, the drain current of the transistor is expressed by the following formula (2).

[0143] [Formula 2]

[0144]

[0145] In formula (2), the upper formula is the formula for the drain current in the linear region, and the lower formula is the formula for the drain current in the saturation region.

[0146] [Field-effect mobility]

[0147] Next, we will explain the field-effect mobility. The field-effect mobility is used as an indicator of the current driving capability of a transistor. As mentioned above, the conduction region of a transistor is divided into a linear region and a saturation region. The field-effect mobility of the transistor can be calculated from the characteristics of each region based on the analysis formula of the drain current based on GCA. When it is necessary to distinguish between them, the field-effect mobility in the linear region and the field-effect mobility in the saturation region are called the linear mobility and the saturation mobility, respectively. The linear mobility is expressed by the following formula (3), and the saturation mobility is expressed by the following formula (4).

[0148] [Formula 3]

[0149]

[0150] [Formula 4]

[0151]

[0152] In this specification, the curves calculated from formulas (3) and (4) are referred to as mobility curves. Figure 3 The mobility curves calculated from the GCA-based drain current analysis are shown. Figure 3 In the figure, the Id-Vg characteristics of the transistor overlap with the mobility curves of linear mobility and saturation mobility.

[0153] exist Figure 3 In this study, the Id-Vg characteristic is calculated from the drain current analysis based on GCA. The shape of the mobility curve helps to understand the internal state of the transistor.

[0154] For example, focusing on Figure 3The shape of the saturation mobility curve in the transistor. When the gate voltage increases, the charge carriers (electrons or holes) in the transistor are accelerated by the electric field and gain energy. Therefore, the charge carriers gain a specified energy due to the electric field, and the saturation mobility increases. However, the charge carriers are not accelerated indefinitely; they lose energy by colliding with thermally vibrating inter-lattice atoms or ionized impurity atoms, resulting in a gradual decrease in saturation mobility.

[0155] 1-2. Manufacturing of transistors for characteristic evaluation

[0156] Next, the structure of a transistor according to one embodiment of the present invention will be described, and the evaluation results of the electrical characteristics of the manufactured transistor will be shown.

[0157] [Example 1 of transistor structure]

[0158] Figure 4A This is a top view of transistor 100A. Figure 4B It is along Figure 4A A cross-sectional view of the dashed-dot line X1-X2. Figure 4C It is along Figure 4A The cross-sectional view of the dashed line Y1-Y2. Note that, for clarity, in... Figure 4A In the diagram, components such as the insulating film 110 are omitted. Sometimes, in the top view of the transistor later, [the following text is incomplete and likely refers to a different element]. Figure 4A Similarly, some constituent elements are omitted. In addition, the direction of the dashed line X1-X2 is sometimes referred to as the channel length (L) direction, and the direction of the dashed line Y1-Y2 is referred to as the channel width (W) direction.

[0159] Figures 4A to 4C The transistor 100A shown includes a conductive film 106 on a substrate 102, an insulating film 104 on the conductive film 106, an oxide semiconductor film 108 on the insulating film 104, an insulating film 110 on the oxide semiconductor film 108, a conductive film 112 on the insulating film 110, the insulating film 104, the oxide semiconductor film 108, and an insulating film 116 on the conductive film 112. The oxide semiconductor film 108 includes a channel region 108i overlapping with the conductive film 112, a source region 108s contacting the insulating film 116, and a drain region 108d contacting the insulating film 116.

[0160] The insulating film 116 contains nitrogen or hydrogen. The insulating film 116 is in contact with the source region 108s and the drain region 108d, so the nitrogen or hydrogen contained in the insulating film 116 is added to the source region 108s and the drain region 108d. The source region 108s and the drain region 108d have high carrier densities when nitrogen or hydrogen is added.

[0161] The transistor 100A may also include an insulating film 118 on the insulating film 116, a conductive film 120a electrically connected to the source region 108s through an opening 141a provided in the insulating films 116 and 118, and a conductive film 120b electrically connected to the drain region 108d through an opening 141b provided in the insulating films 116 and 118. Furthermore, an insulating film 122 may also be provided on the insulating film 118, the conductive film 120a, and the conductive film 120b. Although in Figure 4B and Figure 4C The diagram shows a structure with an insulating film 122, but one embodiment of the present invention is not limited to this and does not necessarily require the insulating film 122.

[0162] In this specification, insulating films 104, 110, 116, 118, and 122 are sometimes referred to as the first insulating film, the second insulating film, the third insulating film, the fourth insulating film, and the fifth insulating film, respectively. Insulating film 104 is used as the first gate insulating film, and insulating film 110 is used as the second gate insulating film. Insulating films 116 and 118 are used as protective insulating films, and insulating film 122 is used as a planarization film.

[0163] The insulating film 110 includes an excess oxygen region. Because the insulating film 110 includes an excess oxygen region, excess oxygen can be supplied to the channel region 108i included by the oxide semiconductor film 108. As a result, oxygen vacancies that would form in the channel region 108i can be filled by the excess oxygen, thus providing a highly reliable semiconductor device.

[0164] Furthermore, to supply excess oxygen to the oxide semiconductor film 108, excess oxygen can also be supplied to the insulating film 104 formed beneath the oxide semiconductor film 108. In this case, the excess oxygen contained in the insulating film 104 may be supplied to the source region 108s and drain region 108d included in the oxide semiconductor film 108. When excess oxygen is supplied to the source region 108s and drain region 108d, the resistance of the source region 108s and drain region 108d will increase.

[0165] On the other hand, in a structure where the insulating film 110 formed on the oxide semiconductor film 108 contains excess oxygen, excess oxygen can be selectively supplied only to the channel region 108i. Alternatively, after supplying excess oxygen to the channel region 108i, the source region 108s, and the drain region 108d, the carrier density of the source region 108s and the drain region 108d can be selectively increased, thereby preventing the resistance of the source region 108s and the drain region 108d from increasing.

[0166] Furthermore, the source region 108s and drain region 108d included in the oxide semiconductor film 108 preferably each contain an element that forms oxygen vacancies or an element bonded to oxygen vacancies. Typical examples of the element that forms oxygen vacancies or an element bonded to oxygen vacancies include hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, titanium, and rare gases. Typical examples of rare gas elements include helium, neon, argon, krypton, and xenon. When the insulating film 116 contains one or more of the above elements, the element that forms oxygen vacancies diffuses from the insulating film 116 to the source region 108s and drain region 108d. And / or, the above-mentioned element that forms oxygen vacancies is added to the source region 108s and drain region 108d through an impurity addition process.

[0167] Impurity elements added to an oxide semiconductor film can break the bonds between the metal element and oxygen, thus creating oxygen vacancies. Alternatively, when an impurity element is added to an oxide semiconductor film, the oxygen bonded to the metal element in the oxide semiconductor film bonds to the impurity element, causing the oxygen to detach from the metal element and form an oxygen vacancy. As a result, the oxide semiconductor film has a higher carrier density, and therefore its conductivity is improved.

[0168] Conductive film 106 is used as the first gate electrode, and conductive film 112 is used as the second gate electrode. Conductive film 120a is used as the source electrode, and conductive film 120b is used as the drain electrode.

[0169] like Figure 4C As shown, opening 143 is provided in insulating films 104 and 110. Conductive film 106 is electrically connected to conductive film 112 through opening 143. Therefore, conductive film 106 and conductive film 112 are subjected to the same potential. Alternatively, opening 143 may not be provided, and different potentials may be applied to conductive film 106 and conductive film 112. Alternatively, opening 143 may not be provided, and conductive film 106 may be used as a light-shielding film. For example, when conductive film 106 is formed using a light-shielding material, light can be suppressed from shining from the bottom into channel region 108i.

[0170] like Figure 4B and Figure 4C As shown, the oxide semiconductor film 108 is opposite to the conductive film 106 used as the first gate electrode and the conductive film 112 used as the second gate electrode, and is sandwiched between the two conductive films used as gate electrodes.

[0171] Furthermore, the length of the conductive film 112 in the channel width direction is greater than the length of the oxide semiconductor film 108 in the channel width direction. In the channel width direction, the oxide semiconductor film 108 is entirely covered by the conductive film 112, sandwiching the insulating film 110. The conductive film 112 and the conductive film 106 are connected through an opening 143 formed in the insulating films 104 and 110, so in the channel width direction, one side of the oxide semiconductor film 108 sandwiches the insulating film 110 and faces the conductive film 112.

[0172] In other words, in the channel width direction of transistor 100A, conductive films 106 and 112 are connected at the openings 143 formed in insulating films 104 and 110, and conductive films 106 and 112 sandwich insulating films 104 and 110 around oxide semiconductor film 108.

[0173] By employing the above structure, the electric fields of the conductive film 106 used as the first gate electrode and the conductive film 112 used as the second gate electrode can be used to surround the oxide semiconductor film 108 included in the transistor 100A. The device structure of a transistor like transistor 100A, which utilizes the electric fields of the first gate electrode and the second gate electrode to surround the oxide semiconductor film 108 in which the channel region is formed, can be called a Surrounded channel (S-channel) structure.

[0174] Because transistor 100A has an S-channel structure, an electric field to induce a channel can be effectively applied to oxide semiconductor film 108 using conductive film 106 or conductive film 112; thereby, the current driving capability of transistor 100A is improved, resulting in a large on-state current characteristic. Because of the large on-state current, transistor 100A can be miniaturized. Furthermore, since transistor 100A has a structure where oxide semiconductor film 108 is surrounded by conductive film 106 and conductive film 112, the mechanical strength of transistor 100A can be improved.

[0175] When viewed from the channel width direction of transistor 100A, an opening different from the opening 143 can be formed on the side of oxide semiconductor film 108 where the opening 143 is not formed.

[0176] [Transistor Manufacturing]

[0177] Next, a transistor equivalent to the aforementioned transistor 100A is formed, and the electrical characteristics of the transistor are evaluated. In this embodiment, the following samples A1 to A3 are manufactured.

[0178] Samples A1 to A3 are all samples of transistors with a channel length L of 2 μm and a channel width W of 3 μm. Samples A1 and A2 are samples of comparative transistors, and sample A3 is a sample of a transistor of one embodiment of the present invention. Samples A1 to A3 are manufactured by the following method: the deposition conditions of the oxide semiconductor film are different, but other steps are the same.

[0179] [Manufacturing method of samples A1 to A3]

[0180] First, a titanium film with a thickness of 10 nm and a copper film with a thickness of 100 nm are formed on a glass substrate using a sputtering apparatus. Then, the conductive film is processed using photolithography.

[0181] Next, a stack comprising four insulating films is formed on the substrate and the conductive film. The insulating films are continuously formed in a vacuum using a plasma-enhanced chemical vapor deposition (PECVD) apparatus. As insulating films, a silicon nitride film with a thickness of 50 nm, a silicon nitride film with a thickness of 300 nm, a silicon nitride film with a thickness of 50 nm, and a silicon oxynitride film with a thickness of 50 nm are sequentially used and stacked.

[0182] Next, an oxide semiconductor film is formed on the insulating film, and this oxide semiconductor film is processed into islands, thereby forming a semiconductor layer. As oxide semiconductor film 108, an oxide semiconductor film with a thickness of 40 nm is formed. The deposition conditions of the oxide semiconductor films in samples A1 to A3 are different.

[0183] The formation conditions for the oxide semiconductor film used in sample A1 were as follows: substrate temperature 170°C; argon gas at a flow rate of 140 sccm and oxygen gas at a flow rate of 60 sccm were introduced into the processing chamber of the sputtering apparatus; the pressure was set to 0.6 Pa; and an AC power of 2.5 kW was applied to the metal oxide target containing indium, gallium, and zinc (In:Ga:Zn = 4:2:4.1 [atomic ratio]). Note that the ratio of oxygen in the overall deposition gas is sometimes referred to as the oxygen flow rate ratio. The oxygen flow rate ratio in the deposition of the oxide semiconductor film in sample A1 was 30-.

[0184] The formation conditions for the oxide semiconductor film used in sample A2 were as follows: substrate temperature was 130°C; argon gas at a flow rate of 180 sccm and oxygen gas at a flow rate of 20 sccm were introduced into the processing chamber of the sputtering apparatus; the pressure was set to 0.6 Pa; and an AC power of 2.5 kW was applied to the metal oxide target containing indium, gallium, and zinc (In:Ga:Zn = 4:2:4.1 [atomic ratio]). The oxygen flow rate ratio in the deposition of the oxide semiconductor film of sample A2 was 10-.

[0185] The formation conditions for the oxide semiconductor film used in sample A3 were as follows: substrate temperature was room temperature (RT); argon gas at a flow rate of 180 sccm and oxygen gas at a flow rate of 20 sccm were introduced into the processing chamber of the sputtering apparatus; the pressure was set to 0.6 Pa; and an AC power of 2.5 kW was applied to the metal oxide target containing indium, gallium, and zinc (In:Ga:Zn = 4:2:4.1 [atomic ratio]). The oxygen flow rate ratio in the deposition of the oxide semiconductor film in sample A3 was 10-.

[0186] Next, an insulating film is formed on the insulating film and the oxide semiconductor layer. As the insulating film, a silicon oxynitride film with a thickness of 150 nm is formed using a PECVD device.

[0187] Next, a heat treatment is performed. The heat treatment is carried out at 350°C for 1 hour in a mixed atmosphere of nitrogen and oxygen.

[0188] Next, openings are formed in the desired areas of the insulating film. Dry etching is used to form the openings.

[0189] Next, an oxide semiconductor film with a thickness of 100 nm is formed on the insulating film and in the openings. This oxide semiconductor film is then processed into island shapes, thereby forming a conductive film. Furthermore, after forming the conductive film, the insulating film in contact with the bottom surface of the conductive film is continuously processed, thereby forming an insulating film.

[0190] As conductive films, an oxide semiconductor film with a thickness of 10 nm, a titanium nitride film with a thickness of 50 nm, and a copper film with a thickness of 100 nm were formed sequentially. The formation conditions for the oxide semiconductor film were as follows: substrate temperature of 170 °C; oxygen gas with a flow rate of 200 sccm was introduced into the processing chamber of the sputtering apparatus; the pressure was set to 0.6 Pa; and an AC power of 2.5 kW was applied to a metal oxide target containing indium, gallium, and zinc (In:Ga:Zn = 4:2:4.1 [atomic ratio]). The titanium nitride film and the copper film were formed using the sputtering apparatus.

[0191] Next, plasma treatment is performed over the oxide semiconductor film, insulating film, and conductive film. A PECVD apparatus is used to perform plasma treatment in a mixed atmosphere containing argon and nitrogen gases at a substrate temperature of 220°C.

[0192] Next, an insulating film is formed on the oxide semiconductor film, the insulating film, and the conductive film. An insulating film is formed by stacking a silicon nitride film with a thickness of 100 nm and a silicon oxynitride film with a thickness of 300 nm using a PECVD device.

[0193] Next, a mask is formed on the formed insulating film, and an opening is formed in the insulating film using the mask.

[0194] A conductive film is formed by filling the openings, and the conductive film is processed into an island shape, thereby forming a conductive film used as a source electrode and a drain electrode. As this conductive film, a titanium film with a thickness of 10 nm and a copper film with a thickness of 100 nm are formed using a sputtering apparatus.

[0195] Subsequently, an insulating film is formed on the insulating film and the conductive film. An acrylic photosensitive resin with a thickness of 1.5 μm is used for the insulating film.

[0196] Through the above steps, samples A1 to A3 are manufactured.

[0197] [Id-Vg characteristics of a transistor]

[0198] Next, the Id-Vg characteristics of the transistors in samples A1 to A3 fabricated above were measured. As measurement conditions for the Id-Vg characteristics of each transistor, the voltage applied to the conductive film used as the first gate electrode (hereinafter also referred to as the gate voltage (Vg)) and the voltage applied to the conductive film used as the second gate electrode (hereinafter also referred to as the back gate voltage (Vbg)) varied from -10V to +10V in increments of 0.25V. The voltage applied to the conductive film used as the source electrode (hereinafter also referred to as the source voltage (Vs)) was 0V (comm), and the voltage applied to the conductive film used as the drain electrode (hereinafter also referred to as the drain voltage (Vd)) was 0.1V and 20V.

[0199] Figure 1A , Figure 1B and Figure 1C The Id-Vg characteristics of samples A1, A2, and A3 are shown respectively. Figures 1A to 1C In the diagram, the first vertical axis represents Id (A), and the second vertical axis represents the field-effect mobility (μFE) (cm). 2 / Vs), with the horizontal axis representing Vg (V). Additionally, field-effect mobility was measured at Vd = 20V.

[0200] like Figures 1A to 1C As shown, the Id-Vg characteristics of transistors exhibit different tendencies when the deposition conditions of the oxide semiconductor film are changed. In particular, the shape of the field-effect mobility curve of the transistor differs.

[0201] from Figures 1A to 1C The shapes of the mobility curves for samples A1 to A3 are shown. The minimum and maximum values ​​of the field-effect mobility in the saturation region of the transistor are calculated, along with values ​​obtained by subtracting the minimum value from the maximum. Here, the saturation region of the transistor is in the range of Vg being 3V or higher and 10V or lower. Gate voltages within this range are generally used in applications such as displays.

[0202] In sample A1, the minimum field-effect mobility in the saturation region of the transistor is 9.8 cm⁻¹. 2 / Vs, with a maximum value of 28.3cm 2 / Vs. This means that the difference between the minimum and maximum field-effect mobility in the saturation region of the transistor in sample A1 is 18.5 cm⁻¹. 2 / Vs. In sample A2, the minimum field-effect mobility in the saturation region of the transistor is 23.3 cm. 2 / Vs, with a maximum value of 51.1cm 2 / Vs. This means that the difference between the minimum and maximum field-effect mobility in the saturation region of the transistor in sample A2 is 27.8 cm⁻¹. 2 / Vs. In sample A3, the minimum field-effect mobility in the saturation region of the transistor is 55.8 cm⁻¹. 2 / Vs, with a maximum value of 67.0cm 2 / Vs. This means that the difference between the minimum and maximum field-effect mobility in the saturation region of the transistor in sample A3 is 11.2 cm⁻¹. 2 / Vs.

[0203] In other words, in sample A1, the minimum field-effect mobility in the saturation region of the transistor is about 65.3% lower than the maximum field-effect mobility. In sample A2, the minimum field-effect mobility in the saturation region of the transistor is about 54.4% lower than the maximum field-effect mobility. In sample A3, the minimum field-effect mobility in the saturation region of the transistor is about 16.7% lower than the maximum field-effect mobility. As described above, sample A3, in which a transistor according to an embodiment of the present invention is formed, has the characteristic that the minimum field-effect mobility in the saturation region of the transistor is 30% or less lower than the maximum field-effect mobility, preferably 20% or less lower.

[0204] Thus, sample A3, which forms a transistor according to one embodiment of the present invention, has the characteristic that the difference between the minimum and maximum field-effect mobility in the saturation region of the transistor is extremely small, specifically 15 cm⁻¹. 2 Below / Vs. Furthermore, sample A3 exhibits high field-effect mobility in the low Vg region (e.g., the region where Vg is greater than 0V and below 5V). When transistors with such characteristics are used, for example, as transistors for pixels in organic EL displays, high current drive capability and high reliability can be obtained.

[0205] 1-3. Evaluation of the shape of the mobility curves simulated by the device

[0206] exist Figures 1A to 1CThe shapes of the mobility curves of the field-effect mobility of the transistors shown are different. Therefore, the shape of the mobility curves is evaluated by device simulation.

[0207] In device simulation, three factors are assumed to determine the shape of the mobility curve: 1. temperature dependence of mobility; 2. donor density distribution in the channel region; and 3. shallow defect state density in the oxide semiconductor film.

[0208] [1. Temperature dependence of migration rate]

[0209] In transistors including oxide semiconductor films, the field-effect mobility increases sharply due to self-heating. The electron mobility (μ) of oxide semiconductor films... n The temperature dependence of ) is expressed by the following formula (5).

[0210] [Formula 5]

[0211]

[0212] In formula (5), μ n300 T represents the electron mobility of an oxide semiconductor film at room temperature. L The lattice temperature is represented. As shown in Equation (5), the field-effect mobility of transistors including oxide semiconductor films increases by a factor of approximately 1.5 of the temperature T.

[0213] [2. Donor density distribution in the channel region]

[0214] The transistors fabricated in samples A1 to A3 have different donor density distributions in their channel regions due to the different deposition conditions of the oxide semiconductor film. In other words, the transistors in samples A1 to A3 have different effective channel lengths.

[0215] Here, refer to Figure 5 Indicate the effective channel length of the transistors in samples A1 to A3.

[0216] Figure 5 This is a schematic diagram illustrating the concept of the effective channel length of a transistor.

[0217] exist Figure 5 In the diagram, GE, GI, and OS represent the gate electrode, gate insulating film, and oxide semiconductor film, respectively. An n-type region is formed in the oxide semiconductor film. The effective channel length of the transistor (L...) eff ) is expressed by the following formula (6).

[0218] [Formula 6]

[0219]

[0220] In formula (6), L g ΔL represents the gate length, and ΔL represents the narrowed width of the channel length.

[0221] For example, the effective channel length of a transistor can be obtained through transmission line model (TLM) analysis.

[0222] In the following explanation, based on the effective channel length described above, we assume a model in which the donor density gradually decreases from the n-type region to the channel region. That is, the donors decrease towards the channel region according to a Gaussian distribution. Figures 6A to 6C A schematic diagram illustrating the donor density of samples A1 to A3 is shown. Figure 6A , Figure 6B and Figure 6C The donor densities of samples A1, A2, and A3 are shown respectively.

[0223] exist Figures 6A to 6C In this context, GE, GI, and OS represent the gate electrode, gate insulating film, and oxide semiconductor film, respectively. Figures 6A to 6C In the oxide semiconductor film shown, the donor density of 5 × 10⁻⁶ is indicated in gray. 18 cm -3 The above area is indicated in black with a donor density of 1×10⁴. 16 cm -3 The following areas.

[0224] from Figures 6A to 6C The results show that the effective channel length of sample A1 is estimated to be 2.0 μm, the effective channel length of sample A2 is estimated to be 1.2 μm, and the effective channel length of sample A3 is estimated to be 0.8 μm. In other words, the ΔL of sample A1, the ΔL of sample A2, and the ΔL of sample A3 are estimated to be 0 μm, 0.4 μm, and 0.6 μm, respectively.

[0225] [3. Shallow defect state density of oxide semiconductor films]

[0226] Next, the shallow defect state density (also known as sDOS) in the oxide semiconductor film will be explained. The sDOS of the oxide semiconductor film can be estimated from the electrical characteristics of the transistor including the oxide semiconductor film. In the following explanation, the interface state density of the transistor is measured. Furthermore, the method considering this interface state density and the number of electrons N trapped by the interface states will be explained. trap A method for predicting subthreshold leakage current under certain conditions.

[0227] By comparing the measured drain current-gate voltage (Id-Vg) characteristics of the transistor with the calculated drain current-gate voltage (Id-Vg) characteristics, the number N of electrons trapped by the interface states can be measured. trap .

[0228] Figure 7 The diagram shows the calculated ideal Id-Vg characteristics and the measured Id-Vg characteristics of a transistor with a source voltage Vs of 0V and a drain voltage Vd of 0.1V. Furthermore, in the transistor measurement results, only the 1×10⁻⁶ drain voltage Id, which is easily measurable, is plotted. -13 Values ​​above A.

[0229] Compared to the calculated ideal Id-Vg characteristics, the measured Id-Vg characteristics show a slower change in drain current Id relative to the gate voltage Vg. This is likely because electrons are captured by shallow interface states located near the energy (denoted as Ec) at the bottom of the conduction band. In this measurement, the number N electrons (per unit area and per unit energy) captured by these shallow interface states is considered using the Fermi distribution function. trap This allows for a more rigorous estimation of the interface state density N. it .

[0230] First, regarding the use Figure 8 The schematic Id-Vg characteristics shown are used to evaluate the number N of electrons trapped by the interface trap state. trap The method is explained below. The dashed line shows the ideal Id-Vg characteristic without trap states obtained through calculation. On the dashed line, ΔV... id This represents the change in gate voltage Vg as the drain current changes from Id1 to Id2. The solid line shows the measured Id-Vg characteristic. On the solid line, ΔV... ex This represents the change in gate voltage Vg as the drain current changes from Id1 to Id2. The potentials of the interface to be observed when the drain current is Id1 and when the drain current is Id2 are respectively referred to as . it1 、 it2 This change is called Δφ. it .

[0231] exist Figure 8 In the above, the measured inclination is smaller than the calculated value, therefore ΔV ex constant ratio ΔV id Large. At this time, ΔV ex With V id The difference between them is equivalent to the potential difference required to capture an electron in a shallow interface state. Therefore, the change in charge caused by the captured electron, ΔQ, can be expressed by the following formula (7). trap .

[0232] [Formula 7]

[0233]

[0234] C tgIt is the combined capacitance of insulators and semiconductors per unit area. Furthermore, the number N of trapped electrons (per unit area and per unit energy) can be used. trap Express ΔQ in equation (8) trap Furthermore, q represents the elementary charge.

[0235] [Formula 8]

[0236]

[0237] Formula (9) is obtained by combining formulas (7) and (8).

[0238] [Formula 9]

[0239]

[0240] Next, by taking Δφ from formula (9) it The limit 0 is obtained by formula (10).

[0241] [Formula 10]

[0242]

[0243] That is, by using the ideal Id-Vg characteristics, the measured Id-Vg characteristics, and formula (10), the number N of electrons trapped at the interface can be estimated. trap Furthermore, the relationship between the drain current and the potential at the interface can be obtained by using the above calculations with a device simulator.

[0244] The number of electrons N per unit area and per unit energy can be expressed by formula (11). trap With interface state density N it The relationship between them.

[0245] [Formula 11]

[0246]

[0247] Here, f(E) represents the Fermi distribution function. N is obtained by fitting Equation (10) to Equation (11). trap , decide N it This can be achieved by setting N. it The device simulator was used to obtain the conduction characteristics including Id < 0.1 pA.

[0248] Will Figure 7 The measured Id-Vg characteristics are applicable to formula (10), in Figure 9 The white circle indicates the extraction of N. trap The result. Figure 9The vertical axis in the equation represents the Fermi energy Ef at the conduction band bottom Ec of the semiconductor. The maximum value is located on the dashed line directly below Ec. When N is used as the value in equation (11), it Assuming the tail distribution in formula (12), such as Figure 9 Like the dashed line, N can be fitted with very high accuracy. trap As a result, the peak value N is obtained as a fitting parameter. ta =1.67×10 13 cm -2 eV -1 and characteristic width W ta =0.105eV.

[0249] [Formula 12]

[0250]

[0251] Figure 10A and Figure 10B The results show the inverse calculation of the Id-Vg characteristics by feeding the obtained interface state fitting curve back to the calculation using a device simulator. Figure 10A The calculated Id-Vg characteristics are shown for drain voltages Vd of 0.1V and 1.8V, and the measured Id-Vg characteristics of the transistor are shown for drain voltages Vd of 0.1V and 1.8V. Figure 10B Therefore Figure 10A The graph shows the logarithmic drain current Id.

[0252] The calculated curves are roughly consistent with the plotted measured values, indicating high repeatability between the calculated and measured values. Therefore, the above method is sufficiently appropriate for calculating the density of shallow defect states.

[0253] [Results of the migration rate curve calculation]

[0254] The sDOS in oxide semiconductor films affects the mobility curve of the field-effect mobility. In particular, near the threshold voltage, electrons are trapped by sDOS, causing a change in the shape of the mobility curve. The sDOS in oxide semiconductor films is expressed by N in equation (12). ta and W ta With respect to the thickness of the oxide semiconductor film (t) OS The product of (12) and (13) is used to represent the mobility curve. Table 1 shows the parameters used in the calculation.

[0255] [Table 1]

[0256] In this embodiment, for changing W taThe mobility curve is calculated based on the value of . Figure 11 W is shown ta The shapes of the mobility curves are different for each value. Figure 11 In, N ta 2.5×10 19 cm -3 eV -1 ΔL is 0. Furthermore, W is set to... ta The seven conditions are 0.015eV, 0.02eV, 0.025eV, 0.03eV, 0.035eV, 0.04eV, and 0.045eV.

[0257] like Figure 11 As shown, W ta The smaller the value, the smaller the energy width of sDOS, and the more rapidly the mobility curve rises. Furthermore, it is known that the smaller the energy width of sDOS, the more the peak value of the mobility curve shifts from the high Vg side to the low Vg side and decreases.

[0258] Next, based on Figures 6A to 6C The donor density distributions of samples A1 to A3 shown are as follows: Figure 11 The shape of the mobility curve shown is calculated for the models corresponding to samples A1 to A3. Figure 12 The calculated mobility curves are shown.

[0259] Figure 12 The calculated mobility curves for models corresponding to samples A1 to A3 are shown. In sample A1, N ta 3.0×10 19 cm -3 eV -1 ΔL is 0, W ta The value is 0.045 eV. In sample A2, N... ta 3.0×10 19 cm -3 eV -1 ΔL is 0.4 μm, W ta The value is 0.035 eV. In sample A3, N... ta 2.5×10 19 cm -3 eV -1 ΔL is 0.6 μm, W ta It is 0.025 eV.

[0260] It can be considered Figure 12 This shows a general reflection of Figures 1A to 1C The results show the shape of the migration curves for samples A1 to A3.

[0261] As mentioned above, sDOS significantly affects the shape of the field-effect mobility curve of a transistor. Therefore, samples A1 to A3 may have different sDOS values ​​in the oxide semiconductor film.

[0262] Therefore, in order to measure the sDOS in the oxide semiconductor film of samples A1 to A3, samples B1 to B3 were manufactured. Samples B1 to B3 differ from samples A1 to A3 only in the size of the transistor. Samples B1, B2, and B3 were manufactured using the same method as samples A1, A2, and A3, respectively.

[0263] Figure 13 The sDOS results for samples B1 to B3 are shown. The transistor size for each of samples B1 to B3 is L / W = 6 / 50 μm.

[0264] like Figure 13 As shown, the highest sDOS was observed in the oxide semiconductor film from sample B1, followed by samples B2 and B3. This means that the highest sDOS was observed in the oxide semiconductor film from sample A1, followed by samples A2 and A3, confirming the accuracy of the device simulation results.

[0265] Furthermore, in each of samples B1 to B3, the peak value of sDOS was less than 5 × 10⁻⁶. 12 cm -2 eV -1 This indicates that samples B1 to B3 each have extremely low sDOS. The peak value of sDOS in the oxide semiconductor film is preferably less than 2.5 × 10⁻⁶. 12 cm -2 eV -1 More preferably less than 1.5 × 10 12 cm -2 eV -1 Further optimization is to select those smaller than 1.0 × 10 12 cm -2 eV -1 .

[0266] Thus, when the sDOS in the oxide semiconductor film is reduced, the mobility curve can rise sharply. Furthermore, the peak value of the mobility curve on the high Vg side can be shifted to the low Vg side, and the peak value can be reduced. That is, when the sDOS in the oxide semiconductor film is reduced, the mobility curve of the field-effect mobility of transistors including oxide semiconductor films can rise sharply, and the saturation of the mobility curve is improved.

[0267] 1-4. Components of a Transistor

[0268] Next, regarding Figures 4A to 4CThe components of the transistor shown are described in detail.

[0269] [Substrate]

[0270] The substrate 102 can be formed using a material with heat resistance capable of withstanding the degree of heat treatment during the manufacturing process.

[0271] Specifically, alkali-free glass, soda-lime glass, potassium glass, crystal glass, quartz, or sapphire can be used. Alternatively, inorganic insulating films can also be used. Examples of such inorganic insulating films include silicon oxide films, silicon nitride films, silicon oxynitride films, and aluminum oxide films.

[0272] The thickness of the aforementioned alkali-free glass can be, for example, 0.2 mm or more and 0.7 mm or less. Alternatively, the aforementioned thickness can be achieved by polishing the alkali-free glass.

[0273] As alkali-free glass, large glass substrates with any of the following dimensions can be used: sixth generation (1500mm × 1850mm), seventh generation (1870mm × 2200mm), eighth generation (2200mm × 2400mm), ninth generation (2400mm × 2800mm), and tenth generation (2950mm × 3400mm). This allows for the manufacture of large-scale display devices.

[0274] Alternatively, a single-crystal semiconductor substrate or polycrystalline semiconductor substrate formed of silicon or silicon carbide, a compound semiconductor substrate formed of silicon germanium, or an SOI substrate can be used as substrate 102.

[0275] Inorganic materials such as metals can also be used as substrate 102. Examples of inorganic materials such as metals include stainless steel and aluminum.

[0276] In addition, organic materials such as resins, resin films, or plastics can also be used as the substrate 102. Examples of resin films include polyesters, polyolefins, polyamides (nylon, aramids, etc.), polyimides, polycarbonates, polyurethanes, acrylic resins, epoxy resins, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), and silicone resins with siloxane bonds.

[0277] As substrate 102, composite materials combining inorganic and organic materials can also be used. Examples of such composite materials include resin films bonded to metal plates or thin glass plates, resin films in which fibrous metals, particulate metals, fibrous glass or particulate glass are dispersed, or inorganic materials in which fibrous resins or particulate resins are dispersed.

[0278] The substrate 102 may support at least one film or layer formed on or under it, and may be one or more of an insulating film, a semiconductor film, or a conductive film.

[0279] [First insulating film]

[0280] The insulating film 104 can be formed by appropriately utilizing sputtering, CVD, evaporation, pulsed laser deposition (PLD), printing, coating, or other methods. The insulating film 104 can be formed, for example, in a single-layer or multi-layer structure having an oxide insulating film and / or a nitride insulating film. To improve the interfacial properties with the oxide semiconductor film 108, the region of the insulating film 104 in contact with the oxide semiconductor film 108 is preferably formed using an oxide insulating film. When the insulating film 104 is formed using an oxide insulating film that releases oxygen upon heating, the oxygen contained in the insulating film 104 can be moved into the oxide semiconductor film 108 by heat treatment.

[0281] The thickness of the insulating film 104 can be 50 nm or more, 100 nm or more and 3000 nm or less, or 200 nm or more and 1000 nm or less. By increasing the thickness of the insulating film 104, the oxygen release of the insulating film 104 can be increased, thereby reducing the interface states at the interface between the insulating film 104 and the oxide semiconductor film 108, as well as the oxygen vacancies contained in the channel region 108i of the oxide semiconductor film 108.

[0282] The insulating film 104 can be formed, for example, in a single-layer or multilayer structure having a silicon oxide film, a silicon oxynitride film, a silicon oxynitride film, a silicon nitride film, an aluminum oxide film, a hafnium oxide film, a gallium oxide film, or a Ga-Zn oxide film. In this embodiment, the insulating film 104 has a multilayer structure of a silicon nitride film and a silicon oxynitride film. By having such a multilayer structure in which the insulating film 104 has a silicon nitride film as the lower layer and a silicon oxynitride film as the upper layer, oxygen can be efficiently supplied to the oxide semiconductor film 108.

[0283] [Oxide semiconductor film]

[0284] The oxide semiconductor film 108 is described in detail in Embodiment 2.

[0285] [Second insulating film]

[0286] Furthermore, the insulating film 110 has the function of supplying oxygen to the oxide semiconductor film 108, especially to the channel region 108i. For example, the insulating film 110 can be formed as a single layer or a stack of oxide insulating films or nitride insulating films. In order to improve the interface characteristics with the oxide semiconductor film 108, the region of the insulating film 110 in contact with the oxide semiconductor film 108 is preferably formed using at least an oxide insulating film. For example, silicon oxide film, silicon oxynitride film, silicon oxynitride film, or silicon nitride film can be used as the insulating film 110.

[0287] The thickness of the insulating film 110 can be 5nm or more and 400nm or less, 5nm or more and 300nm or less, or 10nm or more and 250nm or less.

[0288] Preferably, the insulating film 110 has few defects, typically minimal signals observed by electron spin resonance (ESR). Examples of such signals include those originating from E' centers observed at a g-value of 2.001. Furthermore, E' centers originate from dangling bonds in silicon. The insulating film 110 uses a spin density of 3 × 10⁻⁶ originating from E' centers. 17 spins / cm 3 The following, preferably 5×10 16 spins / cm 3 The following silicon oxide film or silicon oxynitride film is sufficient.

[0289] In the insulating film 110, in addition to the signals mentioned above, a signal originating from nitrogen dioxide (NO2) is sometimes observed. This signal is divided into three signals due to the nuclear spin of N: a first signal, a second signal, and a third signal. The first signal is observed when the g value is 2.037 or higher and 2.039 or lower. The second signal is observed when the g value is 2.001 or higher and 2.003 or lower. The third signal is observed when the g value is 1.964 or higher and 1.966 or lower.

[0290] For example, the insulating film 110 preferably uses a spin density of 1×10⁻⁶ originating from nitrogen dioxide (NO₂). 17 spins / cm 3 Above and below 1×10 18 spins / cm 3 Insulating film.

[0291] Note that nitrogen dioxide (NO2) and other nitrogen oxides (NO) x A state is formed in the insulating film 110. This state is located in the bandgap of the oxide semiconductor film 108. Therefore, when the nitrogen oxide (NO) is formed... xWhen the nitrogen oxide diffuses to the interface between the insulating film 110 and the oxide semiconductor film 108, sometimes this state traps electrons on one side of the insulating film 110. As a result, the trapped electrons remain near the interface between the insulating film 110 and the oxide semiconductor film 108, thereby causing the threshold voltage of the transistor to drift in the positive direction. Therefore, by using a film with a low content of nitrogen oxides as the insulating film 110, the drift of the threshold voltage of the transistor can be reduced.

[0292] As nitrogen oxides (NO) x For insulating films with low ammonia release, silicon oxynitride films can be used, for example. These silicon oxynitride films exhibit a lower ammonia release compared to nitrogen oxides (NOx) as measured by thermal desorption spectroscopy (TDS). x Membranes that release a large amount of ammonia, typically 1×10⁻⁶. 18 cm -3 Above and 5×10 19 cm -3 The following is a summary. Furthermore, the ammonia release mentioned above refers to the total amount released from TDS within the range of a heat treatment temperature of 50°C or higher and 650°C or lower, or 50°C or higher and 550°C or lower.

[0293] Because when heat treatment is performed, nitrogen oxides (NOx) x Nitrogen oxides (NOx) react with ammonia and oxygen, so using insulating films with high ammonia release can reduce nitrogen oxide emissions. x ).

[0294] When analyzing the insulating film 110 using SIMS, the nitrogen concentration in the film is preferably 6 × 10⁻⁶. 20 atoms / cm 3 the following.

[0295] The insulating film 110 can also use hafnium silicate (HfSiO2). x Hafnium silicate containing nitrogen (HfSi) x O y N z Hafnium aluminate (HfAl) containing nitrogen x O y N z It can be formed using high-k materials such as hafnium oxide or halogen oxide. By using high-k materials, the gate leakage current of transistors can be reduced.

[0296] [Third insulating film]

[0297] The insulating film 116 contains nitrogen or hydrogen. Alternatively, the insulating film 116 may also contain fluorine. For example, a nitride insulating film can be used as the insulating film 116. This nitride insulating film can be formed using silicon nitride, silicon oxynitride, silicon oxynitride, silicon fluoride nitride, silicon fluoride, etc. The hydrogen concentration in the insulating film 116 is preferably 1 × 10⁻⁶. 22 atoms / cm 3 That's all. Furthermore, the insulating film 116 contacts the source region 108s and drain region 108d of the oxide semiconductor film 108. Therefore, the concentration of impurities (nitrogen or hydrogen) in the source region 108s and drain region 108d that are in contact with the insulating film 116 increases, thereby increasing the carrier density of the source region 108s and drain region 108d.

[0298] [Fourth insulating film]

[0299] An oxide insulating film can be used as the insulating film 118. Alternatively, a laminate of an oxide insulating film and a nitride insulating film can be used as the insulating film 118. For example, silicon oxide, silicon oxynitride, silicon oxynitride, aluminum oxide, hafnium oxide, gallium oxide, or Ga-Zn oxide can be used as the insulating film 118.

[0300] Furthermore, the insulating film 118 is preferably used as a barrier film against hydrogen or water from the outside.

[0301] The thickness of the insulating film 118 can be 30nm or more and 500nm or more and 100nm or more and 400nm or less.

[0302] [Fifth Insulating Film]

[0303] The insulating film 122 is insulating and is formed using inorganic or organic materials. Examples of such inorganic materials include silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, aluminum oxide, aluminum nitride, etc. Examples of such organic materials include photosensitive resin materials such as acrylic resin or polyimide resin.

[0304] [Conductive film]

[0305] Conductive films 106, 112, 120a, and 120b can be formed using methods such as sputtering, vacuum evaporation, PLD, and thermal CVD. Conductive films 106, 112, 120a, and 120b can be made from conductive metal films, conductive films that reflect visible light, or conductive films that allow visible light to pass through.

[0306] The conductive metal film can be made of a material containing a metallic element selected from aluminum, gold, platinum, silver, copper, chromium, tantalum, titanium, molybdenum, tungsten, nickel, iron, cobalt, palladium, and manganese. Alternatively, an alloy containing any of the aforementioned metallic elements can be used.

[0307] Specifically, as the aforementioned conductive metal film, a two-layer structure consisting of a copper film stacked on a titanium film, a two-layer structure consisting of a copper film stacked on a titanium nitride film, a two-layer structure consisting of a copper film stacked on a tantalum nitride film, and a three-layer structure consisting of a titanium film, a copper film, and a titanium film stacked sequentially can be used. In particular, conductive films containing copper are preferred because they can reduce resistance. An example of a conductive film containing copper is an alloy film containing copper and manganese. This alloy film can be processed using a wet etching method, and is therefore preferred.

[0308] Note that tantalum nitride films are preferably used as conductive films 106, 112, 120a, and 120b. These tantalum nitride films are conductive and have high barrier properties against copper or hydrogen. Because little hydrogen is released from the tantalum nitride film itself, it is suitable as a metal film in contact with or near the oxide semiconductor film 108.

[0309] Conductive polymers or conductive materials can also be used as the conductive films described above.

[0310] The conductive film with the aforementioned function of reflecting visible light can be made of a material containing a metallic element selected from gold, silver, copper, and palladium. In particular, it is preferred because the reflectivity of visible light can be improved by using a conductive film containing silver.

[0311] The conductive film that enables visible light to pass through can be made of materials containing elements selected from indium, tin, zinc, gallium, and silicon. Specifically, In oxide, Zn oxide, In-Sn oxide (also known as ITO), In-Sn-Si oxide (also known as ITSO), In-Zn oxide, In-Ga-Zn oxide, etc., can be used.

[0312] As the conductive film with the aforementioned function of allowing visible light to pass through, a film containing graphene or graphite can also be used. A film containing graphene oxide can be formed by forming a film containing graphene oxide and then reducing it. As a reduction method, methods utilizing heating or a reducing agent can be employed, etc.

[0313] Conductive films 112, 120a, and 120b can be formed using an electroless plating method. Materials that can be deposited using this electroless plating method can be, for example, one or more selected from Cu, Ni, Al, Au, Sn, Co, Ag, and Pd. Cu or Ag is more preferred because it can reduce the resistance of the conductive film.

[0314] When a conductive film is formed using an electroless plating method, a diffusion-preventing film can also be formed beneath the conductive film to prevent the constituent elements of the conductive film from diffusing to the outside. A seed layer capable of allowing the conductive film to grow can also be formed between the diffusion-preventing film and the conductive film. The diffusion-preventing film can be formed, for example, using a sputtering method. For example, a tantalum nitride film or a titanium nitride film can be used as the diffusion-preventing film. The seed layer can be formed using an electroless plating method. The same material as the conductive film formed using the electroless plating method can be used as the seed layer.

[0315] As the conductive film 112, an oxide semiconductor, such as an In-Ga-Zn oxide, can be used. This oxide semiconductor can have a high carrier density when nitrogen or hydrogen is supplied from the insulating film 116. In other words, the oxide semiconductor is used as an oxide conductor (OC). Therefore, the oxide semiconductor can be used as a gate electrode.

[0316] For example, the conductive film 112 may have a single-layer structure of oxide conductor (OC), a single-layer structure of metal film, or a stacked structure of oxide conductor (OC) and metal film.

[0317] Note that preferably, the conductive film 112 has a single-layer structure of a light-shielding metal film or a stacked structure of an oxide conductor (OC) and a light-shielding metal film, because it can block light from reaching the channel region 108i formed below the conductive film 112. When the conductive film 112 has a stacked structure of an oxide semiconductor or oxide conductor (OC) and a light-shielding metal film, any of the following effects will occur when a metal film (e.g., a titanium film or a tungsten film, etc.) is formed on the oxide semiconductor or oxide conductor (OC): the constituent elements of the metal film diffuse to the oxide semiconductor or oxide conductor (OC) side and the oxide semiconductor or oxide conductor (OC) becomes low-resistance; the resistance becomes low due to damage during the deposition of the metal film (e.g., sputtering damage, etc.); and oxygen in the oxide semiconductor or oxide conductor (OC) diffuses into the metal film, thereby forming oxygen vacancies and becoming low-resistance.

[0318] The thickness of conductive films 106, 112, 120a, and 120b can be greater than 30nm and less than 500nm or greater than 100nm and less than 400nm.

[0319] 1-5 Example 2 of transistor structure

[0320] Next, refer to Figure 14A and Figure 14B , Figure 15A and Figure 15B as well as Figure 16A and Figure 16B to and Figures 4A to 4C The different transistor structures shown are explained.

[0321] Figure 14A and Figure 14B This is a cross-sectional view of transistor 100B. Figure 15A and Figure 15B This is a cross-sectional view of transistor 100C. Figure 16A and Figure 16B This is a cross-sectional view of transistor 100D. Top views of transistors 100B, 100C, and 100D are also shown. Figure 4A The top view of transistor 100A shown is the same, so it is not illustrated.

[0322] Figure 14A and Figure 14B The transistor 100B shown differs from transistor 100A in the stacked structure of conductive film 112, the shape of conductive film 112, and the shape of insulating film 110.

[0323] The conductive film 112 of transistor 100B includes a conductive film 112_1 on the insulating film 110 and a conductive film 112_2 on the conductive film 112_1. For example, by using an oxide conductive film as the conductive film 112_1, excess oxygen can be added to the insulating film 110. The aforementioned oxide conductive film can be formed by sputtering in an atmosphere containing oxygen gas. Examples of oxide conductive films that can be used include oxide films containing indium and tin, oxide films containing tungsten and indium, oxide films containing tungsten, indium, and zinc, oxide films containing titanium and indium, oxide films containing titanium, indium, and tin, oxide films containing indium and zinc, oxide films containing silicon, indium, and tin, and oxide films containing indium, gallium, and zinc.

[0324] like Figure 14B As shown, conductive film 112_2 and conductive film 106 are connected through opening 143. By forming opening 143 after forming the conductive film that will become conductive film 112_1, it is possible to achieve... Figure 14B The shape shown. When an oxide conductive film is used as conductive film 112_1, the contact resistance between conductive film 112 and conductive film 106 can be reduced by adopting a structure in which conductive film 112_2 is connected to conductive film 106.

[0325] The conductive film 112 and insulating film 110 of transistor 100B have a tapered shape. More specifically, the lower end of the conductive film 112 is located outside the upper end of the conductive film 112. The lower end of the insulating film 110 is located outside the upper end of the insulating film 110. In addition, the lower end of the conductive film 112 is located at approximately the same position as the upper end of the insulating film 110.

[0326] Preferably, the conductive film 112 and the insulating film 110, like transistor 100B, have a tapered shape, because the coverage of the insulating film 116 can be improved compared to the case of transistor 100A, where the conductive film 112 and the insulating film 110 are rectangular.

[0327] The other components of transistor 100B are the same as those of transistor 100A described above, and it performs the same function.

[0328] Figure 15A and Figure 15B The transistor 100C shown differs from transistor 100A in the stacked structure of conductive film 112, the shape of conductive film 112, and the shape of insulating film 110.

[0329] The conductive film 112 of transistor 100C includes a conductive film 112_1 on the insulating film 110 and a conductive film 112_2 on the conductive film 112_1. Furthermore, the lower end of the conductive film 112_1 is located outside the lower end of the conductive film 112_2. The conductive film 112_1, the conductive film 112_2, and the insulating film 110 can be formed using the same mask. To obtain the above structure, for example, the conductive film 112_2 can be processed using a wet etching method, and the conductive film 112_1 and the insulating film 110 can be processed using a dry etching method.

[0330] By employing the structure of transistor 100C, region 108f is sometimes formed in oxide semiconductor film 108. Region 108f is formed between channel region 108i and source region 108s and between channel region 108i and drain region 108d.

[0331] Region 108f is used as either a high-resistance region or a low-resistance region. The high-resistance region has a resistance equal to that of channel region 108i and does not overlap with the conductive film 112 used as the gate electrode. When region 108f is a high-resistance region, it is used as a bias region. To suppress the decrease in the on-state current of transistor 100C, the length of each of the bias regions 108f in the channel length (L) direction can be less than 1 μm.

[0332] The low-resistance region has a resistance lower than that of the channel region 108i and higher than that of the source region 108s and the drain region 108d. When region 108f is a low-resistance region, it is used as a Lightly Doped Drain (LDD) region. Using region 108f as an LDD region can mitigate the electric field in the drain region, thus reducing the threshold voltage variation of the transistor caused by the electric field in the drain region.

[0333] Note that when region 108f is used as an LDD region, region 108f can be formed by supplying one or more of nitrogen, hydrogen and fluorine from insulating film 116 to region 108f, or by adding impurity elements above conductive film 112_1 using insulating film 110 and conductive film 112_1 as a mask, the impurities being added to oxide semiconductor film 108 through conductive film 112_1 and insulating film 110.

[0334] like Figure 15B As shown, conductive film 112_2 and conductive film 106 are connected through opening 143.

[0335] The other components of transistor 100C are the same as those of transistor 100A described above, and they have the same effect.

[0336] Figure 16A and Figure 16B The transistor 100D shown differs from transistor 100A in the stacked structure of conductive film 112, the shape of conductive film 112, and the shape of insulating film 110.

[0337] The conductive film 112 of the transistor 100D includes a conductive film 112_1 on the insulating film 110 and a conductive film 112_2 on the conductive film 112_1. Furthermore, the lower end of the conductive film 112_1 is located outside the lower end of the conductive film 112_2. Additionally, the lower end of the insulating film 110 is located outside the lower end of the conductive film 112_1. The conductive film 112_1, conductive film 112_2, and insulating film 110 can be formed using the same mask. To obtain the above structure, for example, the conductive film 112_2 and conductive film 112_1 are processed using a wet etching method, and the insulating film 110 is processed using a dry etching method.

[0338] Similar to transistor 100C, in transistor 100D, region 108f is sometimes formed in oxide semiconductor film 108. Region 108f is formed between channel region 108i and source region 108s and between channel region 108i and drain region 108d.

[0339] like Figure 16B As shown, conductive film 112_2 and conductive film 106 are connected through opening 143.

[0340] The other components of transistor 100D are the same as those of transistor 100A described above, and it performs the same function.

[0341] 1-6. Example 3 of transistor structure

[0342] Next, refer to Figure 17A and Figure 17B , Figure 18A and Figure 18B , Figure 19A and Figure 19B , Figure 20A and Figure 20B as well as Figure 21A and Figure 21B to and Figures 4A to 4C The structure of transistor 100A shown is illustrated with different transistor structures.

[0343] Figure 17A and Figure 17B This is a cross-sectional view of transistor 100E. Figure 18A and Figure 18B This is a cross-sectional view of transistor 100F. Figure 19A and Figure 19B This is a cross-sectional view of transistor 100G. Figure 20A and Figure 20B This is a cross-sectional view of transistor 100H. Figure 21A and Figure 21B This is a cross-sectional view of transistor 100J. The top views of transistors 100E, 100F, 100G, 100H, and 100J are shown. Figure 4A The top view of transistor 100A shown is the same, so it is not illustrated.

[0344] Transistors 100E, 100F, 100G, 100H, and 100J differ from transistor 100A in the structure of the oxide semiconductor film 108. All other components are the same as those of transistor 100A, and they perform the same function.

[0345] Figure 17A and Figure 17B The oxide semiconductor film 108 of the transistor 100E shown includes an oxide semiconductor film 108_1 on the insulating film 104, an oxide semiconductor film 108_2 on the oxide semiconductor film 108_1, and an oxide semiconductor film 108_3 on the oxide semiconductor film 108_2. The channel region 108i, the source region 108s, and the drain region 108d each have a three-layer structure of oxide semiconductor film 108_1, oxide semiconductor film 108_2, and oxide semiconductor film 108_3.

[0346] Figure 18A and Figure 18B The oxide semiconductor film 108 of the transistor 100F shown includes an oxide semiconductor film 108_2 on the insulating film 104 and an oxide semiconductor film 108_3 on the oxide semiconductor film 108_2. The channel region 108i, the source region 108s, and the drain region 108d each have a two-layer structure of oxide semiconductor film 108_2 and oxide semiconductor film 108_3.

[0347] Figure 19Aand Figure 19B The oxide semiconductor film 108 of the transistor 100G shown includes an oxide semiconductor film 108_1 on the insulating film 104 and an oxide semiconductor film 108_2 on the oxide semiconductor film 108_1. The channel region 108i, the source region 108s, and the drain region 108d each have a two-layer structure of oxide semiconductor film 108_1 and oxide semiconductor film 108_2.

[0348] Figure 20A and Figure 20B The oxide semiconductor film 108 of the transistor 100H shown includes an oxide semiconductor film 108_1 on the insulating film 104, an oxide semiconductor film 108_2 on the oxide semiconductor film 108_1, and an oxide semiconductor film 108_3 on the oxide semiconductor film 108_2. The channel region 108i has a three-layer structure of oxide semiconductor film 108_1, oxide semiconductor film 108_2, and oxide semiconductor film 108_3, and the source region 108s and drain region 108d each have a two-layer structure of oxide semiconductor film 108_1 and oxide semiconductor film 108_2. Furthermore, in the cross-section of the transistor 100H in the channel width (W) direction, the oxide semiconductor film 108_3 covers the sides of oxide semiconductor film 108_1 and oxide semiconductor film 108_2.

[0349] Figure 21A and Figure 21B The oxide semiconductor film 108 of the transistor 100J shown includes an oxide semiconductor film 108_2 on the insulating film 104 and an oxide semiconductor film 108_3 on the oxide semiconductor film 108_2. The channel region 108i has a two-layer structure of oxide semiconductor film 108_2 and oxide semiconductor film 108_3, and the source region 108s and drain region 108d each have a single-layer structure of oxide semiconductor film 108_2. Furthermore, in a cross-section along the channel width (W) direction of the transistor 100J, the oxide semiconductor film 108_3 covers the side surface of the oxide semiconductor film 108_2.

[0350] The side surface of the channel region 108i in the channel width (W) direction, or the region near that side surface, is susceptible to defects (e.g., oxygen vacancies) due to damage during processing, or is easily contaminated due to impurity adhesion. Therefore, even if the channel region 108i is substantially intrinsic, the side surface of the channel region 108i in the channel width (W) direction, or the region near that side surface, can be activated by applying pressure such as an electric field, thus easily becoming a low-resistance (n-type) region. Furthermore, if the side surface of the channel region 108i in the channel width (W) direction, or the region near that side surface, is an n-type region, then parasitic channels may sometimes form because this n-type region becomes a pathway for charge carriers.

[0351] Therefore, in transistors 100H and 100J, the channel region 108i has a stacked structure, and the sidewalls of the channel region 108i in the channel width (W) direction are covered by one layer of the stack. By adopting this structure, defects on or near the sidewalls of the channel region 108i can be suppressed, or the adhesion of impurities to or near the sidewalls of the channel region 108i can be reduced.

[0352] [With structure]

[0353] Here, refer to Figures 22A to 22C The tape structures of insulating film 104, oxide semiconductor films 108_1, 108_2, 108_3, and insulating film 110 are described. Figures 22A to 22C All are 108i band structures in the channel region.

[0354] Figure 22A An example of a strip structure in the thickness direction of a stack of insulating film 104, oxide semiconductor films 108_1, 108_2, 108_3 and insulating film 110 is shown. Figure 22B An example of a strip structure in the thickness direction of a stack including an insulating film 104, oxide semiconductor films 108_2, 108_3 and an insulating film 110 is shown. Figure 22C An example of a strip structure in the thickness direction of a stack of insulating films 104, oxide semiconductor films 108_1, 108_2, and insulating film 110 is shown. Furthermore, for ease of understanding, the strip structure illustrates the conduction band bottom level (Ec) of insulating films 104, oxide semiconductor films 108_1, 108_2, 108_3, and insulating film 110.

[0355] exist Figure 22A In the strip structure, each of the insulating films 104 and 110 uses a silicon oxide film, the oxide semiconductor film 108_1 uses an oxide semiconductor film formed by a metal oxide target with an atomic ratio of In, Ga and Zn of 1:3:2, the oxide semiconductor film 108_2 uses an oxide semiconductor film formed by a metal oxide target with an atomic ratio of In, Ga and Zn of 4:2:4.1, and the oxide semiconductor film 108_3 uses an oxide semiconductor film formed by a metal oxide target with an atomic ratio of In, Ga and Zn of 1:3:2.

[0356] exist Figure 22BIn the strip structure, each of the insulating films 104 and 110 uses a silicon oxide film, the oxide semiconductor film 108_2 uses an oxide semiconductor film formed by a metal oxide target with an atomic ratio of In, Ga and Zn of 4:2:4.1, and the oxide semiconductor film 108_3 uses an oxide semiconductor film formed by a metal oxide target with an atomic ratio of In, Ga and Zn of 1:3:2.

[0357] exist Figure 22C In the strip structure, each of the insulating films 104 and 110 uses a silicon oxide film, the oxide semiconductor film 108_1 uses an oxide semiconductor film formed by a metal oxide target with an atomic ratio of In, Ga and Zn of 1:3:2, and the oxide semiconductor film 108_2 uses an oxide semiconductor film formed by a metal oxide target with an atomic ratio of In, Ga and Zn of 4:2:4.1.

[0358] like Figure 22A As shown, in oxide semiconductor films 108_1, 108_2, and 108_3, the conduction band bottom energy level changes smoothly. (As...) Figure 22B As shown, in oxide semiconductor films 108_2 and 108_3, the conduction band bottom energy level changes smoothly. Figure 22C As shown, in oxide semiconductor films 108_1 and 108_2, the bottom energy level of the conduction band changes smoothly. In other words, the bottom energy level of the conduction band changes continuously or is continuously coupled. To achieve this band structure, impurities that would form defect states such as trap centers or recombination centers are not present at the interface between oxide semiconductor films 108_1 and 108_2 or at the interface between oxide semiconductor films 108_2 and 108_3.

[0359] In order to form continuous bonding in oxide semiconductor films 108_1, 108_2, and 108_3, it is necessary to use a multi-chamber deposition apparatus (sputtering apparatus) equipped with a lock-up chamber to continuously form films without exposing each film to the atmosphere.

[0360] By adopting Figure 22A , Figure 22B or Figure 22C In the strip structure shown, the oxide semiconductor film 108_2 is used as a well, and in the transistor having the above-described stacked structure, the channel region is formed in the oxide semiconductor film 108_2.

[0361] By providing oxide semiconductor films 108_1 and 108_3, defect states can be moved away from oxide semiconductor film 108_2.

[0362] Sometimes, compared to the conduction band bottom level (Ec) of the oxide semiconductor film 108_2 used as the channel region, the defect states are farther from the vacuum level, and electrons tend to accumulate in the defect states. When electrons accumulate in the defect states, they become negative fixed charges, causing the threshold voltage of the transistor to drift in the positive direction. Therefore, it is preferable that the defect states are closer to the vacuum level than the conduction band bottom level (Ec) of the oxide semiconductor film 108_2. By adopting the above structure, electrons are less likely to accumulate in the defect states. As a result, the on-state current of the transistor can be increased and the field-effect mobility can be improved.

[0363] The conduction band bottom energy level of each of oxide semiconductor films 108_1 and 108_3 is closer to the vacuum level than the conduction band bottom energy level of oxide semiconductor film 108_2. Typically, the difference between the conduction band bottom energy level of oxide semiconductor film 108_2 and the conduction band bottom energy level of each of oxide semiconductor films 108_1 and 108_3 is greater than or equal to 0.15 eV or 0.5 eV, and less than or equal to 2 eV or 1 eV. In other words, the difference between the electron affinity of each of oxide semiconductor films 108_1 and 108_3 and the electron affinity of oxide semiconductor film 108_2 is greater than or equal to 0.15 eV or 0.5 eV, and less than or equal to 2 eV or 1 eV.

[0364] With the above structure, the oxide semiconductor film 108_2 is used as the main current path. That is, the oxide semiconductor film 108_2 is used as the channel region, and the oxide semiconductor films 108_1 and 108_3 are used as oxide insulating films. The oxide semiconductor films 108_1 and 108_3 preferably each include one or more of the metal elements that constitute a portion of the oxide semiconductor film 108_2 forming the channel region. By adopting the above structure, interface scattering is less likely to occur at the interface between oxide semiconductor films 108_1 and 108_2 or at the interface between oxide semiconductor films 108_2 and 108_3. Therefore, carrier movement is not hindered at this interface, and the transistor can have a high field-effect mobility.

[0365] To prevent each of the oxide semiconductor films 108_1 and 108_3 from being used as part of the channel region, the oxide semiconductor films 108_1 and 108_3 are made of materials with sufficiently low conductivity. Therefore, based on their physical properties and / or functions, the oxide semiconductor films 108_1 and 108_3 can be referred to as oxide insulating films. Alternatively, the oxide semiconductor films 108_1 and 108_3 may be made of materials whose electron affinity (the difference between the vacuum level and the conduction band bottom level) is lower than that of the oxide semiconductor film 108_2 and whose conduction band bottom level differs from that of the oxide semiconductor film 108_2 (band offset). Furthermore, to suppress the difference in threshold voltages arising from the drain voltage value, the oxide semiconductor films 108_1 and 108_3 preferably use materials whose conduction band bottom level is closer to the vacuum level than that of the oxide semiconductor film 108_2. For example, the difference between the conduction band bottom energy level of oxide semiconductor film 108_2 and the conduction band bottom energy level of each of oxide semiconductor films 108_1 and 108_3 is preferably 0.2 eV or more, more preferably 0.5 eV or more.

[0366] The oxide semiconductor films 108_1 and 108_3 preferably do not have a spinel-type crystalline structure. This is because if the oxide semiconductor films 108_1 and 108_3 have a spinel-type crystalline structure, the constituent elements of the conductive films 120a and 120b may sometimes diffuse into the oxide semiconductor film 108_2 at the interface between the spinel-type crystalline structure and other regions. Note that the oxide semiconductor films 108_1 and 108_3 are each preferably CAAC-OS as described later, in which case the properties of blocking constituent elements such as copper in the conductive films 120a and 120b are improved.

[0367] Although this embodiment shows an example of an oxide semiconductor film formed using a metal oxide target with an atomic ratio of In, Ga, and Zn of 1:3:2 for each of the oxide semiconductor films 108_1 and 108_3, one embodiment of the present invention is not limited thereto. For example, each of the oxide semiconductor films 108_1 and 108_3 may also be an oxide semiconductor film formed using a metal oxide target with an atomic ratio of In, Ga, and Zn of 1:1:1, 1:1:1.2, 1:3:4, 1:3:6, 1:4:5, 1:5:6, or 1:10:1. Alternatively, the oxide semiconductor films 108_1 and 108_3 may also be oxide semiconductor films formed using a metal oxide target with an atomic ratio of Ga and Zn of 10:1. When oxide semiconductor film 108_2 is formed using a metal oxide target with an atomic ratio of In, Ga, and Zn of 1:1:1, and oxide semiconductor films 108_1 and 108_3 are formed using a metal oxide target with an atomic ratio of Ga and Zn of 10:1, the difference between the conduction band bottom energy level of oxide semiconductor film 108_2 and the conduction band bottom energy level of oxide semiconductor films 108_1 and 108_3 can be 0.6 eV or more, which is preferred.

[0368] When oxide semiconductor films 108_1 and 108_3 are formed using a metal oxide target with an In, Ga, and Zn atomic ratio of 1:1:1, the atomic ratio of In, Ga, and Zn in oxide semiconductor films 108_1 and 108_3 may be 1:β1:β2 (0 < β1 ≤ 2, 0 < β2 ≤ 2). When oxide semiconductor films 108_1 and 108_3 are formed using a metal oxide target with an In, Ga, and Zn atomic ratio of 1:3:4, the atomic ratio of In, Ga, and Zn in oxide semiconductor films 108_1 and 108_3 may be 1:β3:β4 (1 ≤ β3 ≤ 5, 2 ≤ β4 ≤ 6). When oxide semiconductor films 108_1 and 108_3 are formed using a metal oxide target with an atomic ratio of In, Ga, and Zn of 1:3:6, the atomic ratio of In, Ga, and Zn in oxide semiconductor films 108_1 and 108_3 may be 1:β5:β6 (1≤β5≤5, 4≤β6≤8).

[0369] At least a portion of this embodiment can be implemented in combination with other embodiments described in this specification.

[0370] (Implementation Method 2)

[0371] In this embodiment, refer to Figures 23A to 23C , Figure 24 , Figure 25, Figures 26A to 26C , Figures 27A to 27C , Figures 28A to 28C , Figures 29A to 29C , Figures 30A to 30C , Figures 31A to 31C , Figure 32A and Figure 32B , Figure 33 , Figure 34 , Figures 35A1 to 35C2 , Figure 36 , Figures 37A1 to 37C2 as well as Figures 38A to 38C The composition and structure of an oxide semiconductor film that can be used in one embodiment of the present invention will be described.

[0372] 2-1. Composition of oxide semiconductor films

[0373] First, the composition of the oxide semiconductor film will be explained.

[0374] The oxide semiconductor film preferably contains at least indium or zinc. It is particularly preferred to contain both indium and zinc. Additionally, it is preferable to also contain aluminum, gallium, yttrium, or tin. Furthermore, it may contain one or more elements selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium.

[0375] Consider the case where the oxide semiconductor film contains indium, element M, and zinc. Element M can be aluminum, gallium, yttrium, or tin, etc. Alternatively, element M can also be boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc. Note that element M can be a combination of two or more of the above elements.

[0376] First, use Figures 23A to 23C This section describes a preferred atomic ratio range of indium, element M, and zinc in an oxide semiconductor film according to one embodiment of the present invention. Note that the ratio of oxygen atoms is not illustrated. The atomic ratios of indium, element M, and zinc in the oxide semiconductor film are represented by [In], [M], and [Zn], respectively.

[0377] exist Figures 23A to 23C In the diagram, the dashed lines represent the atomic ratios of [In]:[M]:[Zn](1):(1-):1 (-1≤≤1), [In]:[M]:[Zn](1):(1-):2, [In]:[M]:[Zn](1):(1-):3, [In]:[M]:[Zn](1):(1-):4, and [In]:[M]:[Zn](1):(1-):5.

[0378] The dotted-dash line represents the atomic ratios of [In]:[M]:[Zn] = 1:1:β (β ≥ 0), [In]:[M]:[Zn] = 1:2:β, [In]:[M]:[Zn] = 1:3:β, [In]:[M]:[Zn] = 1:4:β, [In]:[M]:[Zn] = 2:1:β, and [In]:[M]:[Zn] = 5:1:β.

[0379] The double-dotted line represents the ratio of the number of atoms in [In]:[M]:[Zn]=(1):2:(1-)(-1≤≤1). Figures 23A to 23C The oxide semiconductor film shown has an atomic ratio of [In]:[M]:[Zn] = 0:2:1 or a value close to it, which is prone to having a spinel-type crystalline structure.

[0380] Figure 23A and Figure 23B An example is shown of a preferred atomic ratio range of indium, element M, and zinc contained in an oxide semiconductor film according to an embodiment of the present invention.

[0381] Figure 24 An example of the crystal structure of InMZnO4 with an atomic ratio of [In]:[M]:[Zn] = 1:1:1 is shown. Figure 24 This is the crystal structure of InMZnO4 when viewed from a direction parallel to the b-axis. Figure 24 The metal element shown in the layer containing M, Zn, and oxygen (hereinafter referred to as the (M,Zn) layer) represents element M or zinc. At this point, the proportions of element M and zinc are equal. Element M and zinc can substitute for each other, and their arrangement is irregular.

[0382] InMZnO4 has a layered crystal structure (also known as a layered structure), such as Figure 24 As shown, the layer containing indium and oxygen (hereinafter referred to as the In layer) : the (M,Zn) layer containing elements M, zinc and oxygen = 1:2.

[0383] Indium and element M can be interchanged. Therefore, element M in a (M, Zn) layer can be replaced by indium, and the layer can be represented as an (In, M, Zn) layer. In this case, a layered structure with In layer : (In, M, Zn) layer = 1 : 2 is obtained.

[0384] Oxides with an atomic ratio of [In]:[M]:[Zn] = 1:1:2 have a layered structure with an In layer : (M,Zn) layer ratio of 1:3. That is, as [Zn] increases relative to [In] and [M], the proportion of the (M,Zn) layer relative to the In layer increases when the oxide is crystallized.

[0385] Note that in oxides, when the In layer : (M, Zn) layer ratio is 1 (not an integer), the oxide sometimes has multiple layered structures with In layer : (M, Zn) layer ratios of 1 (integer). For example, in the case of [In]:[M]:[Zn] = 1:1:1.5, the oxide sometimes has a mixed structure of In layer : (M, Zn) layer ratio 1:2 and In layer : (M, Zn) layer ratio 1:3.

[0386] For example, when forming oxides using a sputtering apparatus, a film is formed with an atomic ratio that is offset from that of the target material. In particular, depending on the substrate temperature during deposition, sometimes the [Zn] of the film is less than that of the target material.

[0387] Sometimes, multiple phases coexist in oxides (e.g., two-phase coexistence, three-phase coexistence, etc.). For example, when the atomic ratio is close to [In]:[M]:[Zn] = 0:2:1, spinel-type and layered-type crystalline structures tend to coexist. When the atomic ratio is close to [In]:[M]:[Zn] = 1:0:0, ferromanganese-type and layered-type crystalline structures tend to coexist. When multiple phases coexist in oxides, grain boundaries sometimes form between different crystalline structures.

[0388] When the indium content of the oxide is high, the carrier mobility (electron mobility) can be improved.

[0389] On the other hand, when the indium and zinc content of the oxide decreases, the carrier mobility decreases. Therefore, the ratio of the number of atoms in the [In]:[M]:[Zn]0:1:0 ratio and the ratio of the number of atoms in the vicinity of this ratio (e.g., Figure 23C In region C), the insulation becomes higher.

[0390] Therefore, the oxide in one embodiment of the present invention preferably has Figure 23A The ratio of the number of atoms in region A. When this ratio of the number of atoms is achieved, a layered structure with high carrier mobility and few grain boundaries can be obtained.

[0391] Figure 23B Region B in the diagram shows the atomic ratios [In]:[M]:[Zn] = 4:2:3 to 4:2:4.1 and their neighboring values. The neighboring values ​​include the atomic ratio [In]:[M]:[Zn] = 5:3:4. Oxides with atomic ratios represented by region B are excellent oxides exhibiting particularly high crystallinity and high carrier mobility.

[0392] When the oxide semiconductor film is an In-M-Zn oxide, it is preferable that the atomic ratio of the metal elements in the sputtering target used to form the In-M-Zn oxide film satisfies In≧M and Zn≧M. Preferably, the atomic ratios of the metal elements in such a sputtering target are In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=2:1:1.5, In:M:Zn=2:1:2.3, In:M:Zn=2:1:3, In:M:Zn=3:1:2, In:M:Zn=4:2:4.1, and In:M:Zn=5:1:7. The atomic ratio of the formed oxide semiconductor film deviates from the aforementioned atomic ratio of the metal elements in the sputtering target in approximately ±40°. For example, when using a sputtering target with an atomic ratio of In:Ga:Zn=4:2:4.1, the resulting oxide semiconductor film may have an atomic ratio of In:Ga:Zn=4:2:3 or similar.

[0393] In this specification, "nearby" refers to a range of ±1 relative to the ratio of atoms of metal atom M, preferably a range of ±0.5. For example, when the composition of the oxide semiconductor film is approximately In:Ga:Zn = 4:2:3, the ratio of Ga is 1 or more and 3 or less (1≤Ga≤3) and the ratio of Zn is 2 or more and 4 or less (2≤Zn≤4), preferably the ratio of Ga is 1.5 or more and 2.5 or less (1.5≤Ga≤2.5) and the ratio of Zn is 2 or more and 4 or less (2≤Zn≤4).

[0394] Note that the conditions for the formation of a layered structure in an oxide semiconductor film are not solely determined by the atomic ratio. The formation of a layered structure is difficult to differentiate based on the atomic ratio. On the other hand, even with the same atomic ratio, a layered structure may sometimes form and sometimes not, depending on the formation conditions. Therefore, the regions illustrated each represent the atomic ratio at which the oxide semiconductor film exhibits a layered structure, and the boundaries between regions A and C are unclear.

[0395] 2-2. Carrier density of oxide semiconductor films

[0396] Next, the carrier density of the oxide semiconductor film will be explained.

[0397] Examples of factors that affect the carrier density of oxide semiconductor films include oxygen vacancies (Vo) and impurities in oxide semiconductor films.

[0398] When the amount of oxygen vacancies in an oxide semiconductor film increases, the defect state density increases if hydrogen bonds to these vacancies (this state can also be called VoH). The defect state density also increases with the amount of impurities in the oxide semiconductor film. Therefore, the carrier density of the oxide semiconductor film can be controlled by controlling the defect state density.

[0399] The following describes transistors that use oxide semiconductor films in the channel region.

[0400] When the aim is to suppress the negative drift of the threshold voltage of a transistor or to reduce the off-state current of a transistor, it is preferable to reduce the carrier density of the oxide semiconductor film. To reduce the carrier density of the oxide semiconductor film, the impurity concentration in the oxide semiconductor film can be reduced to decrease the defect state density. In this specification, a state with low impurity concentration and low defect state density is referred to as "high-purity intrinsic" or "substantially high-purity intrinsic". The carrier density of a high-purity intrinsic oxide semiconductor film is less than 8 × 10⁻⁶. 15 cm -3 Preferably less than 1×10 11 cm -3 More preferably, less than 1×10 10 cm -3 And it is 1×10 -9 cm -3 above.

[0401] On the other hand, when the aim is to increase the on-state current of the transistor or improve the field-effect mobility of the transistor, it is preferable to increase the carrier density of the oxide semiconductor film. When the aim is to increase the carrier density of the oxide semiconductor film, the impurity concentration or defect state density of the oxide semiconductor film is slightly increased. Alternatively, it is preferable to reduce the band gap of the oxide semiconductor film. For example, in the range where an excellent on / off ratio of the transistor's Id-Vg characteristics is obtained, an oxide semiconductor film with a slightly higher impurity concentration or a slightly higher defect state density can be considered substantially intrinsic. Furthermore, an oxide semiconductor film with a high electron affinity and a small band gap, resulting in increased thermally excited electron (carrier) density, can be considered substantially intrinsic. Additionally, transistors using oxide semiconductor films with higher electron affinity have lower threshold voltages.

[0402] The intrinsic carrier density of the oxide semiconductor film is preferably 1 × 10⁻⁶. 5 cm -3 Above and below 1×10 18 cm -3 More preferably 1×10 7 cm -3 Above and 1×10 17 cm -3Hereinafter, 1×10 is further preferred. 9 cm -3 Above and 5×10 16 cm -3 Hereinafter, 1×10 is further preferred. 10 cm -3 Above and 1×10 16 cm -3 Hereinafter, 1×10 is further preferred. 11 cm -3 Above and 1×10 15 cm -3 the following.

[0403] Furthermore, by using substantially intrinsic oxide semiconductor films, the reliability of transistors can sometimes be improved. Here, using... Figure 25 Explain why using oxide semiconductor films in the channel region of transistors improves reliability. Figure 25 This is a diagram illustrating the energy band structure of a transistor using an oxide semiconductor film in the channel region.

[0404] exist Figure 25 In this context, GE represents the gate electrode, GI represents the gate insulating film, OS represents the oxide semiconductor film, and SD represents the source or drain electrode. That is to say, Figure 25 Examples of energy bands for gate electrodes, gate insulating films, oxide semiconductor films, and source or drain electrodes in contact with oxide semiconductor films.

[0405] exist Figure 25 In this study, silicon oxide is used as the gate insulating film, and In-Ga-Zn oxide is used as the oxide semiconductor film. The migration energy level (εf) of defects that may form in the silicon oxide film will form at a position approximately 3.1 eV from the conduction band bottom of the gate insulating film. At a gate voltage (Vg) of 30 V, the Fermi level (Ef) of the silicon oxide film at the interface between the oxide semiconductor film and the silicon oxide film will form at a position approximately 3.6 eV from the conduction band bottom of the gate insulating film. The Fermi level of the silicon oxide film varies depending on the gate voltage. For example, as the gate voltage increases, the Fermi level (Ef) of the silicon oxide film at the interface between the oxide semiconductor film and the silicon oxide film decreases. Figure 25 The white circles in the image represent electrons (charge carriers), and x represents a defect state in the silicon oxide film.

[0406] like Figure 25As shown, when charge carriers are thermally excited under the applied gate voltage, they are captured by defect states (x in the figure), and the charge state of each defect state changes from positive ("+") to neutral ("0"). That is, when the energy of the Fermi level (Ef) of the silicon oxide film is higher than the migration level (εf) of the defect, the charge state of the defect state in the silicon oxide film changes from positive to neutral, and the threshold voltage of the transistor changes in the positive direction.

[0407] When using oxide semiconductor films with different electron affinities, the Fermi level at the interface between the gate insulating film and the oxide semiconductor film may differ. When using an oxide semiconductor film with a higher electron affinity, the conduction band bottom of the gate insulating film is relatively increased at or near the interface between the gate insulating film and the oxide semiconductor film. In this case, defect states may form in the gate insulating film. Figure 25 The energy difference between the Fermi level of the gate insulating film and the Fermi level of the oxide semiconductor film increases. As this energy difference increases, less charge is trapped by the gate insulating film. For example, the change in the charged state of defect states that may form in the silicon oxide film decreases, thus reducing the variation in the transistor's threshold voltage under gate bias temperature (GBT) stress.

[0408] When oxide semiconductor films are used in the channel formation region of transistors, carrier scattering at grain boundaries can be reduced, thus enabling transistors with high field-effect mobility. Furthermore, transistors with high reliability can be achieved.

[0409] Furthermore, the charge trapped by defect states in oxide semiconductor films requires a relatively long time to release, sometimes acting like a fixed charge. Therefore, the electrical characteristics of transistors with channel regions formed in oxide semiconductor films with high defect state density are sometimes unstable.

[0410] Therefore, reducing the impurity concentration in the oxide semiconductor film is effective in stabilizing the electrical characteristics of the transistor. To further reduce the impurity concentration in the oxide semiconductor film, it is preferable to also reduce the impurity concentration in the film adjacent to the oxide semiconductor film. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0411] Here, we will explain the effect of impurities in oxide semiconductor films.

[0412] When an oxide semiconductor film contains silicon or carbon, one of Group 14 elements, defect states are formed. Therefore, the concentrations of silicon or carbon in the oxide semiconductor film, and the concentrations of silicon or carbon near the interface between the oxide semiconductor film and the oxide semiconductor film (measured by secondary ion mass spectrometry (SIMS)) are set to 2 × 10⁻⁶. 18 atoms / cm 3 The following is preferred: 2×10 17 atoms / cm 3 the following.

[0413] Furthermore, when the oxide semiconductor film contains alkali metals or alkaline earth metals, defect states can sometimes form, resulting in charge carriers. Therefore, transistors using oxide semiconductor films containing alkali metals or alkaline earth metals tend to exhibit always-on characteristics. Consequently, it is preferable to reduce the concentration of alkali metals or alkaline earth metals in the oxide semiconductor film. Specifically, the concentration of alkali metals or alkaline earth metals in the oxide semiconductor film, as measured by SIMS, is set to 1 × 10⁻⁶. 18 atoms / cm 3 The following is preferred: 2×10 16 atoms / cm 3 the following.

[0414] Hydrogen contained in an oxide semiconductor film reacts with oxygen bonded to metal atoms to form water, thus sometimes creating oxygen vacancies. When hydrogen enters these oxygen vacancies, electrons are sometimes generated as charge carriers. Additionally, sometimes a portion of the hydrogen bonds with oxygen bonded to metal atoms, generating electrons as charge carriers. Therefore, transistors using oxide semiconductor films containing hydrogen tend to have always-on characteristics. Thus, it is preferable to minimize the amount of hydrogen in the oxide semiconductor film. Specifically, the hydrogen concentration in the oxide semiconductor film, as measured by SIMS, is set to be less than 1 × 10⁻⁶. 20 atoms / cm 3 Preferably less than 1×10 19 atoms / cm 3 More preferably, less than 5×10 18 atoms / cm 3 Further optimization of less than 1×10 18 atoms / cm 3 .

[0415] By using an oxide semiconductor film with sufficiently reduced impurities in the channel formation region of a transistor, the transistor can have stable electrical characteristics.

[0416] The bandgap of the oxide semiconductor film is preferably above 2 eV or above 2.5 eV.

[0417] The thickness of the oxide semiconductor film is 3 nm or more and 200 nm or less, preferably 3 nm or more and 100 nm or less, and more preferably 3 nm or more and 60 nm or less.

[0418] <2-3. Structure of Oxide Semiconductors>

[0419] Next, the structure of oxide semiconductors will be explained.

[0420] Oxide semiconductors are classified into single-crystal oxide semiconductors and non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include CAAC-OS (c-axis-aligned crystalline oxide semiconductor), polycrystalline oxide semiconductors, nc-OS (nanocrystalline oxide semiconductor), a-like OS (amorphous-like oxide semiconductor), and amorphous oxide semiconductors.

[0421] From another perspective, oxide semiconductors are divided into amorphous oxide semiconductors and crystalline oxide semiconductors. Examples of crystalline oxide semiconductors include single-crystal oxide semiconductors, CAAC-OS, polycrystalline oxide semiconductors, and nc-OS.

[0422] Amorphous structures are generally considered to have the following characteristics: they are isotropic but not inhomogeneous; they are in a metastable state and the atomic configuration is not fixed; the bond angles are not fixed; they have short-range order but not long-range order; etc.

[0423] In other words, stable oxide semiconductors cannot be called completely amorphous oxide semiconductors. Furthermore, oxide semiconductors that are not isotropic (e.g., oxide semiconductors with periodic structures in small regions) cannot be called completely amorphous oxide semiconductors. On the other hand, a-like oxide semiconductors, which are not isotropic, have unstable structures including voids. In this respect, a-like oxide semiconductors are physically close to amorphous oxide semiconductors.

[0424] [CAAC-OS]

[0425] First, let's explain CAAC-OS.

[0426] CAAC-OS is one of the oxide semiconductors that contains multiple c-axis oriented crystalline regions (also known as particles).

[0427] CAAC-OS is a highly crystalline oxide semiconductor. The crystallinity of oxide semiconductors can sometimes be reduced due to the incorporation of impurities or the formation of defects, which means that CAAC-OS has fewer impurities and defects (e.g., oxygen vacancies).

[0428] Furthermore, impurities refer to elements other than the main components of an oxide semiconductor, such as hydrogen, carbon, silicon, or transition metals. For example, elements with stronger bonding forces to oxygen than the metals that make up part of the oxide semiconductor (e.g., silicon) can strip oxygen from the oxide semiconductor, disrupting the atomic arrangement and leading to decreased crystallinity. Heavy metals such as iron or nickel, as well as argon, carbon dioxide, and the like, have large atomic radii (or molecular radii) and can also disrupt the atomic arrangement of oxide semiconductors, resulting in decreased crystallinity.

[0429] [nc-OS]

[0430] Next, nc-OS will be explained.

[0431] The analysis of nc-OS using XRD will be explained. When the structure of nc-OS is analyzed using the out-of-plane method, no peaks indicating orientation appear. In other words, the crystals of nc-OS do not exhibit orientation.

[0432] nc-OS is an oxide semiconductor with higher regularity than amorphous oxide semiconductors. Therefore, the defect state density of nc-OS is lower than that of a-like OS and amorphous oxide semiconductors. Note that there is no regularity in crystal orientation among different particles in nc-OS. Therefore, the defect state density of nc-OS is sometimes higher than that of CAAC-OS.

[0433] [a-like OS]

[0434] a-like OS has a structure that is between that of nc-OS and that of amorphous oxide semiconductor.

[0435] a-like OS contains voids or low-density regions. Because a-like OS contains voids, its structure is unstable.

[0436] Because a-like OS contains voids, its density is lower than that of nc-OS and CAAC-OS. Specifically, the density of a-like OS is 78.6% to less than 92.3% of that of single-crystal oxide semiconductors with the same composition. The densities of nc-OS and CAAC-OS are 92.3% to less than 100% of those of single-crystal oxide semiconductors with the same composition. It is very difficult to form oxide semiconductors with densities lower than 78% of the density of single-crystal oxide semiconductors.

[0437] For example, in oxide semiconductors with an In:Ga:Zn atomic ratio of 1:1:1, the density of a single-crystal InGaZnO4 with a rhombohedral crystal structure is 6.357 g / cm³. 3 Therefore, for example, in an oxide semiconductor with an In:Ga:Zn atomic ratio of 1:1:1, the density of a-like OS is 5.0 g / cm³. 3 Above and below 5.9g / cm 3 For example, in oxide semiconductors with an In:Ga:Zn atomic ratio of 1:1:1, the densities of nc-OS and CAAC-OS are 5.9 g / cm³. 3 Above and below 6.3 g / cm 3 .

[0438] When no oxide semiconductors with identical compositions exist in a single crystal state, the density of single-crystal oxide semiconductors with the desired composition can be estimated by combining different single-crystal oxide semiconductors in arbitrary proportions. The density of single-crystal oxide semiconductors with the desired composition can be estimated using a weighted average based on the combination proportions of the different single-crystal oxide semiconductors. Note that it is preferable to estimate the density by minimizing the number of single-crystal oxide semiconductor types combined.

[0439] As described above, oxide semiconductors have various structures and properties. Note that in one embodiment of the oxide semiconductor film of the present invention, two or more of amorphous oxide semiconductors, a-like OS, nc-OS, and CAAC-OS can be mixed together. An example of this is shown below.

[0440] An oxide semiconductor film according to one embodiment of the present invention may include two types of crystalline portions. In other words, the two types of crystalline portions are mixed together in the oxide semiconductor film. One type of crystalline portion (also referred to as the first crystalline portion) has an orientation in the thickness direction (also referred to as the film surface direction or the direction perpendicular to the forming surface or film surface), that is, it has a c-axis orientation. The other type of crystalline portion (also referred to as the second crystalline portion) does not have a c-axis orientation and has a disordered orientation.

[0441] Note that, for simplicity, the crystalline portions are divided into two types: a first crystalline portion having c-axis orientation and a second crystalline portion not having c-axis orientation. Sometimes the crystallinity and crystal size of the first and second crystalline portions are not particularly different and cannot be distinguished. That is, when describing an oxide semiconductor film according to one embodiment of the present invention, the first and second crystalline portions may not be distinguished.

[0442] For example, an oxide semiconductor film according to one embodiment of the present invention includes a plurality of crystalline portions, wherein at least one crystalline portion has a c-axis orientation. Among the crystalline portions present in the film, the proportion of crystalline portions without c-axis orientation may be higher than that of crystalline portions with c-axis orientation. For example, in a transmission electron micrograph of a cross-section in the thickness direction of an oxide semiconductor film according to one embodiment of the present invention, a plurality of crystalline portions are observed, wherein the proportion of second crystalline portions without c-axis orientation is sometimes higher than that of first crystalline portions with c-axis orientation. In other words, in an oxide semiconductor film according to one embodiment of the present invention, the proportion of second crystalline portions without c-axis orientation is higher.

[0443] When the proportion of the second crystalline portion without c-axis orientation in the oxide semiconductor film is high, the following effect can be obtained.

[0444] When a sufficient oxygen supply source is provided near the oxide semiconductor film, the second crystalline portion without c-axis orientation can be used as an oxygen diffusion path. Therefore, when a sufficient oxygen supply source is provided near the oxide semiconductor film, oxygen can be supplied from this source through the second crystalline portion without c-axis orientation to the first crystalline portion with c-axis orientation. This reduces the amount of oxygen vacancies in the oxide semiconductor film. When this oxide semiconductor film is used as the semiconductor film for transistors, high reliability and high field-effect mobility can be obtained.

[0445] In the first crystalline region, specific crystalline planes are oriented in the thickness direction. Therefore, when X-ray diffraction (XRD) measurements are performed in a direction substantially perpendicular to the top surface of the oxide semiconductor film including the first crystalline region, a diffraction peak originating from this first crystalline region is observed at a specified diffraction angle (2θ). However, even if the oxide semiconductor film includes the first crystalline region, a sufficient diffraction peak may not be observed due to X-ray scattering caused by the supporting substrate or background rise. The higher the proportion of the first crystalline region in the oxide semiconductor film, the higher the diffraction peak. Therefore, the height (intensity) of the diffraction peak can be used as an indicator of the crystallinity of the oxide semiconductor film.

[0446] Electron diffraction can be cited as a method for evaluating the crystallinity of oxide semiconductor films. For example, when electron diffraction measurements are performed on a cross-section of an oxide semiconductor film according to an embodiment of the present invention to observe the electron diffraction pattern, a first region with diffraction spots originating from a first crystallization region and a second region with diffraction spots originating from a second crystallization region are observed.

[0447] The first region, with diffraction spots originating from the first crystalline portion, originates from a crystalline portion having a c-axis orientation. The second region, with diffraction spots originating from the second crystalline portion, originates from a crystalline portion that is not oriented or has a disordered orientation. Therefore, sometimes, different patterns are observed depending on the diameter of the electron beam (i.e., the area of ​​the observation region). In this specification, electron diffraction measured using an electron beam with a diameter of 1 nmφ or more and 100 nmφ or less is referred to as nanobeam electron diffraction (NBED).

[0448] Note that the crystallinity of the oxide semiconductor film of one embodiment of the present invention can also be evaluated using methods different from NBED. Examples of methods for evaluating the crystallinity of oxide semiconductor films include electron diffraction, X-ray diffraction, and neutron diffraction. In electron diffraction, in addition to NBED, transmission electron microscopy (TEM), scanning electron microscopy (SEM), converging beam electron diffraction (CBED), selected area electron diffraction (SAED), etc., can be appropriately used.

[0449] In NBED (Nanobe Electron Diffraction), annular patterns are observed in nanobeam electron diffraction patterns obtained using electron beams with relatively large diameters (e.g., 25 nm φ or more and 100 nm φ or 50 nm φ or more and 100 nm φ or less). These annular patterns sometimes exhibit brightness distribution in the radial direction. Conversely, in NBED electron diffraction patterns obtained using electron beams with sufficiently small diameters (e.g., 1 nm φ or more and 10 nm φ or less), multiple spots distributed in the circumferential direction (also called the θ direction) are sometimes observed at the locations of the aforementioned annular patterns. That is, the annular patterns obtained using electron beams with larger diameters are formed by an aggregation of these multiple spots.

[0450] 2-4. Evaluation of the crystallinity of oxide semiconductor films

[0451] Three samples (sample X1 to sample X3), each comprising an oxide semiconductor film, were fabricated, and their crystallinity was evaluated. The three oxide semiconductor films were formed under different conditions. First, the fabrication methods for samples X1 to X3 are described.

[0452] [Sample X1]

[0453] Sample X1 is an oxide semiconductor film with a thickness of approximately 100 nm formed on a glass substrate. This oxide semiconductor film contains indium, gallium, and zinc. The formation conditions for the oxide semiconductor film of Sample X1 are as follows: substrate temperature 170 °C; argon gas at a flow rate of 140 sccm and oxygen gas at a flow rate of 60 sccm are introduced into the processing chamber of the sputtering apparatus; the pressure is set to 0.6 Pa; and an AC power of 2.5 kW is applied to the metal oxide target containing indium, gallium, and zinc (In:Ga:Zn = 4:2:4.1 [atomic ratio]). The oxygen flow rate ratio under the formation conditions of Sample X1 is 30-.

[0454] [Sample X2]

[0455] Sample X2 is a sample with an oxide semiconductor film of approximately 100 nm thickness formed on a glass substrate. The formation conditions for the oxide semiconductor film of Sample X2 are as follows: substrate temperature 130 °C; argon gas at a flow rate of 180 sccm and oxygen gas at a flow rate of 20 sccm are introduced into the processing chamber of the sputtering apparatus. The oxygen flow rate ratio under the formation conditions of Sample X2 is 10-. The conditions other than the substrate temperature and oxygen flow rate ratio are the same as those for Sample X1.

[0456] [Sample X3]

[0457] Sample X3 is a sample with an oxide semiconductor film of approximately 100 nm thickness formed on a glass substrate. The formation conditions of the oxide semiconductor film in Sample X3 are as follows: substrate temperature is room temperature (RT); argon gas at a flow rate of 180 sccm and oxygen gas at a flow rate of 20 sccm are introduced into the processing chamber of the sputtering apparatus. The oxygen flow rate ratio under the formation conditions of Sample X3 is 10-. The conditions other than substrate temperature and oxygen flow rate ratio are the same as those for Sample X1.

[0458] Table 2 shows the formation conditions for samples X1 to X3.

[0459] [Table 2]

[0460] Next, the crystallinity of samples X1 to X3 was evaluated. In this embodiment, crystallinity was evaluated by cross-sectional TEM observation, XRD measurement, and electron diffraction.

[0461] [Cross-section TEM observation]

[0462] Figures 26A to 26C , Figures 27A to 27C as well as Figures 28A to 28C The cross-sectional TEM observations of samples X1 to X3 are shown. Note that... Figure 26A and Figure 26B This is a cross-sectional TEM image of sample X1. Figure 27A and Figure 27B This is a cross-sectional TEM image of sample X2. Figure 28A and Figure 28B This is a cross-sectional TEM image of sample X3.

[0463] Figure 26C , Figure 27C and Figure 28C These are high-resolution transmission electron microscope (HR-TEM) images of cross-sections of samples X1, X2, and X3, respectively. Cross-sectional HR-TEM images can be obtained using the spherical aberration corrector function. Specifically, high-resolution TEM images obtained using the spherical aberration corrector function are referred to as Cs-corrected high-resolution TEM images. For example, Cs-corrected high-resolution TEM images can be observed using an atomic resolution analytical electron microscope such as the JEM-ARM200F manufactured by JEOL Ltd.

[0464] like Figures 26A to 26C and Figures 27A to 27C As shown, in samples X1 and X2, layered crystalline regions with atoms arranged in the thickness direction were observed. In particular, these layered crystalline regions are readily visible in HR-TEM images. Figures 28A to 28C As shown, in sample X3, it is difficult to observe that the atoms are arranged in layers in the thickness direction.

[0465] [XRD Measurement]

[0466] Next, the XRD measurement results of each sample will be explained.

[0467] Figure 29A The XRD measurement results for sample X1 are shown. Figure 30A The XRD measurement results for sample X2 are shown. Figure 31A The XRD measurement results for sample X3 are shown.

[0468] In XRD measurements, the powder method (also known as the θ-2θ method), an out-of-plane method, is used. In the θ-2θ method, the X-ray diffraction intensity is measured by changing the incident angle of the X-rays while simultaneously adjusting the angle of the detector positioned opposite the X-ray source to match the incident angle. Alternatively, grazing-incidence XRD (GIXRD) (also known as the thin-film method or Seemann-Bohlin method) can be used. This GIXRD method is an out-of-plane method where X-rays are incident at an angle of approximately 0.40° from the film surface, and the X-ray diffraction intensity is measured by changing the angle of the detector. Figure 29A , Figure 30A and Figure 31A In the diagram, the vertical axis represents diffraction intensity in arbitrary units, and the horizontal axis represents the angle 2θ.

[0469] like Figure 29A and Figure 30A As shown, peak diffraction intensity was observed near 2θ = 31° in both samples X1 and X2. On the other hand, as... Figure 31A As shown, in sample X3, it is difficult to observe the peak value of diffraction intensity near 2θ = 31°, or the peak value of diffraction intensity near 2θ = 31° is extremely small or non-existent.

[0470] The diffraction angle of the observed peak diffraction intensity (around 2θ = 31°) corresponds to the diffraction angle observed on the (009) plane in the structural model of single-crystal InGaZnO4. Therefore, the aforementioned peak indicates that each of samples X1 and X2 includes a crystalline portion (hereinafter also referred to as a crystalline portion with c-axis orientation or a first crystalline portion) with its c-axis oriented in the thickness direction. Regarding sample X3, it is difficult to determine whether it includes a crystalline portion with c-axis orientation based on XRD measurements.

[0471] Electron Diffraction

[0472] Next, the results of electron diffraction measurements for samples X1 to X3 will be explained. In the electron diffraction measurements, the electron diffraction patterns were obtained when the electron beam was incident perpendicular to the cross-section of each sample. The diameters of the electron beams were set to 1 nmφ and 100 nmφ.

[0473] In electron diffraction, as the diameter of the incident electron beam and the thickness of the sample increase, the electron diffraction pattern tends to show information in the depth direction. Therefore, by reducing not only the diameter of the electron beam but also the thickness of the sample in the depth direction, information about local regions can be obtained. On the other hand, when the thickness of the sample in the depth direction is too small (e.g., less than 5 nm), only information about extremely small regions can be obtained. Therefore, the electron diffraction pattern obtained when crystals exist in extremely small regions is sometimes the same as the electron diffraction pattern of a single crystal. When the analysis of extremely small regions is not the goal, it is preferable to set the thickness of the sample in the depth direction to, for example, 10 nm or more and 100 nm or less, typically 10 nm or more and 50 nm or less.

[0474] Figure 29B and Figure 29C The electron diffraction pattern of sample X1 is shown. Figure 30B and Figure 30C The electron diffraction pattern of sample X2 is shown. Figure 31B and Figure 31C The electron diffraction pattern of sample X3 is shown.

[0475] exist Figure 29B and Figure 29C , Figure 30B and Figure 30C as well as Figure 31B and Figure 31C In the electron diffraction pattern shown, the contrast has been adjusted for clarity. Figure 29B and Figure 29C , Figure 30B and Figure 30C , Figure 31B and Figure 31C In the pattern, the brightest spot in the center is caused by the incident electron beam and is the center of the electron diffraction pattern (also known as the direct spot or transmitted wave).

[0476] In addition, such as Figure 29B As shown, when the diameter of the incident electron beam is set to 1 nmφ, multiple spots distributed in a circular pattern are observed, indicating that the oxide semiconductor film contains multiple extremely small crystalline regions with disordered planar orientation. Figure 29C As shown, when the diameter of the incident electron beam is set to 100 nmφ, multiple diffraction spots from the crystalline region connect, and their brightness is averaged, forming a ring-shaped diffraction pattern. Figure 29C In the study, two ring-shaped diffraction patterns with different radii were observed. These rings are referred to as the first ring and the second ring in order of smaller radius. It can be confirmed that the first ring is brighter than the second ring. Furthermore, two bright spots (also called the first region) were identified at the location overlapping with the first ring.

[0477] The radial distance between the center of the first region and the center of the first ring roughly corresponds to the radial distance between the diffraction spot on the (009) plane and its center in the structural model of single-crystal InGaZnO4. The first region is a diffraction spot caused by c-axis orientation.

[0478] In addition, such as Figure 29C As shown, the observed annular diffraction pattern indicates the presence of crystalline regions with disordered orientation (hereinafter also referred to as crystalline regions without c-axis orientation or second crystalline regions) in the oxide semiconductor film.

[0479] Since the two first regions are arranged symmetrically with respect to the center point of the electron diffraction pattern and their brightness is approximately the same, it can be inferred that the two first regions possess dual symmetry. Furthermore, as mentioned above, the two first regions are diffraction spots arising from c-axis orientation, and the direction of the straight line passing through the two first regions and their center is consistent with the c-axis direction of the crystalline portion. Because... Figure 29C In the figure, the thickness direction is vertical, so it can be known that in the oxide semiconductor film, there exists a crystalline part whose c-axis is oriented in the thickness direction.

[0480] As described above, it can be confirmed that the oxide semiconductor film of sample X1 includes both crystalline portions with c-axis orientation and crystalline portions without c-axis orientation.

[0481] Figure 30B and Figure 30C as well as Figure 31B and Figure 31C The results in the electron diffraction pattern shown are consistent with Figure 29B and Figure 29C The electron diffraction patterns shown are roughly the same. The brightness of the two spots (first region) due to c-axis orientation is brighter in the order of sample X1, sample X2, and sample X3, so it can be seen that the proportion of crystals with c-axis orientation is higher in the above order.

[0482] [Quantitative Methods for the Crystallinity of Oxide Semiconductor Films]

[0483] Next, use Figure 32A and Figure 32B , Figure 33 as well as Figure 34 Examples illustrating quantitative methods for determining the crystallinity of oxide semiconductor films.

[0484] First, prepare the electron diffraction pattern (refer to...). Figure 32A ).

[0485] Figure 32A This is the electron diffraction pattern observed when measuring a 100 nm thick oxide semiconductor film using an electron beam with a diameter of 100 nm φ. Figure 32B Yes Figure 32A The electron diffraction pattern shown is the electron diffraction pattern after comparison and adjustment.

[0486] exist Figure 32B In the study, two distinct spots (first region) were observed above and below the direct spot. These two spots (first region) are diffraction spots corresponding to the (00l) plane in the structural model of InGaZnO4, i.e., originating from the crystalline portion with c-axis orientation. In addition to the first region, a lower brightness annular pattern (second region) was observed on approximately concentric circles within the first region. This annular pattern was obtained by averaging the brightness of the spots originating from the crystalline portion (second crystalline portion) without c-axis orientation using an electron beam with a diameter of 100 nm.

[0487] Here, in the electron diffraction pattern, a first region having diffraction spots arising from crystallization with c-axis orientation and a second region having diffraction spots arising from second crystallization are observed in an overlapping manner. Therefore, by obtaining and comparing the line profiles including the first region and the line profiles including the second region, the crystallinity of the oxide semiconductor film can be quantified.

[0488] First, use Figure 33 The description includes the line outline of the first region and the line outline of the second region.

[0489] Figure 33 A simulated pattern of electron diffraction obtained when an electron beam is irradiated onto the (100) plane of an InGaZnO4 structural model is shown. Auxiliary lines for regions AA', BB', and CC' are attached to the simulated pattern.

[0490] Figure 33 The region AA' shown includes a straight line passing through two diffraction spots and a direct spot originating from the first crystalline part with c-axis orientation. Figure 33 Both regions BB' and CC' shown include a straight line passing through a region where no diffraction spots originating from the first crystal portion with c-axis orientation are observed and a direct spot. The angle between region AA' and region BB' or between region AA' and region CC' is around 34°, specifically, 30° or more and 38° or less, preferably 32° or more and 36° or less, more preferably 33° or more and 35° or less.

[0491] Based on the structure of the oxide semiconductor film, the line outline is presented Figure 34 The trend shown. Figure 34 A conceptual diagram showing the line profiles of each structure, the relative brightness R, and the half-width at half maximum (FWHM) of the spectrum derived from the c-axis orientation obtained from the electron diffraction pattern.

[0492] Figure 34 The relative brightness R shown is the value obtained by dividing the integral intensity of the brightness of region AA' by the integral intensity of the brightness of region BB' or region CC'. The integral intensities of the brightness of regions AA', BB', and CC' are values ​​obtained by removing the brightness of the background caused by the direct spots appearing in the central position.

[0493] The intensity of c-axis orientation can be quantitatively defined by calculating the relative brightness R. For example, as Figure 34As shown, in single-crystal oxide semiconductor films, the peak intensity of the diffraction spots originating from the first crystalline portion with c-axis orientation in region AA' is high, while no diffraction spots originating from the first crystalline portion with c-axis orientation are observed in regions BB' and CC'. Therefore, the relative brightness R is much greater than 1. Furthermore, the relative brightness R decreases in the following order: single crystal, CAAC only (CAAC will be explained in detail later), CAAC + nanocrystal, nanocrystal, and amorphous. In particular, the relative brightness R of nanocrystals and amorphous films without specific orientation is 1.

[0494] As the periodicity of crystallization increases, the spectral intensity of the first crystallite, which exhibits c-axis orientation, increases while the half-width (WHM) of this spectrum decreases. Therefore, the WHM is smallest for single crystals, increasing in the order of CAAC only, CAAC + nanocrystals, and nanocrystals. Amorphous materials have a very large WHM, thus exhibiting a distribution known as a halo.

[0495] [Analysis using line profiles]

[0496] As mentioned above, the intensity ratio between the integral intensity of the brightness of the first region and the integral intensity of the brightness of the second region is important information for inferring the ratio of oriented crystalline parts.

[0497] Therefore, the electron diffraction patterns of samples X1 to X3 were analyzed using line profiles.

[0498] Figure 35A1 and Figure 35A2 The analysis results for sample X1 using line profiles are shown. Figure 35B1 and Figure 35B2 The analysis results for sample X2 using line profiles are shown. Figure 35C1 and Figure 35C2 The analysis results for sample X3 using line profiles are shown.

[0499] Figure 35A1 Yes Figure 29C The electron diffraction pattern shown is supplemented with the electron diffraction patterns of regions AA', BB', and CC'. Figure 35B1 Yes Figure 30C The electron diffraction pattern shown is supplemented with the electron diffraction patterns of regions AA', BB', and CC'. Figure 35C1 Yes Figure 31C The electron diffraction pattern shown is supplemented with the electron diffraction patterns of regions AA', BB', and CC'.

[0500] Regions AA', BB', and CC' can be obtained by normalizing the line profile using the brightness of the direct spot as a reference. This direct spot appears at the center of the electron diffraction pattern. Relative comparisons of samples X1 to X3 can be performed using these regions.

[0501] Furthermore, when calculating the brightness distribution, a more accurate comparison can be made by subtracting the brightness component caused by inelastic scattering from the sample as the background. Here, the brightness component caused by inelastic scattering exhibits an extremely broad distribution in the radial direction, so the brightness of the background can also be approximated by a straight line. For example, by drawing a straight line along the tail of the object's peak value, the region located on the side with lower brightness than that line can be subtracted as the background.

[0502] Here, the integrated intensity of the luminance of regions AA', BB', and CC' is calculated based on the data obtained by subtracting the background using the method described above. Furthermore, the integrated intensity of the luminance of region AA' is divided by the integrated intensity of the luminance of region BB' or the integrated intensity of the luminance of region CC' to obtain the relative luminance R.

[0503] Figure 36 The relative brightness R of samples X1 to X3 is shown. Figure 36 In Figure 35A2 , Figure 35B2 and Figure 35C2 In the brightness distribution shown, the integral intensity of the brightness of region AA' divided by the integral intensity of the brightness of region BB', and the integral intensity of the brightness of region AA' divided by the integral intensity of the brightness of region CC' are calculated in the spectrum to the left and right of the direct spot.

[0504] like Figure 36 As shown, the relative brightness of samples X1 to X3 is as follows: The relative brightness R of sample X1 is 25.00. The relative brightness R of sample X2 is 3.04. The relative brightness R of sample X3 is 1.05. Note that the above relative brightness R is the average of the brightness at four locations. Thus, the relative brightness R is higher in the order of sample X1, sample X2, and sample X3.

[0505] When the oxide semiconductor film of one embodiment of the present invention is used as a channel semiconductor film for forming a transistor, the relative brightness R is preferably greater than 1 and less than 40, more preferably greater than 1 and less than 10, and even more preferably greater than 1 and less than 3. By using this oxide semiconductor film as a semiconductor film, high stability of electrical properties and high field-effect mobility in low gate voltage regions can be achieved simultaneously.

[0506] 2-5. Ratio of crystallized parts

[0507] By analyzing cross-sectional TEM images, the ratio of crystalline regions in oxide semiconductor films can be estimated.

[0508] The image analysis method is explained as follows: First, a two-dimensional Fast Fourier Transform (FFT) is performed on the high-resolution TEM image to obtain an FFT image. The obtained FFT image is then masked to remove regions other than periodic regions. After masking, an Inverse Fast Fourier Transform (IFFT) is performed on the FFT image to obtain a filtered FFT image.

[0509] Thus, a real-space image containing only the crystallized portion can be obtained. Then, the ratio of the crystallized portion can be estimated based on the ratio of the area of ​​the remaining image. Additionally, the ratio of the area outside the crystallized portion can be estimated by subtracting the remaining area from the area used for calculation (also known as the area of ​​the original image).

[0510] Figure 37A1 A cross-sectional TEM image of sample X1 is shown. Figure 37A2 The image shown is the result of analyzing the cross-sectional TEM image of sample X1. Figure 37B1 The TEM image of the cross section of sample X2 is shown. Figure 37B2 The image shown is the result of analyzing the cross-sectional TEM image of sample X2. Figure 37C1 A cross-sectional TEM image of sample X3 is shown. Figure 37C2 The image shown is the result of analyzing the cross-sectional TEM image of sample X3.

[0511] In the images obtained after analysis, the white areas in the oxide semiconductor film correspond to regions including oriented crystalline portions, and the black areas correspond to regions including non-oriented crystalline portions or crystalline portions with disordered orientation.

[0512] according to Figure 37A2 The results show that the area ratio of sample X1 excluding the region containing the oriented crystalline portion is approximately 43.1. According to... Figure 37B2 The results show that the area ratio of sample X2, excluding the region containing the oriented crystalline portion, is approximately 61.7%. According to... Figure 37C2 The results show that the area ratio of sample X3 excluding the region containing the oriented crystalline portion is approximately 89.5%.

[0513] When the ratio of the region other than the oriented crystalline portion in the oxide semiconductor film, as estimated in this way, is 5% or more and less than 40%, the oxide semiconductor film exhibits extremely high crystallinity, extremely high electrical stability, and is not prone to oxygen vacancies, making it preferred. On the other hand, when the ratio of the portion other than the oriented crystalline portion in the oxide semiconductor film is 40% or more and less than 100%, preferably 60% or more and less than 90%, the oxide semiconductor film includes oriented and non-oriented crystalline portions in an appropriate proportion, thus simultaneously achieving high electrical stability and high mobility.

[0514] Here, the region outside the crystallized portion that can be easily identified in the cross-sectional TEM image or based on the analysis of the cross-sectional TEM image can be referred to as the Lateral Growth Buffer Region (LGBR).

[0515] 2-6. Oxygen diffusion into oxide semiconductor films

[0516] The following describes the evaluation results of the ease of oxygen diffusion into the oxide semiconductor film.

[0517] Prepare the following three samples (sample Y1 to sample Y3).

[0518] [Sample Y1]

[0519] First, an oxide semiconductor film with a thickness of approximately 50 nm was formed on a glass substrate using the same method as that used for sample X1 described above. Next, a silicon oxynitride film with a thickness of approximately 30 nm, a silicon oxynitride film with a thickness of approximately 100 nm, and a silicon oxynitride film with a thickness of approximately 20 nm were stacked on the oxide semiconductor film using plasma CVD. Note that in the following description, the oxide semiconductor film and the silicon oxynitride film are sometimes referred to as OS and GI, respectively.

[0520] Next, the mixture was heated at 350°C for 1 hour under a nitrogen atmosphere.

[0521] Next, an In-Sn-Si oxide film with a thickness of 5 nm was formed by sputtering.

[0522] Next, oxygen was added to the silicon oxynitride film. The oxygen addition process was performed using an ashing apparatus under the following conditions: substrate temperature 40°C; oxygen gas at a flow rate of 150 sccm (… 16 O) and oxygen gas with a flow rate of 100 sccm ( 18O) is introduced into the processing chamber; the pressure is 15 Pa; and 4500 W of RF power is supplied for 600 seconds between parallel plate electrodes disposed in the ashing apparatus by applying a bias voltage to one side of the substrate. This is because the silicon oxynitride film contains oxygen at a predominantly component level ( 16 O), so in order to accurately measure the amount of oxygen added due to the oxygen addition treatment, oxygen gas ( 18 O).

[0523] Next, a silicon nitride film with a thickness of about 100 nm was formed using plasma CVD.

[0524] [Sample Y2]

[0525] Sample Y2 is a sample whose oxide semiconductor film formation conditions differ from those of sample Y1. In sample Y2, an oxide semiconductor film with a thickness of approximately 50 nm is formed using the same method as that used in sample X2.

[0526] [Sample Y3]

[0527] Sample Y3 is a sample whose oxide semiconductor film formation conditions differ from those of sample Y1. In sample Y3, an oxide semiconductor film with a thickness of approximately 50 nm was formed using the same method as that used in sample X3.

[0528] Through the above processes, samples Y1 to Y3 are manufactured.

[0529] [SIMS Analysis]

[0530] The secondary ion mass spectrometry (SIMS) method was used to analyze and measure the ions of samples Y1 to Y3. 18 O concentration. In the SIMS analysis, the following three conditions were used: no heating treatment was applied to samples Y1 to Y3; samples Y1 to Y3 were heated at 350°C for 1 hour under a nitrogen atmosphere; and samples Y1 to Y3 were heated at 450°C for 1 hour under a nitrogen atmosphere.

[0531] Figures 38A to 38C The SIMS measurement results are shown. Figure 38A The SIMS measurement results for sample Y1 are shown. Figure 38B The SIMS measurement results for sample Y2 are shown. Figure 38C The SIMS measurement results for sample Y3 are shown.

[0532] Figures 38A to 38C The analysis results are shown for regions including GI and OS. Figures 38A to 38CThe results of SIMS analysis (also known as SSDP (Substrate Side Depth Profile)-SIMS) performed from the substrate side are shown.

[0533] exist Figures 38A to 38C In the diagram, the gray dashed line represents the distribution of samples that were not subjected to heat treatment, the black dashed line represents the distribution of samples subjected to heat treatment at 350℃, and the black solid line represents the distribution of samples subjected to heat treatment at 450℃.

[0534] In each of samples Y1 to Y3, it can be confirmed that 18 O diffuses into GI and also into OS. Additionally, in the order of sample Y1, sample Y2, and sample Y3... 18 O diffuses to deeper locations. Additionally, it can be confirmed that by heating at 350°C or 450°C, 18 O diffuses to deeper locations.

[0535] Based on the above results, it can be confirmed that oxide semiconductor films, which include oriented crystalline regions and non-oriented crystalline regions with a low ratio of oriented crystalline regions, are films that are easily permeable to oxygen; in other words, they are films that easily diffuse with oxygen. Furthermore, by performing heat treatments at 350°C and 450°C, oxygen in the GI film diffuses into the OS.

[0536] The above results indicate that the higher the ratio (density) of oriented crystalline regions, the less easily oxygen diffuses in the thickness direction, and the lower the density, the more easily oxygen diffuses in the thickness direction. The ease of oxygen diffusion in oxide semiconductor films can be examined as follows.

[0537] In oxide semiconductor films that include both oriented crystalline regions and extremely small, non-oriented crystalline regions, the region outside the crystalline regions (LGBR), which can be clearly identified in cross-sectional images, becomes a region where oxygen can easily diffuse, i.e., it becomes an oxygen diffusion path. Therefore, when a sufficient oxygen supply source is provided near the oxide semiconductor film, oxygen can easily diffuse through the LGBR to the oriented crystalline regions, reducing the amount of oxygen vacancies in the film.

[0538] For example, by applying an oxide film that readily releases oxygen in contact with an oxide semiconductor film and then heating it, the oxygen released from the oxide film diffuses through an LGBR (Light Regulator) in the thickness direction into the oxide semiconductor film. Oxygen can also diffuse through the LGBR in the transverse direction into the oriented crystalline regions. Thus, sufficient oxygen diffuses into the oriented crystalline regions and other areas within the oxide semiconductor film, effectively reducing oxygen vacancies in the film.

[0539] For example, in the presence of hydrogen atoms that do not bond with metal atoms in an oxide semiconductor film, oxygen atoms sometimes bond to these hydrogen atoms, forming OH groups and becoming immobilized. Thus, a certain amount (e.g., 1 × 10⁻⁶) is deposited at a low temperature to form this film. 17 cm -3 The hydrogen atoms (approximately 600-600 ohms) are captured by oxygen vacancies (Vo) in the oxide semiconductor film (these hydrogen atoms are also called VoH), thereby suppressing the formation of OH. Furthermore, because VoH generates charge carriers, a certain amount of charge carriers exist in the oxide semiconductor film. Thus, an oxide semiconductor film with increased charge carrier density can be formed. During deposition, oxygen vacancies are also formed simultaneously; however, as mentioned above, introducing oxygen via LGBR can reduce these oxygen vacancies. Using the above method, an oxide semiconductor film with high charge carrier density and sufficiently reduced oxygen vacancies can be formed.

[0540] Furthermore, because extremely small, non-oriented crystallites form in regions other than the oriented crystallites during deposition, distinct grain boundaries are not observed in the oxide semiconductor film. These extremely small crystallites are located between multiple oriented crystallites. These tiny crystallites are formed laterally due to heating during deposition, thereby bonding with adjacent oriented crystallites. These extremely small crystallites also serve as regions for generating charge carriers. When an oxide semiconductor film with this structure is used in a transistor, the field-effect mobility is considered to be significantly improved.

[0541] Furthermore, it is preferable to perform plasma treatment under an oxygen atmosphere after forming an oxide semiconductor film and an oxide insulating film such as a silicon oxide film thereon. This treatment not only supplies oxygen to the film but also reduces the hydrogen concentration. For example, during plasma treatment, fluorine remaining in the treatment chamber may sometimes be doped into the oxide semiconductor film. This fluorine exists as negatively charged fluorine atoms, which bond with positively charged hydrogen atoms due to Coulomb forces to form HF. During this plasma treatment, HF is released to the outside of the oxide semiconductor film, resulting in a reduction of the hydrogen concentration in the oxide semiconductor film. Additionally, during plasma treatment, oxygen atoms and hydrogen atoms may sometimes bond to form H₂O, which is released to the outside of the film.

[0542] Additionally, consider a structure where a silicon oxide film (or silicon oxynitride film) is stacked on an oxide semiconductor film. Fluorine in the silicon oxide film may combine with hydrogen bonds in the film to exist in an electrically neutral HF state, thus not affecting the electrical properties of the oxide semiconductor film. Sometimes Si-F bonds are formed, which are also electrically neutral. HF in the silicon oxide film does not affect oxygen diffusion.

[0543] Due to the aforementioned mechanism, oxygen vacancies in the oxide semiconductor film can be reduced, as can hydrogen atoms that are not bonded to metal atoms, thus improving reliability. Furthermore, when the carrier density of the oxide semiconductor film reaches a certain level, its electrical properties can be considered improved.

[0544] 2-7. Deposition methods of oxide semiconductor films

[0545] Hereinafter, a method for depositing an oxide semiconductor film according to one embodiment of the present invention will be described.

[0546] An oxide semiconductor film according to one embodiment of the present invention can be formed by sputtering in an oxygen-containing atmosphere.

[0547] The substrate temperature during deposition is above room temperature and below 150°C, preferably above 50°C and below 150°C, more preferably above 100°C and below 150°C, and typically 130°C. By setting the substrate temperature within the above range, the ratio of oriented crystalline portions to non-oriented crystalline portions can be controlled.

[0548] The oxygen flow rate ratio (oxygen partial pressure) during deposition is preferably 1 or more and less than 33, more preferably 5 or more and less than 30, even more preferably 5 or more and less than 20, and still more preferably 5 or more and less than 15, typically 10. By reducing the oxygen flow rate, more non-oriented crystalline portions can be included in the film.

[0549] Therefore, by setting the substrate temperature and oxygen flow rate during deposition to the aforementioned ranges, an oxide semiconductor film comprising oriented crystalline portions and non-oriented crystalline portions can be obtained. By setting the substrate temperature and oxygen flow rate to the aforementioned ranges, the ratio of oriented crystalline portions to non-oriented crystalline portions can be controlled.

[0550] The oxide targets that can be used for the formation of oxide semiconductor films are not limited to In-Ga-Zn oxides; for example, In-M-Zn oxides (where M is Al, Ga, Y, or Sn) can be used.

[0551] When using a sputtering target containing a polycrystalline oxide with multiple grains to form an oxide semiconductor film, it is easier to obtain a crystalline oxide semiconductor film compared to using a sputtering target that does not contain a polycrystalline oxide.

[0552] The deposition mechanism of oxide semiconductor films is examined below. When a sputtering target has multiple grains, each with a layered structure, and cleavage easily occurs at the grain interfaces, ions colliding with the sputtering target can cleave the grains to form planar or granular sputtered particles. Since these planar or granular sputtered particles are deposited on the substrate, an oxide semiconductor film with nanocrystals may be formed. Furthermore, it can be considered that by heating the substrate, the nanocrystals bond or rearrange themselves on the substrate surface, thus easily forming an oxide semiconductor film containing oriented crystalline regions.

[0553] Note that the above analysis assumes the use of sputtering. Sputtering is preferred because it allows for easy control of crystallinity. Besides sputtering, other methods include pulsed laser deposition (PLD), plasma-enhanced chemical vapor deposition (PECVD), thermal CVD (Chemical Vapor Deposition), ALD (Atomic Layer Deposition), and vacuum evaporation. As an example of thermal CVD, MOCVD (Metal Organic Chemical Vapor Deposition) can be cited.

[0554] This embodiment can be implemented in appropriate combinations with other embodiments described in this specification.

[0555] (Implementation Method 3)

[0556] In this embodiment, using Figure 39 , Figure 40 , Figure 41 , Figure 42 , Figures 43A to 43D , Figure 44 , Figure 45 as well as Figure 46 The description includes an example of a display device that incorporates a semiconductor device according to one embodiment of the present invention.

[0557] Figure 39 This is a top view showing an example of a display device. Figure 39The display device 700 shown includes: a pixel portion 702 disposed on a first substrate 701; a source driving circuit portion 704 and a gate driving circuit portion 706 disposed on the first substrate 701; a sealant 712 disposed around the pixel portion 702, the source driving circuit portion 704, and the gate driving circuit portion 706; and a second substrate 705 disposed opposite to the first substrate 701. Note that the first substrate 701 and the second substrate 705 are sealed by the sealant 712. That is, the pixel portion 702, the source driving circuit portion 704, and the gate driving circuit portion 706 are sealed by the first substrate 701, the sealant 712, and the second substrate 705. Note that although in Figure 39 Although not shown in the figure, a display element is disposed between the first substrate 701 and the second substrate 705.

[0558] Furthermore, in the display device 700, an FPC (Flexible Printed Circuit) terminal portion 708 is provided in an area on the first substrate 701 not surrounded by the sealant 712, electrically connected to the pixel portion 702, the source drive circuit portion 704, and the gate drive circuit portion 706. The FPC terminal portion 708 is connected to an FPC 716, and various signals are supplied to the pixel portion 702, the source drive circuit portion 704, and the gate drive circuit portion 706 via the FPC 716. The pixel portion 702, the source drive circuit portion 704, the gate drive circuit portion 706, and the FPC terminal portion 708 are each connected to a signal line 710. Various signals supplied by the FPC 716 are supplied to the pixel portion 702, the source drive circuit portion 704, the gate drive circuit portion 706, and the FPC terminal portion 708 via the signal lines 710.

[0559] Alternatively, multiple gate drive circuit sections 706 may be provided in the display device 700. Although an example of a display device 700 in which the source drive circuit section 704 and the gate drive circuit section 706 are formed on a first substrate 701 on which the pixel section 702 is formed is shown, the device is not limited to this structure. For example, only the gate drive circuit section 706 may be formed on the first substrate 701, or only the source drive circuit section 704 may be formed on the first substrate 701. In this case, a structure in which a substrate on which the source drive circuit or gate drive circuit is formed (e.g., a drive circuit substrate formed from a single-crystal semiconductor film or a polycrystalline semiconductor film) may be formed on the first substrate 701 may also be used. Furthermore, there are no particular limitations on the connection method for the separately formed drive circuit substrate, and methods such as COG (Chip On Glass) and wire bonding can be used.

[0560] In addition, the pixel section 702, the source drive circuit section 704, and the gate drive circuit section 706 included in the display device 700 include a plurality of transistors.

[0561] Furthermore, the display device 700 may include various components. Examples of such components include electroluminescent (EL) elements (including organic and inorganic EL elements, organic EL elements, inorganic EL elements, LEDs, etc.), light-emitting transistor elements (transistors that emit light according to current), electron emission elements, liquid crystal elements, electronic ink elements, electrophoretic elements, electrowetting elements, plasma display panels (PDPs), MEMS (microelectromechanical systems) displays (e.g., grating light valves (GLVs), digital micromirror devices (DMDs), digital micro shutter (DMS) elements, interferometric modulation display (IMOD) elements, etc.), piezoelectric ceramic displays, etc.

[0562] In addition, examples of display devices using EL elements include EL displays. Examples of display devices using electron emission elements include field emission displays (FEDs) or surface-conduction electron-emitter displays (SEDs). Examples of display devices using liquid crystal elements include liquid crystal displays (LCDs) (transmissive LCDs, semi-transmissive LCDs, reflective LCDs, intuitive LCDs, projected LCDs). Examples of display devices using electronic ink elements or electrophoretic elements include electronic paper. Note that when implementing a semi-transmissive or reflective liquid crystal display, it is sufficient to make part or all of the pixel electrodes function as reflective electrodes. For example, it is sufficient to make part or all of the pixel electrodes contain aluminum, silver, etc. Furthermore, in this case, storage circuits such as SRAM can also be placed under the reflective electrodes. This can further reduce power consumption.

[0563] The display method of the display device 700 can be progressive scan or interlaced scan. Furthermore, the color elements controlled within pixels during color display are not limited to the three colors RGB (R for red, G for green, and B for blue). For example, it can be composed of four pixels: R, G, B, and W (white). Alternatively, in a PenTile arrangement, a color element can be composed of two colors from RGB. These two colors can vary depending on the color element. Alternatively, one or more colors such as yellow, cyan, and magenta can be added to RGB. Additionally, the display area size of each color element's pixel can be different. However, the disclosed invention is not limited to color display devices but can also be applied to monochrome display devices.

[0564] In addition, to enable full-color display by using white light (W) for backlighting (organic EL elements, inorganic EL elements, LEDs, fluorescent lamps, etc.), a color layer (also called a filter) can be used. As a color layer, red (R), green (G), blue (B), yellow (Y), etc., can be appropriately combined. By using a color layer, color reproduction can be further improved compared to not using a color layer. At this time, it is also possible to directly use white light from the area excluding the color layer for display by setting areas that include the color layer and areas that do not. By partially setting areas excluding the color layer, when displaying bright images, the brightness reduction caused by the color layer can sometimes be reduced, resulting in a power consumption reduction of about 20% to 30%. Note that when using self-emissive elements such as organic or inorganic EL elements for full-color display, R, G, B, Y, and W can also be emitted from elements having each luminous color. By using self-emissive elements, power consumption can sometimes be further reduced compared to using a color layer.

[0565] In addition, as a method of colorization, the above-mentioned method of converting a portion of white light into red, green and blue light through a color filter (color filter method); the method of using red, green and blue light (three-color method); and the method of converting a portion of blue light into red or green light (color conversion method or quantum dot method).

[0566] In this embodiment, using Figure 40 , Figure 41 and Figure 42 Explain the structure of liquid crystal elements and EL elements used as display elements. Figure 40 and Figure 41 Each is along Figure 39 The cross-sectional view shown by the dotted-dash line QR illustrates the structure of a liquid crystal element used as a display element. Additionally, Figure 42It is along Figure 39 The cross-sectional view of the dotted-dash line QR shown illustrates the structure of an EL element used as a display element.

[0567] Below, firstly, it is explained Figure 40 , Figure 41 as well as Figure 42 The common parts are explained, followed by the different parts.

[0568] 3-1. Common parts of display devices

[0569] Figure 40 , Figure 41 as well as Figure 42 The display device 700 shown includes: a lead-in wiring section 711; a pixel section 702; a source drive circuit section 704; and an FPC terminal section 708. The lead-in wiring section 711 includes signal lines 710. The pixel section 702 includes a transistor 750 and a capacitor 790. The source drive circuit section 704 includes a transistor 752.

[0570] Transistors 750 and 752 both have the same structure as transistor 100B described above. Transistors 750 and 752 may also have the structures of other transistors shown in the above embodiments.

[0571] The transistor used in this embodiment comprises a highly purified oxide semiconductor film in which the formation of oxygen vacancies is suppressed. This transistor can reduce off-state current. Therefore, the hold time of electrical signals such as image signals can be extended, and the write interval can also be extended when the power is on. Therefore, the refresh frequency can be reduced, thereby achieving the effect of suppressing power consumption.

[0572] Furthermore, the transistors used in this embodiment exhibit high field-effect mobility, enabling high-speed driving. For example, by using such high-speed driving transistors in a liquid crystal display device, the switching transistors for the pixel section and the driving transistors for the driving circuit section can be formed on the same substrate. In other words, since a separate semiconductor device formed from silicon wafers or the like is not required for the driving circuit, the number of components in the semiconductor device can be reduced. Additionally, high-quality images can be provided in the pixel section by using high-speed driving transistors.

[0573] The capacitor 790 includes: a lower electrode formed by processing a conductive film identical to the conductive film used as the first gate electrode in the transistor 750; and an upper electrode formed by processing a conductive film identical to the conductive film used as the source electrode or drain electrode in the transistor 750. Furthermore, between the lower electrode and the upper electrode, there are: an insulating film formed by forming an insulating film identical to the insulating film used as the first gate insulating film in the transistor 750; and an insulating film formed by forming an insulating film identical to the insulating film used as a protective insulating film in the transistor 750. That is, the capacitor 790 has a laminated structure in which an insulating film serving as a dielectric film is sandwiched between a pair of electrodes.

[0574] In addition, Figure 40 , Figure 41 as well as Figure 42 In this process, a planarization insulating film 770 is provided on transistors 750, 752 and capacitor 790.

[0575] Figure 40 , Figure 41 as well as Figure 42 While both the transistor 750 included in the pixel section 702 and the transistor 752 included in the source drive circuit section 704 have the same structure, they are not limited thereto. For example, the pixel section 702 and the source drive circuit section 704 may use different transistors. Specifically, examples include a structure where the pixel section 702 uses a top-gate transistor and the source drive circuit section 704 uses a bottom-gate transistor, or a structure where the pixel section 702 uses a bottom-gate transistor and the source drive circuit section 704 uses a top-gate transistor. Furthermore, the term "source drive circuit section 704" may be replaced with the term "gate drive circuit section."

[0576] The signal line 710 and the conductive film used as the source and drain electrodes of transistors 750 and 752 are formed in the same process. When the signal line 710 is formed using a material containing copper, the signal delay due to wiring resistance is reduced, thus enabling large-screen displays.

[0577] Additionally, the FPC terminal portion 708 includes a connecting electrode 760, an anisotropic conductive film 780, and an FPC 716. The connecting electrode 760 and the conductive film used as the source and drain electrodes of transistors 750 and 752 are formed in the same process. Furthermore, the connecting electrode 760 and the terminals included in the FPC 716 are electrically connected through the anisotropic conductive film 780.

[0578] Alternatively, glass substrates can be used as the first substrate 701 and the second substrate 705. Flexible substrates can also be used as the first substrate 701 and the second substrate 705. Examples of flexible substrates include plastic substrates.

[0579] Additionally, a structure 778 is provided between the first substrate 701 and the second substrate 705. The structure 778 is a columnar spacer obtained by selectively etching the insulating film, used to control the distance (cell gap) between the first substrate 701 and the second substrate 705. Alternatively, a spherical spacer may also be used as the structure 778.

[0580] Additionally, on one side of the second substrate 705, there is a light-shielding film 738 used as a black matrix, a coloring film 736 used as a color filter, and an insulating film 734 in contact with the light-shielding film 738 and the coloring film 736.

[0581] 3-2. Structural examples of display devices using liquid crystal elements

[0582] Figure 40 The display device 700 shown includes a liquid crystal element 775. The liquid crystal element 775 includes a conductive film 772, a conductive film 774, and a liquid crystal layer 776. The conductive film 774 is disposed on one side of the second substrate 705 and serves as a counter electrode. Figure 40 The display device 700 shown can change the orientation state of the liquid crystal layer 776 by applying a voltage between the conductive film 772 and the conductive film 774, thereby controlling the transmission and non-transmission of light to display images.

[0583] The conductive film 772 is electrically connected to the conductive film of the transistor 750, which serves as the source and drain electrodes. The conductive film 772 is formed on the planarized insulating film 770 and serves as a pixel electrode, i.e., an electrode of the display element.

[0584] As the conductive film 772, a conductive film that is transparent to visible light or a conductive film that is reflective to visible light can be used. For example, a material containing one selected from indium (In), zinc (Zn), and tin (Sn) is preferably used as the conductive film that is transparent to visible light. For example, a material containing aluminum or silver can be used as the conductive film that is reflective to visible light.

[0585] When the conductive film 772 is a conductive film that is reflective to visible light, the display device 700 is a reflective liquid crystal display device. Furthermore, when the conductive film 772 is a conductive film that is transmissive to visible light, the display device 700 is a transmissive liquid crystal display device.

[0586] By changing the structure on the conductive film 772, the driving method of the liquid crystal element can be changed. Figure 41 An example is shown here. Furthermore, Figure 41 The display device 700 shown is an example of using a horizontal electric field mode (e.g., FFS mode) as the driving method for liquid crystal elements. Figure 41 In the structure shown, an insulating film 773 is disposed on the conductive film 772, and a conductive film 774 is disposed on the insulating film 773. At this time, the conductive film 774 functions as a common electrode, and the orientation state of the liquid crystal layer 776 can be controlled by the electric field generated between the conductive film 772 and the conductive film 774 through the insulating film 773.

[0587] Note that, although in Figure 40 and Figure 41 Although not shown in the diagram, an alignment film can also be provided on the side of conductive film 772 and / or conductive film 774 that contacts liquid crystal layer 776. Furthermore, although in Figure 40 and Figure 41 Although not illustrated, optical components (optical substrates) such as polarizing components, phase difference components, and anti-reflection components can be appropriately incorporated. For example, circular polarization utilizing polarizing and phase difference substrates can also be used. Furthermore, backlighting, sidelighting, etc., can also be used as light sources.

[0588] When liquid crystal elements are used as display elements, thermotropic liquid crystals, low-molecular-weight liquid crystals, high-molecular-weight liquid crystals, high-molecular-weight dispersed liquid crystals, ferroelectric liquid crystals, and antiferroelectric liquid crystals can be used. These liquid crystal materials exhibit cholesteric phases, smectic phases, cubic phases, chiral nematic phases, and homogeneous phases, depending on the conditions.

[0589] Furthermore, when using a lateral electric field, liquid crystals exhibiting a blue phase can be used without an alignment film. The blue phase is a type of liquid crystal phase that appears just before the cholesteric liquid crystal transitions to a homogeneous phase when the temperature is raised. Because the blue phase only appears within a narrow temperature range, a liquid crystal composition containing several wt% or more chiral reagents is used in the liquid crystal layer to broaden the temperature range. Since the liquid crystal composition containing the blue phase liquid crystal and the chiral reagent has a fast response speed and is optically isotropic, alignment processing is unnecessary. Additionally, since no alignment film is required, friction processing is eliminated, preventing electrostatic damage caused by friction processing, thereby reducing defects and breakage of the liquid crystal display device during the manufacturing process. Furthermore, the blue phase liquid crystal material exhibits low viewing angle dependence.

[0590] In addition, when liquid crystal elements are used as display elements, the following modes can be used: TN (Twisted Nematic) mode, IPS (In-Plane-Switching) mode, FFS (Fringe Field Switching) mode, ASM (Axially Symmetric aligned Micro-cell) mode, OCB (Optical Compensated Birefringence) mode, FLC (Ferroelectric Liquid Crystal) mode, and AFLC (Anti-Ferroelectric Liquid Crystal) mode.

[0591] Alternatively, a normally black liquid crystal display device can be used, such as a transmissive liquid crystal display device employing vertical alignment (VA) mode. Examples of vertical alignment modes include MVA (Multi-Domain Vertical Alignment), PVA (Patterned Vertical Alignment), and ASV modes.

[0592] 3-3. Display devices using light-emitting elements

[0593] Figure 42 The display device 700 shown includes a light-emitting element 782. The light-emitting element 782 includes a conductive film 772, an EL layer 786, and a conductive film 788. Figure 42 The display device 700 shown can display images by emitting light using the EL layer 786 included in the light-emitting element 782. Furthermore, the EL layer 786 may contain inorganic compounds such as organic compounds or quantum dots.

[0594] Examples of materials that can be used in organic compounds include fluorescent or phosphorescent materials. Furthermore, examples of materials that can be used for quantum dots include colloidal quantum dots, alloy quantum dots, core-shell quantum dots, and nucleated quantum dots. Additionally, quantum dots containing elements belonging to Groups 12 and 16, Groups 13 and 15, or Groups 14 and 16 can also be used. Alternatively, quantum dot materials containing elements such as cadmium (Cd), selenium (Se), zinc (Zn), sulfur (S), phosphorus (P), indium (In), tellurium (Te), lead (Pb), gallium (Ga), arsenic (As), and aluminum (Al) can be used.

[0595] The aforementioned organic and inorganic compounds can be deposited using methods such as vapor deposition (including vacuum vapor deposition), droplet jetting (also known as inkjet printing), coating, and gravure printing. Furthermore, the EL layer 786 can also contain low-molecular-weight materials, medium-molecular-weight materials (including oligomers and dendritic polymers), or high-molecular-weight materials.

[0596] Here, refer to Figures 43A to 43D This describes the method for forming the EL layer 786 using droplet jetting. Figures 43A to 43D This is a cross-sectional view illustrating the formation method of the EL layer 786.

[0597] First, a conductive film 772 is formed on the planarized insulating film 770, and an insulating film 730 is formed in such a way that it covers a portion of the conductive film 772 (see reference). Figure 43A ).

[0598] Next, droplets 784 are ejected from the droplet ejection device 783 onto the exposed portion of the conductive film 772, which serves as an opening in the insulating film 730, to form a layer 785 containing a composition. The droplets 784 are a composition containing a solvent, which adheres to the conductive film 772 (see reference). Figure 43B ).

[0599] In addition, the process of spraying droplets 784 can also be carried out under reduced pressure.

[0600] Next, the solvent in layer 785 containing the components is removed and the layer is cured to form EL layer 786 (see reference). Figure 43C ).

[0601] As a method for removing solvent, a drying process or a heating process can be performed.

[0602] Next, a conductive film 788 is formed on the EL layer 786, thereby forming a light-emitting element 782 (see reference). Figure 43D ).

[0603] As described above, by using the droplet jetting method to form the EL layer 786, the components can be selectively jetted, thus reducing material loss. Furthermore, since it eliminates the need for processes such as photolithography for shape processing, the process can be simplified, thereby achieving cost reduction.

[0604] In addition, the above-mentioned droplet jetting method is a general term for droplet jetting units, including units with nozzles having component jetting orifices or heads having one or more nozzles.

[0605] Next, refer to Figure 44 Explain the droplet ejection device used in the droplet ejection method. Figure 44 This is a schematic diagram illustrating the droplet ejection device 1400.

[0606] The droplet ejection device 1400 includes a droplet ejection unit 1403. The droplet ejection unit 1403 includes a head 1405 and a head 1412.

[0607] By controlling the control unit 1407, which is connected to the head 1405 and head 1412, via the computer 1410, pre-programmed patterns can be drawn.

[0608] Alternatively, the marking can be performed using a mark 1411 formed on the substrate 1402 as a reference, for example. Or, a reference point can be determined using the edge of the substrate 1402 as a reference. Here, the mark 1411 is detected by the imaging unit 1404 and converted into a digital signal by the image processing unit 1409. Then, the digital signal is recognized by the computer 1410, a control signal is generated, and the control signal is transmitted to the control unit 1407.

[0609] As the imaging unit 1404, an image sensor using a charge-coupled device (CCD) or complementary metal-oxide-semiconductor (CMOS) can be utilized. Furthermore, data of the pattern to be formed on the substrate 1402 is stored in the storage medium 1408, and control signals can be transmitted to the control unit 1407 based on this data to control each head of the droplet ejection unit 1403, including the head 1405 and head 1412. The ejected material is supplied to the heads 1405 and 1412 from the material supply sources 1413 and 1414 respectively via pipes.

[0610] The interior of head 1405 includes a space filled with liquid material, shown by dashed line 1406, and a nozzle serving as an injection port. Not shown here, head 1412 has the same internal structure as head 1405. When the size of the nozzle of head 1405 differs from that of the nozzle of head 1412, different materials with different widths can be sprayed simultaneously. Each head can spray and depict multiple luminescent materials. In the case of depicting a wide area, to increase throughput, the same material can also be sprayed simultaneously from multiple nozzles for depicting. When using a large substrate, heads 1405 and 1412 can... Figure 44 The substrate can be scanned freely in the X, Y, and Z directions indicated by the arrows, and the area for drawing the pattern can be freely set, thus allowing multiple identical patterns to be drawn on a single substrate.

[0611] Alternatively, the composition can be sprayed under reduced pressure. The composition can be sprayed while the substrate is heated. After spraying, one or both drying and firing are performed. Both drying and firing are heat treatments, but their purpose, temperature, and time differ. Drying and firing processes are performed under normal or reduced pressure using laser irradiation, rapid thermal annealing, or heating in a furnace. Note that there are no particular restrictions on the timing or number of heat treatments. The temperature required for successful drying and firing depends on the substrate material and the properties of the composition.

[0612] Through the above steps, the EL layer 786 can be formed using a droplet jetting device.

[0613] To reiterate Figure 42 The display device 700 shown is shown.

[0614] exist Figure 42 In the display device 700 shown, an insulating film 730 is provided on the planarized insulating film 770 and the conductive film 772. The insulating film 730 covers a portion of the conductive film 772. The light-emitting element 782 adopts a top-emitting structure. Therefore, the conductive film 788 is transparent and allows light emitted by the EL layer 786 to pass through. Note that although a top-emitting structure is illustrated in this embodiment, it is not limited to this. For example, a bottom-emitting structure that emits light to one side of the conductive film 772 or a double-sided emitting structure that emits light to both one side of the conductive film 772 and one side of the conductive film 788 can also be applied.

[0615] Additionally, a coloring film 736 is provided at the position overlapping with the light-emitting element 782, and a light-shielding film 738 is provided at the position overlapping with the insulating film 730, in the winding wiring portion 711, and in the source drive circuit portion 704. The coloring film 736 and the light-shielding film 738 are covered by the insulating film 734. A sealing film 732 fills the space between the light-emitting element 782 and the insulating film 734. Note that although an example is shown in... Figure 42 The display device 700 shown has a structure in which a color film 736 is provided, but it is not limited to this. For example, when the EL layer 786 is formed by separate coating, a structure in which the color film 736 is not provided may also be used.

[0616] 3-4. Examples of structures for setting up input / output devices in display devices

[0617] exist Figure 41 and Figure 42 The display device 700 shown may also include an input / output device. Examples of such an input / output device include a touchscreen.

[0618] Figure 45 Shown in Figure 41The display device 700 shown has a structure in which a touch screen 791 is provided. Figure 46 Shown in Figure 42 The display device 700 shown has a structure in which a touch screen 791 is provided.

[0619] Figure 45 Is Figure 41 The diagram shows a cross-sectional view of the structure in which a touch screen 791 is provided in the display device 700. Figure 46 Is Figure 42 The diagram shows a cross-sectional view of the structure in which a touch screen 791 is provided in the display device 700.

[0620] First, the following explanation Figure 45 and Figure 46 The touchscreen 791 shown.

[0621] Figure 45 and Figure 46 The touchscreen 791 shown is an In-Cell type touchscreen disposed between the substrate 705 and the color film 736. The touchscreen 791 can be formed on one side of the substrate 705 before the light-shielding film 738 and the color film 736 are formed.

[0622] The touchscreen 791 includes a light-shielding film 738, an insulating film 792, electrodes 793, 794, an insulating film 795, electrodes 796, and an insulating film 797. For example, by bringing a detection object such as a finger or stylus close, the change in mutual capacitance between electrodes 793 and 794 can be detected.

[0623] In addition, Figure 45 and Figure 46 The upper part of the transistor 750 shown illustrates the intersection of electrodes 793 and 794. Electrode 796 is electrically connected to the two electrodes 793 that clamp electrode 794 through an opening provided in the insulating film 795. Furthermore, in Figure 45 and Figure 46 The diagram shows a structure in which the area where the electrode 796 is provided is located in the pixel section 702, but it is not limited to this. For example, it may also be formed in the source drive circuit section 704.

[0624] Electrodes 793 and 794 are disposed in the area overlapping with the light-shielding film 738. Furthermore, as... Figure 45 As shown, electrode 793 is preferably arranged in a manner that does not overlap with light-emitting element 782. Furthermore, as... Figure 46As shown, electrode 793 is preferably arranged in a manner that does not overlap with liquid crystal element 775. In other words, electrode 793 has an opening in the area where it overlaps with light-emitting element 782 and liquid crystal element 775. That is, electrode 793 has a grid shape. By adopting this structure, electrode 793 can have a structure that does not block the light emitted by light-emitting element 782. Alternatively, electrode 793 can also have a structure that does not block the light transmitted through liquid crystal element 775. Therefore, since the brightness reduction caused by the arrangement of touch screen 791 is minimal, a display device with high visibility and reduced power consumption can be realized. Furthermore, electrode 794 can also have the same structure.

[0625] Since electrodes 793 and 794 do not overlap with the light-emitting element 782, they can be made of metal materials with low visible light transmittance. When electrodes 793 and 794 do not overlap with the liquid crystal element 775, they can also be made of metal materials with low visible light transmittance.

[0626] Therefore, compared with electrodes using oxide materials with high visible light transmittance, the resistance of electrodes 793 and 794 can be reduced, thereby improving the sensor sensitivity of the touch screen.

[0627] For example, conductive nanowires can also be used for electrodes 793, 794, and 796. The average diameter of these nanowires can be 1 nm or more and 100 nm or less, preferably 5 nm or more and 50 nm or less, and more preferably 5 nm or more and 25 nm or less. Furthermore, metal nanowires such as Ag nanowires, Cu nanowires, and Al nanowires, or carbon nanotubes, can be used as the aforementioned nanowires. For example, when Ag nanowires are used as any one or all of electrodes 664, 665, and 667, a visible light transmittance of 89% or more and a sheet resistance of 40 Ω² or more and 100 Ω² or less can be achieved.

[0628] Although Figure 45 and Figure 46 The diagram shows the structure of an In-Cell type touchscreen, but it is not limited to this. For example, an On-Cell type touchscreen formed on the display device 700 or an Out-Cell type touchscreen attached to the display device 700 may also be used.

[0629] Thus, the display device of one embodiment of the present invention can be used in combination with touch screens of various types.

[0630] At least a portion of this embodiment can be implemented in combination with other embodiments described in this specification.

[0631] (Implementation Method 4)

[0632] In this embodiment, an example of a semiconductor device according to one embodiment of the present invention is described. The transistor shown in this embodiment is suitable for miniaturization.

[0633] 4-1. Examples of transistor structures suitable for miniaturization

[0634] Figures 47A to 47C A top view of transistor 200 is shown. Figure 47A This is a top view of transistor 200. Note that, for clarity, in... Figure 47A Part of the membrane is omitted. Figure 47B It is along Figure 47A The cross-sectional view shown is the dotted-dash line X1-X2. Figure 47C It is a cross-sectional view along Y1-Y2.

[0635] Transistor 200 includes: conductors 205 (conductors 205a and 205b) and 260 (conductors 260a and 260b) used as gate electrodes; insulators 220, 222, 224 and 250 used as gate insulating layers; oxide semiconductors 230 (oxide semiconductors 230a, 230b and 230c) having regions in which channels are formed; conductor 240a used as one of the source and drain electrodes; conductor 240b used as the other of the source and drain electrodes; and insulator 280 containing excess oxygen.

[0636] The oxide semiconductor 230 includes oxide semiconductor 230a, oxide semiconductor 230b on oxide semiconductor 230a, and oxide semiconductor 230c on oxide semiconductor 230b. When transistor 200 is turned on, current mainly flows through oxide semiconductor 230b (forming a channel). On the other hand, sometimes current flows through the vicinity of the interface between oxide semiconductor 230a and oxide semiconductor 230c and oxide semiconductor 230b (sometimes forming a mixed region), while other regions of oxide semiconductor 230a and oxide semiconductor 230c are used as insulators.

[0637] exist Figures 47A to 47C In the structure, the conductor 260 used as the gate electrode has a stacked structure including conductor 260a and conductor 260b. Additionally, an insulator 270 is included on the conductor 260 used as the gate electrode.

[0638] The conductor 205 uses a metal film containing elements selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium, or a metal nitride film (titanium nitride film, molybdenum nitride film, tungsten nitride film) containing the above elements. Alternatively, conductive materials such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide with added silicon oxide may also be used.

[0639] For example, tantalum nitride, a conductor with hydrogen-blocking properties, can be used as conductor 205a, and highly conductive tungsten can be stacked on top of it as conductor 205b. By using this combination, hydrogen diffusion into the oxide semiconductor 230 can be suppressed while maintaining the conductivity of the wiring. Figures 47A to 47C The diagram shows a two-layer structure of conductor 205a and conductor 205b, but it is not limited to this and can be a single layer or a stacked structure of three or more layers.

[0640] Each of insulators 220 and 224 is preferably an oxygen-containing insulator, such as a silicon oxide film or a silicon oxynitride film. In particular, an insulator containing excess oxygen (containing oxygen in excess of its stoichiometric composition) is preferably used as insulator 224. By providing the aforementioned insulator containing excess oxygen in contact with the oxide constituting transistor 200, oxygen vacancies in the oxide can be filled. Note that insulators 220 and 224 do not necessarily have to be formed from the same material.

[0641] As the insulator 222, one or more of the following insulators, either single-layer or multilayer, are preferably used: silicon oxide, silicon oxynitride, silicon oxynitride, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST). Alternatively, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators. Furthermore, these insulators may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may also be laminated onto the aforementioned insulators.

[0642] The insulator 222 may also have a multilayer structure with two or more layers. In this case, it is not limited to a multilayer structure made of the same material, but may also be a multilayer structure made of different materials.

[0643] When an insulator 222 containing a high-k material is included between insulators 220 and 224, under certain conditions, insulator 222 can trap electrons, increasing the threshold voltage. That is, insulator 222 may sometimes be negatively charged.

[0644] For example, when silicon oxide is used for insulators 220 and 224, and materials with many electron-trapping states, such as hafnium oxide, aluminum oxide, and tantalum oxide, are used for insulator 222, the potential of conductor 205 is maintained above the potentials of the source and drain electrodes for more than 10 milliseconds, typically more than 1 minute, at a temperature higher than the operating or storage temperature of the semiconductor device (e.g., 125°C or higher and 450°C or lower, typically 150°C or higher and 300°C or lower). As a result, electrons move from the oxide constituting transistor 200 to conductor 205. At this time, a portion of the moving electrons are trapped by the electron-trapping states of insulator 222.

[0645] In a transistor where the required number of electrons are captured in the electron-trapping state of insulator 222, the threshold voltage shifts to the positive side. The amount of electrons captured can be controlled by controlling the voltage of conductor 205, thereby controlling the threshold voltage. By employing this structure, transistor 200 becomes a normally-off transistor that is in a non-conducting state (also known as a closed state) even when the gate voltage is 0V.

[0646] Furthermore, the electron trapping process can be performed during the transistor manufacturing process. For example, it can be performed at any stage before shipping, such as after the formation of the conductors connected to the source or drain conductors of the transistor, after the completion of the preceding process (wafer processing), after the wafer dicing process, or after packaging.

[0647] The threshold voltage can be controlled by appropriately adjusting the thicknesses of insulators 220, 222, and 224. Furthermore, a transistor with low leakage current in the off-state can be provided. Additionally, a transistor with stable electrical characteristics can be provided. Furthermore, a transistor with high on-state current can be provided. Furthermore, a transistor with small subthreshold swing can be provided. Furthermore, a transistor with high reliability can be provided.

[0648] Oxide semiconductors 230a, 230b, and 230c are formed using metal oxides such as In-M-Zn oxide (where M is Al, Ga, Y, or Sn). In-Ga oxide or In-Zn oxide can also be used as oxide semiconductor 230.

[0649] As the insulator 250, one or more single layers or stacks of insulators selected from silicon oxide, silicon oxynitride, silicon oxynitride, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST) can be used. Alternatively, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide can be added to these insulators. Furthermore, these insulators can be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride can also be stacked on the aforementioned insulators.

[0650] Furthermore, similar to insulator 224, insulator 250 preferably uses an oxide insulator whose oxygen content exceeds the stoichiometric composition. By providing the aforementioned insulator containing excess oxygen in a manner that contacts the oxide semiconductor 230, oxygen vacancies in the oxide semiconductor 230 can be reduced.

[0651] The insulator 250 can be an insulating film that blocks oxygen or hydrogen, such as aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, or silicon nitride. When such a material is used to form the insulator, the insulator serves as a layer to prevent the release of oxygen from the oxide semiconductor 230 or the introduction of impurities such as hydrogen from the outside.

[0652] Insulator 250 may also have the same stacked structure as insulators 220, 222, and 224. When insulator 250 has an insulator that traps electrons required for the electron-trapping state, the threshold voltage of transistor 200 can drift to the positive side. By adopting this structure, transistor 200 becomes a normally-off transistor that is in a non-conducting state (also known as a closed state) even when the gate voltage is 0V.

[0653] In addition, Figures 47A to 47C In the semiconductor device shown, a barrier film, in addition to the insulator 250, can be provided between the oxide semiconductor 230 and the conductor 260. The oxide semiconductor 230c can have barrier properties.

[0654] For example, by providing an insulating film containing excess oxygen in contact with the oxide semiconductor 230, and surrounding the insulating film with a barrier film, the oxide can be made to be in a state that is approximately consistent with the stoichiometric composition or in a state of oxygen supersaturation exceeding the stoichiometric composition. Furthermore, impurities such as hydrogen can be prevented from entering the oxide semiconductor 230.

[0655] One of conductors 240a and 240b is used as the source electrode, and the other is used as the drain electrode.

[0656] Conductors 240a and 240b can be made of metals such as aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, or tungsten, or alloys with these elements as the main components. The accompanying drawings show a single-layer structure, but a multi-layered structure with two or more layers can also be used.

[0657] For example, titanium films and aluminum films can be laminated. Alternatively, a two-layer structure can be used, consisting of an aluminum film laminated on a tungsten film, a copper film laminated on a copper-magnesium-aluminum alloy film, a copper film laminated on a titanium film, or a copper film laminated on a tungsten film.

[0658] Alternatively, a three-layer structure can be used, in which an aluminum or copper film is laminated on a titanium or titanium nitride film and a titanium or titanium nitride film is formed thereon; or a three-layer structure can be used, in which an aluminum or copper film is laminated on a molybdenum or molybdenum nitride film and a molybdenum or molybdenum nitride film is formed thereon. Additionally, transparent conductive materials containing indium oxide, tin oxide, or zinc oxide can be used.

[0659] The conductor 260 used as the gate electrode can be formed, for example, by using metals selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, and tungsten, alloys composed of the above metals, or alloys combining the above metals. Alternatively, one or more metals selected from manganese and zirconium can be used. Furthermore, semiconductors such as polycrystalline silicon doped with impurity elements such as phosphorus, and silicides such as nickel silicides can also be used.

[0660] For example, a two-layer structure of titanium film stacked on aluminum film. Alternatively, a two-layer structure of titanium film stacked on titanium nitride film, a two-layer structure of tungsten film stacked on titanium nitride film, or a two-layer structure of tantalum nitride film or tungsten nitride film stacked on tungsten film can also be used.

[0661] There are also three-layer structures, such as stacking an aluminum film on a titanium film and then stacking a titanium film on top of that. In addition, alloy films or nitride films composed of aluminum and one or more elements selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium can also be used.

[0662] As the conductor 260, transparent conductive materials such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide with added silicon oxide can also be used. Alternatively, a multilayer structure of the aforementioned transparent conductive materials and the aforementioned metals can be employed.

[0663] The conductor 260a is formed using thermal CVD, MOCVD, and ALD methods. In particular, atomic layer deposition (ALD) is preferred for forming the conductor 260a. Using ALD and similar methods reduces plasma damage to the insulator 250. Furthermore, ALD improves coverage, making it a preferred method. Therefore, a highly reliable transistor 200 can be provided.

[0664] In addition, the conductor 260b is formed using highly conductive materials such as tantalum, tungsten, copper, and aluminum.

[0665] An insulator 270 is formed by covering the conductor 260. When an oxide material that has deoxygenated is used for the insulator 280, a substance that blocks oxygen is used as the insulator 270 to prevent the conductor 260 from oxidizing due to deoxygenated oxygen.

[0666] For example, a metal oxide such as aluminum oxide can be used as the insulator 270. The insulator 270 can be formed to a thickness that prevents oxidation of the conductor 260. For example, the insulator 270 is formed to a thickness of 1 nm or more and 10 nm or less, preferably 3 nm or more and 7 nm or less.

[0667] Therefore, oxidation of the conductor 260 can be suppressed, and desorbed oxygen can be effectively supplied from the insulator 280 to the oxide semiconductor 230.

[0668] An insulator 280 is provided on the transistor 200. The insulator 280 preferably comprises an oxide whose oxygen content exceeds its stoichiometric composition. That is, a region with more oxygen than the stoichiometric composition is preferably formed in the insulator 280 (hereinafter also referred to as an excess oxygen region). In particular, when an oxide semiconductor is used in the transistor 200, forming an insulator with an excess oxygen region as an interlayer film or the like near the transistor 200 reduces oxygen vacancies in the transistor 200, thereby improving reliability.

[0669] As an insulator with an excess oxygen region, it is preferable to use an oxide material in which some oxygen is removed due to heating.

[0670] For example, materials containing silicon oxide or silicon oxynitride are preferred as such materials. Alternatively, metal oxides may also be used. Note that in this specification, "silicon oxynitride" refers to a material with an oxygen content greater than a nitrogen content, and "silicon oxynitride" refers to a material with a nitrogen content greater than an oxygen content.

[0671] The insulator 280 covering the transistor 200 can also be used as a planarization film covering the uneven shape underneath.

[0672] 4-2. Application Examples of Transistors Suitable for Miniaturization

[0673] The following are examples illustrating cases where transistors with different compositions are stacked.

[0674] Figure 48 The semiconductor device shown includes transistor 400, transistor 200, and capacitor 410.

[0675] Transistor 200 is a transistor whose channel is formed in a semiconductor layer containing oxide semiconductor. Because transistor 200 has a small off-state current, by using this transistor in a semiconductor device (memory device), stored data can be retained for a long time. In other words, because a semiconductor device (memory device) that does not require refresh operation or has an extremely low refresh frequency can be formed, power consumption can be significantly reduced.

[0676] like Figure 48 As shown, the semiconductor device includes transistor 400, transistor 200, and capacitor 410. Transistor 200 is disposed on transistor 400, and capacitor 410 is disposed on both transistor 400 and transistor 200.

[0677] The transistor 400 is disposed on the substrate 401 and includes a conductor 406, an insulator 404, a semiconductor region 402 which is part of the substrate 401, and low-resistance regions 408a and 408b which are used as source and drain regions, respectively.

[0678] Transistor 400 can be a p-channel transistor or an n-channel transistor.

[0679] The region forming the channel or its vicinity in semiconductor region 402, as well as low-resistance regions 408a and 408b used as source and drain regions, preferably contain semiconductors such as silicon-based semiconductors, and more preferably contain single-crystal silicon. Additionally, materials containing Ge (germanium), SiGe (silicon-germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), etc., may be used. Furthermore, silicon, by applying stress to the crystal lattice and changing the interplanar spacing to control the effective quality, may also be used. Furthermore, transistor 400 may also be a HEMT (High Electron Mobility Transistor) using GaAs and GaAlAs, etc.

[0680] In the low resistance regions 408a and 408b, in addition to the semiconductor material suitable for the semiconductor region 402, elements such as arsenic and phosphorus that impart n-type conductivity or elements such as boron that impart p-type conductivity are also included.

[0681] The conductor 406 used as the gate electrode can be a conductive material such as silicon, a semiconductor material, a metal material, an alloy material, or a metal oxide material, which contains elements that impart n-type conductivity, such as arsenic and phosphorus, or elements that impart p-type conductivity, such as boron.

[0682] The threshold voltage can be adjusted by utilizing the material of the conductor to determine the work function. Specifically, titanium nitride or tantalum nitride are preferred as conductors. To ensure the conductivity and embeddability of the conductor, a stack of metal materials such as tungsten or aluminum is preferred as the conductor, especially tungsten in terms of heat resistance.

[0683] Figure 48 The transistor 400 shown is just an example and is not limited to this structure. Appropriate transistors can be used depending on the circuit structure or driving method.

[0684] Insulators 420, 422, 424 and 426 are stacked sequentially in a manner that covers transistor 400.

[0685] Insulators 420, 422, 424 and 426 may be made of materials such as silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum oxynitride, and aluminum nitride.

[0686] Insulator 422 is used as a planarization film to flatten the steps caused by transistors 400 and the like disposed beneath it. To improve flatness, the top surface of insulator 422 can also be planarized by a planarization process such as chemical mechanical polishing (CMP).

[0687] As an insulator 424, a barrier film is preferably used to prevent hydrogen or impurities from diffusing from the substrate 401 or transistor 400 to the area where transistor 200 is disposed.

[0688] For example, silicon nitride formed by CVD can be used as an example of a film that blocks hydrogen diffusion. However, when hydrogen diffuses into a semiconductor element having an oxide semiconductor, such as transistor 200, the characteristics of that semiconductor element sometimes degrade. Therefore, it is preferable to provide a film that suppresses hydrogen diffusion between transistor 200 and transistor 400. Specifically, the film that suppresses hydrogen diffusion is one with a low amount of hydrogen detachment.

[0689] The dielectric constant of insulator 426 is preferably lower than that of insulator 424. For example, the relative dielectric constant of insulator 426 is preferably less than 4, more preferably less than 3. Furthermore, for example, the relative dielectric constant of insulator 424 is preferably less than 0.7 times that of insulator 426, more preferably less than 0.6 times. By using a material with a low dielectric constant for the interlayer film, the parasitic capacitance generated between the wirings can be reduced.

[0690] Conductors 428 and 430, which are electrically connected to capacitor 410 or transistor 200, are embedded in insulators 420, 422, 424, and 426. Conductors 428 and 430 are used as plugs or wiring. Note that, as explained later, the same reference numerals are sometimes used to denote multiple conductors used as plugs or wiring. Furthermore, in this specification, wiring and plugs electrically connected to the wiring can also be a single component. That is, sometimes a portion of the conductor is used as an electrode, or sometimes a portion of the conductor is used as a plug.

[0691] The materials used for the plugs and wiring (conductors 428 and 430, etc.) can be single layers or stacks of conductive materials such as metals, alloys, metal nitrides, or metal oxides. High-melting-point materials such as tungsten or molybdenum, which combine heat resistance and conductivity, are preferred, with tungsten being particularly preferred. Alternatively, low-resistance conductive materials such as aluminum or copper are preferred. Using low-resistance conductive materials reduces wiring resistance.

[0692] Conductors 428 and 430 preferably include conductors that block hydrogen. In particular, it is preferable to form a conductor that blocks hydrogen in the opening of the insulator 424. Due to this structure, transistors 400 and 200 can be separated by the barrier layer, and hydrogen diffusion from transistor 400 to transistor 200 can be suppressed.

[0693] As a conductor that blocks hydrogen, tantalum nitride, for example, can be used. By layering tantalum nitride and highly conductive tungsten, hydrogen diffusion from transistor 400 can be suppressed while maintaining the conductivity of the wiring. In this case, it is preferable that the tantalum nitride layer that blocks hydrogen is in contact with the insulator 424 that blocks hydrogen.

[0694] Wiring layers can also be provided on insulator 426 and conductor 430. For example, in Figure 48 Insulators 450, 452, and 454 are stacked sequentially. A conductor 456 is formed within insulators 450, 452, and 454. The conductor 456 is used as a plug or wiring. The conductor 456 can be formed using the same material as conductors 428 and 430.

[0695] Conductor 456 is preferably formed using a low-resistance conductive material such as aluminum or copper. By using a low-resistance conductive material, the wiring resistance can be reduced. When copper is used as conductor 456, it is preferable to layer a conductor used to suppress copper diffusion. As a conductor to suppress copper diffusion, for example, tantalum, tantalum nitride or other tantalum-containing alloys, ruthenium and ruthenium-containing alloys can be used.

[0696] For example, an insulator 450 is preferably made of a material that inhibits copper diffusion or has the ability to block oxygen and hydrogen. For example, silicon nitride can be used as an example of a film that inhibits copper diffusion. Therefore, the same material as insulator 424 can be used for insulator 450.

[0697] In particular, it is preferable that the conductor for suppressing copper diffusion is disposed in such a way that it contacts the opening of the insulator 450 for suppressing copper diffusion, and that copper is stacked on the conductor for suppressing copper diffusion. Due to this structure, copper diffusion to the area surrounding the wiring can be suppressed.

[0698] Insulator 458, insulator 210, insulator 212 and insulator 214 are sequentially stacked on insulator 454. Any or all of insulator 458, insulator 210, insulator 212 and insulator 214 are preferably formed using a material that inhibits copper diffusion or has the ability to block oxygen or hydrogen.

[0699] Insulators 458 and 212 are preferably formed, for example, a film that inhibits the diffusion of copper or a barrier film that prevents hydrogen or impurities from diffusing from the region where the substrate 401 or transistor 400 is formed to the region where the transistor 200 is formed. Therefore, insulators 458 and 212 can be made of the same material as insulator 424.

[0700] Insulator 210 can be made of the same material as insulator 420. For example, silicon oxide film or silicon oxynitride film can be used as insulator 210.

[0701] For example, metal oxides such as aluminum oxide, hafnium oxide, and tantalum oxide are preferably used as insulators 214.

[0702] In particular, aluminum oxide has a high barrier effect against the permeation of impurities such as oxygen, hydrogen, and moisture that cause changes in the electrical characteristics of transistors. Therefore, during or after the transistor manufacturing process, aluminum oxide can prevent impurities such as hydrogen and moisture from entering the transistor 200. Furthermore, it can prevent oxygen from being released from the oxides constituting the transistor 200. Therefore, aluminum oxide is suitable as a protective film for the transistor 200.

[0703] An insulator 216 is formed on insulator 214. Insulator 216 can be made of the same material as insulator 420. For example, a silicon oxide film or a silicon oxynitride film can be used as insulator 216.

[0704] Conductors 218 and conductors 205 constituting transistor 200 are embedded in insulators 458, 210, 212, 214, and 216. Conductors 218 are used as plugs or wiring for electrical connection with capacitor 410 or transistor 400. Conductors 218 can be formed using the same material as conductors 428 and 430.

[0705] In particular, the conductor 218 in contact with insulators 458, 212, and 214 is preferably a conductor that inhibits copper diffusion or has the property of blocking oxygen, hydrogen, and water. Due to this structure, transistors 400 and 200 can be completely separated using layers that inhibit copper diffusion or have the property of blocking oxygen, hydrogen, and water. That is, copper diffusion from conductor 456 can be inhibited, and hydrogen diffusion from transistor 400 to transistor 200 can be inhibited.

[0706] A transistor 200 and an insulator 280 are disposed on an insulator 214. Figure 48 The transistor 200 shown is just an example and is not limited to this structure. Appropriate transistors can be used depending on the circuit structure or driving method.

[0707] Insulators 282, 284, and 470 are sequentially stacked on insulator 280. Conductors 244 are embedded in insulators 220, 222, 224, 280, 282, 284, and 470. Conductors 245, etc., connected to the conductors in the upper layers are provided on conductors such as conductors 240a and 240b included in transistor 200. Conductors 244 are used as plugs or wiring for electrical connection with capacitor 410, transistor 200, or transistor 400. Conductors 244 can be formed using the same material as conductors 428 and 430.

[0708] One or both of insulators 282 and 284 are preferably made of a material that blocks oxygen or hydrogen. Therefore, insulator 282 can be made of the same material as insulator 214. Insulator 284 can be made of the same material as insulator 212.

[0709] For example, insulator 282 is preferably made of metal oxides such as aluminum oxide, hafnium oxide, and tantalum oxide.

[0710] In particular, aluminum oxide has a high barrier effect against the permeation of impurities such as oxygen, hydrogen, and moisture that cause changes in the electrical characteristics of transistors. Therefore, during or after the transistor manufacturing process, aluminum oxide can prevent impurities such as hydrogen and moisture from entering the transistor 200. Furthermore, it can prevent oxygen from being released from the oxides constituting the transistor 200. Therefore, aluminum oxide is suitable as a protective film for the transistor 200.

[0711] The insulator 284 is preferably a barrier film to prevent hydrogen or impurities from diffusing from the area where the capacitor 410 is disposed to the area where the transistor 200 is disposed. Therefore, the insulator 284 can be made of the same material as the insulator 424.

[0712] For example, silicon nitride formed by CVD can be used as an example of a film that blocks hydrogen diffusion. However, when hydrogen diffuses into a semiconductor element having an oxide semiconductor, such as transistor 200, the characteristics of that semiconductor element sometimes degrade. Therefore, it is preferable to provide a film that suppresses hydrogen diffusion between transistor 200 and transistor 400. Specifically, the film that suppresses hydrogen diffusion is one with a low amount of hydrogen detachment.

[0713] Therefore, the transistor 200 and the insulator 280 containing the excess oxygen region can be sandwiched by a stacked structure of insulators 210, 212, and 214 and a stacked structure of insulators 282 and 284. Insulators 210, 212, 214, 282, and 284 have barrier properties that inhibit the diffusion of impurities such as oxygen, hydrogen, and water.

[0714] Therefore, the diffusion of oxygen released from insulator 280 and transistor 200 into the layer where capacitor 410 or transistor 400 is formed can be suppressed. Alternatively, the diffusion of impurities such as hydrogen and water from the layer above insulator 282 and the layer below insulator 214 into transistor 200 can be suppressed.

[0715] In other words, oxygen can be efficiently supplied from the excess oxygen region of the insulator 280 to the oxide forming the channel in the transistor 200, thereby reducing oxygen vacancies. Furthermore, the formation of oxygen vacancies in the oxide forming the channel in the transistor 200 due to impurities can be prevented. Therefore, the oxide forming the channel in the transistor 200 can be formed as an oxide semiconductor with low defect state density and stable characteristics. That is, reliability can be improved while suppressing variations in the electrical characteristics of the transistor 200.

[0716] A capacitor 410 and a conductor 474 are formed on an insulator 470. The capacitor 410 is formed on the insulator 470 and includes conductors 462, 480, 482, 484, and 466. The conductor 474 is used as a plug or wiring for electrical connection with the capacitor 410, transistor 200, or transistor 400.

[0717] Conductor 462 can be made of conductive materials such as metals, alloys, and metal oxides. High-melting-point materials such as tungsten or molybdenum, which have both heat resistance and conductivity, are preferred, and tungsten is particularly preferred. When conductor 462 is formed together with other components such as conductors, low-resistance metal materials such as Cu (copper) or Al (aluminum) can be used.

[0718] Conductor 474 can be formed using the same material as conductor 462, which is used as an electrode of the capacitor.

[0719] Insulators 480, 482, and 484 are formed on conductors 474 and 462, respectively. Examples of materials that can be used as insulators 480, 482, and 484 include silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum oxynitride, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium oxynitride, and hafnium nitride. In the accompanying drawings, a three-layer structure is used, but single-layer, two-layer, or four-layer or higher stacked structures can also be used.

[0720] For example, preferably, materials with high dielectric strength, such as silicon oxynitride, are used as insulators 480 and 484, and a laminated structure of a material with high dielectric constant (high-k), such as alumina, and a material with high dielectric strength, such as silicon oxynitride, is used as insulator 484. By adopting this structure, capacitor 410 can have sufficient capacitance due to the high dielectric constant (high-k) insulator, and can have higher insulation strength due to the high dielectric strength insulator to avoid electrostatic discharge.

[0721] Conductor 466 is formed on conductor 462 with insulators 480, 482, and 484 in between. Conductor 466 can be made of conductive materials such as metals, alloys, or metal oxides. High-melting-point materials such as tungsten or molybdenum, which have both heat resistance and conductivity, are preferred, and tungsten is particularly preferred. When conductor 466 is formed simultaneously with other components such as conductors, low-resistance metal materials such as Cu (copper) or Al (aluminum) can be used.

[0722] For example, such as Figure 48As shown, insulators 480, 482, and 484 are formed to cover the top and side surfaces of conductor 462. Furthermore, conductor 466 is formed by covering the top and side surfaces of conductor 462 with insulators 480, 482, and 484 in between.

[0723] In other words, a capacitor is also formed on the side of the conductor 462, thus increasing the capacitance per projected area of ​​the capacitor. Therefore, it is possible to achieve miniaturization, high integration, and micro-scale of semiconductor devices.

[0724] An insulator 460 is formed on the conductor 466 and the insulator 484. The insulator 460 can be formed using the same material as the insulator 420. The insulator 460 covering the capacitor 410 can also be used as a planarization film covering the uneven shape underneath.

[0725] The above are examples of applications.

[0726] At least a portion of this embodiment can be implemented in combination with other embodiments described in this specification.

[0727] (Implementation Method 5)

[0728] In this embodiment, using Figures 49A to 49C This describes a display device that includes a semiconductor device according to one embodiment of the present invention.

[0729] 5. Circuit structure of the display device

[0730] Figure 49A The display device shown includes: a region having pixels with display elements (hereinafter referred to as pixel section 502); a circuit section (hereinafter referred to as driving circuit section 504) disposed outside the pixel section 502 and having circuitry for driving the pixels; circuitry (hereinafter referred to as protection circuitry 506) each having the function of a protection element; and a terminal section 507. Alternatively, the protection circuitry 506 may be omitted.

[0731] Part or all of the drive circuit section 504 is preferably formed on the same substrate as the pixel section 502. This reduces the number of components and terminals. When part or all of the drive circuit section 504 is not formed on the same substrate as the pixel section 502, part or all of the drive circuit section 504 can be mounted by COG or TAB (Tape Automated Bonding).

[0732] The pixel unit 502 includes a circuit (hereinafter referred to as pixel circuit 501) for driving a plurality of display elements arranged in X rows (X is a natural number of 2 or more) and Y columns (Y is a natural number of 2 or more). The driving circuit unit 504 includes a circuit (hereinafter referred to as gate driver 504a) for supplying signals (scan signals) for selecting pixels and a circuit (hereinafter referred to as source driver 504b) for supplying signals (data signals) for driving the display elements in the pixels.

[0733] The gate driver 504a includes a shift register, etc. The gate driver 504a receives signals for driving the shift register via terminal 507 and outputs signals. For example, the gate driver 504a receives a start pulse signal, a clock signal, etc., and outputs a pulse signal. The gate driver 504a has the function of controlling the potential of the wiring supplied with scan signals (hereinafter referred to as scan lines GL_1 to GL_X). Alternatively, multiple gate drivers 504a can be provided, and each of the multiple gate drivers 504a can individually control scan lines GL_1 to GL_X. Alternatively, the gate driver 504a has the function of supplying an initialization signal. However, it is not limited to this; the gate driver 504a can also supply other signals.

[0734] The source driver 504b includes a shift register, etc. The source driver 504b receives signals for driving the shift register and signals from which data signals (image signals) are derived via terminal section 507. The source driver 504b has the function of generating data signals to be written to the pixel circuit 501 based on the image signals. Furthermore, the source driver 504b has the function of controlling the output of the data signals according to pulse signals generated by inputs such as start pulse signals and clock signals. Additionally, the source driver 504b has the function of controlling the potential of the wiring to which the data signals are supplied (hereinafter referred to as data lines DL_1 to DL_Y). Alternatively, the source driver 504b has the function of supplying an initialization signal. However, it is not limited to this; the source driver 504b can supply other signals.

[0735] The source driver 504b may include, for example, multiple analog switches. By sequentially turning on the multiple analog switches, the source driver 504b can output a signal obtained by time-dividing an image signal as a data signal. Furthermore, the source driver 504b may also include a shift register, etc.

[0736] Pulse signals and data signals are input to each of the plurality of pixel circuits 501 via one of the plurality of scan lines GL supplied with scan signals and one of the plurality of data lines DL supplied with data signals, respectively. Furthermore, gate driver 504a controls the writing and holding of data signals in each of the plurality of pixel circuits 501. For example, a pulse signal is input from gate driver 504a to the pixel circuit 501 in the m-th row and n-th column via scan line GL_m (m is a natural number less than or equal to X), and a data signal is input from source driver 504b to the pixel circuit 501 in the m-th row and n-th column via data line DL_n (n is a natural number less than or equal to Y) according to the potential of scan line GL_m.

[0737] Figure 49A The protection circuit 506 shown is connected, for example, to the scan line GL between the gate driver 504a and the pixel circuit 501. Alternatively, the protection circuit 506 is connected to the data line DL between the source driver 504b and the pixel circuit 501. Alternatively, the protection circuit 506 may be connected to the wiring between the gate driver 504a and the terminal portion 507. Alternatively, the protection circuit 506 may be connected to the wiring between the source driver 504b and the terminal portion 507. Furthermore, the terminal portion 507 refers to the portion provided with terminals for inputting power, control signals, and image signals to the display device from external circuitry.

[0738] The protection circuit 506 is a circuit that makes the wiring connected to it conductive with other wiring when a potential outside a certain range is supplied to the wiring connected to it.

[0739] like Figure 49A As shown, by providing a protection circuit 506 to the pixel section 502 and the driving circuit section 504, the display device's tolerance to overcurrent caused by ESD (Electro Static Discharge) and the like can be improved. However, the structure of the protection circuit 506 is not limited to this. For example, a structure in which the gate driver 504a is connected to the protection circuit 506 or a structure in which the source driver 504b is connected to the protection circuit 506 may also be used. Alternatively, a structure in which the terminal section 507 is connected to the protection circuit 506 may also be used.

[0740] In addition, although Figure 49A The illustration shows an example of a drive circuit section 504 including a gate driver 504a and a source driver 504b, but it is not limited thereto. For example, it is also possible to form only the gate driver 504a and mount a separately prepared substrate (e.g., a drive circuit substrate formed of a single-crystal semiconductor film or a polycrystalline semiconductor film) on it.

[0741] in addition, Figure 49A The multiple pixel circuits 501 shown can, for example, employ... Figure 49BThe structure shown.

[0742] Figure 49B The pixel circuit 501 shown includes a liquid crystal element 570, a transistor 550, and a capacitor 560. The transistor shown in the previous embodiment can be applied to transistor 550.

[0743] The potential of one of the pairs of electrodes of the liquid crystal element 570 is appropriately set according to the specifications of the pixel circuit 501. The orientation state of the liquid crystal element 570 is set according to the data being written. Alternatively, a common potential can be supplied to one of the pairs of electrodes of the liquid crystal element 570 in each of the plurality of pixel circuits 501. Furthermore, the potential supplied to one of the pairs of electrodes of the liquid crystal element 570 in a pixel circuit 501 within one row may differ from the potential supplied to one of the pairs of electrodes of the liquid crystal element 570 in a pixel circuit 501 within another row.

[0744] For example, the driving method for a display device including the liquid crystal element 570 can also use the following modes: TN mode; STN mode; VA mode; ASM (Axially Symmetric aligned Micro-cell) mode; OCB (Optically Compensated Birefringence) mode; FLC (Ferroelectric Liquid Crystal) mode; AFLC (Anti-Ferroelectric Liquid Crystal) mode; MVA mode; PVA (Patterned Vertical Alignment) mode; IPS mode; FFS mode; or TBA (Transverse Bend Alignment) mode, etc. In addition to the above driving methods, other driving methods for the display device include ECB (Electrically Controlled Birefringence) mode, PDLC (Polymer Dispersed Liquid Crystal) mode, PNLC (Polymer Network Liquid Crystal) mode, and guest-host mode, etc. However, it is not limited to this; various liquid crystal elements and driving methods can be used as liquid crystal elements and their driving methods.

[0745] In the pixel circuit 501 at row m and column n, one of the source and drain electrodes of transistor 550 is electrically connected to the data line DL_n, and the other of the source and drain electrodes is electrically connected to the other electrode of a pair of electrodes in the liquid crystal element 570. The gate electrode of transistor 550 is electrically connected to the scan line GL_m. Transistor 550 has the function of controlling the writing of data signals by being turned on or off.

[0746] One electrode of the pair of electrodes of capacitor 560 is electrically connected to the wiring supplied with the potential (hereinafter referred to as the potential supply line VL), and the other electrode is electrically connected to the other electrode of the pair of electrodes of liquid crystal element 570. Furthermore, the potential of the potential supply line VL is appropriately set according to the specifications of pixel circuit 501. Capacitor 560 functions as a storage capacitor for storing written data.

[0747] For example, in including Figure 49B In the display device shown by pixel circuit 501, through Figure 49A The gate driver 504a shown sequentially selects the pixel circuits 501 of each row and turns on the transistors 550 to write data signals.

[0748] When transistor 550 is turned off, the pixel circuit 501, on which data is being written, remains in a held state. By performing the above steps row by row, an image can be displayed.

[0749] Figure 49A The multiple pixel circuits 501 shown can, for example, employ... Figure 49C The structure shown.

[0750] Figure 49C The pixel circuit 501 shown includes transistors 552 and 554, capacitor 562, and light-emitting element 572. The transistors shown in the previous embodiments can be used in one or both of transistors 552 and 554.

[0751] One of the source and drain electrodes of transistor 552 is electrically connected to the wiring for which a data signal is supplied (hereinafter referred to as data line DL_n). Furthermore, the gate electrode of transistor 552 is electrically connected to the wiring for which a gate signal is supplied (hereinafter referred to as scan line GL_m).

[0752] Transistor 552 has the function of controlling the writing of data signals by being turned on or off.

[0753] One of the electrodes of capacitor 562 is electrically connected to the wiring supplied with potential (hereinafter referred to as potential supply line VL_a), and the other electrode is electrically connected to the other of the source and drain electrodes of transistor 552.

[0754] Capacitor 562 has the function of a storage capacitor for storing the data that has been written.

[0755] One of the source and drain electrodes of transistor 554 is electrically connected to the potential supply line VL_a. Furthermore, the gate electrode of transistor 554 is electrically connected to the other of the source and drain electrodes of transistor 552.

[0756] One of the anode and cathode of the light-emitting element 572 is electrically connected to the potential supply line VL_b, and the other is electrically connected to the other of the source and drain electrodes of the transistor 554.

[0757] As the light-emitting element 572, for example, an organic electroluminescent element (also known as an organic EL element) can be used. Note that the light-emitting element 572 is not limited to an organic EL element, and an inorganic EL element made of inorganic materials can also be used.

[0758] In addition, one of the potential supply lines VL_a and VL_b is supplied with a high power supply potential VDD, and the other is supplied with a low power supply potential VSS.

[0759] For example, in including Figure 49C In the display device shown by pixel circuit 501, through Figure 49A The gate driver 504a shown sequentially selects the pixel circuits 501 of each row and turns on the transistor 552 to write data signals.

[0760] When transistor 552 is turned off, the pixel circuit 501, on which data is being written, remains in a held state. Furthermore, the amount of current flowing between the source and drain electrodes of transistor 554 is controlled according to the potential of the written data signal, and the light-emitting element 572 emits light with a brightness corresponding to the amount of current flowing through it. By performing the above steps row by row, an image can be displayed.

[0761] This embodiment can be implemented in appropriate combinations with other embodiments described in this specification.

[0762] (Implementation Method 6)

[0763] In this embodiment, refer to Figures 50A to 50C , Figures 51A to 51C , Figure 52A and Figure 52B as well as Figure 53A and Figure 53B Examples of transistor circuit structures that can be applied to the embodiments described above will be explained.

[0764] 6. Example of an inverter circuit structure

[0765] Figure 50AThis diagram shows an inverter applicable to shift registers and buffers included in a drive circuit. Inverter 800 outputs a logically inverted signal, derived from the signal supplied to input terminal IN, to output terminal OUT. Inverter 800 includes multiple OS transistors. Signal S BG It is a signal that can switch the electrical characteristics of the OS transistor.

[0766] Figure 50B This is an example of inverter 800. Inverter 800 includes OS transistor 810 and OS transistor 820. Inverter 800 can be formed using only n-channel transistors, so it can be manufactured at a lower cost compared to the case where inverters are formed using CMOS (Complementary Metal Oxide Semiconductor).

[0767] Alternatively, the inverter 800, including the OS transistor, can also be placed on the CMOS circuit composed of Si transistors. Because the inverter 800 can overlap with the CMOS circuit, the increase in circuit area caused by adding the inverter 800 can be suppressed.

[0768] OS transistors 810 and 820 both include a first gate used as a front gate, a second gate used as a back gate, a first terminal used as one of the source and drain, and a second terminal used as the other of the source and drain.

[0769] The first gate of the OS transistor 810 is connected to the second terminal. The second gate of the OS transistor 810 is connected to the supply signal S. BG The wiring connections are as follows: The first terminal of the OS transistor 810 is connected to the supply voltage VDD. The second terminal of the OS transistor 810 is connected to the output terminal OUT.

[0770] The first gate of OS transistor 820 is connected to the input terminal IN. The second gate of OS transistor 820 is connected to the input terminal IN. The first terminal of OS transistor 820 is connected to the output terminal OUT. The second terminal of OS transistor 820 is connected to the wiring for the supply voltage VSS.

[0771] Figure 50C This is a timing diagram used to illustrate the operation of inverter 800. Figure 50C The timing diagram shows the signal waveforms at the input terminal IN, the output terminal OUT, and the signal S. BG The signal waveform and the change in the threshold voltage of the OS transistor 810.

[0772] By signal S BGThe threshold voltage of the OS transistor 810 can be controlled by applying a second gate to the OS transistor 810.

[0773] Signal S BG It has a voltage V used to shift the threshold voltage in the negative direction. BG_A And the voltage V used to shift the threshold voltage in the positive direction BG_B By applying a voltage V to the second gate BG_A This can cause the threshold voltage of the OS transistor 810 to drift negatively, becoming the threshold voltage V. TH_A Additionally, by applying a voltage V to the second gate... BG_B This can cause the threshold voltage of the OS transistor 810 to drift in the positive direction, thus becoming the threshold voltage V. TH_B .

[0774] To make the above explanation visual, Figure 51A The Id-Vg curve is shown as one of the electrical characteristic indicators of a transistor.

[0775] By increasing the voltage of the second gate to voltage V BG_A The curves showing the electrical characteristics of the aforementioned OS transistor 810 can be plotted to... Figure 51A The curve drift is represented by the dashed line 840. Additionally, by reducing the voltage of the second gate to voltage V... BG_B The curves showing the electrical characteristics of the aforementioned OS transistor 810 can be plotted to... Figure 51A The curve drift, represented by the solid line 841, is shown in the figure. This is achieved by using signal S... BG Switch to voltage V BG_A or voltage V BG_B ,like Figure 51A As shown, the threshold voltage of the OS transistor 810 can be shifted in the positive or negative direction.

[0776] The threshold voltage V is obtained by shifting the threshold voltage in the positive direction. TH_B This can put the OS transistor 810 in a state where current does not easily flow. Figure 51B Visually represent the current state.

[0777] like Figure 51B As shown, the current I flowing through the OS transistor 810 can be... B Extremely small. Therefore, when the signal applied to the input terminal IN is high and the OS transistor 820 is turned on, the voltage at the output terminal OUT can be drastically reduced.

[0778] like Figure 51B As shown, the OS transistor 810 can be placed in a state where current does not easily flow, so it can... Figure 50CThe timing diagram shown causes a sharp change in the signal waveform 831 at the output terminal. Because the current flowing between the wiring for the supply voltage VDD and the wiring for the supply voltage VSS can be reduced, it can operate with low power consumption.

[0779] Additionally, the threshold voltage V is obtained by shifting the threshold voltage in the negative direction. TH_A This allows the OS transistor 810 to be in a state where current can flow easily. Figure 51C Visually represent the current state. For example... Figure 51C As shown, the current I flowing at this time can be... A Set to be at least greater than current I B The value of . Therefore, when the signal applied to the input terminal IN is low and the OS transistor 820 is in the off state (OFF), the voltage at the output terminal OUT can be increased sharply. For example Figure 51C As shown, the OS transistor 810 can be placed in a state where current can easily flow, so it can... Figure 50C The timing diagram shown causes a sharp change in the signal waveform 832 at the output terminal.

[0780] Note that signal S BG The control of the threshold voltage of OS transistor 810 is preferably performed before switching the state of OS transistor 820, i.e., before times T1 and T2. For example, as Figure 50C As shown, preferably, the threshold voltage of the OS transistor 810 is changed from the threshold voltage V before the moment T1 when the signal applied to the input terminal IN is switched to a high level. TH_A Switch to threshold voltage V TH_B Additionally, such as Figure 50C As shown, preferably, the threshold voltage of the OS transistor 810 is reduced from the threshold voltage V before the moment T2 when the signal applied to the input terminal IN is switched to a low level. TH_B Switch to threshold voltage V TH_A .

[0781] Note that, although Figure 50C The timing diagram shows the switching signal S based on the signal applied to the input terminal IN. BG While the structure is correct, other structures can also be used. For example, a structure can be used that maintains the second gate of the floating OS transistor 810 at a voltage used to control the threshold voltage. Figure 52A An example of this circuit structure is shown.

[0782] exist Figure 52A In addition to Figure 50B In addition to the circuit structure shown, an OS transistor 850 is also included. The first terminal of the OS transistor 850 is connected to the second gate of the OS transistor 810. The second terminal of the OS transistor 850 is connected to the supply voltage V.BG_B (or voltage V) BG_A The wiring connection of the OS transistor 850. The first gate of the OS transistor 850 is connected to the supply signal S. F The wiring connection. The second gate of the OS transistor 850 is connected to the supply voltage V. BG_B (or voltage V) BG_A Wiring connections.

[0783] Reference Figure 52B The timing diagram Figure 52A The work will be explained.

[0784] Before the signal applied to the input terminal IN is switched to a high level at time T3, the threshold voltage used to control the OS transistor 810 is applied to the second gate of the OS transistor 810. The signal S... F The OS transistor 850 is set to high level and turned on, affecting node N. BG Apply a voltage V to control the threshold voltage. BG_B .

[0785] At node N BG Become voltage V BG_B Next, the OS transistor 850 is turned off. Because the off-state current of the OS transistor 850 is extremely small, keeping it off maintains the stability of node N. BG The voltage V maintained BG_B Therefore, a voltage V is applied to the second gate of the OS transistor 850. BG_B The number of operations is reduced, so the rewrite voltage V can be reduced. BG_B The required power consumption.

[0786] Note that, although in Figure 50B and Figure 52A The circuit structure shown depicts a configuration where a voltage is applied to the second gate of the OS transistor 810 via external control; however, other configurations are also possible. For example, a configuration could be used where a voltage is generated based on a signal applied to the input terminal IN to control a threshold voltage, which is then applied to the second gate of the OS transistor 810. Figure 53A An example of this circuit structure is shown.

[0787] Figure 53A Shown in Figure 50B The circuit structure shown includes a CMOS inverter 860 added between the input terminal IN and the second gate of the OS transistor 810. The input terminal of the CMOS inverter 860 is connected to the input terminal IN. The output terminal of the CMOS inverter 860 is connected to the second gate of the OS transistor 810.

[0788] Reference Figure 53B The timing diagram Figure 53A The work will be explained. Figure 53B The timing diagram shows the signal waveforms at the input terminal IN, the output terminal OUT, the output waveform IN_B of the CMOS inverter 860, and the change in the threshold voltage of the OS transistor 810.

[0789] The output waveform IN_B, which is the logical inversion of the signal applied to the input terminal IN, can be used as a signal to control the threshold voltage of the OS transistor 810. Therefore, as... Figures 51A to 51C As explained, the threshold voltage of the OS transistor 810 can be controlled. For example, in Figure 53B At time T4, the signal applied to the input terminal IN is high, and the OS transistor 820 is turned on. At this time, the output waveform IN_B is low. Therefore, the OS transistor 810 can be placed in a state where current does not flow easily, thus drastically reducing the voltage rise at the output terminal OUT.

[0790] In addition, Figure 53B At time T5, the signal applied to the input terminal IN is low, and the OS transistor 820 is off. At this time, the output waveform IN_B is high. Therefore, the OS transistor 810 can be placed in a state where current can easily flow, thus drastically increasing the voltage at the output terminal OUT.

[0791] As described above, in this embodiment, the voltage of the back gate of the inverter, including the OS transistor, is switched according to the logic of the signal at the input terminal IN. By employing this structure, the threshold voltage of the OS transistor can be controlled. By controlling the threshold voltage of the OS transistor according to the signal applied to the input terminal IN, the voltage at the output terminal OUT can be drastically changed. Furthermore, the through current between the power supply wirings can be reduced. Therefore, low power consumption can be achieved.

[0792] This embodiment can be implemented in appropriate combinations with other embodiments described in this specification.

[0793] (Implementation Method 7)

[0794] In this embodiment, refer to Figures 54A to 54E , Figure 55A and Figure 55B , Figure 56A and Figure 56B as well as Figures 57A to 57C An example of a semiconductor device that uses an oxide semiconductor transistor (OS transistor) as described in the above embodiments in multiple circuits will be described.

[0795] 7. Examples of circuit structures for semiconductor devices

[0796] Figure 54A This is a block diagram of semiconductor device 900. Semiconductor device 900 includes power supply circuit 901, circuit 902, voltage generation circuit 903, circuit 904, voltage generation circuit 905, and circuit 906.

[0797] Power supply circuit 901 generates reference potential V ORG The circuit. Voltage V ORG It is not limited to a single voltage; it can also be multiple voltages. Voltage V ORG It can be generated based on a voltage V0 applied from outside the semiconductor device 900. The semiconductor device 900 can generate a voltage V based on a power supply voltage applied from outside. ORG Therefore, the semiconductor device 900 can operate even without multiple external power supply voltages.

[0798] Circuits 902, 904, and 906 operate with different power supply voltages. For example, the power supply voltage of circuit 902 is based on voltage V. ORG and voltage V SS (V) ORG V SS The voltage applied to the circuit. For example, the power supply voltage of circuit 904 is based on voltage V. POG and voltage V SS (V) POG V ORG The voltage applied to the circuit. For example, the power supply voltage of circuit 906 is based on voltage V. ORG Voltage V SS and voltage V NEG (V) ORG V SS V NEG The voltage applied. Additionally, if the voltage V... SS Setting the voltage to the same level as ground potential (GND) can reduce the variety of voltages generated by the power supply circuit 901.

[0799] The voltage generation circuit 903 generates voltage V. POG The circuit. The voltage generation circuit 903 can be based on the voltage V applied from the power supply circuit 901. ORG And the generated voltage V POG Therefore, the semiconductor device 900, including circuit 904, can operate based on a power supply voltage applied from the outside.

[0800] The voltage generation circuit 905 generates voltage V. NEG The circuit. The voltage generation circuit 905 can be based on the voltage V applied from the power supply circuit 901. ORG And the generated voltage V NEGTherefore, the semiconductor device 900, including circuit 906, can operate based on a power supply voltage applied from the outside.

[0801] Figure 54B It is based on voltage V POG Example of a working circuit 904. Figure 54C This is an example of a signal waveform used to make circuit 904 work.

[0802] Figure 54B Transistor 911 is shown. The signal applied to the gate of transistor 911 is, for example, based on voltage V. POG and voltage V SS This signal is generated based on voltage V when transistor 911 is turned on. POG The generation is based on voltage V when transistor 911 is in a non-conducting state. SS And generated. For example Figure 54C As shown, voltage V POG Higher than voltage V ORG Therefore, transistor 911 can more reliably connect the source (S) and drain (D) electrically. As a result, circuit 904, which reduces malfunctions, can be implemented.

[0803] Figure 54D It is based on voltage V NEG Example of a working circuit 906. Figure 54E This is an example of a signal waveform used to make circuit 906 work.

[0804] Figure 54D A transistor 912 with a back gate is shown. The signal applied to the gate of transistor 912 is, for example, based on a voltage V. ORG and voltage V SS This signal is generated based on voltage V when transistor 912 is turned on. ORG The generation is based on voltage V when transistor 912 is in a non-conducting state. SS And thus generated. Additionally, the signal applied to the back gate of transistor 912 is based on voltage V. NEG And generated. For example Figure 54E As shown, voltage V NEG Below voltage V SS (GND). Therefore, the threshold voltage of transistor 912 can be shifted in the positive direction. Thus, transistor 912 can be made non-conducting more reliably, thereby reducing the current flowing between the source (S) and drain (D). As a result, circuit 906 with reduced malfunctions and low power consumption can be achieved.

[0805] In addition, voltage V NEG It can also be applied directly to the back gate of transistor 912. Alternatively, it can be based on voltage V.ORG and voltage V NEG A signal is generated and applied to the gate of transistor 912, and the signal is applied to the back gate of transistor 912.

[0806] in addition, Figure 55A and Figure 55B Show Figure 54D and Figure 54E Examples of variations.

[0807] exist Figure 55A In the circuit diagram shown, a transistor 922 is positioned between voltage generation circuit 905 and circuit 906, and its conduction state can be controlled by control circuit 921. Transistor 922 is an n-channel OS transistor. The control signal S output by control circuit 921... BG This is the signal that controls the conduction state of transistor 922. Additionally, transistors 912A and 912B included in circuit 906 are the same OS transistors as transistor 922.

[0808] Figure 55B The timing diagram shows the control signal S BG Potential and node N BG The potential change at node N. BG The potential represents the back gate potential state of transistors 912A and 912B. Under control signal S... BG When the voltage level is high, transistor 922 is in the ON state, and node N... BG Become voltage V NEG Then, in the control signal S BG When it is low, node N BG It is in an electrically floating state. Because transistor 922 is an OS transistor, its off-state current is small. Therefore, even at node N... BG Even when in an electrically floating state, the applied voltage V can be maintained. NEG .

[0809] in addition, Figure 56A An example of a circuit structure that can be applied to the voltage generation circuit 903 described above is shown. Figure 56A The voltage generation circuit 903 shown is a 5-stage charge pump comprising diodes D1 to D5, capacitors C1 to C5, and inverter INV. The clock signal CLK is applied directly to capacitors C1 to C5, or through inverter INV. The power supply voltage of inverter INV is based on voltage V. ORG and voltage V SS When the applied voltage is applied, it can be boosted to voltage V by the supply clock signal CLK. ORG A voltage V that is 5 times the positive voltage POGNote that the forward voltage of diodes D1 through D5 is 0V. Alternatively, the desired voltage V can be obtained by changing the number of stages in the charge pump. POG .

[0810] in addition, Figure 56B An example of a circuit structure that can be applied to the voltage generation circuit 905 described above is shown. Figure 56B The voltage generation circuit 905 shown is a four-stage charge pump including diodes D1 to D5, capacitors C1 to C5, and inverter INV. The clock signal CLK is applied directly to capacitors C1 to C5, or through inverter INV. The supply voltage of inverter INV is based on voltage V. ORG and voltage V SS When a voltage is applied, the voltage V can be obtained from the ground potential, i.e., the voltage V, by supplying the clock signal CLK. SS Step down to voltage V ORG A voltage V that is 4 times the negative voltage NEG Note that the forward voltage of diodes D1 through D5 is 0V. Alternatively, the desired voltage V can be obtained by changing the number of stages in the charge pump. NEG .

[0811] Note that the circuit structure of the voltage generation circuit 903 described above is not limited to... Figure 56A The circuit diagram shown has the following structure. Figures 57A to 57C A modified example of the voltage generation circuit 903 is shown. Figures 57A to 57C In the voltage generation circuits 903A to 903C shown, variations of the voltage generation circuit 903 can be achieved by changing the voltage supplied to each wiring or by changing the configuration of the components.

[0812] Figure 57A The voltage generation circuit 903A shown includes transistors M1 to M10, capacitors C11 to C14, and inverter INV1. The clock signal CLK is supplied directly or via inverter INV1 to the gates of transistors M1 to M10. The voltage V is increased by applying the clock signal CLK. ORG The increase is equivalent to the voltage V. ORG With V SS The potential difference is four times that of the voltage V, from which the voltage V can be obtained. POG Furthermore, by changing the number of stages in the charge pump, the desired voltage V can be obtained. POG .exist Figure 57A In the voltage generation circuit 903A shown, by using OS transistors as transistors M1 to M10, the off-state current can be reduced, and the leakage of charge held in capacitors C11 to C14 can be suppressed. Therefore, the voltage V can be generated. ORG Efficiently boost voltage to V POG .

[0813] in addition, Figure 57B The voltage generation circuit 903B shown includes transistors M11 to M14, capacitors C15 and C16, and inverter INV2. The clock signal CLK is supplied directly to the gates of transistors M11 to M14, or via inverter INV2. The voltage V is increased by applying the clock signal CLK. ORG The increase is equivalent to the voltage V. ORG With V SS The voltage V can be obtained by taking twice the potential difference. POG .exist Figure 57B In the voltage generation circuit 903B shown, by using OS transistors as transistors M11 to M14, the off-state current can be reduced, and the leakage of charge held in capacitors C15 and C16 can be suppressed. Therefore, the voltage V can be generated. ORG Efficiently boost voltage to V POG .

[0814] in addition, Figure 57C The voltage generation circuit 903C shown includes an inductor Ind1, a transistor M15, a diode D6, and a capacitor C17. The conduction state of transistor M15 is controlled by the control signal EN. Due to the control signal EN, a voltage V can be generated. ORG Boost voltage V POG Because Figure 57C The voltage generation circuit 903C shown uses an inductor Ind1 for voltage boosting, so it can boost voltage with high efficiency.

[0815] As described above, in the structure of this embodiment, the voltage required for the circuits included in the semiconductor device can be generated inside the semiconductor device. Therefore, the number of power supply voltages applied from outside the semiconductor device can be reduced.

[0816] This embodiment can be implemented in appropriate combinations with other embodiments described in this specification.

[0817] (Implementation Method 8)

[0818] In this embodiment, refer to Figure 58 , Figures 59A to 59E , Figures 60A to 60G as well as Figure 61A and Figure 61B A display module and an electronic device including a semiconductor device according to one embodiment of the present invention will be described.

[0819] 8-1. Display Module

[0820] Figure 58The display module 7000 shown includes a touch screen 7004 connected to FPC 7003, a display panel 7006 connected to FPC 7005, a backlight 7007, a bezel 7009, a printed circuit board 7010, and a battery 7011, located between the upper cover 7001 and the lower cover 7002.

[0821] For example, the semiconductor device of one embodiment of the present invention can be used in a display panel 7006.

[0822] The upper cover 7001 and the lower cover 7002 can be appropriately changed in shape and size according to the size of the touch screen 7004 and the display panel 7006.

[0823] The touchscreen 7004 can be a resistive or capacitive touchscreen and can overlap with the display panel 7006. Furthermore, the opposing substrate (sealed substrate) of the display panel 7006 can also function as a touchscreen. Alternatively, an optical touchscreen can be formed by placing a light sensor within each pixel of the display panel 7006.

[0824] The backlight 7007 has a light source 7008. Note that, although in Figure 58 The illustration shows a structure in which a light source 7008 is arranged on a backlight 7007, but it is not limited to this. For example, the light source 7008 can also be arranged at the end of the backlight 7007 and a light diffuser plate can be used. When using a self-emissive light-emitting element such as an organic EL element, or when using a reflective panel, a structure in which the backlight 7007 is not provided can be adopted.

[0825] In addition to protecting the display panel 7006, the bezel 7009 also serves as electromagnetic shielding to block electromagnetic waves generated by the operation of the printed circuit board 7010. Furthermore, the bezel 7009 can also function as a heat sink.

[0826] The printed circuit board 7010 includes a power supply circuit and a signal processing circuit for outputting video and clock signals. The power supply to the power supply circuit can be an external commercial power supply or a separately installed battery 7011. When using a commercial power supply, the battery 7011 can be omitted.

[0827] In addition, components such as polarizers, phase difference plates, and prism sheets can also be installed in the display module 7000.

[0828] 8-2. Electronic Equipment 1

[0829] also, Figures 59A to 59E Examples of electronic devices are shown.

[0830] Figure 59A This is an exterior view of the camera 8000 equipped with a viewfinder 8100.

[0831] The camera 8000 includes a housing 8001, a display unit 8002, operation buttons 8003, a shutter button 8004, etc. In addition, the camera 8000 is equipped with a detachable lens 8006.

[0832] Here, although the lens 8006 of the camera 8000 is detachable from the housing 8001 and interchangeable, the lens 8006 may also be included in the housing 8001.

[0833] The camera 8000 can take an image by pressing the shutter button 8004. Alternatively, the display unit 8002 is used as a touchscreen, and images can also be taken by touching the display unit 8002.

[0834] The housing 8001 of the camera 8000 includes an insert with electrodes, a viewfinder 8100 or a flash unit, etc., which can be connected to the housing 8001.

[0835] The viewfinder 8100 includes a housing 8101, a display unit 8102, and buttons 8103, etc.

[0836] The housing 8101 includes an inserter that fits into the camera 8000, allowing the viewfinder 8100 to be connected to the camera 8000. Additionally, the inserter includes electrodes that can display images received from the camera 8000 via these electrodes on the display unit 8102.

[0837] Button 8103 is used as a power button. By using button 8103, the display unit 8102 can be switched between displaying and not displaying.

[0838] The display device of one embodiment of the present invention can be applied to the display unit 8002 of a camera 8000 and the display unit 8102 of a viewfinder 8100.

[0839] In addition, Figure 59A In this case, the camera 8000 and the viewfinder 8100 are separate and detachable electronic devices, but a viewfinder with a display device can also be built into the housing 8001 of the camera 8000.

[0840] also, Figure 59B This is an image of the 8200 head-mounted display.

[0841] The head-mounted display 8200 includes a mounting section 8201, a lens 8202, a main body 8203, a display section 8204, and a cable 8205. Additionally, a battery 8206 is built into the mounting section 8201.

[0842] Power is supplied from battery 8206 to main body 8203 via cable 8205. Main body 8203 includes a wireless receiver, etc., and displays video data such as received image data on display unit 8204. In addition, by using a camera installed in main body 8203 to capture the user's eyeball and eyelid movements, and calculating the coordinates of the user's viewpoint based on the captured data, the user's viewpoint can be used as an input method.

[0843] Alternatively, multiple electrodes can be provided at the location of the mounting section 8201 that is touched by the user. The main body 8203 can also be configured to identify the direction of the user's eyes by detecting the current flowing through the electrodes according to the user's eye movements. Furthermore, the main body 8203 can be configured to monitor the user's pulse by detecting the current flowing through the electrodes. The mounting section 8201 can have various sensors such as temperature sensors, pressure sensors, and acceleration sensors to display the user's biometric information on the display section 8204. In addition, the main body 8203 can also be configured to detect the user's head movements, etc., and synchronously change the image displayed on the display section 8204 in sync with the user's head movements, etc.

[0844] The display device according to one embodiment of the present invention can be used in the display unit 8204.

[0845] Figures 59C to 59E This is an external view of the head-mounted display 8300. The head-mounted display 8300 includes a housing 8301, a display unit 8302, a fixing strap 8304, and a pair of lenses 8305.

[0846] The user can see the display on the display unit 8302 through the lens 8305. Preferably, the display unit 8302 is curved. By arranging the display unit 8302 in a curved manner, the user can experience a high degree of realism. Note that in this embodiment, a structure with one display unit 8302 is shown, but it is not limited to this; for example, a structure with two display units 8302 can also be used. In this case, by setting the display unit to correspond to each of the user's eyes, three-dimensional display utilizing parallax can be performed.

[0847] The display device according to one embodiment of the present invention can be applied to the display unit 8302. Because the display device including the semiconductor device according to one embodiment of the present invention has extremely high resolution, even if... Figure 59E By using the 8305 lens to magnify the image, the user can see a more realistic image without seeing the pixels.

[0848] 8-3. Electronic Equipment 2

[0849] then, Figures 59A to 59E Showing with Figures 60A to 60GExamples of different electronic devices are shown.

[0850] Figures 60A to 60G The electronic device shown includes a housing 9000, a display unit 9001, a speaker 9003, operation keys 9005 (including a power switch or operation switch), a connection terminal 9006, a sensor 9007 (which has the function of measuring the following factors: force, displacement, position, velocity, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, tilt, vibration, odor, or infrared radiation), a microphone 9008, etc.

[0851] Figures 60A to 60G The electronic device shown has various functions. For example, it can display various information (still images, moving images, text images, etc.) on a display panel; it can have a touch panel; it can display a calendar, date, or time; it can control processing using various software (programs); it has wireless communication capabilities; it can connect to various computer networks using wireless communication; it can send or receive various data using wireless communication; it can read programs or data stored in a storage medium and display them on the display panel; etc. Note that... Figures 60A to 60G The electronic device shown may have functions not limited to those described above, but may possess a variety of functions. Furthermore, although in Figures 60A to 60G Although not illustrated, the electronic device may include multiple display units. Furthermore, a camera or similar device may be incorporated into the electronic device to provide the following functions: the ability to capture still images; the ability to capture moving images; the ability to store captured images in a storage medium (external storage medium or storage medium built into the camera); the ability to display captured images on a display unit; and so on.

[0852] The following is a detailed explanation. Figures 60A to 60G The electronic device shown.

[0853] Figure 60A This is a perspective view showing the television unit 9100. A large display unit 9001, for example, 50 inches or more or 100 inches or more, can be assembled into the television unit 9100.

[0854] Figure 60BThis is a perspective view showing a portable information terminal 9101. The portable information terminal 9101 has one or more functions, such as a telephone, an electronic notebook, and an information reading device. Specifically, it can be used as a smartphone. Furthermore, the portable information terminal 9101 may be equipped with a speaker 9003, a connection terminal 9006, a sensor 9007, etc. Additionally, the portable information terminal 9101 can display text and image information on multiple surfaces. For example, three operation buttons 9050 (also called operation icons or simply icons) can be displayed on one surface of the display unit 9001. Additionally, information 9051, represented by a dashed rectangle, can be displayed on another surface of the display unit 9001. Furthermore, examples of information 9051 include notifications of received emails, SNS (Social Networking Services), or phone calls; the title and sender of emails or SNS messages; date; time; battery level; and antenna reception strength. Alternatively, operation buttons 9050 can be displayed instead of information 9051 in the same location where information 9051 is displayed.

[0855] Figure 60C This is a perspective view showing a portable information terminal 9102. The portable information terminal 9102 has the function of displaying information on three or more surfaces of the display unit 9001. Here, examples are shown where information 9052, information 9053, and information 9054 are displayed on different surfaces. For example, the user of the portable information terminal 9102 can check its display (in this case, information 9053) while the portable information terminal 9102 is placed in an upper pocket. Specifically, the phone number or name of the caller is displayed in a position that allows the user to view this information from above the portable information terminal 9102. The user can check this display without taking the portable information terminal 9102 out of their pocket, thereby determining whether to answer the call.

[0856] Figure 60DThis is a perspective view showing a watch-type portable information terminal 9200. The portable information terminal 9200 can execute various applications such as mobile phone use, email, article reading and editing, music playback, internet communication, and computer games. Furthermore, the display surface of the display unit 9001 is curved, allowing for display on the curved surface. Additionally, the portable information terminal 9200 can perform short-range wireless communication according to communication standards. For example, the portable information terminal can communicate with a headset capable of wireless communication, thus enabling hands-free calling. Furthermore, the portable information terminal 9200 includes a connection terminal 9006, allowing direct data exchange with other information terminals via a connector. Charging can also be performed via the connection terminal 9006. Moreover, charging can also be performed wirelessly without using the connection terminal 9006.

[0857] Figures 60E to 60G This is a perspective view showing the foldable portable information terminal 9201. Additionally, Figure 60E This is a perspective view of the 9201 portable information terminal in its unfolded state. Figure 60F This is a perspective view of the portable information terminal 9201 when it is unfolded or folded. Figure 60G This is a perspective view of the portable information terminal 9201 in its folded state. The portable information terminal 9201 is highly portable in its folded state, and its unfolded state offers excellent visibility due to its large, seamlessly integrated display area. The display unit 9001 included in the portable information terminal 9201 is supported by three outer shells 9000 connected by hinges 9055. By bending two of the outer shells 9000 together via the hinges 9055, the portable information terminal 9201 can be reversibly changed from an unfolded state to a folded state. For example, the portable information terminal 9201 can be bent with a radius of curvature of 1 mm or more and 150 mm or less.

[0858] then, Figure 61A and Figure 61B Showing with Figures 59A to 59E , Figures 60A to 60G Examples of different electronic devices are shown. Figure 61A and Figure 61B It is a perspective view of a display device that includes multiple display panels. Figure 61A This is a perspective view of multiple display panels being rolled up. Figure 61B This is a perspective view when the object is not rolled up.

[0859] Figure 61A and Figure 61B The display device 9500 shown includes multiple display panels 9501, a shaft portion 9511, and a bearing portion 9512. Each of the multiple display panels 9501 includes a display area 9502 and a light-transmitting area 9503.

[0860] The multiple display panels 9501 are flexible. Adjacent display panels 9501 are arranged with a portion overlapping each other. For example, the light-transmitting areas 9503 of two adjacent display panels 9501 can overlap. By using multiple display panels 9501, a display device with a large screen can be realized. Furthermore, the display panels 9501 can be rolled up depending on the application, thus enabling a highly versatile display device.

[0861] Figure 61A and Figure 61B The illustration shows a case where the display areas 9502 of adjacent display panels 9501 are separated from each other, but it is not limited to this. For example, a continuous display area 9502 can also be achieved by overlapping the display areas 9502 of adjacent display panels 9501 without gaps.

[0862] The electronic device shown in this embodiment includes a display unit for displaying certain information. Note that the semiconductor device of one embodiment of the...

Claims

1. A transistor, in, In the saturation region of the transistor, the difference between the minimum and maximum values ​​of the transistor's field-effect mobility is 15 cm⁻¹. 2 / Vs and below Furthermore, the minimum value of the field-effect mobility of the transistor is less than 30% lower than the maximum value of the field-effect mobility.

2. A semiconductor device, comprising: The first semiconductor layer contains only germanium; as well as A second semiconductor layer comprising indium, situated above the first semiconductor layer.

Images