Semiconductor devices

Abstract

A semiconductor device including a backside power delivery network (BSPDN) is provided. The semiconductor device includes: a semiconductor substrate including a first side and a second side on a side of the semiconductor substrate opposite to the first side; an active pattern on the first side; a gate structure intersecting the active pattern; source / drain regions connected to the active pattern on the side surface of the gate structure; a front wiring structure connected to at least one of the gate structure and the source / drain regions on the first side; a rear wiring structure on the second side; and a contact pattern in the semiconductor substrate, wherein the contact pattern is connected to the rear wiring structure, and wherein the height of the contact pattern in a vertical direction intersecting the first side is less than the thickness of the semiconductor substrate in the vertical direction.

Description

Cross-references to related applications

[0001] This application claims priority to and all benefits arising therefrom of Korean Patent Application No. 10-2024-0176604, filed on December 2, 2024, with the Korean Intellectual Property Office, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] This invention relates to a semiconductor device and a method for manufacturing a semiconductor device. More specifically, this invention relates to a semiconductor device including a backside power delivery network (BSPDN) and a method for manufacturing a semiconductor device. Background Technology

[0003] Semiconductor devices have attracted much attention as important components in the electronics industry due to their characteristics such as miniaturization, versatility, and / or low production costs. Semiconductor devices can be divided into semiconductor memory devices that store logic data, semiconductor logic devices that perform computational processing on logic data, and hybrid semiconductor devices that include memory elements and logic elements.

[0004] As the electronics industry advances to higher levels, the demands on the characteristics of semiconductor devices are increasing. For example, there is a growing need for high reliability, high speed, and / or multifunctionality in semiconductor devices. To meet these characteristics, the structures within semiconductor devices are becoming more complex and highly integrated.

[0005] On the other hand, as semiconductor devices become highly integrated, the width of the wiring patterns and through-hole patterns that realize semiconductor devices is reduced. As a result, the voltage drop (e.g., IR drop) of the power delivery network (PDN) that supplies the power supply voltage to the integrated circuit becomes a serious problem. Summary of the Invention

[0006] Various aspects of the present invention provide a semiconductor device that makes it easier to perform fault analysis.

[0007] The present invention also provides a method for manufacturing a semiconductor device with improved PVC sensitivity.

[0008] The aspects of the present invention are not limited to those set forth herein. These and other aspects of the present invention will become more apparent to one skilled in the art upon reference to the detailed description of the present invention provided below.

[0009] According to one aspect of the present invention, a semiconductor device is provided, the semiconductor device comprising: a semiconductor substrate including a first side and a second side on a side of the semiconductor substrate opposite to the first side; an active pattern on the first side; a gate structure intersecting the active pattern; a source / drain region connected to the active pattern on a side of the gate structure; a front wiring structure connected to at least one of the gate structure and the source / drain region on the first side; a rear wiring structure on the second side; and a contact pattern in the semiconductor substrate, wherein the contact pattern is connected to the rear wiring structure, wherein the height of the contact pattern in a vertical direction intersecting the first side is less than the thickness of the semiconductor substrate in the vertical direction.

[0010] According to one aspect of the present invention, a semiconductor device is provided, the semiconductor device comprising: a semiconductor substrate including a first side and a second side on a side of the semiconductor substrate opposite to the first side; an active pattern on the first side; a gate structure intersecting the active pattern; a source / drain region connected to the active pattern on a side of the gate structure; a front wiring structure connected to the source / drain region on the first side; a contact pattern in the semiconductor substrate, wherein the contact pattern is spaced apart from the gate structure and the source / drain region; a first rear wiring pattern connected to the contact pattern on the second side; a second rear wiring pattern separated from the first rear wiring pattern; and a through-hole extending in a vertical direction and connecting the front wiring structure and the second rear wiring pattern.

[0011] According to one aspect of the present invention, a semiconductor device is provided, comprising a first region and a second region. The semiconductor device includes: a semiconductor substrate including a first side and a second side on a side of the semiconductor substrate opposite to the first side; a first active pattern on the first side of the first region; a first gate structure intersecting the first active pattern; a first source / drain region connected to the first active pattern on a side surface of the first gate structure; a second active pattern on the first side of the second region; a second gate structure intersecting the second active pattern; a second source / drain region connected to the second active pattern on a side surface of the second gate structure; and an interlayer insulating layer covering the first gate structure, the first source / drain region, the second gate structure, and the second source / drain region. An insulating film on a first side; a front wiring structure on an interlayer insulating film; a first rear wiring pattern on a second side of a first region; a second rear wiring pattern on a second side of a second region, the second rear wiring pattern being separate from the first rear wiring pattern; a rear source / drain contact that passes through the semiconductor substrate of the first region and connects the first source / drain region and the first rear wiring pattern; and a contact pattern in the semiconductor substrate of the second region, wherein the contact pattern is connected to the second rear wiring pattern, wherein, in a vertical direction intersecting the first side, a first thickness of the semiconductor substrate of the first region is less than a second thickness of the semiconductor substrate of the second region, and a first height of the rear source / drain contact in the vertical direction is greater than a second height of the contact pattern in the vertical direction. Attached Figure Description

[0012] The above and other aspects and features of the inventive concept will become clearer from the detailed description of exemplary embodiments of the inventive concept with reference to the accompanying drawings, in which: Figure 1 This is a schematic cross-sectional view used to illustrate a semiconductor device according to some embodiments. Figure 2 This is a schematic cross-sectional view used to illustrate a semiconductor device according to some embodiments. Figure 3 This is a schematic cross-sectional view used to illustrate a semiconductor device according to some embodiments. Figure 4 This is a schematic cross-sectional view used to illustrate a semiconductor device according to some embodiments. Figure 5 This is a schematic cross-sectional view used to illustrate a semiconductor device according to some embodiments. Figure 6 This is a schematic cross-sectional view used to illustrate a semiconductor device according to some embodiments. Figure 7 This is a schematic cross-sectional view used to illustrate a semiconductor device according to some embodiments. Figure 8This is a schematic cross-sectional view used to illustrate a semiconductor device according to some embodiments. Figures 9 to 18 This is a diagram illustrating intermediate steps of a method for manufacturing a semiconductor device according to some embodiments. Figures 19 to 21 This is a diagram illustrating intermediate steps of a method for manufacturing a semiconductor device according to some embodiments. Figures 22 to 24 This is a diagram illustrating intermediate steps of a method for manufacturing a semiconductor device according to some embodiments. Detailed Implementation

[0013] It should be understood that although the terms "first," "second," etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. Thus, for example, a first element, first component, or first segment discussed below may be referred to as a second element, second component, or second segment without departing from the teachings of the inventive concept. A first element, component, region, layer, or segment discussed in one part of the specification may be referred to as a second element, component, region, layer, or segment in another part of the specification or in the claims without departing from the teachings of the invention. Furthermore, in some cases, even if the terms "first," "second," etc., are not used in the specification, the terms may still be referred to as "first" or "second" in the claims to distinguish different claimed elements from each other.

[0014] As used herein, the term “semiconductor device” can be, for example, a semiconductor chip (i.e., a semiconductor device that is isolated (e.g., diced) from a wafer).

[0015] For example, as can be seen in the accompanying figures, items described in the singular form herein may be provided in the plural form. Therefore, it should be understood that, unless the context otherwise indicates, the description of a single item provided in the plural form may apply to the remaining multiple items.

[0016] It should be understood that when the terms “comprising” or “including” and / or “containing” are used in this specification, they indicate the presence of the listed features, areas, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, areas, integers, steps, operations, elements, components and / or groups thereof.

[0017] The term “identical” as used herein, when used with reference to orientation, layout, location, shape, size, composition, quantity or other measure, does not necessarily mean exactly the same orientation, layout, location, shape, size, composition, quantity or other measure, but is intended to cover substantially identical orientation, layout, location, shape, size, composition, quantity or other measure within the typical variations that can be caused by conventional manufacturing processes.

[0018] To facilitate the description of the relationship between one element or feature shown in the figure and another, spatial relative terms such as “below,” “under,” “above,” “front,” “front side,” “back,” and “rear side” are used herein. It should be understood that spatial relative terms are intended to cover different orientations of the device in use or operation other than those shown in the figure. For example, if the device in the figure is flipped, an element described as “below” other elements or features would therefore be oriented as “above” other elements or features. Thus, the term “below” can encompass both above and below orientations. The device may adopt other orientations (rotated 90 degrees or facing other directions), and the spatial relative descriptive terms used herein will be interpreted accordingly.

[0019] It should be understood that when a component is referred to as being "connected to" another component or "located on" another component, it may be directly connected to or located on that other component, or there may be intermediate components. Conversely, when a component is referred to as being "directly connected to" another component, or "in contact with" another component (or in any form using the word "in contact"), there are no intermediate components at the point of contact.

[0020] As used herein, the terms “cover” and “cover” are intended to mean that one element is directly above or slightly above another element. An element “covering” another element does not need to cover the entire top surface of the “covered” element below. The term is intended to mean that an element “covers” all or any part of the element below it.

[0021] As used herein, items described as "electrically connected" are configured to allow electrical signals to be transmitted from one item to another. Therefore, passive conductive components (e.g., wires, pads, internal wires, etc.) that are physically connected to passive electrically insulating components (e.g., prepreg layers of printed circuit boards, electrically insulating adhesives connecting two devices, electrically insulating underfill or molding layers, etc.) are not electrically connected to that component. In this specification, although multi-channel MBCFETs are included... TM Examples of electronic components included in a semiconductor device are shown, but these are merely examples. As another example, a semiconductor device may include a tunneling transistor (tunneling FET), a VFET (vertical FET), a CFET (complementary FET), or a three-dimensional (3D) transistor. Alternatively, a semiconductor device may include a bipolar junction transistor, a laterally diffused metal-oxide-semiconductor (LDMOS), etc.

[0022] In the following text, reference will be made to Figures 1 to 8 A semiconductor device according to an exemplary embodiment is described.

[0023] Figure 1This is a schematic cross-sectional view used to illustrate a semiconductor device according to some embodiments.

[0024] Reference Figure 1 According to some embodiments, a semiconductor device includes a first region I and a second region II. The first region I and the second region II may be adjacent to each other or may be separate from each other.

[0025] The first region I can be a region equipped with a backside power delivery network (BSPDN). For example, the first region I can be a cell region in a semiconductor chip that uses the backside power delivery network. The cell region can be a logic cell region or a memory cell region such as a static random access memory (SRAM) cell.

[0026] Region II can be a region equipped with a front-side power delivery network (FSPDN). For example, Region II can be a core region, analog region, and / or input / output region in a semiconductor chip that includes a rear-side power delivery network and uses a front-side power delivery network.

[0027] Additionally, refer to Figure 1 A semiconductor device according to some embodiments includes a semiconductor substrate 100, a first active pattern AP1, a second active pattern AP2, a first gate structure GS1, a second gate structure GS2, a first source / drain region SD1, a second source / drain region SD2, a first interlayer insulating film 190, a second interlayer insulating film 192, a third interlayer insulating film 194, a first source / drain contact FCA1, a first gate contact FCB1, a second source / drain contact FCA2, a second gate contact FCB2, a through-hole TV, a front wiring structure FW, a rear source / drain contact BCA, a rear gate contact BCB, a rear insulating film 300, a first contact pattern CP1, a rear wiring structure BW, and a connection terminal 390.

[0028] Semiconductor substrate 100 may be bulk silicon or silicon-on-insulator (SOI). Alternatively, semiconductor substrate 100 may be a silicon substrate, or may include other materials, such as silicon germanium, silicon germanium-on-insulator (SGOI), indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. In this example, semiconductor substrate 100 may be a substrate on which an epitaxial layer is formed on a base substrate.

[0029] The semiconductor substrate 100 may include a first side 100a and a second side 100b, which are two opposing sides of the semiconductor substrate. In the following description, the first side 100a may be referred to as the front side of the semiconductor substrate 100, and the second side 100b may be referred to as the back side of the semiconductor substrate 100.

[0030] In some embodiments, in the vertical direction Z intersecting the first side 100a, the first thickness T1 of the semiconductor substrate 100 in the first region I may be less than the second thickness T2 of the semiconductor substrate in the second region II. In some embodiments, the second thickness T2 may be about 100 nm or less, or about 90 nm or less, and the first thickness T1 may be less than the second thickness T2. In some embodiments, the second thickness T2 may be less than about 70 nm or less than about 60 nm, and the first thickness T1 may be less than the second thickness T2. For example, the second thickness T2 may be about 50 nm to about 70 nm or about 55 nm to about 65 nm, and the first thickness T1 may be about 1 nm to about 40 nm or about 5 nm to about 35 nm.

[0031] The first active pattern AP1 may be formed on the first side 100a of the first region I. The first active pattern AP1 may extend longitudinally in a first direction X1 parallel to the first side 100a.

[0032] The second active pattern AP2 may be formed on the first side 100a of the second region II. The second active pattern AP2 may extend longitudinally in a second direction X2 parallel to the first side 100a. The second direction X2 may be the same as the first direction X1 or may be a different direction from the first direction X1.

[0033] Each of the first active pattern AP1 and the second active pattern AP2 may include silicon (Si) or germanium (Ge) as an elemental semiconductor material. In the example, each of the first active pattern AP1 and the second active pattern AP2 may include a compound semiconductor, such as a group IV-IV compound semiconductor or a group III-V compound semiconductor. For example, a group IV-IV compound may be a binary compound including at least two of carbon (C), silicon (Si), germanium (Ge), and tin (Sn), or it may be a compound formed by doping these elements with group IV elements. For example, a group III-V compound semiconductor may be one of a binary, ternary, or quaternary compound formed by combining at least one of aluminum (Al), gallium (Ga), and indium (In) as group III elements with at least one of phosphorus (P), arsenic (As), and antimony (Sb) as group V elements.

[0034] In some embodiments, each of the first active pattern AP1 and the second active pattern AP2 may include a plurality of bridge patterns 111 to 113 spaced apart from the first side 100a. The bridge patterns 111 to 113 may be arranged sequentially along a vertical direction Z intersecting the first side 100a and spaced apart from each other. The bridge patterns 111 to 113 may be used as an MBCFET including a multi-bridge channel. TMThe number of bridge patterns 111 to 113 included in each of the first active pattern AP1 and the second active pattern AP2 is merely an example and is not limited to the illustration.

[0035] A first gate structure GS1 may be formed on a first side 100a of the first region I. The first gate structure GS1 may intersect with a first active pattern AP1. For example, the first gate structure GS1 may be parallel to the first side 100a and extend longitudinally in a third direction Y1 intersecting the first direction X1. In some embodiments, bridge patterns 111 to 113 of the first active pattern AP1 may extend in the first direction X1 and pass through the first gate structure GS1.

[0036] A second gate structure GS2 may be formed on a first side 100a of the second region II. The second gate structure GS2 may intersect with the second active pattern AP2. For example, the second gate structure GS2 may be parallel to the first side 100a and extend longitudinally in a fourth direction Y2 that intersects with the second direction X2. In some embodiments, bridge patterns 111 to 113 of the second active pattern AP2 may extend in the second direction X2 and pass through the second gate structure GS2.

[0037] In some embodiments, each of the first gate structure GS1 and the second gate structure GS2 may include a gate dielectric film 120, a gate electrode 130, a gate spacer 140, and a gate capping film 150.

[0038] The gate dielectric film 120 may be stacked on the semiconductor substrate 100, the first active pattern AP1, and the second active pattern AP2. The gate dielectric film 120 may be located between the semiconductor substrate 100 and the gate electrode 130, between the first active pattern AP1 and the gate electrode 130, and between the second active pattern AP2 and the gate electrode 130.

[0039] The gate dielectric film 120 may include a dielectric material, such as at least one of silicon oxide, silicon oxynitride, silicon nitride, and a high dielectric constant material having a higher dielectric constant than silicon oxide. For example, the high dielectric constant material may include (but is not limited to) hafnium oxide (HfO2), zirconium oxide (ZrO2), lanthanum oxide (La2O3), aluminum oxide (Al2O3), titanium oxide (TiO2), strontium titanium oxide (SrTiO3), lanthanum aluminum oxide (LaAlO3), yttrium oxide (Y2O3), and hafnium oxynitride (HfO2). x N y Zirconium oxynitride (ZrO) x N y ), Lanthanum oxide (La2O) x N y ), aluminum oxide (Al2O) x N y), titanium oxynitride (TiO2) x N y ), SrTiO2 x N y ), Lanthanum aluminum oxynitride (LaAlO) x N y ), Yttrium oxynitride (Y2O) x N y ( ) and at least one of their combinations.

[0040] The gate electrode 130 may intersect with the first active pattern AP1 and the second active pattern AP2. Each of the bridge patterns 111 to 113 of the first active pattern AP1 may extend in the first direction X1 and pass through the gate electrode 130 of the first gate structure GS1. Each of the bridge patterns 111 to 113 of the second active pattern AP2 may extend in the second direction X2 and pass through the gate electrode 130 of the second gate structure GS2.

[0041] The gate electrode 130 may comprise at least one of the following conductive materials: such as (but not limited to) TiN, WN, TaN, Ru, TiC, TaC, Ti, Ag, Al, TiAl, TiAlN, TiAlC, TaCN, TaSiN, Mn, Zr, W, Al, and combinations thereof. The gate electrode 130 may be formed by (but not limited to) a substitution process.

[0042] Although the gate electrode 130 is shown as a single film, this is merely an example, and the gate electrode 130 can of course be a multilayer film formed by stacking multiple conductive films. The gate electrode 130 may include, for example, a work function adjustment film for adjusting the work function and a filling conductive film to fill the space formed by the work function adjustment film. For example, the work function adjustment film may include at least one of TiN, TaN, TiC, TaC, TiAlC, and combinations thereof. For example, the filling conductive film may include W or Al.

[0043] Gate spacer 140 may extend along the side of gate electrode 130. Each of bridge patterns 111 to 113 of the first active pattern AP1 may extend in a first direction X1 and pass through gate spacer 140 of the first gate structure GS1. Each of bridge patterns 111 to 113 of the second active pattern AP2 may extend in a second direction X2 and pass through gate spacer 140 of the second gate structure GS2. Gate spacer 140 may include an insulating material, such as (but not limited to) at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon boron nitride, silicon boron carbonitride, silicon oxycarbide, and combinations thereof.

[0044] The gate capping film 150 may extend along the upper side of the gate electrode 130. The gate capping film 150 may include an insulating material, such as (but not limited to) at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon boron nitride, silicon boron carbonitride, silicon oxycarbide, and combinations thereof.

[0045] In some embodiments, each of the first gate structure GS1 and the second gate structure GS2 may further include an inner spacer 145. The inner spacer 145 may be formed on the side surface of the gate electrode 130 between bridge patterns 111 to 113. The inner spacer 145 may be formed on the side surface of the gate electrode 130 between the fin pattern 110 and the bridge patterns 111 to 113. The inner spacer 145 may include an insulating material, such as (but not limited to) at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon boron nitride, silicon boron carbonitride, silicon oxycarbide, and combinations thereof. In some embodiments, the inner spacer 145 may be omitted.

[0046] The first source / drain region SD1 may be formed on the first side 100a of the first region I. The first source / drain region SD1 may be formed on at least one side (e.g., both sides) of the first gate structure GS1. The first source / drain region SD1 may be connected to the first active pattern AP1. For example, each of the bridge patterns 111 to 113 of the first active pattern AP1 may pass through the first gate structure GS1 and be connected to the first source / drain region SD1. The first source / drain region SD1 may be separated from the gate electrode 130 of the first gate structure GS1 by the gate dielectric film 120, the gate spacer 140 and / or the inner spacer 145.

[0047] In some embodiments, the first source / drain region SD1 may include an epitaxial layer. For example, the first source / drain region SD1 may include an epitaxial pattern grown from the semiconductor substrate 100 and / or the first active pattern AP1 of the first region I by an epitaxial growth method.

[0048] The second source / drain region SD2 may be formed on the first side 100a of the second region II. The second source / drain region SD2 may be formed on at least one side (e.g., both sides) of the second gate structure GS2. The second source / drain region SD2 may be connected to the second active pattern AP2. For example, each of the bridge patterns 111 to 113 of the second active pattern AP2 may pass through the second gate structure GS2 and be connected to the second source / drain region SD2. The second source / drain region SD2 may be separated from the gate electrode 130 of the second gate structure GS2 through the gate dielectric film 120, the gate spacer 140, and / or the inner spacer 145.

[0049] In some embodiments, the second source / drain region SD2 may include an epitaxial layer. For example, the second source / drain region SD2 may include an epitaxial pattern grown from the semiconductor substrate 100 and / or the second active pattern AP2 of the second region II by an epitaxial growth method.

[0050] The first source / drain region SD1 and the second source / drain region SD2 may have the same or different conductivity types. When the first source / drain region SD1 and / or the second source / drain region SD2 are configured as the source / drain regions of an NFET, each of the first source / drain region SD1 and / or the second source / drain region SD2 may include an N-type impurity (e.g., P, Sb, or As) or an impurity for preventing the diffusion of N-type impurities. When the first source / drain region SD1 and / or the second source / drain region SD2 are configured as the source / drain regions of a PFET, each of the first source / drain region SD1 and / or the second source / drain region SD2 may include a P-type impurity (e.g., B, In, Ga, or Al) or an impurity for preventing the diffusion of P-type impurities.

[0051] The first interlayer insulating film 190 can fill the space on the side of the first gate structure GS1 and the side of the second gate structure GS2. The first interlayer insulating film 190 can cover the first source / drain region SD1 and the second source / drain region SD2. The second interlayer insulating film 192 can be formed on the first gate structure GS1, the second gate structure GS2 and the first interlayer insulating film 190. The third interlayer insulating film 194 can be formed on the second interlayer insulating film 192.

[0052] For example, the first interlayer insulating film 190, the second interlayer insulating film 192, and the third interlayer insulating film 194 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonate, boron silicon nitride, boron silicon carbonitride, silicon carbonitride, and a low dielectric constant material having a dielectric constant smaller than that of silicon oxide. The low dielectric constant material may include, for example (but not limited to), FOX (flowable oxide), TOSZ (Torene SilaZene), USG (undoped silicate glass), BSG (borosilicate glass), PSG (phosphosilicate glass), BPSG (borophosphosilicate glass), PETEOS (plasma-enhanced tetraethyl orthosilicate), FSG (fluorosilicate glass), CDO (carbon-doped silicon oxide), degelatin, aerogel, amorphous fluorinated carbon, OSG (organosilicon glass), parylene, BCB (bisbenzocyclobutene), SiLK, polyimide, porous polymer materials, and combinations thereof.

[0053] A first source / drain contact FCA1 may be formed on the upper side of the first source / drain region SD1. The first source / drain contact FCA1 may be connected to the first source / drain region SD1. For example, the first source / drain contact FCA1 may pass through the first interlayer insulating film 190 and the second interlayer insulating film 192 and contact the upper side of the first source / drain region SD1.

[0054] The second source / drain contact FCA2 may be formed on the upper side of the second source / drain region SD2. The second source / drain contact FCA2 may be connected to the second source / drain region SD2. For example, the second source / drain contact FCA2 may pass through the first interlayer insulating film 190 and the second interlayer insulating film 192 and contact the upper side of the second source / drain region SD2.

[0055] A first gate contact FCB1 may be formed on the upper side of the first gate structure GS1. The first gate contact FCB1 may be connected to the gate electrode 130 of the first gate structure GS1. For example, the first gate contact FCB1 may pass through the gate capping film 150, the second interlayer insulating film 192 and the third interlayer insulating film 194 of the first gate structure GS1, and contact the upper side of the gate electrode 130 of the first gate structure GS1.

[0056] The second gate contact FCB2 may be formed on the upper side of the second gate structure GS2. The second gate contact FCB2 may be connected to the gate electrode 130 of the second gate structure GS2. For example, the second gate contact FCB2 may pass through the gate capping film 150, the second interlayer insulating film 192 and the third interlayer insulating film 194 of the second gate structure GS2, and contact the upper side of the gate electrode 130 of the second gate structure GS2.

[0057] The through-hole element TV may extend in the vertical direction Z. The through-hole element TV may pass through the semiconductor substrate 100 of the second region II. For example, a field insulating film 105 may be formed covering at least a portion of the side surface of the semiconductor substrate 100 of the second region II. The through-hole element TV may extend in the vertical direction Z and pass through the field insulating film 105, the first interlayer insulating film 190, the second interlayer insulating film 192, and the third interlayer insulating film 194.

[0058] Each of the first source / drain contact FCA1, the first gate contact FCB1, the second source / drain contact FCA2, the second gate contact FCB2, and the through-hole TV may include at least one conductive material, such as (but not limited to) at least one of the following: metals (such as cobalt (Co), titanium (Ti), tantalum (Ta), ruthenium (Ru), tungsten (W), or cobalt tungsten phosphide (CoWP)), conductive metal nitrides (such as titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN)) and / or silicides (such as nickel silicide (NiSi), cobalt silicide (CoSi), tungsten silicide (WSi), titanium silicide (TiSi), niobium silicide (NbSi), or tantalum silicide (TaSi)).

[0059] The front wiring structure FW can be formed on the first side 100a of the first region I and the second region II. For example, the front wiring structure FW can be formed on the third interlayer insulating film 194. The front wiring structure FW may include a front interlayer insulating film 210, front wiring patterns F1 to F3, and a front through-hole pattern FV. The front wiring patterns F1 to F3 can form a multilayer wiring structure in the front interlayer insulating film 210. The front through-hole pattern FV can interconnect the front wiring patterns F1 to F3 in the vertical direction Z. The number, quantity, and arrangement of the front interlayer insulating film 210, the front wiring patterns F1 to F3, and the front through-hole pattern FV are merely exemplary and are not limited to the number, quantity, and arrangement shown in the figures.

[0060] The front wiring structure FW can be electrically connected to the first source / drain region SD1, the first gate structure GS1, the second source / drain region SD2, and / or the second gate structure GS2. For example, the front wiring patterns F1 to F3 and / or the front through-hole pattern FV can be electrically connected to the first source / drain contact FCA1, the first gate contact FCB1, the second source / drain contact FCA2, and / or the second gate contact FCB2.

[0061] In some embodiments, a first through-hole contact 195 may be formed through the third interlayer insulating film 194. Each of the first source / drain contact FCA1 and / or the second source / drain contact FCA2 may be connected to one of the lower front wiring patterns F1 via the first through-hole contact 195.

[0062] In some embodiments, each of the first gate contact FCB1 and / or the second gate contact FCB2 may be connected to the corresponding lower front wiring pattern F1.

[0063] In some embodiments, the front wiring structure FW can provide a power delivery network for the second region II. For example, the front wiring patterns F1 to F3 of the second region II may include a first front wiring pattern 221. The first front wiring pattern 221 may be connected to the second source / drain region SD2. The first front wiring pattern 221 may be configured to be supplied with a power supply voltage (e.g., V). DD or V SS The power supply wiring of the semiconductor device in the second region II is formed on the first side 100a of the second region II. Therefore, the first front wiring pattern 221 can form a front power delivery network (FSPDN) that provides power supply voltage to the semiconductor device in the second region II.

[0064] In some embodiments, the front wiring structure FW of the second region II may be connected to the pass-through element TV. For example, the pass-through element TV may be connected to the first front wiring pattern 221. The first front wiring pattern 221 may electrically connect the second source / drain region SD2 to the pass-through element TV.

[0065] A rear source / drain contact BCA may be formed on the underside of the first source / drain region SD1. The rear source / drain contact BCA may be connected to the first source / drain region SD1. In some embodiments, the first height D11 of the rear source / drain contact BCA in the vertical direction Z may be equal to or greater than the first distance H1 between the first source / drain region SD1 and the second side 100b of the first region I in the vertical direction Z. The rear source / drain contact BCA may pass through the semiconductor substrate 100 of the first region I and contact the underside of the first source / drain region SD1.

[0066] A rear gate contact BCB may be formed on the lower side of the first gate structure GS1. The rear gate contact BCB may be connected to the gate electrode 130 of the first gate structure GS1. In some embodiments, the second height D21 of the rear gate contact BCB in the vertical direction Z may be greater than the first thickness T1 of the semiconductor substrate 100 of the first region I. The rear gate contact BCB may pass through the semiconductor substrate 100 of the first region I and the gate dielectric film 120 of the first gate structure GS1, and contact the lower side of the gate electrode 130 of the first gate structure GS1.

[0067] For example, the rear gate contact BCB may pass through the semiconductor substrate 100 of the first region I and contact the lower side of the gate electrode 130 of the first gate structure GS1. In some embodiments, the rear gate contact BCB may be omitted.

[0068] The rear source / drain contact BCA and the rear gate contact BCB may each include a conductive material, such as (but not limited to) at least one of the following: metals (such as cobalt (Co), titanium (Ti), tantalum (Ta), ruthenium (Ru), tungsten (W) or cobalt tungsten phosphide (CoWP)), conductive metal nitrides (such as titanium nitride (TiN), tantalum nitride (TaN) or tungsten nitride (WN)) and / or silicides (such as nickel silicide (NiSi), cobalt silicide (CoSi), tungsten silicide (WSi), titanium silicide (TiSi), niobium silicide (NbSi) or tantalum silicide (TaSi)).

[0069] The back insulating film 300 may be formed on the second side 100b of the semiconductor substrate 100 in the first region I. Although the thickness of the back insulating film 300 is shown to be the same as the difference between the first thickness T1 and the second thickness T2, this is only an example. Unlike the example shown, the thickness of the back insulating film 300 may be greater than or less than the difference between the first thickness T1 and the second thickness T2.

[0070] The back insulating film 300 may include, for example (but not limited to), at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, boron silicon nitride, boron silicon carbonitride, silicon carbonitride, and a low dielectric constant material having a dielectric constant smaller than that of silicon oxide.

[0071] A first contact pattern CP1 may be formed in the semiconductor substrate 100 of the second region II. The first contact pattern CP1 may be connected to the semiconductor substrate 100 of the second region II. The first contact pattern CP1 may be in contact with the second side 100b. For example, the first contact pattern CP1 may extend from the second side 100b toward the first side 100a in the vertical direction Z.

[0072] In some embodiments, the first contact pattern CP1 may be spaced apart from the first side 100a. For example, the third height D12 of the first contact pattern CP1 in the vertical direction Z may be less than the second thickness T2 of the semiconductor substrate 100 in the second region II.

[0073] In some embodiments, the first contact pattern CP1 may be formed at the same level as the downstream source / drain contact BCA. In this specification, "at the same level" means formed using the same manufacturing process. For example, the downstream source / drain contact BCA and the first contact pattern CP1 may comprise the same material or have the same material composition.

[0074] In some embodiments, the first contact pattern CP1 may overlap with the second source / drain region SD2 in the vertical direction Z. The first contact pattern CP1 may be spaced apart from the second source / drain region SD2 in the vertical direction Z.

[0075] In some embodiments, the third height D12 of the first contact pattern CP1 may be less than the first height D11 of the subsequent source / drain contact BCA. This may be due to the thickness difference between the semiconductor substrate 100 of the first region I and the semiconductor substrate 100 of the second region II in the etching process used to form the subsequent source / drain contact BCA and the first contact pattern CP1.

[0076] The back wiring structure BW can be formed on the second side 100b of the first region I and the second region II. For example, the back wiring structure BW can be formed below the back insulating film 300 and the semiconductor substrate 100 in the second region II. The back wiring structure BW may include a back wiring inter-insulating film 310, back wiring patterns B1 to B3, and a back through-hole pattern BV. The back wiring patterns B1 to B3 can form a multilayer wiring structure in the back wiring inter-insulating film 310. The back through-hole pattern BV can be interconnected with the back wiring patterns B1 to B3 in the vertical direction Z. The number, quantity, and arrangement of the back surface inter-insulating film 310, the back surface wiring patterns B1 to B3, and the back surface through-hole pattern BV are only examples and are not limited to the number, quantity, and arrangement shown in the figures.

[0077] The rear wiring structure BW can be electrically connected to the first source / drain region SD1 and / or the first gate structure GS1. For example, the rear wiring patterns B1 to B3 and / or the rear through-hole pattern BV can be electrically connected to the rear source / drain contact BCA and / or the rear gate contact BCB.

[0078] In some embodiments, a second through-hole contact 305 may be formed through the rear insulating film 300. The rear source / drain contact BCA and / or the rear gate contact BCB may each be connected to one of the lower rear wiring patterns B1 via the second through-hole contact 305.

[0079] In some embodiments, the back wiring structure BW can provide a power delivery network for the first region I. For example, the back wiring patterns B1 to B3 of the first region I may include a first back wiring pattern 321. The first back wiring pattern 321 may be connected to the first source / drain region SD1. The first back wiring pattern 321 may be configured to be supplied with a power supply voltage (e.g., V). DD or V SS The power supply wiring of the semiconductor device in the first region I is thus formed on the second side 100b of the first region I. Therefore, the first back wiring pattern 321 can form a backside power delivery network (BSPDN) that supplies power voltage to the semiconductor device in the first region I.

[0080] In some embodiments, the rear wiring structure BW may be connected to the through-hole TV. For example, the rear wiring patterns B1 to B3 of the second region II may include a second rear wiring pattern 322. The second rear wiring pattern 322 may be connected to the through-hole TV. The through-hole TV may extend in the vertical direction Z to electrically connect the first front wiring pattern 221 and the second rear wiring pattern 322. Although the second rear wiring pattern 322 is shown in contact with the through-hole TV, this is only an example. Unlike the example shown, some of the rear through-hole patterns BV may be located between the through-hole TV and the second rear wiring pattern 322.

[0081] The rear wiring structure BW can be connected to the first contact pattern CP1. For example, the rear wiring patterns B1 to B3 of the second region II may include a third rear wiring pattern 323. The third rear wiring pattern 323 can be connected to the first contact pattern CP1. Although the third rear wiring pattern 323 is shown in contact with the first contact pattern CP1, this is only an example. Unlike the example shown, some of the rear through-hole patterns BV may be located between the first contact pattern CP1 and the third rear wiring pattern 323.

[0082] The third rear wiring pattern 323 may not provide a power transmission network for the second zone II. For example, the third rear wiring pattern 323 may be electrically isolated from the first rear wiring pattern 321 and the second rear wiring pattern 322 that provide a power transmission network.

[0083] In some embodiments, the first contact pattern CP1 and the third back wiring pattern 323 may be electrically floated.

[0084] Connection terminals 390 may be formed on the second side 100b of the first region I and the second region II. For example, connection terminals 390 may be formed below the rear wiring inter-insulation film 310. Connection terminals 390 may be electrically connected to the rear wiring structure BW. For example, connection terminals 390 may be connected to the upper rear wiring pattern B3 through some of the rear through-hole pattern BV. More than one connection terminal 390 may exist, including a first connection terminal, a second connection terminal, etc.

[0085] The connection terminal 390 can be, for example (but not limited to), solder balls, bumps, etc. Semiconductor devices in Region I and Region II can be electrically connected to external electronic devices, etc., via the connection terminal 390. For example, the power supply voltage (e.g., V...) DD or V SS The first source / drain region SD1 can be applied through the connection terminal 390 of the first region I, the first rear wiring pattern 321, and the rear source / drain contact BCA. For example, the power supply voltage (e.g., V) DD or V SSThe second source / drain region SD2 can be applied through the second region II connection terminal 390, the second rear wiring pattern 322, the through-hole TV, the first front wiring pattern 221, and the second source / drain contact FCA2.

[0086] To reduce the voltage drop (e.g., IR drop) of the power delivery network (PDN) associated with the high integration of semiconductor devices, so-called back-side power delivery networks (BSPDNs) have been investigated, which place the power delivery network on the back side of the semiconductor substrate. With advancements in processes for back-side power delivery networks, the thickness of semiconductor substrates continues to decrease, leading to reduced detection power for fault analysis such as PVC (passive voltage contrast). For example, in semiconductor chips that include a back-side power delivery network, some regions, such as the core region (hereinafter, FSPDN region), can still utilize the front-side power delivery network. However, as the thickness of the semiconductor substrate is reduced through thinning processes on the back side of the semiconductor substrate (e.g., to 100 nm or less, or 70 nm or less), the amount of electrons supplied from the semiconductor substrate decreases, and the sensitivity of PVC to the FSPDN region decreases.

[0087] Conversely, according to some embodiments, a semiconductor device may utilize a first contact pattern CP1 and a back wiring structure BW connected to the first contact pattern CP1 to improve the sensitivity of the PVC to the FSPDN region. Specifically, as described above, the first contact pattern CP1 may be connected to a semiconductor substrate 100 that is a second region II designated as an FSPDN region, and the back wiring structure BW of the second region II may include a third back wiring pattern 323 connected to the first contact pattern CP1. The first contact pattern CP1 and the third back wiring pattern 323 may compensate for the second thickness T2 of the semiconductor substrate 100 of the second region II (e.g., reduced to 100 nm or less or 70 nm or less), and supply an additional amount of electrons to the semiconductor substrate 100 of the second region II. Therefore, the sensitivity of the PVC to the FSPDN region is improved, and a semiconductor device that facilitates defect analysis can be provided. The thickness of the layer may refer to the dimension in a direction perpendicular to the surface of the layer. The direction perpendicular to the surface may refer to its average orientation and does not include the smallest unintended deviations (e.g., pits) that may form during the manufacturing process.

[0088] Figure 2 This is a schematic cross-sectional view used to illustrate a semiconductor device according to some embodiments. For ease of explanation, the above utilizes... Figure 1 Repeated portions of the description may be the same as those described herein, and such repeated portions will be briefly explained or omitted.

[0089] Reference Figure 2 According to some embodiments, the semiconductor device includes a second contact pattern CP2.

[0090] The second contact pattern CP2 may be formed in the semiconductor substrate 100 of the second region II. The second contact pattern CP2 may be connected to the semiconductor substrate 100 of the second region II. The second contact pattern CP2 may be in contact with the second side 100b. For example, the second contact pattern CP2 may extend from the second side 100b toward the first side 100a in the vertical direction Z.

[0091] In some embodiments, the second contact pattern CP2 may be formed at the same level as the rear gate contact BCB. For example, the rear gate contact BCB and the second contact pattern CP2 may comprise the same material or have the same material composition.

[0092] In some embodiments, the second contact pattern CP2 may overlap with the second gate structure GS2 in the vertical direction Z. The second contact pattern CP2 may also be spaced apart from the second gate structure GS2 in the vertical direction Z.

[0093] In some embodiments, the fourth height D22 of the second contact pattern CP2 in the vertical direction Z may be smaller than the second height D21 of the rear gate contact BCB in the vertical direction Z. This may be due to the thickness difference between the semiconductor substrate 100 of the first region I and the semiconductor substrate 100 of the second region II during the etching process for forming the rear gate contact BCB and the second contact pattern CP2.

[0094] Figure 3 This is a schematic cross-sectional view used to illustrate a semiconductor device according to some embodiments. For ease of explanation, the above utilizes... Figure 1 and Figure 2 Repeated portions of the description may be identical to those described herein and will be simply described or omitted.

[0095] Reference Figure 3 According to some embodiments, the semiconductor device includes both a first contact pattern CP1 and a second contact pattern CP2.

[0096] Because the first contact pattern CP1 can be used in conjunction with the above. Figure 1 The first contact pattern CP1 is identical to the one described above, and the second contact pattern CP2 can be used in conjunction with the above. Figure 2 The second contact pattern CP2 is the same as described below, and its detailed description will not be provided below.

[0097] In some embodiments, the first contact pattern CP1 and the second contact pattern CP2 may be electrically connected. For example, the first contact pattern CP1 and the second contact pattern CP2 may be electrically connected via rear wiring patterns B1 to B3 and a rear through-hole pattern BV.

[0098] Figure 4This is a schematic cross-sectional view used to illustrate a semiconductor device according to some embodiments. For ease of explanation, the above utilizes... Figures 1 to 3 Repeated portions of the description may be identical to those described herein, and such repeated portions will be briefly explained or omitted.

[0099] Reference Figure 4 According to some embodiments, the semiconductor device includes a third contact pattern CP3.

[0100] A third contact pattern CP3 may be formed in the semiconductor substrate 100 of the second region II. The third contact pattern CP3 may be connected to the semiconductor substrate 100 of the second region II. The third contact pattern CP3 may be in contact with the second side 100b. For example, the third contact pattern CP3 may extend from the second side 100b toward the first side 100a in the vertical direction Z.

[0101] In some embodiments, the third contact pattern CP3 may be formed at the same level as the second through-hole contact 305. For example, the second through-hole contact 305 and the third contact pattern CP3 may be made of the same material or have the same material composition.

[0102] Although the third contact pattern CP3 is shown to overlap with the second source / drain region SD2 in the vertical direction Z, this is merely an example. Unlike the example shown, the third contact pattern CP3 may overlap with the second gate structure GS2 in the vertical direction Z. The third contact pattern CP3 may also be spaced apart from the second source / drain region SD2 and / or the second gate structure GS2 in the vertical direction Z.

[0103] In some embodiments, the fifth height D31 of the second through-hole contact 305 in the vertical direction Z may differ from the sixth height D32 of the third contact pattern CP3 in the vertical direction Z. For example, as shown, the fifth height D31 may be greater than the sixth height D32. This is due to the difference in etching selectivity between the back insulating film 300 and the semiconductor substrate 100 during the etching process used to form the second through-hole contact 305 and the third contact pattern CP3.

[0104] Figure 5 This is a schematic cross-sectional view used to illustrate a semiconductor device according to some embodiments. For ease of explanation, the above utilizes... Figures 1 to 4 Repeated portions of the description may be identical to those described herein, and such repeated portions will be briefly explained or omitted.

[0105] Reference Figure 5 In a semiconductor device according to some embodiments, a first contact pattern CP1 is electrically connected to a connection terminal 390.

[0106] For example, the upper rear wiring pattern B3 of the second region II may include a fourth rear wiring pattern 341 electrically connected to the third rear wiring pattern 323. Some of the rear through-hole patterns BV may connect a portion of the connection terminal 390 to the fourth rear wiring pattern 341. A predetermined bias voltage (e.g., ground voltage or negative (-) voltage) may be applied to the semiconductor substrate 100 of the second region II from an external electronic device or the like through the connection terminal 390. For example, the predetermined bias voltage may be applied to the semiconductor substrate 100 of the second region II through the connection terminal 390, the fourth rear wiring pattern 341, the third rear wiring pattern 323, and the first contact pattern CP1.

[0107] Figure 6 This is a schematic cross-sectional view used to illustrate a semiconductor device according to some embodiments. For ease of explanation, the above utilizes... Figures 1 to 5 Repeated portions of the description may be identical to those described herein, and such repeated portions will be briefly explained or omitted.

[0108] Reference Figure 6 In a semiconductor device according to some embodiments, the rear source / drain contact BCA and / or the rear gate contact BCB pass through the rear insulating film 300 and the semiconductor substrate 100.

[0109] For example, the rear source / drain contact BCA can pass through the rear insulating film 300 and the semiconductor substrate 100 of the first region I to connect one of the lower rear wiring patterns B1 to the first source / drain region SD1.

[0110] Alternatively, for example, the rear gate contact BCB may pass through the rear insulating film 300, the semiconductor substrate 100 of the first region I, and the gate dielectric film 120 of the first gate structure GS1 to connect another of the lower rear wiring patterns B1 to the gate electrode 130 of the first gate structure GS1.

[0111] In some embodiments, the third height D12 of the first contact pattern CP1 in the vertical direction Z may be less than the first height D11 of the subsequent source / drain contact BCA in the vertical direction Z.

[0112] In some embodiments, the fourth height D22 of the second contact pattern CP2 in the vertical direction Z may be smaller than the second height D21 of the rear gate contact BCB in the vertical direction Z.

[0113] Figure 7 This is a schematic cross-sectional view used to illustrate a semiconductor device according to some embodiments. For ease of explanation, the above utilizes... Figures 1 to 6 The repeated portions of the description may be the same as those described herein, and the repeated content will be briefly explained or omitted.

[0114] Reference Figure 7The semiconductor device according to some embodiments includes an insulating substrate 102.

[0115] An insulating substrate 102 may be disposed in a first region I. A semiconductor substrate 100 may be disposed in a second region II, or may not be disposed in the first region I. The insulating substrate 102 may include (but is not limited to) at least one of silicon oxide, silicon oxynitride, silicon carbonitride, and combinations thereof. As an example, the insulating substrate 102 may include a silicon oxide film.

[0116] An insulating substrate 102 may be located between the back wiring structure BW and the first source / drain region SD1 of the first region I, and between the back wiring structure BW and the first gate structure GS1 of the first region I. For example, the insulating substrate 102 may include a third side 102a and a fourth side 102b opposite to each other. The first source / drain region SD1 and the first gate structure GS1 may be formed on the third side 102a. The back wiring structure BW of the first region I may be formed on the fourth side 102b.

[0117] Although the third thickness T3 of the insulating substrate 102 in the vertical direction Z is shown to be the same as the second thickness T2 of the semiconductor substrate 100 in the vertical direction Z of the second region II, this is merely an example. Unlike the example shown, the third thickness T3 may of course be greater than or less than the second thickness T2.

[0118] Each of the rear source / drain contact BCA and / or the rear gate contact BCB may extend in the vertical direction Z and pass through the insulating substrate 102. For example, the rear source / drain contact BCA may pass through the insulating substrate 102 to connect one of the lower rear wiring patterns B1 to the first source / drain region SD1. Alternatively, for example, the rear gate contact BCB may pass through the insulating substrate 102 and the gate dielectric film 120 and connect the other of the lower rear wiring patterns B1 to the gate electrode 130 of the first gate structure GS1.

[0119] Figure 8 This is a schematic cross-sectional view used to illustrate a semiconductor device according to some embodiments. For ease of explanation, the above utilizes... Figures 1 to 6 Repeated portions of the description may be identical to those described herein, and such repeated portions will be briefly explained or omitted.

[0120] Reference Figure 8 The semiconductor device according to some embodiments includes a base insulating film 302, a conductive plate 304, and an insulating isolation pattern 306.

[0121] A base insulating film 302 may be formed on the second side 100b of the semiconductor substrate 100 in the first region I. The base insulating film 302 may be located between the semiconductor substrate 100 in the first region I and the conductive plate 304. The rear source / drain contact BCA may pass through the base insulating film 302 and the semiconductor substrate 100 in the first region I and be connected to the first source / drain region SD1.

[0122] A conductive plate 304 may be formed beneath the base insulating film 302. The conductive plate 304 may be positioned between the rear source / drain contact BCA and the rear wiring structure BW. The rear source / drain contact BCA can be electrically connected to the rear wiring structure BW via the conductive plate 304. For example, a first rear wiring pattern 321 may be connected to the conductive plate 304.

[0123] The isolation insulating pattern 306 may be located between the first gate structure GS1 and the rear wiring structure BW. The isolation insulating pattern 306 may overlap with the first gate structure GS1 in the vertical direction Z. The isolation insulating pattern 306 may extend in the vertical direction Z to cut the conductive plate 304, the basic insulating film 302 and the semiconductor substrate 100 of the first region I.

[0124] The insulating pattern 306 may include (but is not limited to) at least one of silicon nitride, silicon oxynitride, silicon oxycarbide, boron silicon nitride, boron silicon carbonitride, silicon carbonitride, and combinations thereof.

[0125] In the following text, reference will be made to Figures 1 to 24 A method for manufacturing a semiconductor device according to an exemplary embodiment is described.

[0126] Figures 9 to 18 This is a diagram illustrating intermediate steps in a method for manufacturing a semiconductor device according to some embodiments. For ease of description, the above utilizes... Figures 1 to 8 Repeated portions of the description may be identical to those described herein and will be simply described or omitted.

[0127] Reference Figure 9 A first active pattern AP1, a second active pattern AP2, a first gate structure GS1, a second gate structure GS2, a first source / drain region SD1, a second source / drain region SD2, and a first interlayer insulating film 190 are formed on a semiconductor substrate 100 and a field insulating film 105.

[0128] A first active pattern AP1 may be formed on a first side 100a of the first region I. A second active pattern AP2 may be formed on a first side 100a of the second region II. A first gate structure GS1 may intersect with the first active pattern AP1. A second gate structure GS2 may intersect with the second active pattern AP2. A first source / drain region SD1 is formed on at least one side (e.g., both sides) of the first gate structure GS1 and may be connected to the first active pattern AP1. A second source / drain region SD2 is formed on at least one side (e.g., both sides) of the second gate structure GS2 and may be connected to the second active pattern AP2. A first interlayer insulating film 190 may fill the space on the side of the first gate structure GS1 and the side of the second gate structure GS2. The first interlayer insulating film 190 may cover the first source / drain region SD1 and the second source / drain region SD2.

[0129] Reference Figure 10 This forms a first source / drain contact FCA1, a first gate contact FCB1, a second source / drain contact FCA2, a second gate contact FCB2, and a through-hole TV.

[0130] For example, a second interlayer insulating film 192 may be formed on the first interlayer insulating film 190. A first source / drain contact FCA1 may pass through the first interlayer insulating film 190 and the second interlayer insulating film 192 and is connected to the first source / drain region SD1. A second source / drain contact FCA2 may pass through the first interlayer insulating film 190 and the second interlayer insulating film 192 and is connected to the second source / drain region SD2.

[0131] Next, a third interlayer insulating film 194 can be formed on the second interlayer insulating film 192. The first gate contact FCB1 can pass through the gate capping film 150, the second interlayer insulating film 192, and the third interlayer insulating film 194, and is connected to the gate electrode 130 of the first gate structure GS1. The second gate contact FCB2 can pass through the gate capping film 150, the second interlayer insulating film 192, and the third interlayer insulating film 194, and is connected to the gate electrode 130 of the second gate structure GS2. The through-hole member TV can extend in the vertical direction Z and pass through the field insulating film 105, the first interlayer insulating film 190, the second interlayer insulating film 192, and the third interlayer insulating film 194.

[0132] Reference Figure 11 This forms the front wiring structure (FW).

[0133] A front wiring structure FW can be formed on the third interlayer insulating film 194. The front wiring structure FW can be electrically connected to the first source / drain contact FCA1, the first gate contact FCB1, the second source / drain contact FCA2, the second gate contact FCB2 and / or the through-hole TV.

[0134] Reference Figure 12 The front wiring structure (FW) is attached to the carrier substrate 400.

[0135] For example, the carrier substrate 400 can be attached to Figure 11 The resulting structure. After attaching the carrier substrate 400, the structure can be... Figure 11 The resulting structure is flipped. For example, as... Figure 12 As shown, the second side 100b of the semiconductor substrate 100 may face upwards. In some embodiments, the front wiring structure FW may be attached to the carrier substrate 400 via an oxide-oxide bonding process.

[0136] Reference Figure 13 A thinning process is performed on the semiconductor substrate 100.

[0137] For example, a post-grinding process can be performed on the second side 100b of the semiconductor substrate 100. As the thinning process is performed, the thickness of the semiconductor substrate 100 can be reduced. In some embodiments, after performing the thinning process, the thickness of the semiconductor substrate 100 can be about 100 nm or less, or about 70 nm or less. For example, after performing the thinning process, the thickness of the semiconductor substrate 100 can be about 50 nm to about 70 nm, or about 55 nm to about 65 nm.

[0138] Reference Figure 14 A recessed process is performed on the semiconductor substrate 100 in the first region I.

[0139] For example, a mask pattern MP can be formed on the second side 100b of the semiconductor substrate 100 in the second region II. The mask pattern MP may include (but is not limited to) a photoresist pattern. Then, an etching process can be performed on the second side 100b of the semiconductor substrate 100 in the first region I by using the mask pattern MP as an etching mask. As the etching process is performed, the first thickness T1 of the semiconductor substrate 100 in the first region I in the vertical direction Z may be less than the second thickness T2 of the semiconductor substrate 100 in the vertical direction Z of the second region II. For example, after the etching process, the second thickness T2 may be about 50 nm to about 70 nm, or about 55 nm to about 65 nm, and the first thickness T1 may be about 1 nm to about 40 nm, or about 5 nm to about 35 nm.

[0140] After the etching process is performed, the mask pattern MP can be removed.

[0141] Reference Figure 15 After forming the source / drain contact BCA and the first contact pattern CP1.

[0142] The source / drain contact BCA can pass through the semiconductor substrate 100 of the first region I and be connected to the first source / drain region SD1. The first contact pattern CP1 can be connected to the semiconductor substrate 100 of the second region II.

[0143] In some embodiments, the rear source / drain contact BCA and the first contact pattern CP1 may be formed at the same level as each other. For example, the rear source / drain contact BCA and the first contact pattern CP1 may be formed by the same etching process and the same deposition process. Due to the thickness difference between the semiconductor substrate 100 in the first region I and the semiconductor substrate 100 in the second region II, the third height D12 of the first contact pattern CP1 may be smaller than the first height D11 of the rear source / drain contact BCA.

[0144] Reference Figure 16 After forming the gate contact BCB.

[0145] The rear gate contact BCB can pass through the semiconductor substrate 100 of the first region I and the gate dielectric film 120 of the first gate structure GS1, and is connected to the gate electrode 130 of the first gate structure GS1.

[0146] Although the rear gate contact BCB is described as being formed after the rear source / drain contact BCA and the first contact pattern CP1, this is merely an example. Of course, the rear source / drain contact BCA and the first contact pattern CP1 can be formed after the rear gate contact BCB, as described above. Figure 15 and Figure 16 The explanations are different.

[0147] Reference Figure 17 After forming, the insulating film 300 and the second through-piece contact 305 are formed.

[0148] A back insulating film 300 may be formed on the second side 100b of the semiconductor substrate 100 in the first region I. A second through-contact 305 may pass through the back insulating film 300 and be connected to the back source / drain contact BCA and / or the back gate contact BCB.

[0149] Reference Figure 18 This forms the back wiring structure BW.

[0150] A back wiring structure BW can be formed on the semiconductor substrate 100 of the back insulating film 300 and the second region II. The back wiring structure BW can be electrically connected to the back source / drain contact BCA, the back gate contact BCB and / or the first contact pattern CP1.

[0151] Next, refer to Figure 1 A connection terminal 390 is formed on the rear wiring structure BW. Therefore, it can be manufactured using the above-mentioned... Figure 1The semiconductor device described.

[0152] Figures 19 to 21 This is a diagram illustrating intermediate steps of a method for manufacturing a semiconductor device according to some embodiments. For ease of explanation, the above utilizes... Figures 1 to 18 Repeated portions of the description may be identical to those described herein, and these repeated portions will be briefly explained or omitted. For example, Figure 19 It is used to explain in Figure 14 The diagram shows the intermediate steps of the subsequent process.

[0153] Reference Figure 19 This forms the source / drain contact BCA.

[0154] The source / drain contact BCA can pass through the semiconductor substrate 100 of the first region I and is connected to the first source / drain region SD1.

[0155] Reference Figure 20 After forming the gate contact BCB and the second contact pattern CP2.

[0156] The rear gate contact BCB can pass through the semiconductor substrate 100 of the first region I and the gate dielectric film 120 of the first gate structure GS1, and is connected to the gate electrode 130 of the first gate structure GS1. The second contact pattern CP2 can be connected to the semiconductor substrate 100 of the second region II.

[0157] In some embodiments, the rear gate contact BCB and the second contact pattern CP2 may be formed at the same level as each other. For example, the rear gate contact BCB and the second contact pattern CP2 may be formed by the same etching process and the same deposition process. Due to the thickness difference between the semiconductor substrate 100 in the first region I and the semiconductor substrate 100 in the second region II, the fourth height D22 of the second contact pattern CP2 may be smaller than the second height D21 of the rear gate contact BCB.

[0158] Although the rear gate contact BCB and the second contact pattern CP2 are described as being formed after the rear source / drain contact BCA, this is merely an example. Of course, the rear source / drain contact BCA can be formed after the rear gate contact BCB and the second contact pattern CP2, as described above. Figure 19 and Figure 20 The differences are explained.

[0159] Reference Figure 21 After forming the insulating film 300 and the second through-piece contact 305, the above-described process can be performed. Figure 18 and Figure 1 The steps described are as follows. Therefore, the above-described method can be manufactured. Figure 2 The semiconductor device described.

[0160] Figures 22 to 24 This is a diagram illustrating intermediate steps in a method for manufacturing a semiconductor device according to some embodiments. For ease of explanation, the above utilizes... Figures 1 to 18 Repeated portions of the description may be identical to those described herein, and these repeated portions will be briefly explained or omitted. For example, Figure 22 It is used to explain in Figure 14 The intermediate steps of the subsequent steps are shown in the diagram.

[0161] Reference Figure 22 This forms the source / drain contact BCA and the gate contact BCB.

[0162] The rear source / drain contact BCA can pass through the semiconductor substrate 100 of the first region I and is connected to the first source / drain region SD1. The rear gate contact BCB can pass through the semiconductor substrate 100 of the first region I and the gate dielectric film 120 of the first gate structure GS1 and is connected to the gate electrode 130 of the first gate structure GS1.

[0163] The post-source / drain contact BCA can be formed after the post-gate contact BCB is formed, or it can be formed before the post-gate contact BCB is formed.

[0164] Reference Figure 23 After forming, the insulating film is 300.

[0165] A back insulating film 300 may be formed on the second side 100b of the semiconductor substrate 100 in the first region I.

[0166] Reference Figure 24 This forms the second through-piece contact 305 and the third contact pattern CP3.

[0167] The second through-contact 305 can pass through the rear insulating film 300 and is connected to the rear source / drain contact BCA and / or the rear gate contact BCB. The third contact pattern CP3 can be connected to the semiconductor substrate 100 of the second region II.

[0168] In some embodiments, the second through-hole contact 305 and the third contact pattern CP3 may be formed at the same level as each other. For example, the second through-hole contact 305 and the third contact pattern CP3 may be formed by the same etching process and the same deposition process. Due to the difference in etch selectivity between the back insulating film 300 and the semiconductor substrate 100, the fifth height D31 of the second through-hole contact 305 and the sixth height D32 of the third contact pattern CP3 may be different from each other.

[0169] While the inventive concept has been described with particular illustration and reference to exemplary embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope of the inventive concept as defined by the appended claims. Therefore, it is intended that the present embodiments be regarded in all respects as illustrative rather than restrictive, and that the scope of the invention be indicated by reference to the appended claims rather than the foregoing description.

Claims

1. A semiconductor device, comprising: A semiconductor substrate, comprising a first side and a second side on the side of the semiconductor substrate opposite to the first side; Active pattern on the first side; A gate structure that intersects with the active pattern; The source / drain regions connected to the active pattern are located on the side of the gate structure; A front wiring structure connected to at least one of the gate structure and the source / drain regions, on the first side; The rear wiring structure on the second side; as well as Contact patterns in the semiconductor substrate, wherein the contact patterns are connected to the back wiring structure. The height of the contact pattern in the vertical direction intersecting the first side is less than the thickness of the semiconductor substrate in the vertical direction.

2. The semiconductor device according to claim 1, in, The front wiring structure includes power wiring configured to be subjected to a power supply voltage.

3. The semiconductor device according to claim 2, further comprising: A through-hole member, which extends in the vertical direction and connects to the power supply wiring. The rear wiring structure includes a first rear wiring pattern connected to the contact pattern and a second rear wiring pattern connected to the through-piece. The first rear wiring pattern and the second rear wiring pattern are separate from each other.

4. The semiconductor device according to claim 1, in, The contact pattern overlaps with the source / drain region in the vertical direction.

5. The semiconductor device according to claim 4, in, The contact pattern is spaced apart from the source / drain region in the vertical direction.

6. The semiconductor device according to claim 1, in, The contact pattern overlaps with the gate structure in the vertical direction.

7. The semiconductor device according to claim 6, in, The contact pattern is spaced apart from the gate structure in the vertical direction.

8. The semiconductor device according to claim 1, in, The active pattern includes a plurality of bridge patterns, each of which is spaced apart from the semiconductor substrate in the vertical direction and passes through the gate structure.

9. The semiconductor device according to claim 1, in, The thickness of the semiconductor substrate in the vertical direction is 100 nm or less.

10. The semiconductor device according to claim 1, in, The contact pattern is electrically levitated.

11. A semiconductor device, comprising: A semiconductor substrate, comprising a first side and a second side on the side of the semiconductor substrate opposite to the first side; Active pattern on the first side; A gate structure that intersects with the active pattern; The source / drain regions connected to the active pattern are located on the side of the gate structure; A front wiring structure connected to the source / drain region is located on the first side; A contact pattern in the semiconductor substrate, wherein the contact pattern is spaced apart from the gate structure and the source / drain region; A first rear wiring pattern connected to the contact pattern, which is on the second side; A second post-wiring pattern, which is separate from the first post-wiring pattern; and A through-hole extends in a vertical direction intersecting the first side and connects the front wiring structure and the second rear wiring pattern.

12. The semiconductor device according to claim 11, in, The source / drain region is configured to be supplied with a power voltage through the second back wiring pattern, the through-hole, and the front wiring structure.

13. The semiconductor device of claim 11, further comprising: An insulating film between rear wiring patterns covering the first and second rear wiring patterns, which is on the second side; as well as A first connection terminal is connected to the second rear wiring pattern below the rear wiring interlayer insulating film.

14. The semiconductor device of claim 13, further comprising: The second connection terminal is connected to the first rear wiring pattern below the rear wiring interlayer insulating film.

15. The semiconductor device according to claim 11, in, The height of the contact pattern in the vertical direction is less than the thickness of the semiconductor substrate in the vertical direction.

16. A semiconductor device comprising a first region and a second region, the semiconductor device comprising: A semiconductor substrate, comprising a first side and a second side on the side of the semiconductor substrate opposite to the first side; The first active pattern on the first side of the first region; A first gate structure that intersects with the first active pattern; The first source / drain region is connected to the first active pattern and is located on the side of the first gate structure; The second active pattern on the first side of the second region; A second gate structure that intersects with the second active pattern; Connected to the second source / drain region of the second active pattern, which is on the side of the second gate structure; An interlayer insulating film covering the first gate structure, the first source / drain region, the second gate structure, and the second source / drain region is located on the first side; Front wiring structure on the interlayer insulating film; The first rear wiring pattern on the second side of the first region; A second rear wiring pattern on the second side of the second region, the second rear wiring pattern being separate from the first rear wiring pattern; A rear source / drain contact that passes through the semiconductor substrate of the first region and connects the first source / drain region and the first rear wiring pattern; as well as A contact pattern in the semiconductor substrate of the second region, wherein the contact pattern is connected to the second post-wiring pattern. Wherein, in the vertical direction intersecting the first side, the first thickness of the semiconductor substrate in the first region is less than the second thickness of the semiconductor substrate in the second region, and The first height of the post-source / drain contact in the vertical direction is greater than the second height of the contact pattern in the vertical direction.

17. The semiconductor device according to claim 16, in, The second height is less than the second thickness.

18. The semiconductor device according to claim 16, in, The contact pattern overlaps with the second source / drain region in the vertical direction.

19. The semiconductor device according to claim 16, in, The first source / drain region is configured to be supplied with a power supply voltage through the first rear wiring pattern and through the rear source / drain contacts.

20. The semiconductor device of claim 16, further comprising: The third rear wiring pattern is separate from the second rear wiring pattern; as well as A through-hole member extends in the vertical direction and connects the front wiring structure and the third rear wiring pattern. The second source / drain region is configured to be supplied with a power supply voltage through the third back wiring pattern, the through-hole, and the front wiring structure.

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